DE1212149C2 - Static counter - Google Patents

Description

XH ₃ = a * or λ & H _s *

β & If ₂ *) W (λ & H ₀ ^ = h * or (I & F ₂ *) V (A & W ₀ *) _ _

(T & H ₂ *) V (λ & T ₂ & H ₀ ') V (r ₂ & H ₂ *) = h _u * or (T & W ₂ *) V (λ & T ₈ & H ₀ *) V (r ₂ & H _t *)

where r _{2 means} the switchover signal for the payment direction.

= h _u *

The patent 1 205 147 relates to a static counter for counting up and down and optional pre-setting of any binary number and means for converting to a decimal counter with and without decimal presetting for counting up and down, which is controlled by counting signals and Auxiliary counting signals of any form is controlled, the auxiliary counting signals compared to the counting signals are staggered in time.

Various forms of binary and decimal counters are proposed in US Pat. No. 1,205,147.

The invention has set itself the task of creating counters that by simple switching can be used either as binary or decimal counters.

The invention relates to a static counter for counting up and down and optional presetting of any binary number and with means for converting into a decimal counter with and without decimal presetting for counting up and down, which is controlled by counting signals and auxiliary counting signals of any form, the auxiliary counting signals are offset in time with respect to the counting signals, and a main memory outputting the counting result and an auxiliary memory assigned to it are provided for each counting stage, the times of setting and clearing of the main memory being determined by the assigned auxiliary memory, which has different switching states at the times mentioned, and by at least one counting stage of the preceding binary digits or a counting signal or auxiliary counting signal according to patent 1 205 147. The invention consists in that the counter consists of groups of four counting stages (0, 1, II, III) and that in each group an operating mode signal A den t is introduced that one and the same counter wal, works as a binary or decimal counter. Eir further embodiment r is correspondingly assigned a logic circuit controlled by the /".-Signal Vc for a down-counter in the 1st group the main memory dei counting stage I, which generates a signal ά, and the auxiliary memory of the counting stage III by a Α- Signal-controlled logic circuit assigned, which generates a signal h ' ; for a down counter in the / group, the main memories of counting stages I and II are assigned a logic circuit controlled by the λ signal, which generates a signal a' ; for a switchable Up-down counters in the 1st group are assigned a logic circuit controlled by the / signal, which generates a signal a ' , to the main memories of counting stages I and II, and to the secondary memory of

Counting stage lit is assigned a logic circuit controlled by the / signal which generates a signal h _u '. According to a further training, the logic circuits controlling the switching of the mode of operation (binary-decimal) for the /. Group following switching functions

V HJ

= α 'or χ & Η ₃ ^{ (I & HJ) V (XSlHJ) = h < or (Χ & F ₂ ') V (A & ZZ ₀ O

(A & ZZ ₂ O ^ν (λ & ~ ri & ^ o ') V (i- ₂ & ZZ ₂ OV = Α. * Or (Τ & ZZ ₂ OV (A SlT ₂ Sl WJ) V (r ₂ &"

The invention is illustrated schematically with reference to in the drawings !! illustrated embodiments in more detail explained.

The F i g. 1 shows the 0th group of an up-counter that can be switched over (binary-decimal). The upper index attached to the designations A for the output signals of the main memory and the designations H for the auxiliary memory relates to the group. According to the invention, a signal a ° is fed into the setting stage of the main memory of counting stage I and a signal /; ° is fed into the holding stage of the auxiliary memory of counting stage III.

The counter according to FIG. 1 emerged from the basic circuit of a binary up counter according to the main patent application, in which the signal a " does not occur in the counting stage I and instead of the signal A ⁰ the signal H _{2 is passed} to the counting stage III or from the basic circuit of a decimal up counter after the Main patent application, in which instead of the signal a " the signal H ₃ ^{0 is passed} to the counting stage I and instead of the signal h ° the signal / Z ₀ ^{0 is} fed to the counting stage III.

The F i g. 4 shows circuits for generating the Signaisa *. The circuit according to FIG. 4a consists of an or-not stage which is controlled by the negated operating mode signal A and the negated auxiliary signal H ₃ * of the counter stage II. The circuit according to FIG. 4b consists of a girier and-not stage, which is driven by the signals A and Hj- .

If the mode signal A is = O, then a * = L, X = L, then iii = H ₃ K

The F i g. 5 shows circuits for generating the

Signal h *. The circuit according to FIG. 5a consists of two input AND stages with a mer / non stage connected downstream.

. The one input AND stage is negated by

Operating mode signal A and controlled by the output signal H ₂ ^{1 of} the auxiliary memory of counting stage II, the other input and stage is controlled by the operating mode signal A and the output signal HJ of the auxiliary memory of counting stage 0.

The circuit according to FIG. 5b consists of two input AND stages, which is followed by an OR-not stage. The_one input AND stage is controlled by the signals A and H ₂ ¹ , the other input AND stage by the signals X and HJ .

If the mode signal A = 0, then h ^{ = H ₂ ¹ , if X = L, then h ¹ = HJ.

40

45 If the signal λ corresponding to L occurs, the counter operates according to FIG. 1 as forward decimal number, if the signal X occurs corresponding to 0, this counter works as an forward binary counter.

FIG. 2 'shows the 0th group of a down counter which can be switched over in its mode of operation (binary-decimal). 4 signal formed ß ° in the setting stage of the main memory of the counting stages I and II according to FIG. 2 introduced. If the signal X occurs in accordance with L , the counter operates according to FIG. 2 as a downward decimal counter, the Signa! X corresponds to 0, this counter works as a downward binary counter.

The F i g. 3 shows the 0th group of a (binary-decimal) switchable up / down counter. According to the invention, that according to FIG. 4 formed signal a ° in the main memory of the counting stages I and II according to FIG. 3 introduced and a signal h _u ° to the auxiliary memory of the counting stage III according to FIG. 3 led.

The F i g. 6 shows circuits for generating the signal h _u ^l . The circuit according to FIG. 6a consists of three input-AND stages with a downstream or-not-not stage. The input AND stages are each controlled by the signal X, the negated switchover signal for the counting direction r ₂ and the signal HJ, the signal X and the signal HJ and the switchover _{signal r 2} for the counting direction.

The circuit according to FIG. 6b consists of three input AND stages followed by an OR stage. The input AND stages are each controlled by the signal X, T ₂ and HJ, X and HJ, TJJ and r ₂ .

When the mode signal is A = O, so is

A * = HJ V (r, & HJ),
if X = L, then

Λ * = (F ₂ Sl HJ) V (r ₂ & HJ).

If the signal X occurs in accordance with L , the counter operates according to FIG. 3 as a decimal switchable up / down counter, if the signal X occurs corresponding to 0, this counter works as a binary switchable up / down counter.

1 sheet of drawings

Claims (5)

Patent claims: 1. Static counter for up and down counting and optional presetting of any Binary number and with means for converting into a decimal counter with and without decimal presetting for upward and downward counting, which is controlled by auxiliary counting signals of any form is, the auxiliary counting signals are offset in time with respect to the counting signals, and each Counting stage a main memory outputting the counting result and an auxiliary memory assigned to it are provided, the times of setting and clearing the main memory are fixed through the assigned auxiliary memory, which has various switching states at the specified times has, and by at least one counting stage of the preceding binary digits or a counting signal or Counting auxiliary signal according to patent 1205 147, thereby characterized in that the counter consists of groups with four counting levels (0, I, II, III) each and that in each group a mode signal (λ) is introduced in such a way that one and the same counter works either as binary or decimal counter. 2. Static counter according to claim 1, characterized in that for an up counter in the i. Group the main memory of the counting stage (/) is assigned a logic circuit controlled by the Α signal, which generates a signal (a *) , and the auxiliary memory of the counting stage (III) is assigned a logic circuit controlled by the Α signal, which generates a signal (W). 3. Static counter according to claim 1, characterized in that for a down counter in the i. Group, the main memories of the counting stage (I and II) are assigned a logic circuit controlled by the Α signal, which generates a signal (a *): 4. Static counter according to claim 1, characterized in that for a switchable up-down counter in the i. Group, the main memories of the counting stage (I and II) are assigned a logic circuit controlled by the A ~ signal, which ^{generates a signal (α 1} ), and the auxiliary memory of the counting stage (III) is assigned a logic circuit controlled by the λ signal that generates a signal (A ₁₄ '). 5. Static counter according to claim 1
Mode of operation (binary-decimal controlling
have functions to 4, characterized in that the switching of the logic circuits for the /. Groups following switching