DE118513T1 - METHOD FOR PRODUCING A CMOS STRUCTURE. - Google Patents

Claims (9)

Claims 1. Method of forming, in a semiconductor substrate, structures of integrated circuits with complementary ones η-channel and p-channel devices with insulated gate electrode, characterized by the steps: - Forming a silicon layer (35) over the first structure, the first contact regions, the n-substrate contact regions (39S, 39D) contact, and has second contact areas, the p-substrate contact areas Contact (41S, 41D); - Doping selected areas of the silicon layer (35) with an n-type dopant, the selected areas include the first contact areas; - heating the resulting structure to an oxidizing atmosphere to form an oxide masking layer (37N) over the doped, selected areas of the silicon to form converting layer (35); - Using the oxide masking layer (37N) as a mask, doping unmasked areas of the structure with a p-dopant and - heating the resulting structure to the n-dopant concentration in the n-substrate contact regions (39S, 39D) and the p-dopant concentration in the to increase p-substrate contact areas (41S, 41D). 2. The method according to claim 1, characterized by the steps: - removing the oxide (35N, 37P) formed on the silicon layer (35); - applying a metallic layer (42) over the resulting structure and - delimiting the metallic layer (42) so as to form connecting conductors which are the first and second Contact contact areas of the silicon layer (35). 3. The method according to claim 2, characterized by the step: - Forming a passivation layer (43) over the structure after the step of delimiting. 4. The method according to claim 1, characterized in that before the step of forming a silicon layer (35) the steps are carried out: - Selective implantation of the structure with an n-dopant excluding the selected areas for p-channel devices; - Heating the substrate in order to drive the n-dopant in, creating η-doped regions (29S, 29D) for the n-channel devices are formed, and one forming an initial oxide masking layer (3ON) on the areas implanted with the n-dopant; - Using the initial oxide masking layer (30N) as a mask, doping the substrate with one p-dopants to form p-doped regions (31S, 31D) for the p-channel devices and - Forming an intermediate dielectric layer (33) on the structure with openings corresponding to the n and p-substrate contact areas (39S, 39D; 41S, 41D). 5. The method according to claim 4, characterized in that the n-substrate contact areas (39S, 39D) in the η-doped areas (29S, 29D) and the p-substrate contact areas (41S, 41D) in the p-doped Areas (31S, 31D) are included. 6. The method according to claim 4, characterized in that before the step of the selective Implanting the structure with an n-dopant the steps are carried out: - Provision of polysilicon gate electrodes (27N, 27P) for η-channel and p-channel devices and polysilicon interconnects (27C), and that the initial oxide masking layer (30N, 30C) is the n-channel gate electrodes (27N) and the polysilicon interconnects (27C). 7. The method according to claim 6, characterized in that the silicon layer (35) third Having contact areas in contact with areas of the polysilicon interconnects (27C). 8. The method according to claim 1, characterized in that the silicon layer (35) in Form of undoped, polycrystalline silicon is deposited. 9. The method according to any one of the preceding claims, characterized in that the n-dopant Arsenic and the p-dopant is boron.