DE112022004806T5 - SEMICONDUCTOR HOUSING - Google Patents

Abstract

A semiconductor package includes a die pad, a semiconductor device disposed on the die pad and having a chip with a main surface, a main surface electrode disposed on the main surface, a terminal electrode disposed on the main surface electrode, and a sealing insulator that includes a first matrix resin and first fillers and covers a periphery of the terminal electrode on the main surface to expose a part of the terminal electrode, and a package body that includes a second matrix resin and second fillers and that seals the die pad and the semiconductor device to cover the sealing insulator.

Description

Technical area

This application claims the benefit of priority from the Japanese Patent Application No. 2021-181321 , filed on November 5, 2021, and the entire contents of that application are incorporated herein by reference. The present disclosure relates to a semiconductor package.

State of the art

Patent Literature 1 discloses a semiconductor device including a semiconductor substrate, an electrode, and a protective film. The electrode is formed on the semiconductor substrate. The protective film has a laminated structure including an inorganic protective film and an organic protective film and covering the electrode.

List of objections

Patent literature

Patent Literature 1: US Patent Application Publication No. 2019/0080976

Brief description of the invention

Technical problem

An embodiment provides a semiconductor package that can improve reliability.

the solution of the problem

An embodiment provides a semiconductor package including a die pad, a semiconductor device disposed on the die pad and having a chip with a main surface, a main surface electrode disposed on the main surface, a terminal electrode disposed on the main surface electrode, and a sealing insulator that includes a first matrix resin and first fillers and covers a periphery of the terminal electrode on the main surface to expose a part of the terminal electrode, and a package body that includes a second matrix resin and second fillers and that seals the die pad and the semiconductor device to cover the sealing insulator.

The above and other objects, features and effects of the present invention will be explained from the following description of embodiments with reference to the accompanying drawings.

Short description of the drawings

• [ 1 ] 1 is a plan view of a semiconductor device according to a first embodiment.
• [ 2 ] 2 is a cross-sectional view along the 1 shown line II-II.
• [ 3 ] 3 is an enlarged plan view showing a main part of an internal portion of a chip.
• [ 4 ] 4 is a cross-sectional view along the 3 shown line IV-IV.
• [ 5 ] 5 is an enlarged cross-sectional view showing a peripheral portion of the chip.
• [ 6 ] 6 is a plan view showing layout examples of a gate electrode and a source electrode.
• [ 7 ] 7 is a plan view showing a layout example of an upper insulating film.
• [ 8th ] 8th is a plan view showing a semiconductor package in which the semiconductor device of 1 can be installed.
• [ 9 ] 9 is a cross-sectional view along the 8th shown line IX-IX.
• [ 10A ] 10A is an enlarged cross-sectional view showing a first configuration example of a 9 shown area X.
• [ 10B ] 10B is an enlarged cross-sectional view showing a second configuration example of a 9 shown area X.
• [ 10C ] 10C is an enlarged cross-sectional view showing a third configuration example of a 9 shown area X.
• [ 11 ] 11 is a perspective view showing a wafer structure that can be used at a time of manufacturing.
• [ 12 ] 12 is a top view that gives you 11 shown device area.
• [ 13A ] 13A is a cross-sectional view showing an exemplary manufacturing process for the 1 semiconductor device shown.
• [ 13B ] 13B is a cross-sectional view showing one step 13A shows.
• [ 13C ] 13C is a cross-sectional view showing one step 13B shows.
• [ 13D ] 13D is a cross-sectional view showing one step 13C shows.
• [ 13E ] 13E is a cross-sectional view showing one step 13D shows.
• [ 13F ] 13F is a cross-sectional view showing one step 13E shows.
• [ 13G ] 13G is a cross-sectional view showing one step 13F shows.
• [ 13H ] 13H is a cross-sectional view showing one step 13G shows.
• [ 13I ] 13I is a cross-sectional view showing one step 13H shows.
• [ 14A ] 14A is a cross-sectional view showing an exemplary manufacturing process for the 8th semiconductor package shown.
• [ 14B ] 14B is a cross-sectional view showing one step 14A shows.
• [ 14C ] 14C is a cross-sectional view showing one step 14B shows.
• [ 15 ] 15 is a plan view showing a semiconductor device according to a second embodiment.
• [ 16 ] 16 is a plan view showing a semiconductor device according to a third embodiment.
• [ 17 ] 17 is a cross-sectional view along the 16 shown line XVII-XVII.
• [ 18 ] 18 is a circuit diagram showing an electrical configuration of the 16 semiconductor device shown.
• [ 19 ] 19 is a plan view showing a semiconductor device according to a fourth embodiment.
• [ 20 ] 20 is a cross-sectional view along the 19 shown line XX-XX.
• [ 21 ] 21 is a plan view showing a semiconductor device according to a fifth embodiment.
• [ 22 ] 22 is a plan view showing a semiconductor device according to a sixth embodiment.
• [ 23 ] 23 is a plan view showing a semiconductor device according to a seventh embodiment.
• [ 24 ] 24 is a plan view showing a semiconductor device according to an eighth embodiment.
• [ 25 ] 25 is a cross-sectional view along the 24 shown line XXV-XXV.
• [ 26 ] 26 is a plan view showing a semiconductor package in which the semiconductor device of 24 can be installed.
• [ 27 ] 27 is a perspective view showing a semiconductor package in which the semiconductor device of 1 and the 24 shown semiconductor device can be incorporated.
• [ 28 ] 28 is an exploded perspective view of the 27 shown housing.
• [ 29 ] 29 is a cross-sectional view along the 27 shown line XXIX-XXIX.
• [ 30 ] 30 is a cross-sectional view showing a modified example of the chip that can be applied to each embodiment.
• [ 31 ] 31 is a cross-sectional view showing a modified example of a sealing insulator that can be applied to each embodiment.

Description of embodiments

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The accompanying drawings are schematic views without precise illustrations, and their scales and the like are not always the same. In addition, identical reference numerals are assigned to corresponding structures in the accompanying drawings, and duplicate descriptions thereof are omitted or simplified. For the structures whose description is omitted or simplified, the description given before the omission or simplification applies.

1 is a plan view of a semiconductor device 1A according to a first embodiment. 2 is a cross-sectional view along the 1 shown line II-II. 3 is an enlarged plan view showing a main part of an inner portion of a chip 2. 4 is a cross-sectional view along the 3 shown line IV-IV. 5 is an enlarged cross-sectional view showing a peripheral portion of the chip 2. 6 is a plan view showing layout examples of a gate electrode 30 and a source electrode 32. 7 is a plan view showing a layout example of an upper insulating film 38.

With reference to 1 until 7 In this embodiment, the semiconductor device 1A includes a chip 2 which includes a single crystal of a wide band gap semiconductor and which is formed in a hexahedral shape (in particular icularly in the shape of a rectangular parallelepiped). That is, the semiconductor device 1A is a "wide band gap semiconductor device". The chip 2 may be referred to as a "semiconductor chip" or a "wide band gap semiconductor chip". The wide band gap semiconductor is a semiconductor having a band gap that exceeds the band gap of Si (silicon). Examples of wide band gap semiconductors are GaN (gallium nitride), SiC (silicon carbide) and C (diamond).

The chip 2 is a "SiC chip" including a SiC single crystal of a hexagonal crystal as an example of the wide band gap semiconductor. That is, the semiconductor device 1A is a "SiC semiconductor device." The SiC single crystal of the hexagonal crystal has a plurality of polytypes including 2H (hexagonal) SiC single crystal, 4H SiC single crystal, 6H SiC single crystal, and the like. In this embodiment, an example will be given in which the chip 2 includes the 4H SiC single crystal, but this does not exclude the selection of other polytypes.

The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are each quadrangular in shape when viewed from their normal direction Z (hereinafter referred to simply as "top view"). The normal direction Z is also a direction of the thickness of the chip 2. The first main surface 3 and the second main surface 4 are preferably each formed by a c-plane of the SiC single crystal.

In this case, the first main surface 3 is preferably formed by a silicon surface of the SiC single crystal, and the second main surface 4 is preferably formed by a carbon surface of the SiC single crystal. The first main surface 3 and the second main surface 4 may each have an off angle inclined by a predetermined angle with respect to the c-plane in a predetermined off angle direction. The off angle is preferably an a-axis direction ([11-20] direction) of the SiC single crystal. The off angle may exceed 0° and be not greater than 10°. The off angle is preferably not greater than 5°. The second main surface 4 may be composed of a ground surface having grinding marks or may be composed of a smooth surface without grinding marks.

The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face each other in a second direction Y that intersects (in particular, is orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face each other in the first direction X. The first direction X may be an m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Of course, the first direction X may be the a-axis direction of the SiC single crystal, and the second direction Y may be the m-axis direction of the SiC single crystal. The first to fourth side surfaces 5A to 5D may each be composed of a ground surface with grinding marks, or may each be composed of a smooth surface without grinding marks.

The chip 2 has a thickness of not less than 5 µm and not more than 250 µm with respect to the normal direction 2. The thickness of the chip 2 may be not more than 100 µm. The thickness of the chip 2 is preferably not more than 50 µm. More preferably, the thickness of the chip 2 is not more than 40 µm. The first to fourth side surfaces 5A to 5D may each have a length of not less than 0.5 mm and not more than 10 mm in plan view.

The lengths of the first to fourth side surfaces 5A to 5D are preferably not less than 1 mm. The lengths of the first to fourth side surfaces 5A to 5D are particularly preferably not less than 2 mm. That is, the chip 2 preferably has a planar area of not less than 1 mm ² (preferably not less than 2 mm ² ) and preferably has a thickness of not more than 100 µm (preferably not more than 50 µm). The lengths of the first to fourth side surfaces 5A to 5D are set to a range of not less than 4 mm and not more than 6 mm in this embodiment.

The semiconductor device 1A includes a first semiconductor region 6 of n-type (first conductivity type) formed in a region (surface layer portion) on the first main surface 3 side within the chip 2. The first semiconductor region 6 is formed in a layered form extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. The first semiconductor region 6 is composed of an epitaxial layer (specifically, a SiC epitaxial layer) in this embodiment. The first semiconductor region 6 may have a thickness of not less than 1 µm and not more than 50 µm with respect to the normal direction Z. The thickness of the first semiconductor region 6 is preferably not less than 3 µm and not more than 30 µm. The thickness of the first semiconductor region 6 is particularly preferably not less than 5 µm and not more than 25 µm.

The semiconductor device 1A includes an n-type second semiconductor region 7 formed in a region (surface layer portion) on the second main surface 4 side within the chip 2. The second semiconductor region 7 is formed in a layered shape extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. The second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is composed of a semiconductor substrate (specifically, a SiC semiconductor substrate) in this embodiment. That is, the chip 2 has a laminated structure including the semiconductor substrate and the epitaxial layer.

The second semiconductor region 7 may have a thickness of not less than 1 μm and not more than 200 μm with respect to the normal direction 2. The thickness of the second semiconductor region 7 is preferably not less than 5 μm and not more than 50 μm. In particular, the thickness of the second semiconductor region 7 is preferably not less than 5 μm and not more than 20 μm. In view of a possible defect occurring in the first semiconductor region 6, the thickness of the second semiconductor region 7 is preferably not less than 10 μm. The thickness of the second semiconductor region 7 is most preferably smaller than the thickness of the first semiconductor region 6. According to the relatively small thickness of the second semiconductor region 7, a resistance value (for example, an on-resistance) due to the second semiconductor region 7 can be reduced. Of course, the thickness of the second semiconductor region 7 may exceed the thickness of the first semiconductor region 6.

The semiconductor device 1A includes an active surface 8 (active surface), an outer surface 9 (outer surface), and first to fourth connection surfaces 10A to 10D (connection surface) formed in the first main surface 3. The active surface 8, the outer surface 9, and the first to fourth connection surfaces 10A to 10D define a mesa portion 11 (plateau) in the first main surface 3. The active surface 8 may be referred to as a “first surface portion,” the outer surface 9 may be referred to as a “second surface portion,” and the first to fourth connection surfaces 10A to 10D may be referred to as “connection surface portions.” The active surface 8, the outer surface 9, and the first to fourth connection surfaces 10A to 10D (that is, the mesa portion 11) may be considered as components of the chip 2 (the first main surface 3).

The active surface 8 is formed at a distance inward from a peripheral edge of the first main surface 3 (the first to fourth side surfaces 5A to 5D). The active surface 8 has a flat surface extending in the first direction X and the second direction Y. The active surface 8 in this embodiment is quadrangular in shape in plan view, with the four sides running parallel to the first to fourth side surfaces 5A to 5D.

The outer surface 9 is positioned outside the active surface 8 and is recessed toward the thickness direction of the chip 2 (the second main surface 4 side) from the active surface 8. Specifically, the outer surface 9 is recessed to a depth less than the thickness of the first semiconductor region 6 to expose the first semiconductor region 6. The outer surface 9 extends in a band shape along the active surface 8 and is formed in a ring shape (specifically, a quadrangular ring shape) around the active surface 8 in plan view. The outer surface 9 has a flat surface extending in the first direction X and the second direction Y and formed substantially parallel to the active surface 8. The outer surface 9 is continuous with the first to fourth side surfaces 5A to 5D.

The first to fourth connection surfaces 10A to 10D extend in the normal direction 2 and connect the active surface 8 and the outer surface 9. The first connection surface 10A is positioned on the first side surface 5A side, the second connection surface 10B is positioned on the second side surface 5B side, the third connection surface 10C is positioned on the third side surface 5C side, and the fourth connection surface 10D is positioned on the fourth side surface 5D side. The first connection surface 10A and the second connection surface 10B extend in the first direction X and face each other in the second direction Y. The third connection surface 10C and the fourth connection surface 10D extend in the second direction Y and face each other in the first direction X.

The first to fourth connection surfaces 10A to 10D may extend substantially vertically between the active surface 8 and the outer surface 9 so that the mesa portion 11 is defined in the shape of a quadrangular column. The first to fourth connection surfaces 10A to 10D may be inclined downward from the active surface 8 to the outer surface 9 so that the mesa portion 11 is defined in the shape of a quadrangular pyramid. Thus, the semiconductor device 1A includes the mesa portion 11 formed in the first semiconductor region 6 on the first main surface 3. The mesa portion 11 is formed only in the first semiconductor region 6 and is not formed in the second semiconductor region 7.

The semiconductor device 1A includes a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure 12 formed in the active surface 8 (the first main surface 3). In 2 The MISFET structure 12 is shown in simplified form by a dashed line. The following is explained with reference to 3 and 4 a specific structure of the MISFET structure 12 is described.

The MISFET structure 12 includes a p-type (second conductivity type) body region 13 formed in a surface layer portion of the active surface 8. The body region 13 is formed at a distance to the active surface 8 side from a bottom portion of the first semiconductor region 6. The body region 13 is formed in a layered shape extending along the active surface 8. The body region 13 may be exposed from parts of the first to fourth interconnection surfaces 10A to 10D.

The MISFET structure 12 includes an n-type source region 14 formed in a surface layer portion of the body region 13. The source region 14 has a higher n-type impurity concentration than the first semiconductor region 6. The source region 14 is formed at a distance to the active surface 8 side from a bottom portion of the body region 13. The source region 14 is formed in a layered shape extending along the active surface 8. The source region 14 may be exposed from an entire region of the active surface 8. The source region 14 may be exposed from parts of the first to fourth connection surfaces 10A to 10D. The source region 14 forms a channel within the body region 13 between the first semiconductor region 6 and the source region 14.

The MISFET structure 12 includes a plurality of gate structures 15 formed in the active surface 8. The plurality of gate structures 15 are arranged at intervals in the first direction X and each formed in a band shape extending in the second direction Y in plan view. The plurality of gate structures 15 penetrate the body region 13 and the source region 14 to reach the first semiconductor region 6. The plurality of gate structures 15 control inversion and non-inversion of the channel in the body region 13.

Each of the gate structures 15 in this embodiment includes a gate trench 15a, a gate insulating film 15b, and an embedded gate electrode 15c. The gate trench 15a is formed in the active surface 8 and defines a wall surface of the gate structure 15. The gate insulating film 15b covers the wall surface of the gate trench 15a. The embedded gate electrode 15c is embedded in the gate trench 15a with the gate insulating film 15b interposed therebetween, and faces the channel across the gate insulating film 15b.

The MISFET structure 12 includes a plurality of source structures 16 formed in the active surface 8. The plurality of source structures 16 are each arranged in a region between a pair of adjacent gate structures 15 in the active surface 8. The plurality of source structures 16 are each formed in a band shape extending in the second direction Y in plan view. The plurality of source structures 16 penetrate the body region 13 and the source region 14 so as to reach the first semiconductor region 6. The plurality of source structures 16 have depths that exceed the depths of the gate structures 15. In particular, the plurality of source structures 16 have depths that substantially correspond to the depth of the outer surface 9.

Each of the source structures 16 includes a source trench 16a, a source insulating film 16b, and an embedded source electrode 16c. The source trench 16a is formed in the active surface 8 and defines a wall surface of the source structure 16. The source insulating film 16b covers the wall surface of the source trench 16a. The embedded source electrode 16c is embedded in the source trench 16a with the source insulating film 16b interposed therebetween.

The MISFET structure 12 includes a plurality of p-type contact regions 17, each formed in a region along the source structure 16 within the chip 2. The plurality of contact regions 17 have a higher p-type impurity concentration than the body region 13. Each of the contact regions 17 covers the sidewall and bottom wall of each of the source structures and is electrically connected to the body region 13.

The MISFET structure 12 includes a plurality of p-type well regions 18, each formed in a region along the source structure 16 within the chip 2. Each of the well regions 18 may have a p-type impurity concentration higher than that of the body region 13 and lower than that of the contact regions 17. Each of the well regions 18 covers the corresponding source structure 16 with the corresponding contact region 17 disposed therebetween. Each of the well regions 18 covers the sidewall and the bottom wall of the corresponding source structure 16 and is electrically connected to the body region 13 and the contact regions 17.

With reference to 5 the semiconductor device 1A includes a p-type outer contact region 19 formed in a surface layer portion of the outer surface 9. The outer contact region 19 has a higher p-type impurity concentration than the body region 13. The outer contact region 19 is formed at intervals from a peripheral edge of the active surface 8 and a peripheral edge of the outer surface 9, and has a band shape extending along the active surface 8 in plan view.

In this embodiment, the outer contact region 19 is formed in a ring shape (in particular a square ring shape) around the active surface 8 in plan view. The outer contact region 19 is formed at a distance to the side of the outer surface 9 from the bottom section of the first semiconductor region 6. The outer contact region 19 is positioned on the side of the bottom section of the first semiconductor region 6 with respect to the bottom walls of the plurality of gate structures 15 (the plurality of source structures 16).

The semiconductor device 1A includes a p-type outer well region 20 formed in the surface layer portion of the outer surface 9. The outer well region 20 has a lower p-type impurity concentration than the outer contact region 19. The p-type impurity concentration of the outer well region 20 is preferably substantially equal to the p-type impurity concentration of the well regions 18. The outer well region 20 is formed in a region between the peripheral edge of the active surface 8 and the outer contact region 19 and has a band shape extending along the active surface 8 in plan view.

In this embodiment, the outer well region 20 is formed in a ring shape (in particular a square ring shape) around the active surface 8 in plan view. The outer well region 20 is formed at a distance to the side of the outer surface 9 from the bottom portion of the first semiconductor region 6. The outer well region 20 can be formed deeper than the outer contact region 19. The outer well region 20 is positioned on the side of the bottom portion of the first semiconductor region 6 with respect to the plurality of gate structures 15 (the plurality of source structures 16).

The outer well region 20 is electrically connected to the outer contact region 19. The outer well region 20 in this embodiment extends from the side of the outer contact region 19 toward the side of the first to fourth connection surfaces 10A to 10D and covers the first to fourth connection surfaces 10A to 10D. The outer well region 20 is electrically connected to the body region 13 in the surface layer portion of the active surface 8.

The semiconductor device 1A includes at least one (preferably not less than 2 and not more than 20) p-type field region 21 formed in a region between the peripheral edge of the outer surface 9 and the external contact region 19 in the surface layer portion of the outer surface 9. The semiconductor device 1A in this embodiment includes five field regions 21. The plurality of field regions 21 relax an electric field inside the chip 2 on the outer surface 9. The number, width, depth, p-type impurity concentration, etc. of the field region 21 are arbitrary, and various values can be adopted depending on the electric field to be relaxed.

The plurality of field regions 21 are arranged at intervals from the side of the outer contact region 19 to the side of the peripheral edge of the outer surface 9. The plurality of field regions 21 are each formed in a band shape that extends along the active surface 8 in plan view. In this embodiment, the plurality of field regions 21 are each formed in a ring shape (in particular a square ring shape) around the active surface 8 in plan view. Thus, the plurality of field regions 21 are each formed as an FLR region (field limiting ring region).

The plurality of field regions 21 are formed at intervals to the outer surface 9 side from the bottom portion of the first semiconductor region 6. The plurality of field regions 21 are formed with respect to the bottom walls of the plurality of gate structures 15 (the plurality of source structures 16) on the side of the bottom portion of the first semiconductor region 6. The plurality of field regions 21 can be deeper than the outer contact region 19. The innermost field region 21 can be connected to the outer contact region 19.

The semiconductor device 1A includes a main surface insulating film 25 covering the first main surface 3. The main surface insulating film 25 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The main surface insulating film 25 in this embodiment has a single-layer structure composed of the silicon oxide film. In particular, the main surface insulating film 25 preferably includes the silicon oxide film composed of an oxide of the chip 2.

The main surface insulating film 25 covers the active surface 8, the outer surface 9, and the first to fourth connection surfaces 10A to 10D. The main surface insulating film 25 covers the active surface 8 so as to be continuous with the gate insulating film 15b and the source insulating film 16b and to expose the embedded gate electrode 15c and the embedded source electrode 16c. The main surface insulating film 25 covers the outer surface 9 and the first to fourth connection surfaces 10A to 10D so as to cover the outer contact region 19, the outer well region 20, and the plurality of field regions 21.

The main surface insulating film 25 may be continuous with the first to fourth side surfaces 5A to 5D. In this case, an outer wall of the main surface insulating film 25 may be composed of a ground surface having grinding marks. The outer wall of the main surface insulating film 25 may form a single ground surface with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the main surface insulating film 25 may be formed at a distance inward from the peripheral edge of the outer surface 9 and may expose the first semiconductor region 6 from a peripheral edge portion of the outer surface 9.

The semiconductor device 1A includes a sidewall structure 26 formed on the main surface insulating film 25 so as to cover at least one of the first to fourth connection surfaces 10A to 10D on the outer surface 9. The sidewall structure 26 is formed in a ring shape (specifically, a square ring shape) around the active surface 8 in this embodiment in plan view. The sidewall structure 26 may have a portion overlapping with the active surface 8. The sidewall structure 26 may include an inorganic insulator or a polysilicon. The sidewall structure 26 may be a sidewall wiring electrically connected to the plurality of source structures 16.

The semiconductor device 1A includes an interlayer insulating film 27 formed on the main surface insulating film 25. The interlayer insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The interlayer insulating film 27 in this embodiment has a single-layer structure composed of the silicon oxide film.

The interlayer insulating film 27 covers the active surface 8, the outer surface 9, and the first to fourth connection surfaces 10A to 10D with the main surface insulating film 25 interposed therebetween. Specifically, the interlayer insulating film 27 covers the active surface 8, the outer surface 9, and the first to fourth connection surfaces 10A to 10D across the sidewall structure 26. The interlayer insulating film 27 covers the MISFET structure 12 on the active surface 8 side, and covers the outer contact region 19, the outer well region 20, and the plurality of field regions 21 on the outer surface 9 side.

The interlayer insulating film 27 is continuous with the first to fourth side surfaces 5A to 5D in this embodiment. An outer wall of the interlayer insulating film 27 may be composed of a ground surface having grinding marks. The outer wall of the interlayer insulating film 27 may form a single ground surface with the first to fourth side surfaces 5A to 5D. Of course, the outer wall of the interlayer insulating film 27 may be formed at a distance inward from the peripheral edge of the outer surface 9 and may expose the first semiconductor region 6 from the peripheral edge portion of the outer surface 9.

The semiconductor device 1A includes a gate electrode 30 disposed on the first main surface 3 (the interlayer insulating film 27). The gate electrode 30 may be referred to as a “gate main surface electrode.” The gate electrode 30 is disposed at an inner portion of the first main surface 3 at a distance from the peripheral edge of the first main surface 3. The gate electrode 30 is disposed on the active surface 8 in this embodiment. Specifically, the gate electrode 30 is disposed in a region adjacent to a central portion of the third connection surface 10C (the third side surface 5C) at the peripheral edge portion the active surface 8. The gate electrode 30 is square in plan view in this embodiment. Of course, the gate electrode 30 can also be formed in plan view as a polygonal shape other than the square shape, a circular shape or an elliptical shape.

The gate electrode 30 preferably has a planar area of not more than 25% of the first main surface 3. The planar area of the gate electrode 30 may be not more than 10% of the first main surface 3. The gate electrode 30 may have a thickness of not less than 0.5 μm and not more than 15 μm. The gate electrode 30 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

The gate electrode 30 may include at least one of a pure Cu film (a Cu film with a purity of not less than 99%), a pure Al film (an Al film with a purity of not less than 99%), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The lower gate conductor layer 31 has a laminated structure including the Ti film and the Al alloy film (in this embodiment, AlSiCu alloy film) laminated in this order from the chip 2 side.

The semiconductor device 1A includes a source electrode 32 disposed on the first main surface 3 (the interlayer insulating film 27) at a distance from the gate electrode 30. The source electrode 32 may be referred to as a "source main surface electrode". The source electrode 32 is disposed at an inner portion of the first main surface 3 at a distance from the peripheral edge of the first main surface 3. The source electrode 32 is disposed on the active surface 8 in this embodiment. The source electrode 32 in this embodiment has a body electrode portion 33 and at least one (in this embodiment, a plurality of) drawer electrode portions 34A, 34B.

The body electrode portion 33 is arranged in a region on the side of the fourth side surface 5D (the fourth connection surface 10D) at a distance from the gate electrode 30 and faces the gate electrode 30 in the first direction X in plan view. The body electrode portion 33 in this embodiment is formed in a polygonal shape (specifically, quadrangular shape) in plan view in which four sides are parallel to the first to fourth side surfaces 5A to 5D in plan view.

The plurality of drawer electrode portions 34A, 34B include a first drawer electrode portion 34A on one side (the first side surface 5A side) and a second drawer electrode portion 34B on the other side (the second side surface 5B side). The first drawer electrode portion 34A is led out from the body electrode portion 33 to a region located on one side (the first side surface 5A side) of the second direction Y with respect to the gate electrode 30, and faces the gate electrode 30 in the second direction Y in plan view.

The second drawer electrode portion 34B is led out from the body electrode portion 33 to a region located on the other side (the second side surface 5B side) of the second direction Y with respect to the gate electrode 30, and faces the gate electrode 30 in plan view in the second direction Y. That is, the plurality of drawer electrode portions 34A, 34B enclose the gate electrode 30 in plan view from both sides of the second direction Y.

The source electrode 32 (the body electrode portion 33 and the drawer electrode portions 34A, 34B) penetrates the interlayer insulating film 27 and the main surface insulating film 25, and is electrically connected to the plurality of source structures 16, the source region 14, and the plurality of well regions 18. Of course, the source electrode 32 does not have to have the drawer electrode portions 34A, 34B, and may be composed of only the body electrode portion 33.

The source electrode 32 has a planar area that exceeds the planar area of the gate electrode 30. The planar area of the source electrode 32 is preferably not less than 50% of the first main surface 3. More preferably, the planar area of the source electrode 32 is not less than 75% of the first main surface 3. The source electrode 32 may have a thickness of not less than 0.5 μm and not more than 15 μm. The source electrode 32 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

The source electrode 32 may be at least one of a pure Cu film (a Cu film having a purity of not less than 99%), a pure Al film (an Al film having a purity of not less than 99%), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. The source electrode 32 in this embodiment has a laminated structure including the Ti film and the Al alloy film (AlSiCu alloy film in this embodiment) laminated in this order from the chip 2 side. The source electrode 32 preferably has the same conductive material as the gate electrode 30.

The semiconductor device 1A includes at least one (in this embodiment, a plurality of) gate wirings 36A, 36B that are led out from the gate electrode 30 to the first main surface 3 (the interlayer insulating film 27). The plurality of gate wirings 36A, 36B preferably include the same conductive material as the gate electrode 30. The plurality of gate wirings 36A, 36B cover the active surface 8 in this embodiment and do not cover the outer surface 9. The plurality of gate wirings 36A, 36B are led out to a region between the peripheral edge of the active surface 8 and the source electrode 32 and each extend in a band-like manner along the source electrode 32 in plan view.

Specifically, the plurality of gate wirings 36A, 36B include a first gate wiring 36A and a second gate wiring 36B. The first gate wiring 36A is led out from the gate electrode 30 to a region on the first side surface 5A side in plan view. The first gate wiring 36A includes a portion extending in a band shape in the second direction Y along the third side surface 5C and a portion extending in a band shape in the first direction X along the first side surface 5A. The second gate wiring 36B is led out from the gate electrode 30 to a region on the second side surface 5B side in plan view. The second gate wiring 36B includes a portion extending in a band shape in the second direction Y along the third side surface 5C and a portion extending in a band shape in the first direction X along the second side surface 5B.

The plurality of gate wirings 36A, 36B intersect (specifically, perpendicularly intersect) both end portions of the plurality of gate structures 15 at the peripheral edge portion of the active surface 8 (the first main surface 3). The plurality of gate wirings 36A, 36B penetrate the interlayer insulating film 27 and are electrically connected to the plurality of gate structures 15. The plurality of gate wirings 36A, 36B may be directly connected to the plurality of gate structures 15 or may be electrically connected to the plurality of gate structures 15 via a conductor film.

The semiconductor device 1A includes a source wiring 37 that is led out from the source electrode 32 to the first main surface 3 (the interlayer insulating film 27). The source wiring 37 preferably includes the same conductive material as the source electrode 32. The source wiring 37 is formed in a band shape and extends along the peripheral edge of the active surface 8 in a region that is further on the outer surface 9 side than the plurality of gate wirings 36A, 36B. The source wiring 37 is formed in a ring shape (specifically, a square ring shape) around the gate electrode 30, the source electrode 32, and the plurality of gate wirings 36A, 36B in this embodiment in plan view.

The source wiring 37 covers the sidewall structure 26 with the interlayer insulating film 27 interposed therebetween, and is led out from the active surface 8 side to the outer surface 9 side. The source wiring 37 preferably covers an entire area of the sidewall structure 26 over an entire circumference. The source wiring 37 penetrates the interlayer insulating film 27 and the main surface insulating film 25 on the outer surface 9 side, and has a portion connected to the outer surface 9 (particularly, the outer contact region 19). The source wiring 37 may penetrate the interlayer insulating film 27 and may be electrically connected to the sidewall structure 26.

The semiconductor device 1A includes an upper insulating film 38 that selectively covers the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A, 36B, and the source wiring 37. The upper insulating film 38 has a gate opening 39 that exposes an inner portion of the gate electrode 30, and covers a peripheral edge portion of the gate electrode 30 over an entire circumference. The gate opening 39 is formed quadrangular in plan view in this embodiment.

The upper insulating film 38 has a source opening 40 exposing an inner portion of the source electrode 32, and covers a peripheral edge portion of the source electrode 32 over the entire circumference. The source opening 40 is formed polygonally along the source electrode 32 in plan view in this embodiment. The upper insulating film 38 covers entire regions of the plurality of gate wirings 36A, 36B and an entire region of the source wiring 37.

The upper insulating film 38 covers the side wall structure 26 with the interlayer insulating film 27 interposed therebetween, and is led out from the active surface 8 side to the outer surface 9 side. The upper insulating film 38 is formed at a distance inward from the peripheral edge of the outer surface 9 (the first to fourth side surfaces 5A to 5D), and covers the outer contact region 19, the outer well region 20, and the plurality of field regions 21. The upper insulating film 38 defines a dicing line 41 with the peripheral edge of the outer surface 9.

The dicing line 41 is formed in a band shape extending along the peripheral edge of the outer surface 9 (the first to fourth side surfaces 5A to 5D) in plan view. The dicing line 41 is formed in a ring shape (specifically, a quadrangular ring shape) around the inner portion of the first main surface 3 (the active surface 8) in this embodiment in plan view. In this embodiment, the dicing line 41 exposes the interlayer insulating film 27.

Of course, in a case where the main surface insulating film 25 and the interlayer insulating film 27 expose the outer surface 9, the dicing line 41 may expose the outer surface 9. The second dicing line 41 may have a thickness of not less than 1 μm and not more than 200 μm. The width of the dicing line 41 is a width in a direction orthogonal to an extending direction of the dicing line 41. The width of the dicing line 41 is preferably not less than 5 μm and not more than 50 μm.

The upper insulating film 38 preferably has a thickness that exceeds the thickness of the gate electrode 30 and the thickness of the source electrode 32. The thickness of the upper insulating film 38 is preferably less than the thickness of the chip 2. The thickness of the upper insulating film 38 may be not less than 3 µm and not more than 35 µm. The thickness of the upper insulating film 38 is preferably not more than 25 µm.

The upper insulating film 38 has a laminated structure including, in this embodiment, an inorganic insulating film 42 and an organic insulating film 43 laminated in this order from the chip 2 side. The upper insulating film 38 may include at least one of the inorganic insulating film 42 and the organic insulating film 43, and may not necessarily include the inorganic insulating film 42 and the organic insulating film 43 at the same time. The inorganic insulating film 42 selectively covers the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A, 36B, and the source wiring 37, and defines a part of the gate opening 39, a part of the source opening 40, and a part of the dicing line 41.

The inorganic insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. Preferably, the inorganic insulating film 42 includes an insulating material different from that of the interlayer insulating film 27. The inorganic insulating film 42 preferably includes the silicon nitride film. Preferably, the inorganic insulating film 42 has a thickness smaller than the thickness of the interlayer insulating film 27. The thickness of the inorganic insulating film 42 may be not less than 0.1 µm and not more than 5 µm.

The organic insulating film 43 selectively covers the inorganic insulating film 42 and defines a part of the gate opening 39, a part of the source opening 40, and a part of the dicing street 41. Specifically, the organic insulating film 43 partially exposes the inorganic insulating film 42 in a wall surface of the gate opening 39. In addition, the organic insulating film 43 partially exposes the inorganic insulating film 42 in a wall surface of the source opening 40. In addition, the organic insulating film 43 partially exposes the inorganic insulating film 42 in a wall surface of the dicing street 41.

Of course, the organic insulating film 43 may cover the inorganic insulating film 42 such that the inorganic insulating film 42 is not exposed from the wall surface of the gate opening 39. The organic insulating film 43 may cover the inorganic insulating film 42 such that the inorganic insulating film 42 is not exposed from the wall surface of the source opening 40. The organic insulating film 43 may cover the inorganic insulating film 42 such that the inorganic insulating film 42 is not exposed from the wall surface of the dicing line 41. In these cases, the organic insulating film 43 may cover an entire area of the inorganic insulating film 42.

The organic insulating film 43 is preferably composed of a resin film other than a thermosetting resin. The organic insulating film 43 may be composed of a translucent resin or a transparent resin. The organic insulating film 43 may be composed of a negative type photosensitive resin film or a positive type photosensitive resin film. The organic insulating film 43 is preferably composed of a polyimide film, a polyamide film or a polybenzoxazole film. The organic insulating film 43 includes the polybenzoxazole film in this embodiment.

The organic insulating film 43 preferably has a thickness that exceeds the thickness of the inorganic insulating film 42. The thickness of the organic insulating film 43 preferably exceeds the thickness of the interlayer insulating film 27. More preferably, the thickness of the organic insulating film 43 exceeds the thickness of the gate electrode 30 and the thickness of the source electrode 32. The thickness of the organic insulating film 43 may be not less than 3 µm and not more than 30 µm. The thickness of the organic insulating film 43 is preferably not more than 20 µm.

The semiconductor device 1A includes a gate terminal electrode 50 disposed on the gate electrode 30. The gate terminal electrode 50 is erected in a columnar manner on a portion of the gate electrode 30 exposed from the gate opening 39. The gate terminal electrode 50 has a smaller area than the area of the gate electrode 30 in plan view and is disposed at the inner portion of the gate electrode 30 at a distance from the peripheral edge of the gate electrode 30.

The gate terminal electrode 50 has a gate terminal surface 51 and a gate terminal side wall 52. The gate terminal surface 51 extends flat along the first main surface 3. The gate terminal surface 51 may be composed of a ground surface with grinding marks. The gate terminal side wall 52 is located on the upper insulating film 38 (in particular the organic insulating film 43) in this embodiment.

That is, the gate terminal electrode 50 has a portion in contact with the inorganic insulating film 42 and the organic insulating film 43. The gate terminal side wall 52 extends substantially vertically to the normal direction 2. Here, "substantially vertically" includes a mode that extends in the laminate direction while being curved (meandering). The gate terminal side wall 52 includes a portion facing the gate electrode 30 with the upper insulating film 38 interposed therebetween. The gate terminal side wall 52 is preferably composed of a smooth surface without a grinding mark.

The gate terminal electrode 50 has a first protruding portion 53 protruding outward at a lower end portion of the gate terminal side wall 52. The first protruding portion 53 is formed in a region on the side of the upper insulating film 38 (the organic insulating film 43) as an intermediate portion of the gate terminal side wall 52. The first protruding portion 53 extends along an outer surface of the upper insulating film 38 and is formed in a tapered shape in which a thickness gradually decreases in cross-sectional view from the gate terminal side wall 52 toward the tip portion. The first protruding portion 53 therefore has a sharp-edged tip portion having an acute angle. Of course, the gate terminal electrode 50 may be formed without the first protruding portion 53.

The gate terminal electrode 50 preferably has a thickness that exceeds the thickness of the gate electrode 30. The thickness of the gate terminal electrode 50 is defined by a distance between the gate electrode 30 and the gate terminal surface 51. More preferably, the thickness of the gate terminal electrode 50 exceeds the thickness of the upper insulating film 38. The thickness of the gate terminal electrode 50 in this embodiment exceeds the thickness of the chip 2. Of course, the thickness of the gate terminal electrode 50 may be less than the thickness of the chip 2. The thickness of the gate terminal electrode 50 may be not less than 10 µm and not more than 300 µm. The thickness of the gate terminal electrode 50 is preferably not less than 30 µm. More preferably, the thickness of the gate terminal electrode 50 is not less than 80 µm and not more than 200 µm.

A planar area of the gate terminal electrode 50 is to be set according to the planar area of the first main surface 3. The planar area of the gate terminal electrode 50 is defined by a planar area of the gate terminal surface 51. The planar area of the gate terminal electrode 50 is preferably not more than 25% of the first main surface 3. The planar area of the gate terminal electrode 50 may be not more than 10% of the first main surface 3.

When the first main surface 3 has the planar area of not less than 1 mm ² , the planar area of the gate terminal electrode 50 may be not less than 0.4 mm ² . The gate terminal electrode 50 may have a polygonal shape (for example, a rectangular shape) having a planar area of not less than 0.4 mm × 0.7 mm. The gate terminal electrode 50 in this embodiment is formed as a polygonal shape (quadrangular shape with four corners cut out in a rectangular shape) having four sides in plan view that are parallel to the first to fourth side surfaces 5A to 5D. Of course, the gate terminal electrode 50 may be formed as a quadrangular shape in plan view, a polygonal shape other than the four square shape, a circular shape or an elliptical shape.

The gate terminal electrode 50 has a laminated structure including, in this embodiment, a first gate conductor film 55 and a second gate conductor film 56 laminated in this order from the gate electrode 30 side. The first gate conductor film 55 may include a Ti-based metal film. The first gate conductor film 55 may have a single-layer structure composed of a Ti film or a TiN film. The first gate conductor film 55 may have a laminated structure including the Ti film and the TiN film laminated in any order.

The first gate conductor film 55 has a thickness smaller than the thickness of the gate electrode 30. The first gate conductor film 55 covers the gate electrode 30 in the form of a film within the gate opening 39 and is extended in the form of a film onto the upper insulating film 38. The first gate conductor film 55 forms a part of the first protrusion portion 53. The first gate conductor film 55 does not necessarily have to be formed and may be omitted.

The second gate conductor film 56 forms a body of the gate terminal electrode 50. The second gate conductor film 56 may include a Cu-based metal film. The Cu-based metal film may be a pure Cu film (Cu film with a purity of not less than 99%) or a Cu alloy film. The second gate conductor film 56 includes a pure Cu plating film in this embodiment. The second gate conductor film 56 preferably has a thickness that exceeds the thickness of the gate electrode 30. More preferably, the thickness of the second gate conductor film 56 exceeds the thickness of the upper insulating film 38. The thickness of the second gate conductor film 56 exceeds the thickness of the chip 2 in this embodiment.

The second gate conductor film 56 covers the gate electrode 30 with the first gate conductor film 55 interposed therebetween within the gate opening 39 and is led out onto the upper insulating film 38 with the first gate conductor film 55 interposed therebetween. The second gate conductor film 56 forms a part of the first protrusion portion 53. That is, the first protrusion portion 53 has a laminated structure including the first gate conductor film 55 and the second gate conductor film 56. The second gate conductor film 56 preferably has a thickness exceeding the thickness of the first gate conductor film 55 in the first protrusion portion 53.

The semiconductor device 1A includes a source terminal electrode 60 disposed on the source electrode 32. The source terminal electrode 60 is erected in a columnar manner on a portion of the source electrode 32 exposed from the source opening 40. The source terminal electrode 60 may have a smaller area than the area of the source electrode 32 in plan view and may be disposed at an inner portion of the source electrode 32 at a distance from the peripheral edge of the source electrode 32.

The source terminal electrode 60 in this embodiment is arranged on the body electrode portion 33 of the source electrode 32 and is not arranged on the drawer electrode portions 34A, 34B of the source electrode 32. This reduces an opposing area between the gate terminal electrode 50 and the source terminal electrode 60. Such a structure effectively reduces the risk of a short circuit between the gate terminal electrode 50 and the source terminal electrode 60 in a case where conductive adhesives such as solders and metal pastes are to be adhered to the gate terminal electrode 50 and the source terminal electrode 60. Of course, conductive bonding members such as circuit boards or lead wires (for example, bonding wires) may be connected to the gate terminal electrode 50 and the source terminal electrode 60. In this case, a risk of a short circuit between the conductive bonding member on the gate terminal electrode 50 side and the conductive bonding member on the source terminal electrode 60 side can be reduced.

The source terminal electrode 60 has a source terminal surface 61 and a source terminal side wall 62. The source terminal surface 61 extends flat along the first main surface 3. The source terminal surface 61 can be composed of a ground surface with grinding marks. The source terminal side wall 62 is located on the upper insulating film 38 (in particular the organic insulating film 43) in this embodiment.

That is, the source terminal electrode 60 has a portion that is in contact with the inorganic insulating film 42 and the organic insulating film 43. The source terminal side wall 62 extends substantially vertically to the normal direction Z. Here, “substantially vertically” includes a mode that extends in the laminate direction while being curved (meandering). The source terminal side wall 62 includes a portion that is directed to the source electrode 32. with the upper insulating film 38 disposed therebetween. The source terminal side wall 62 is preferably composed of a smooth surface without a grinding mark.

The source terminal electrode 60 has a second protruding portion 63 protruding outward at a lower end portion of the source terminal side wall 62. The second protruding portion 63 is formed in a region on the side of the upper insulating film 38 (the organic insulating film 43) as an intermediate portion of the source terminal side wall 62. The second protruding portion 63 extends along the outer surface of the upper insulating film 38 and is formed in a tapered shape in which a thickness gradually decreases in cross-sectional view from the source terminal side wall 62 toward the tip portion. The second protruding portion 63 therefore has a sharp-edged tip portion having an acute angle. Of course, the source terminal electrode 60 may be formed without the second protruding portion 63.

The source terminal electrode 60 preferably has a thickness that exceeds the thickness of the source electrode 32. The thickness of the source terminal electrode 60 is defined by a distance between the source electrode 32 and the source terminal surface 61. More preferably, the thickness of the source terminal electrode 60 exceeds the thickness of the upper insulating film 38. The thickness of the source terminal electrode 60 exceeds the thickness of the chip 2 in this embodiment.

Of course, the thickness of the source terminal electrode 60 may be less than the thickness of the chip 2. The thickness of the source terminal electrode 60 may be not less than 10 µm and not more than 300 µm. The thickness of the source terminal electrode 60 is preferably not less than 30 µm. More preferably, the thickness of the source terminal electrode 60 is not less than 80 µm and not more than 200 µm. The thickness of the source terminal electrode 60 is substantially equal to the thickness of the gate terminal electrode 50.

A planar area of the source terminal electrode 60 is to be set according to the planar area of the first main surface 3. The planar area of the source terminal electrode 60 is defined by a planar area of the source terminal surface 61. Preferably, the planar area of the source terminal electrode 60 exceeds the planar area of the source terminal surface 50. The planar area of the source terminal electrode 60 is preferably not less than 50% of the first main surface 3. More preferably, the planar area of the source terminal electrode 60 is not less than 75% of the first main surface 3.

In a case where the first main surface 3 has a planar area of not less than 1 mm ² , the planar area of the source terminal electrode 60 is preferably not less than 0.8 mm ² . In this case, the planar area of each source terminal electrode 60 is particularly preferably not less than 1 mm ² . The source terminal electrode 60 may be formed in a polygonal shape and have a planar area of not less than 1 mm × 1.4 mm. In this embodiment, the source terminal electrode 60 is formed in a quadrangular shape and has four sides in plan view that are parallel to the first to fourth side surfaces 5A to 5D. Of course, the source terminal electrode 60 may be formed in a polygonal shape other than the quadrangular shape, a circular shape, or an elliptical shape in plan view.

The source terminal electrode 60 has a laminated structure including, in this embodiment, a first source conductor film 67 and a second source conductor film 68 laminated in this order from the source electrode 32 side. The first source conductor film 67 may include a Ti-based metal film. The first source conductor film 67 may have a single-layer structure composed of a Ti film or a TiN film. The first source conductor film 67 may have a laminated structure including the Ti film and the TiN film in any order. The first source conductor film 67 is preferably composed of the same conductive material as the first gate conductor film 55.

The first source conductor film 67 has a thickness smaller than the thickness of the source electrode 32. The first source conductor film 67 covers the source electrode 32 in the form of a film within the source opening 40 and is extended in the form of a film onto the upper insulating film 38. The first source conductor film 67 forms a part of the second protrusion portion 63. The thickness of the first source conductor film 67 is substantially equal to the thickness of the first gate conductor film 55. The first source conductor film 67 does not necessarily have to be formed and may be omitted.

The second source conductor film 68 forms a body of the source terminal electrode 60. The second source conductor film 68 may include a Cu-based metal film. The Cu-based metal film may be a pure Cu film (Cu film with a purity of not less than 99%) or a Cu alloy film. The second source conductor film 68 includes a pure Cu plating film in this embodiment. The second source conductor film 68 is preferably composed of the same conductive material as the second gate conductor film 56.

The second source conductor film 68 preferably has a thickness that exceeds the thickness of the source electrode 32. More preferably, the thickness of the second source conductor film 68 exceeds the thickness of the upper insulating film 38. The thickness of the second source conductor film 68 exceeds the thickness of the chip 2 in this embodiment. The thickness of the second source conductor film 68 is substantially equal to the thickness of the second gate conductor film 56.

The second source conductor film 68 covers the source electrode 32 with the first source conductor film 67 interposed therebetween within the source opening 40 and is led out onto the upper insulating film 38 with the first source conductor film 67 interposed therebetween. The second source conductor film 68 forms a part of the second protrusion portion 63. That is, the second protrusion portion 63 has a laminated structure including the first source conductor film 67 and the second source conductor film 68. The second source conductor film 68 preferably has a thickness exceeding the thickness of the first source conductor film 67 in the second protrusion portion 63.

The semiconductor device 1A includes a sealing insulator 71 covering the first main surface 3. The sealing insulator 71 covers a periphery of the gate terminal electrode 50 and a periphery of the source terminal electrode 60 such that a part of the gate terminal electrode 50 and a part of the source terminal electrode 60 are exposed on the first main surface 3. Specifically, the sealing insulator 71 covers the active surface 8, the outer surface 9, and the first to fourth connection surfaces 10A to 10D such that the gate terminal electrode 50 and the source terminal electrode 60 are exposed.

The sealing insulator 71 exposes the gate terminal surface 51 and the source terminal surface 61, and covers the gate terminal side wall 52 and the source terminal side wall 62. In this embodiment, the sealing insulator 71 covers the first protrusion portion 53 of the gate terminal electrode 50 and faces the upper insulating film 38 with the first protrusion portion 53 interposed therebetween. The sealing insulator 71 prevents the gate terminal electrode 50 from falling off. Also, in this embodiment, the sealing insulator 71 covers the second protrusion portion 63 of the source terminal electrode 60 and faces the upper insulating film 38 with the second protrusion portion 63 interposed therebetween. The sealing insulator 71 prevents the source terminal electrode 60 from falling off.

The sealing insulator 71 covers the dicing line 41 at the peripheral edge portion of the outer surface 9. The sealing insulator 71 directly covers the interlayer insulating film 27 on the dicing line 41 in this embodiment. Of course, when the chip 2 (the outer surface 9) or the main surface insulating film 25 is exposed from the dicing line 41, the sealing insulator 71 may directly cover the chip 2 or the main surface insulating film 25 on the dicing line 41.

The sealing insulator 71 has an insulating main surface 72 and an insulating side wall 73. The insulating main surface 72 extends flat along the first main surface 3. The insulating main surface 72 forms a single flat surface with the gate connection surface 51 and the source connection surface 61. The insulating main surface 72 may be composed of a ground surface with grinding marks. In this case, the insulating main surface 72 preferably forms a single ground surface with the gate connection surface 51 and the source connection surface 61.

The insulating side wall 73 extends from a peripheral edge of the insulating main surface 72 toward the chip 2 and forms a single flat surface with the first to fourth side surfaces 5A to 5D. The insulating side wall 73 is formed substantially perpendicular to the insulating main surface 72. The angle that the insulating side wall 73 forms with the insulating main surface 72 may be not less than 88° and not more than 92°. The insulating side wall 73 may be composed of a ground surface having grinding marks. The insulating side wall 73 may form a single ground surface with the first to fourth side surfaces 5A to 5D.

The sealing insulator 71 preferably has a thickness that exceeds the thickness of the gate electrode 30 and the thickness of the source electrode 32. More preferably, the thickness of the sealing insulator 71 exceeds the thickness of the upper insulating film 38. The thickness of the sealing insulator 71 in this embodiment exceeds the thickness of the chip 2. Of course, the thickness of the sealing insulator 71 may be less than the thickness of the chip 2. The thickness of the sealing insulator 71 may be not less than 10 µm and not more than 300 µm. The thickness of the sealing insulator 71 is preferably not less than 30 µm. More preferably the thickness of the sealing insulator 71 is not less than 80 µm and not more than 200 µm. The thickness of the sealing insulator 71 is substantially equal to the thickness of the gate terminal electrode 50 and the thickness of the source terminal electrode 60.

Regarding 2 and 5 the sealing insulator 71 includes a first matrix resin 74, a plurality of fillers 75 and a plurality of first flexible particles 76 (flexible agent). In 5 the plurality of first flexible particles 76 are each indicated by a thick circle. The sealing insulator 71 is configured such that a mechanical strength is adjusted by the first matrix resin 74, the plurality of fillers 75, and the plurality of first flexible particles 76.

The sealing insulator 71 may include a coloring material such as carbon black that colors the first matrix resin 74. The first matrix resin 74 is preferably composed of a thermosetting resin. The first matrix resin 74 may include at least one of an epoxy resin, a phenolic resin, and a polyimide resin as an example of the thermosetting resin. The first matrix resin 74 includes the epoxy resin in this embodiment.

The plurality of first fillers 75 are added to the first matrix resin 74 and are composed of one or both of spherical objects each composed of an insulator and indeterminate objects each composed of an insulator. The indeterminate object has a random shape other than a spherical shape, for example, a grain shape, a piece shape, or a fragment shape. The indeterminate object may have an edge. In accordance with an aspect of suppressing damage by filler attack, in this embodiment, the plurality of first fillers 75 are each composed of the spherical object.

The plurality of first fillers 75 may include at least one of ceramics, oxides and nitrides. The plurality of first fillers 75 in this embodiment are each composed of silicon oxide particles (silicon particles). The plurality of first fillers 75 may each have a particle size of not less than 1 nm and not more than 100 μm. The particle sizes of the plurality of first fillers 75 are preferably not more than 50 μm.

The sealing insulator 71 preferably includes the plurality of first fillers 75 having different particle sizes. The plurality of first fillers 75 may include a plurality of small-sized first fillers 75a, a plurality of medium-sized first fillers 75b, and a plurality of large-sized first fillers 75c. The plurality of fillers 75 are preferably added to the first matrix resin 74 in a content (density) that is, in this order, the small-sized first filler 75a, the medium-sized first filler 75b, and the large-sized first filler 75c.

The small-sized first fillers 75a may have a thickness that is less than the thickness of the source electrode 32 (the gate electrode 30). The particle sizes of the small-sized first fillers 75a may be not less than 1 nm and not more than 1 μm. The medium-sized fillers 75b may have a thickness that exceeds the thickness of the source electrode 32 and is not more than the thickness of the upper insulating film 38. The particle sizes of the medium-sized first fillers 75b may be not less than 1 μm and not more than 20 μm.

The first large-size fillers 75c may have a thickness exceeding the thickness of the upper insulating film 38. The plurality of first fillers 75 may include at least one large-size filler exceeding any of the thickness of the first semiconductor region 6 (the epitaxial layer), the thickness of the second semiconductor region 7 (the substrate), and the thickness of the chip 2. The particle sizes of the first large-size fillers 75c may be not less than 20 μm and not more than 100 μm. The particle sizes of the first large-size fillers 75c are preferably not more than 50 μm.

An average particle size of the plurality of first fillers 75 may be not less than 1 μm and not more than 10 μm. The average particle size of the plurality of first fillers 75 is preferably not less than 4 μm and not more than 8 μm. Of course, the plurality of first fillers 75 does not necessarily have to include all of the small-size first fillers 75a, the medium-size first fillers 75b, and the large-size first fillers 75c at the same time, and may also be composed of one or both of the small-size first fillers 75a and the medium-size first fillers 75b. For example, in this case, a maximum particle size of the plurality of first fillers 75 (the medium-size first fillers 75b) may be not more than 10 μm.

The sealing insulator 71 may include a plurality of filler fragments 75d each having a broken particle shape in a surface layer portion of the insulating main surface 72 and in a surface layer portion of the insulating side wall 73. The plurality of filler fragments 75d fragments 75d may each be formed from any one of a portion of the small size first fillers 75a, a portion of the medium size first fillers 75b, or a portion of the large size first fillers 75c.

The plurality of filler fragments 75d positioned on the insulating main surface 72 side each have a broken portion formed along the insulating main surface 72 so as to face the insulating main surface 72. The plurality of filler fragments 75d positioned on the insulating side wall 73 side each have a broken portion formed along the insulating side wall 73 so as to face the insulating side wall 73. The broken portions of the plurality of filler fragments 75d may be exposed from the insulating main surface 72 and the insulating side wall 73, or may be partially or completely covered with the first matrix resin 74. The plurality of filler fragments 75d do not affect the structures on the side of the chip 2 because the plurality of filler fragments 75d are located in the surface layer portions of the insulating main surface 72 and the insulating side wall 73.

The plurality of first fillers 75 are added to the first matrix resin 74 such that a ratio of a first total cross-sectional area to a unit cross-sectional area is higher than a ratio of a cross-sectional area of the first matrix resin 74 to the unit cross-sectional area. That is, a first filler density of the plurality of first fillers 75 occupying the sealing insulator 71 is higher than a first resin density of the first matrix resin 74 occupying the sealing insulator 71.

Specifically, the plurality of first fillers 75 are added to the matrix resin 74 such that a ratio of a total cross-sectional area to a unit cross-sectional area is not less than 60% and not more than 95%. In other words, the plurality of first fillers 75 are added to the first matrix resin 74 in a proportion of not less than 60% by weight and not more than 95% by weight. A first total cross-sectional area (first filler density) of the plurality of first fillers 75 is preferably not less than 75% and not more than 90%. More preferably, the first total cross-sectional area (first filler density) of the plurality of first fillers 75 is not less than 80%.

When a first cross-sectional area of a random first measurement region extracted from a cross section where the sealing insulator 71 is exposed is 1, the ratio of the first total cross-sectional area of the plurality of first fillers 75 is the ratio of the first total cross-sectional area of the plurality of first fillers 75 included in the measurement region. As the first measurement region, a region including the plurality of first fillers 75 is selected. For example, the first measurement region with the first fillers 75 of not less than 10 and not more than 100 can be selected.

The first measurement range may include at least one of the small size fillers 75a, the medium size fillers 75b, and the large size fillers 75c, but may not necessarily include all of the small size fillers 75a, the medium size fillers 75b, and the large size fillers 75c. Of course, the first total cross-sectional area of the plurality of first fillers 75 may be obtained from the first measurement range including at least two types of the small fillers 75a, the medium size fillers 75b, and the large fillers 75c. Alternatively, the first total cross-sectional area of the plurality of first fillers 75 may be obtained from the first measurement range including all of the small fillers 75a, the medium size fillers 75b, and the large fillers 75c.

The cross-sectional area of the first measuring region is set to a random value according to the thickness of the sealing insulator 71. For example, the cross-sectional area of the first measuring region can be set in a range from not less than 1 µm squared or 1 µm ² to not more than 100 µm squared (= not less than 25 or 1 µm ² and not more than 10000 µm ² ). For example, the cross-sectional area of a measurement region may be in any of the ranges of not less than 1 µm square and not more than 5 µm square, not less than 5 µm square and not more than 10 µm square, not less than 10 µm square and not more than 20 µm square, not less than 20 µm square and not more than 30 µm square, not less than 30 µm square and not more than 40 µm square, not less than 40 µm square and not more than 50 µm square, not less than 40 µm square and not more than 50 µm square, not less than 50 µm square and not more than 60 µm square, not less than 60 µm square and not more than 70 µm square, not less than 70 µm square and not more than 80 µm square, not less than 80 µm square and not more than 90 µm square, and not less than 90 µm square and not more than 100 µm square.

For example, when the first measurement range of 10 µm squared (= 100 pm ² ) is extracted, the first total cross-sectional area of the plurality of first fillers 75 is not less than 60 µm ² and not more than 95 µm ² . The ratio of the first total cross-sectional area of the plurality of first fillers 75 calculated in this way can be converted into a ratio per 1 mm ² , a ratio per 100 µm ² , a ratio per 10 µm ² , etc.

Of course, the ratio of the first total cross-sectional area of the plurality of first fillers 75 can be calculated from an average of the ratios of a plurality of first total cross-sectional areas obtained from a plurality of first measurement areas. In a region other than the region where the plurality of first fillers 75 are exposed in the first measurement region, the first matrix resin 74 and the plurality of first flexible particles 76 are exposed.

The plurality of first flexible particles 76 are added to the first matrix resin 74. The plurality of first flexible particles 76 may include at least one of silicone-based first flexible particles 76, acrylic-based first flexible particles 76, and butadiene-based first flexible particles 76. The sealing insulator 71 preferably includes the silicone-based first flexible particles 76. The plurality of first flexible particles 76 preferably have an average particle size that is smaller than the average particle size of the plurality of first fillers 75. The average particle size of the plurality of first flexible particles 76 is preferably not less than 1 nm and not more than 1 μm. A maximum particle size of the plurality of first flexible particles 76 is preferably not more than 1 μm.

The plurality of first flexible particles 76 are added to the first matrix resin 74 such that a ratio of a total cross-sectional area to a unit cross-sectional area is not less than 0.1% and not more than 10%. In other words, the plurality of first flexible particles 76 are added to the first matrix resin 74 in a content ranging from not less than 0.1% by weight to not more than 10% by weight. The average particle size and the content of the plurality of first flexible particles 76 are to be appropriately set according to an elastic modulus to be imparted to the sealing insulator 71 at the time of manufacturing and/or after manufacturing. For example, by making the plurality of first flexible particles 76 have an average particle size in the submicrometer range (= not more than 1 μm), it is possible to contribute to a low elastic modulus and a small curing shrinkage of the sealing insulator 71.

The semiconductor device 1A includes a drain electrode 77 (second main surface electrode) covering the second main surface 4. The drain electrode 77 is electrically connected to the second main surface 4. The drain electrode 77 forms an ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The drain electrode 77 may cover an entire region of the second main surface 4 so as to be continuous with the peripheral edge of the chip 2 (the first to fourth side surfaces 5A to 5D).

The drain electrode 77 may cover the second main surface 4 at a distance from the peripheral edge of the chip 2. The drain electrode 77 is configured such that a drain-source voltage of not less than 500 V and not more than 3000 V is to be applied between the source terminal electrode 60 and the drain electrode 77. That is, the chip 2 is configured such that a voltage of not less than 500 V and not more than 3000 V is to be applied between the first main surface 3 and the second main surface 4.

As described above, the semiconductor device 1A includes the chip 2, the gate electrode 30 (the source electrode 32: main surface electrode), the gate terminal electrode 50 (the source terminal electrode 60), and the sealing insulator 71. The chip 2 has the first main surface 3. The gate electrode 30 (the source electrode 32) is arranged on the first main surface 3. For example, the gate terminal electrode 50 (the source terminal electrode 60) is arranged on the gate electrode 30 (the source electrode 32). The sealing insulator 71 covers the periphery of the gate terminal electrode 50 (the source terminal electrode 60) on the first main surface 3 so that the gate terminal electrode 50 (the source terminal electrode 60) is exposed. The sealing insulator 71 includes the first matrix resin 74 and the plurality of first fillers 75.

According to this structure, a strength of the sealing insulator 71 can be adjusted by the first matrix resin 74 and the plurality of first fillers 75. Also according to this structure, an object to be sealed can be protected from external forces and moisture (dampness) by the sealing insulator 71. That is, the object to be sealed can be protected from damage (including peeling) due to external forces and deterioration (including corrosion). due to moisture. In this way, it is possible to avoid shape defects and variations in electrical characteristics. As a result, it is possible to provide the semiconductor device 1A that can improve reliability.

The plurality of first fillers 75 are preferably added to the first matrix resin 74 such that the ratio of the first total cross-sectional area to the unit cross-sectional area is higher than the ratio of the cross-sectional area of the first matrix resin 74 to the unit cross-sectional area. According to this structure, the sealing insulator 71 can have increased mechanical strength, and the chip 2 can have less deformation and/or variation in electrical characteristics due to the stress from the sealing insulator 71. Also, according to such a structure, the sealing insulator 71 can be subjected to less stress and can thereby be formed with a relatively large thickness. That is, it is possible to protect the sealing target while causing the chip 2 to have less deformation and/or variation in electrical characteristics due to the stress from the sealing insulator 71.

The plurality of first fillers 75 are preferably added to the first matrix resin 74 so that the ratio of the total cross-sectional area to the unit cross-sectional area is not less than 60%. According to this structure, the mechanical strength of the sealing insulator 71 can be adequately increased. The first total cross-sectional area is preferably not more than 95%. The plurality of first fillers 75 may each be composed of the spherical object and/or an indefinite object. The plurality of first fillers 75 are each preferably composed of the spherical object. The sealing insulator 71 preferably includes the plurality of first fillers 75 having different particle sizes.

The semiconductor device 1A preferably includes the upper insulating film 38 partially covering the gate electrode 30 (the source electrode 32). According to this structure, an object to be sealed can be protected from external forces and moisture with the upper insulating film 38. That is, according to this structure, the object to be sealed can be protected by both the upper insulating film 38 and the sealing insulator 71.

In such a structure, the sealing insulator 71 preferably has the portion that directly covers the upper insulating film 38. The sealing insulator 71 preferably has the portion that covers the gate electrode 30 (the source electrode 32) via the upper insulating film 38 interposed therebetween. The gate terminal electrode 50 (the source terminal electrode 60) preferably has the portion that directly covers the upper insulating film 38. The upper insulating film 38 preferably includes one or both of the inorganic insulating film 42 and the organic insulating film 43. The organic insulating film 43 is preferably composed of the photosensitive resin film.

The upper insulating film 38 is preferably thicker than the gate electrode 30 (the source electrode 32). The upper insulating film 38 is preferably thinner than the chip 2. The sealing insulator 71 is preferably thicker than the gate electrode 30 (the source electrode 32). The sealing insulator 71 is preferably thicker than the upper insulating film 38. More preferably, the sealing insulator 71 is thicker than the chip 2.

The sealing insulator 71 preferably exposes the gate terminal surface 51 (the source terminal surface 61) of the gate terminal electrode 50 (the source terminal electrode 60) and preferably covers the gate terminal sidewall 52 (the source terminal sidewall 62). That is, the sealing insulator 71 preferably protects the gate terminal electrode 50 (the source terminal electrode 60) from the gate terminal sidewall 52 (the source terminal sidewall 62).

In this case, the sealing insulator 71 preferably has the insulating main surface 72 which forms the single flat surface with the gate terminal surface 51 (the source terminal surface 61). The sealing insulator 71 preferably has the insulating side wall 73 which forms the single flat surface with the first to fourth side surfaces 5A to 5D (side surface) of the chip 2. According to this structure, the object to be sealed which is positioned on the side of the first main surface 3 can be adequately protected with the sealing insulator 71.

The above structures are effective when the gate terminal electrode 50 (the source terminal electrode 60) having a relatively large planar area and/or a relatively large thickness is applied to the chip 2 having a relatively large planar area and/or a relatively small thickness. The gate terminal electrode 50 (the source terminal electrode 60) having the relatively large planar area and/or the relatively large thickness is also effective in absorbing heat generated on the chip 2 side and dissipating the heat to the outside.

For example, the gate terminal electrode 50 (the source terminal electrode 60) is preferably thicker than the gate electrode 30 (the source electrode 32). The gate terminal electrode 50 (the source terminal electrode 60) is preferably thicker than the upper insulating film 38. More preferably, the gate terminal electrode 50 (the source terminal electrode 60) is thicker than the chip 2. For example, the gate terminal electrode 50 may cover the area of not more than 25% of the first main surface 3 in plan view, and the source terminal electrode 60 may cover the area of not less than 50% of the first main surface 3 in plan view.

For example, the chip 2 may have the first main surface 3 having an area of not less than 1 mm ² in plan view. The chip 2 may have the thickness of not more than 100 µm in cross-sectional view. The chip 2 preferably has the thickness of not more than 50 µm in cross-sectional view. The chip 2 may have the laminated structure including the semiconductor substrate and the epitaxial layer. In this case, the epitaxial layer is preferably thicker than the semiconductor substrate.

In the above structures, the chip 2 preferably includes the single crystal of the wide band gap semiconductor. The single crystal of the wide band gap semiconductor is effective in improving the electrical characteristics. In addition, according to the single crystal of the wide band gap semiconductor, it is possible to achieve thinning of the chip 2 and increasing the planar area of the chip 2 while suppressing deformation of the chip 2 with a relatively high hardness. Thinning of the chip 2 and increasing the planar area of the chip 2 are also effective in improving the electrical characteristics.

The structure having the sealing insulator 71 is also effective in a structure including the drain electrode 77 covering the second main surface 4 of the chip 2. The drain electrode 77 forms a potential difference (for example, not less than 500 V and not more than 3000 V) with the source electrode 32 across the chip 2. Particularly, in a case where the chip 2 is relatively thin, since a distance between the source electrode 32 and the drain electrode 77 is shortened, the risk of a discharge phenomenon between the peripheral edge of the first main surface 3 and the source electrode 32 increases. In this point, according to the structure having the sealing insulator 71, an insulating property between the peripheral edge of the first main surface 3 and the source electrode 32 can be improved, and thus the discharge phenomenon can be suppressed.

8th is a plan view showing a semiconductor package 201A in which the semiconductor device 1A of 1 should be installed. 9 is a cross-sectional view along the 8th shown line IX-IX. 10A is an enlarged cross-sectional view showing a first configuration example of a region X formed in 9 shown. The semiconductor package 201A may be referred to as a “semiconductor module.”

Regarding 8 to 10A the semiconductor package 201A includes a metal plate 202. The metal plate 202 has a first plate surface 203 on one side, a second plate surface 204 on the other side, and first to fourth plate side surfaces 205A to 205D connecting the first plate surface 203 and the second plate surface 204. The first plate side surface 205A and the second plate side surface 205B extend in the first direction X and face each other in the second direction Y. The third plate side surface 205C and the fourth plate side surface 205D extend in the second direction Y and face each other in the first direction X.

The metal plate 202 in this embodiment integrally includes a die pad 206 and a heat spreader 207. The die pad 206 is positioned on one side in the first direction X (on the second plate side surface 205B), while the heat spreader 207 is positioned on the other side in the first direction X (on the first plate side surface 205A). The die pad 206 is formed in a four-sided shape in plan view. A portion of the first plate surface 203 formed by the die pad 206 is formed as a placement surface for the semiconductor device 1A.

The heat spreader 207 is formed as a drawer portion that is drawn out from the die pad 206. The heat spreader 207 is drawn out from the die pad 206 in a four-sided shape (more precisely, in a polygonal shape with corner portions notched out) in plan view. The heat spreader 207 has a through hole 208 that is circular in plan view.

The thickness of the metal plate 202 preferably exceeds the thickness of the chip 2. More preferably, the thickness of the metal plate 202 exceeds the thickness of the sealing insulator 71. Most preferably, the thickness of the metal plate 202 exceeds the total thickness of the thickness of the chip 2 and the sealing insulator 71. insulator 71 (ie, the thickness of the semiconductor device 1A).

The semiconductor package 201A includes a plurality (three in this embodiment) of lead terminals 209. The plurality of lead terminals 209 are arranged on the second side wall 205B side. The plurality of lead terminals 209 are each formed in a band shape extending in the orthogonal direction to the second side wall 205B (i.e., the second direction Y). The lead terminals 209 on both sides of the plurality of lead terminals 209 are arranged at intervals from the die pad 206, and the lead terminals 209 at a center are formed integrally with the die pad 206. An arrangement of the lead terminals 209 to be connected to the metal plate 202 is arbitrary.

The semiconductor package 201A encloses the semiconductor device 1A disposed on the first plate surface of the die pad 206. The semiconductor device 1A is disposed on the die pad 206 in a position where the drain electrode 77 faces the die pad 206 and is electrically connected to the die pad 206.

The semiconductor package 201A includes a conductive adhesive 210 that is disposed between the drain electrode 77 and the die pad 206 and that electrically and mechanically connects the semiconductor device 1A to the die pad 206. The conductive adhesive 210 may include a solder or a metal paste. The solder may be a lead-free solder. The metal paste may include at least one of Au, Ag, and Cu. The Ag paste may be composed of an Ag sintering paste. The Ag sintering paste is composed of a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.

The semiconductor package 201A includes a plurality of lead wires 211 (conductive connection member) that electrically connect the semiconductor device 1A to the corresponding lead terminals 209. At least one lead wire 211 electrically connects the gate terminal electrode 50 to the inner portion of the corresponding lead terminal 209. At least one lead wire 211 electrically connects the source terminal electrode 60 to the inner portion of the corresponding lead terminal 209.

The lead wires 211 in this embodiment are each composed of a metal wire (i.e., a bonding wire). The lead wires 211 include at least one of a gold wire, a copper wire, and an aluminum wire. Of course, the lead wires 211 may each be composed of a metal plate 202 such as a metal bracket instead of the metal wire.

The semiconductor package 201A includes a substantially rectangular parallelepiped-shaped package body 212. The package body 212 seals the metal plate 202, the plurality of lead terminals 209, the semiconductor device 1A, the conductive adhesive 210, and the plurality of lead wires 211 so that the plurality of lead terminals 209 are partially exposed.

The case body 212 has a first surface 213 on one side, a second surface 214 on the other side, and first to fourth side walls 215A to 215D connecting the first surface 213 and the second surface 214. The first surface 213 is positioned on the first plate surface 203 side of the metal plate 202 and faces the first plate surface 203 with the plurality of lead wires 211 and the semiconductor device 1A interposed therebetween. The second surface 214 is positioned on the second plate surface 204 side of the metal plate 202.

The first side wall 215A is positioned on the first plate side surface 205A side of the metal plate 202 and extends along the first plate side surface 205A. The second side wall 215B is positioned on the second plate side surface 205B side of the metal plate 202 and extends along the second plate side surface 205B. The third side wall 215C is positioned on the third plate side surface 205C side of the metal plate 202 and extends along the third plate side surface 205C. The fourth side wall 215D is positioned on the fourth plate side surface 205D side of the metal plate 202 and extends along the fourth plate side surface 205D.

The sealing thickness of a portion of the package body 212 positioned between the first surface 213 and the sealing insulator 71 of the semiconductor device 1A preferably exceeds the thickness of the chip 2. More preferably, the sealing thickness exceeds the thickness of the sealing insulator 71. Most preferably, the sealing thickness exceeds the total thickness of the thickness of the chip 2 and the sealing insulator 71 (i.e., the thickness of the semiconductor device 1A).

The package body 212 has, for the structure on the side of the semiconductor device 1A, a portion that directly covers the first to fourth side surfaces 5A to 5D of the chip 2, a portion that covers the insulating main surface 72 of the sealing insulator 71, and a portion directly covering the insulating side wall 73 of the sealing insulator 71. The package body 212 covers the insulating main surface 72 and the insulating side wall 73 by filling the grinding marks of the insulating main surface 72 and the grinding marks of the insulating side wall 73. The package body 212 also has a portion directly covering a portion of the gate terminal surface 51 of the gate terminal electrode 50 exposed by the lead wires 211, and a portion directly covering a portion of the source terminal surface 61 of the source terminal electrode 60 exposed by the lead wires 211.

The package body 212 covers the die pad 206 of the metal plate 202 and exposes the heat spreader 207 (the through hole 208) of the metal plate 202 on the first side wall 215A side for the structure on the outside of the semiconductor device 1A. The package body 212 has a portion that directly covers the first plate surface 203 of the metal plate 202 and a portion that directly covers the first to fourth plate side surfaces 205A to 205D of the metal plate 202.

In this embodiment, the housing body 212 exposes the second plate surface 204 of the metal plate 202 through the second surface 214. The second surface 214 forms a single flat surface with the second plate surface 204 in this embodiment. Of course, the housing body 212 may cover part or all of the second plate surface 204. The housing body 212 may also cover the entire area of the metal plate 202.

The housing body 212 exposes the plurality of lead terminals 209 through the second side wall 215B. The housing body 212 covers inner end portions of the plurality of lead terminals 209 and exposes band portions and outer end portions of the plurality of lead terminals 209. The housing body 212 covers the entire area of the plurality of lead wires 211.

The housing body 212 in this embodiment includes a second matrix resin 216, a plurality of second fillers 217 and a plurality of second flexible particles 218 (flexible agent). In 10A the plurality of second flexible particles 218 are each shown by a thick circle. The case body 212 is configured so that its mechanical strength can be adjusted by the second matrix resin 216, the plurality of second fillers 217 and the plurality of second flexible particles 218.

The case body 212 may contain a colorant that colors the second matrix resin 216, such as carbon black. The second matrix resin 216 is preferably composed of a thermosetting resin. The second matrix resin 216 may include at least one of an epoxy resin, a phenol resin, and a polyimide resin as an example of the thermosetting resin. The second matrix resin 216 may include a thermosetting resin of the same type as that of the first matrix resin 74 of the sealing insulator 71 or of a different type than that. The second matrix resin 216 in this embodiment includes a thermosetting resin of the same type as the first matrix resin 74 (i.e., epoxy resin).

The plurality of second fillers 217 are each composed of an insulating spherical object and/or an insulating indeterminate object and are added to the second matrix resin 216. The indeterminate object has a random shape other than a sphere, for example, a grain shape, a piece shape, or a fragment shape. The indeterminate object may have an edge. Like the plurality of first fillers 75, in this embodiment, the plurality of second fillers 217 are each composed of the spherical object to prevent damage to the semiconductor device 1A (the chip 2, the gate terminal electrode 50, the source terminal electrode 60, the sealing insulator 71, etc.) by filler attack.

Of course, the plurality of first fillers 75 of the sealing insulator 71 may each be composed of the spherical object, while the plurality of second fillers 217 may each be composed of the indefinite object. In addition, the plurality of first fillers 75 may each be composed of the indefinite object, while the plurality of second fillers 217 may each be composed of the spherical object. In addition, the plurality of first fillers 75 may each be composed of the indefinite object, and the plurality of second fillers 217 may each be composed of the indefinite object.

The plurality of second fillers 217 may include at least one of ceramics, oxides and nitrides. The plurality of second fillers 217 may each include an insulator of the same type as the plurality of first fillers 75 or of a different type than the plurality of first fillers 75. The plurality of second fillers 217 in this embodiment is each composed of an insulator of the same type as the plurality of first fillers 75 (ie, a silicon oxide particle). The plurality of second fillers 217 may each have a particle size of not less than 1 nm and not more than 100 µm. The particle size of the plurality of second fillers 217 is preferably not more than 50 gm.

The case body 212 preferably includes the plurality of second fillers 217 having different particle sizes. The plurality of second fillers 217 may include a plurality of small-sized second fillers 217a, a plurality of medium-sized second fillers 217b, and a plurality of large-sized second fillers 217c. The plurality of second fillers 217 are preferably added to the second matrix resin 216 in a content (density) in the order of the small-sized second fillers 217a, the medium-sized second fillers 217b, and the large-sized second fillers 217c.

The second small-size fillers 217a may have a thickness that is less than the thickness of the source electrode 32 (the thickness of the gate electrode 30). The particle size of the second small-size fillers 217a may be not less than 1 nm and not more than 1 μm. The second medium-size fillers 217b may have a thickness that exceeds the thickness of the source electrode 32 and is not more than the thickness of the upper insulating film 38. The particle size of the second medium-size fillers 217b may be not less than 1 μm and not more than 20 μm.

The second large-size fillers 217c may have a thickness exceeding the thickness of the upper insulating film 38. The plurality of second fillers 217 may include at least one second large-size filler 217c that exceeds any of the thickness of the first semiconductor region 6 (the epitaxial layer), the thickness of the second semiconductor region 7 (the substrate), and the thickness of the chip 2. The particle size of the second large-size fillers 217c may be not less than 20 μm and not more than 100 μm. The particle size of the second large-size fillers 217c is preferably not more than 50 μm.

The plurality of second fillers 217 may include at least one second filler 217 (second large size filler 217c) that exceeds the thickness of the chip 2. The plurality of second fillers 217 may include at least one second filler 217 (second large size filler 217c) that has a thickness that exceeds the thickness of the chip 2 and is smaller than the thickness of the sealing insulator 71. The plurality of second fillers 217 may include at least one second filler 217 (second large size filler 217c) that exceeds the thickness of the sealing insulator 71.

The plurality of second fillers 217 may include at least one second filler 217 (second large-size filler 217c) that exceeds the total thickness of the thickness of the chip 2 and the thickness of the sealing insulator 71. Of course, in a case where the sealing insulator 71 is thinner than the chip 2, the plurality of second fillers 217 may include at least one second filler 217 (second large-size filler 217c) whose thickness exceeds the thickness of the sealing insulator 71 and is smaller than the thickness of the chip 2.

An average particle size of the plurality of second fillers 217 may be not smaller than the average particle size of the plurality of first fillers 75 or may be smaller than the average particle size of the plurality of first fillers 75. The average particle size of the plurality of second fillers 217 may be not less than 1 μm and not more than 20 μm. The average particle size of the plurality of second fillers 217 is preferably not less than 4 μm and not more than 16 μm. Of course, the plurality of second fillers 217 may not include all of the small-size second fillers 217a, the medium-size second fillers 217b, and the large-size second fillers 217c, and may also be composed of one or both of the small-size second fillers 217a and the medium-size second fillers 217b. For example, in this case, a maximum particle size of the plurality of second fillers 217 (the middle-sized second fillers 217b) may be not more than 10 μm.

The plurality of second fillers 217 are added to the second matrix resin 216 such that a ratio of a second total cross-sectional area to a unit cross-sectional area is higher than a ratio of the cross-sectional area of the second matrix resin 216 to the unit cross-sectional area. That is, a second filler density of the plurality of second fillers 217 occupying the case body 212 is higher than a second resin density of the second matrix resin 216 occupying the case body 212.

Specifically, the plurality of second fillers 217 are added to the second matrix resin 216 so that the ratio of the total cross-sectional area to the unit cross-sectional area is not less than 60% and not more than 95%. In other words, the plurality of second fillers 217 are added to the second matrix resin 216 in a content of not less than 60% by weight and not more than 95% by weight. The second total cross-sectional area (second filler density) of the plurality of second fillers 217 is preferably not more than 75% and not more than 95%.

The ratio of the second total cross-sectional area of the plurality of second fillers 217 is the ratio of the total cross-sectional area of the plurality of second fillers 217 included in any second measurement range extracted from the cross section through which the case body 212 is exposed when the cross-sectional area of the second measurement range is set to 1. A range including the plurality of second fillers 217 is selected as the second measurement range. For example, the second measurement range may be selected to include 10 or more and 100 or less second fillers 217.

The second measurement range does not necessarily include all of the second small fillers 217a, the second medium fillers 217b, and the second large fillers 217c, as long as it includes at least one type of the second small fillers 217a, the second medium fillers 217b, and the second large fillers 217c. Of course, the second total cross-sectional area of the plurality of second fillers 217 can be obtained from the second measurement range including at least two types of the second small fillers 217a, the second medium fillers 217b, and the second large fillers 217c. The total cross-sectional area of the plurality of second fillers 217 can also be obtained from the second measurement range including all of the small fillers 217a, the medium fillers 217b, and the large fillers 217c.

The cross-sectional area of the second measuring region is set to an arbitrary value depending on the thickness of the housing body 212. The cross-sectional area of the first measuring region can be set, for example, in a range from not less than 1 µm square to not more than 100 µm square (= not less than 25 µm ² and not more than 10000 µm ² ). The cross-sectional area of the first measuring region may be within any range of, for example, not less than 1 µm square and not more than 5 µm square, not less than 5 µm square and not more than 10 µm square, not less than 10 µm square and not more than 20 µm square, not less than 20 µm square and not more than 30 µm square, not less than 30 µm square and not more than 40 µm square, not less than 40 µm square and not more than 50 µm square, not less than 40 µm square and not more than 50 µm square, not less than 50 µm square and not more than 60 µm square, not less than 60 µm square and not more than 70 µm square. square, not less than 70 µm square and not more than 80 µm square, not less than 80 µm square and not more than 90 µm square, and not less than 90 µm square and not more than 100 µm square.

For example, in a case where the second measurement range of 10 µm squared (= 100 µm ² ) is extracted, the first total cross-sectional area of the plurality of first fillers 217 is not less than 80 µm ² and not more than 95 µm ² . The ratio of the total cross-sectional area of the plurality of second fillers 217 calculated in this way can be converted into a ratio per 1 mm ² , a ratio per 100 µm ² , a ratio per 10 µm ² , or the like.

The cross-sectional area of the second measurement region is preferably equal to the cross-sectional area of the first measurement region applied to the sealing insulator 71. Of course, the ratio of the second total cross-sectional area of the plurality of second fillers 217 can be calculated from an average value of the ratios of the plurality of total cross-sectional areas of the plurality of second measurement regions. In a region of the second measurement region other than the region where the plurality of second fillers 217 are exposed, the second matrix resin 216 and the plurality of second flexible particles 218 are exposed.

The plurality of second fillers 217 are added to the second matrix resin 216 to have a second total cross-sectional area which, in this embodiment, differs from the first total cross-sectional area of the plurality of first fillers 75 in a unit cross-sectional area. That is, the ratio of the second total cross-sectional area (the second filler density) differs from the ratio of the first total cross-sectional area (the first filler density). Preferably, the second total cross-sectional area exceeds the first total cross-sectional area. That is, the ratio of the second total cross-sectional area preferably exceeds the ratio of the first total cross-sectional area.

The ratio of the second total cross-sectional area may be set within a ratio range of not less than 0.1% and not more than 10% higher than the ratio of the first total cross-sectional area. In particular, the ratio of the second total cross-sectional area may be set by a ratio within any range of not less than 0.1% and not more than 1%, not less than 1% and not more than 2%, not less than 2% and not more than 3%, not less than 3% and not more than 4%, not less than 4% and not more than 5%, not less than 5% and not more than 6%. less than 6% and not more than 7%, not less than 7% and not more than 8%, not less than 8% and not more than 9% and not less than 9% and not more than 10% higher than the ratio of the first total average area.

For example, in a case where the ratio of the first total cross-sectional area is set in a range of not less than 75% and not more than 85%, the ratio of the second total cross-sectional area is adjusted in a range of more than 75% and not more than 95%, under the condition that the ratio of the second total cross-sectional area is higher than the ratio of the first total cross-sectional area. The ratio of the second total cross-sectional area is preferably higher than the ratio of the first total cross-sectional area by a ratio within a range of 5% 12% (i.e., not less than 3% and not more than 7%). For example, in a case where the ratio of the first total cross-sectional area is set in a range of not less than 75% and not more than 85%, the ratio of the second total cross-sectional area is preferably set in a range of more than 78% and not more than 92%.

The plurality of second flexible particles 218 are added to the second matrix resin 216. The plurality of second flexible particles 218 may include at least one of silicone-based flexible particles, acrylic-based flexible particles, and butadiene-based flexible particles. The plurality of second flexible particles 218 may include an insulator of the same type as or a different type from the plurality of first flexible particles 76 of the sealing insulator 71.

The plurality of second flexible particles 218 in this embodiment is composed of flexible particles of the same type as the plurality of first flexible particles 76 (i.e., silicone-based flexible particles). The plurality of second flexible particles 218 preferably have an average particle size that is smaller than the average particle size of the plurality of second fillers 217. The average particle size of the plurality of second flexible particles 218 is preferably not less than 1 nm and not more than 1 µm. A maximum particle size of the plurality of second flexible particles 218 is preferably not more than 1 µm.

The plurality of second flexible particles 218 are added to the second matrix resin 216 such that the ratio of a total cross-sectional area to a unit cross-sectional area is not less than 0.1% and not more than 10%. In other words, the plurality of second flexible particles 218 are added to the second matrix resin 216 in a content within a range of not less than 0.1% by weight and not more than 10% by weight. The average particle size and the content of the plurality of second flexible particles 218 are to be appropriately set according to an elastic modulus to be imparted to the case body 212 at the time of manufacturing and/or after manufacturing. For example, by having the plurality of second flexible particles 218 have an average particle size in the submicrometer range (= not more than 1 μm), it is possible to contribute to a low elastic modulus and a small curing shrinkage of the case body 212.

Therefore, the housing body 212 is formed separately from the sealing insulator 71 and forms a boundary portion 219 with the sealing insulator 71. The housing body 212 is in close contact with the sealing insulator 71 but is not integrated with the sealing insulator 71. Of course, the housing body 212 may include a portion that is integrated with a portion of the sealing insulator 71 so as to cause the boundary portion 219 to partially disappear.

The plurality of first fillers 75 and the plurality of second fillers 217 are each constructed of a spherical object, and the case body 212 in this embodiment has no filler fragment 75d in the vicinity of the boundary portion 219. Accordingly, the boundary portion 219 is observed as a plurality of filler fragments 75d of the plurality of first fillers 75 formed in a surface layer portion of the insulating main surface 72 and a surface layer portion of the insulating side wall 73.

The boundary portion 219 is also a point where the ratio of the first total cross-sectional area (the plurality of first fillers 75) to the ratio of the second total cross-sectional area (the plurality of second fillers 217) changes. The boundary portion 219 is also a manufacturing process path formed by different manufacturing methods. The boundary portion 219 may have a plurality of fine voids (holes) between the sealing insulator 71 and the case body 212. In this case, the size of the plurality of fine voids is not less than 1 nm and not more than 1 μm. That is, the size of the plurality of fine voids may be not larger than the particle size of the first small fillers 75a (the second small fillers 217a).

The package body 212 includes the second matrix resin 216, the plurality of second fillers 217, and the plurality of second flexible particles 218 that are in contact with the first to fourth side surfaces 5A to 5D of the chip 2. The package body 212 also includes the second matrix resin 216, the plurality of second fillers 217, and the plurality of second flexible particles 218 that are in contact with the insulating main surface 72 and the insulating side wall 73 of the sealing insulator 71.

At least the second matrix resin 216 fills the grinding marks of the insulating main surface 72 and the grinding marks of the insulating side wall 73. At least the second matrix resin 216 preferably contacts the plurality of filler fragments 75d of the sealing insulator 71 (specifically, the broken portions of the filler fragments 75d). Here, “contact” includes a mode in which the second matrix resin 216 is in direct contact with (covers) the filler fragments 75d and a mode in which the second matrix resin 216 is in indirect contact with (covers) the filler fragments 75d with the first matrix resin 74 interposed therebetween.

Of course, either the plurality of second fillers 217 (especially the second small fillers 217a) or the plurality of second flexible particles 218 may fill the grinding track of the insulating main surface 72 and the grinding track of the insulating side wall 73. Of course, either the plurality of second fillers 217 or the plurality of second flexible particles 218 may contact the plurality of filler fragments 75d (especially the broken portions of the filler fragments 75d). Here, “contact” includes a mode in which the second fillers 217 (the second flexible particles 218) are in direct contact with (cover) the filler fragments 75d, and a mode in which the second fillers 217 (the second flexible particles 218) are in indirect contact with (cover) the filler fragments 75d with the first matrix resin 74 interposed therebetween.

The second matrix resin 216 contacts the first matrix resin 74 and/or the first fillers 75 (including the filler fragments 75d) on the insulating main surface 72 or the insulating sidewall 73, respectively, and does not enter the first matrix resin 74. Also, the plurality of second fillers 217 contacts the first matrix resin 74 and/or the first fillers 75 (including the filler fragments 75d) on the insulating main surface 72 or the insulating sidewall 73, respectively, and does not enter the first matrix resin 74. Also, the plurality of second flexible particles 218 contacts the first matrix resin 74 and/or the first fillers 75 (including the filler fragments 75d) on the insulating main surface 72 or the insulating sidewall 73, respectively, and does not enter the first matrix resin 74.

That is, the plurality of second fillers 217 and the plurality of second flexible particles 218 are not added to the sealing insulator 71 (the first matrix resin 74). “Not added” here means a structure in which the number of the second fillers 217 (second flexible particles 218) in contact with the sealing insulator 71 exceeds the number of the second fillers 217 (second flexible particles 218) that have entered the sealing insulator 71, and a portion of the aforementioned boundary portion 219 is formed by a portion of the plurality of second fillers 217 (second flexible particles 218). The second fillers 217 (the second flexible particles 218) that have accidentally and completely entered the sealing insulator 71 during the manufacturing process can be regarded as one of the first fillers 75 (first flexible particles 76).

The package body 212 further includes the second matrix resin 216, the plurality of second fillers 217, and the plurality of second flexible particles 218 that contact the gate pad surface 51 and the source pad surface 61. At least the second matrix resin 216 fills the grinding tracks of the gate pad surface 51 and the grinding tracks of the source pad surface 61. Of course, either the plurality of second fillers 217 (specifically, the second small fillers 217a) or the plurality of second flexible particles 218 may fill the grinding track of the gate pad surface 51 and the grinding track of the source pad surface 61.

10B is an enlarged cross-sectional view showing a second configuration example of the area X shown in 9 shown. Differences to the first configuration example (see 10A) are described below, and the description of the first configuration example (see 10A) also applies to the others.

Regarding 10B the housing body 212 may include at least one second filler 217 whose particle size exceeds the maximum particle size of the plurality of first fillers 75 in any cross-section including the seal insulator 71 and the housing body 212. The arbitrary cross-section may be a single cross-section including the first measurement region and the second measurement region. The arbitrary cross-section may be a single cross-section in which the entire cross-sectional shape of the seal ction insulator 71 and the entire cross-sectional shape of the housing body 212 appear.

The plurality of second fillers 217 may include the second filler 217 whose maximum particle size exceeds the maximum particle size of the plurality of first fillers 75. In this case, the average particle size of the plurality of second fillers 217 in the second measurement range may exceed the average particle size of the plurality of first fillers 75 in the first measurement range.

A particle size ratio of the maximum particle size of the second fillers 217 in the second measuring range to the maximum particle size of the first fillers 75 in the first measuring range may be not less than 1.5 and not more than 20. The particle size ratio may have a value in any range of not less than 1.5 and not more than 2, not less than 2 and not more than 4, not less than 4 and not more than 6, not less than 6 and not more than 8, not less than 8 and not more than 10, not less than 10 and not more than 12, not less than 12 and not more than 14, not less than 14 and not more than 16, not less than 16 and not more than 18, and not less than 18 and not more than 20. The particle size ratio is preferably not less than 2 and not more than 10. These numerical ranges are merely examples and do not prevent the particle size ratio from reaching a value of not less than 20 (for example, a value of not less than 20 and not more than 100).

In such a configuration as described above, the plurality of first fillers 75 may be composed of the first small fillers 75a, the first medium-sized fillers 75b, and the first large fillers 75c. In this case, the maximum particle size of the second large fillers 217c is set according to the second fillers 217 to exceed the maximum particle size of the first fillers 75 (the first large fillers 75c). The plurality of first fillers 75 may also be composed of the first small-sized fillers 75a and the first medium-sized fillers 75b.

The plurality of first fillers 75 may also be composed of only the first small fillers 75a. In these cases, the plurality of second fillers 217 may include the plurality of medium-sized second fillers 217b and/or the plurality of large-sized second fillers 217c. In this case, a maximum particle size of the medium-sized second fillers 217b and/or the large-sized second fillers 217c is set to exceed a maximum particle size of the small-sized first fillers 75a and/or the medium-sized first fillers 75b.

10C is an enlarged cross-sectional view showing a third configuration example of the area X shown in 9 shown. Differences to the first configuration example (see 10A) are described below, and the description of the first configuration example (see 10A) also applies to the others. Of course, the third configuration example can be applied to the second configuration example (see 10B) .

With reference to 10C the case body 212 may form a gap portion 219a with the sealing insulator 71 at the boundary portion 219. The gap portion 219a is a cavity portion in which the sealing insulator 71 and the case body 212 are not present. The gap portion 219a may be formed along either the insulating main surface 72 or the insulating side wall 73.

The gap width of the gap portion 219a on the insulating side wall 73 side is preferably smaller than the gap width of the gap portion 219a on the insulating main surface 72 side. In other words, the contact length per unit length of the case body 212 (the second matrix resin 216) with respect to the insulating side wall 73 (the first matrix resin 74) in the cross-sectional view preferably exceeds the contact length per unit length of the case body 212 (the second matrix resin 216) with respect to the insulating main surface 72 (the first matrix resin 74).

The gap width is defined by the cavity distance between the sealing insulator 71 and the case body 212 in the cross-sectional view. Of course, the gap portion 219a may be formed on the insulating main surface 72 side, while it may not be formed on the insulating side wall 73 side. Also, the gap portion 219a may be formed on the insulating side wall 73 side, while it may not be formed on the insulating main surface 72 side.

The gap width of the gap portion 219a is preferably not more than the particle size of at least the first medium-sized fillers 75b (the second medium-sized fillers 217b). That is, the gap width of the gap portion 219a may be not less than 1 µm and not more than 20 µm. It is particularly preferable that the gap width of the gap portion 219a is not more than the particle size of the first small fillers 75a (the second small fillers 217a). That is, the gap width of the gap portion 219a may be not less than 1 nm and not more than 1 μm. Of course, the gap width of the gap portion 219a may be not less than the particle size of the first small fillers 75a (the second small fillers 217a).

The case body 212 may form a gap portion 219a with one or both of the gate terminal surface 51 of the gate terminal electrode 50 and the source terminal surface 61 of the source terminal electrode 60 at the boundary portion 219. That is, the gap portion 219a formed in a region on the insulating main surface 72 may extend to a region on one or both of the gate terminal surface 51 and the source terminal surface 61. In other words, the gap portion 219a on the gate terminal surface 51 (the source terminal surface 61) side may extend to the insulating main surface 72 side.

As described above, the semiconductor package 201A includes the die pad 206, the semiconductor device 1A, and the package body 212. The semiconductor device 1A is arranged on the die pad 206. The semiconductor device 1A includes the chip 2, the gate electrode 30 (the source electrode 32: the main surface electrode), the gate terminal electrode 50 (the source terminal electrode 60), the sealing insulator 71. The chip 2 has the first main surface 3. The gate electrode 30 (the source electrode 32) is arranged on the first main surface 3. For example, the gate terminal electrode 50 (the source terminal electrode 60) is arranged on the gate electrode 30 (the source electrode 32).

The sealing insulator 71 covers the periphery of the gate terminal electrode 50 (the source terminal electrode 60) on the first main surface 3 so as to expose a part of the gate terminal electrode 50 (the source terminal electrode 60). The sealing insulator 71 encloses the first matrix resin 74 and the plurality of first fillers 75. The package body 212 seals the die pad 206 and the semiconductor device 1A to cover the sealing insulator 71. The package body 212 encloses the second matrix resin 216 and the plurality of second fillers 217.

According to this structure, the mechanical strength of the case body 212 can be adjusted with the second matrix resin 216 and the plurality of second fillers 217. According to this structure, the case body 212 also enables the semiconductor device 1A to be protected from external forces and/or moisture. That is, it is possible to protect the semiconductor device 1A from damage by external forces and/or deterioration by moisture. Thereby, shape errors and deviations in electrical characteristics of, for example, the semiconductor device 1A can be reduced.

On the other hand, the sealing insulator 71 enables the sealing target to be protected from external forces and/or moisture via the package body 212 on the semiconductor device 1A side. That is, it is possible to protect the sealing target from damage by external forces via the package body 212 and/or deterioration by moisture via the package body 212. Thereby, shape errors and deviations in electrical characteristics of, for example, the semiconductor device 1A can be reduced. As a result, it is possible to provide the semiconductor package 201A that can improve reliability.

It is preferable that the plurality of first fillers 75 of the first filler density are added to the first matrix resin 74, and that the plurality of second fillers 217 of the second filler density different from the first filler density are added to the second matrix resin 216. It is preferable that the plurality of first fillers 75 are added to the first matrix resin 74 so that the unit cross-sectional area becomes the first total cross-sectional area, and that the plurality of second fillers 217 are added to the second matrix resin 216 so that the unit cross-sectional area becomes the second total cross-sectional area different from the first total cross-sectional area.

In other words, the ratio of the second total cross-sectional area to the unit cross-sectional area is preferably different from the ratio of the first total cross-sectional area to the unit cross-sectional area. According to these structures, the mechanical strength of the case body 212 can be adjusted with respect to the mechanical strength of the semiconductor device 1A. In this case, the ratio of the second total cross-sectional area (the second filler density) is preferably higher than the ratio of the first total cross-sectional area (the first filler density). According to this structure, the mechanical strength of the case body 212 can be higher than the mechanical strength of the sealing insulator 71.

It is also conceivable to set the ratio of the second total cross-sectional area so that it is smaller than the ratio of the first total cross-sectional area, so that the mechanical strength strength of the housing body 212 is smaller than the mechanical strength of the sealing insulator 71. In this case, deformation of the sealing insulator 71 due to a temperature change may cause the sealing insulator 71 to detach from the housing body 212.

In addition, deformation of the sealing insulator 71 may result in deformation of the chip 2, causing the chip 2 to separate from the package body 212. Deformation of the sealing insulator 71 and/or the chip 2 may result in shape defects and deviations in electrical characteristics of the semiconductor device 1A. Also, in a case where the package body 212 has reduced mechanical strength, deformation of, for example, the die pad 206 due to a temperature change may cause the die pad 206 to separate from the package body 212.

Accordingly, the mechanical strength of the package body 212 is preferably higher than the mechanical strength of the seal insulator 71. According to this structure, the seal insulator 71 can have reduced deformation and also have reduced detachment from the package body 212. In addition, as the strength of the package body 212 increases, for example, the die pad 206 can deform less and also have less detachment from the package body 212.

The plurality of first fillers 75 are preferably added to the first matrix resin 74 such that the ratio of the first total cross-sectional area to the unit cross-sectional area is higher than the ratio of the cross-sectional area of the first matrix resin 74 to the unit cross-sectional area. Also, the plurality of second fillers 217 are preferably added to the second matrix resin 216 such that the ratio of the second total cross-sectional area to the unit cross-sectional area is higher than the ratio of the cross-sectional area of the second matrix resin 216 to the unit cross-sectional area. In this case, it is preferable that the ratio of the first total cross-sectional area is not less than 60% and that the ratio of the second total cross-sectional area is not less than 60%.

The matrix resin 74 is preferably composed of the thermosetting resin. The second matrix resin 216 is preferably composed of the thermosetting resin. The plurality of first fillers 75 are preferably each composed of the spherical object and/or an indeterminate object. The plurality of second fillers 217 are preferably each composed of the spherical object and/or an indeterminate object. It is particularly preferred that the plurality of first fillers 75 are each composed of the spherical object. It is also particularly preferred that the plurality of second fillers 217 are each composed of the spherical object.

It is particularly preferable that the sealing insulator 71 includes the plurality of first fillers 75 having different particle sizes. It is particularly preferable that the case body 212 includes the plurality of second fillers 217 having different particle sizes. The plurality of first fillers 75 preferably each have the particle size of not less than 1 nm and not more than 100 µm. The plurality of second fillers 217 preferably each have the particle size of not less than 1 nm and not more than 100 µm.

11 is a perspective view showing a wafer structure 80 used in the manufacture of the 1 semiconductor device 1A shown is to be used. 12 is a cross-sectional view showing a 11 shown device area 86. With reference to 11 and 12 the wafer structure 80 includes a wafer 81 formed in a disk shape. The wafer 81 is intended to form a base of the chip 2. The wafer 81 has a first wafer main surface 82 on one side, a second wafer main surface 83 on the other side, and a wafer side surface 84 connecting the first wafer main surface 82 and the second wafer main surface 83.

The wafer 81 has a mark 85 indicating a crystal orientation of the SiC single crystal on the wafer side surface 84. The mark 85 in this embodiment includes an alignment flat cut out in a straight line in plan view. The alignment flat extends in the second direction Y in this embodiment. The alignment flat does not necessarily have to extend in the second direction Y and may extend in the first direction X.

Of course, the mark 85 may include a first alignment flat extending in the first direction X and a second alignment flat extending in the second direction Y. Furthermore, the mark 85 may have an alignment notch cut toward a central portion of the wafer 81 instead of the alignment flat. The alignment notch may be a notched portion cut in a polygonal shape such as a triangle shape and a quadrilateral shape in plan view.

The wafer 81 may have a diameter of not less than 50 mm and not more than 300 mm (i.e., not less than 2 inches and not more than 12 inches). The diameter of the wafer structure 80 is defined by a length of a chord passing through a center of the wafer structure 80 outside of the mark 85. The wafer structure 80 may have a thickness of not less than 100 µm and not more than 1100 µm.

The wafer structure 80 includes the first semiconductor region 6 formed in a region on the first wafer main surface 82 side and the second semiconductor region 7 formed in a region on the second wafer main surface 83 side inside the wafer 81. The first semiconductor region 6 is formed by an epitaxial layer and the second semiconductor region 7 is formed by a semiconductor substrate. That is, the first semiconductor region 6 is formed by epitaxially growing a semiconductor single crystal from the second semiconductor region 7 by an epitaxial growth method. The second semiconductor region 7 preferably has a thickness exceeding the thickness of the first semiconductor region 6.

The wafer structure 80 includes a plurality of device regions 86 and a plurality of planned cutting lines 87 provided in the first wafer main surface 82. The plurality of device regions 86 are regions each corresponding to the semiconductor device 1A. The plurality of device regions 86 are each arranged in a quadrangular shape in plan view. In this embodiment, the plurality of device regions 86 are arranged in a matrix structure along the first direction X and the second direction Y in plan view.

The plurality of planned cutting lines 87 are lines (band-shaped regions) defining positions as the first to fourth side surfaces 5A to 5D of the chip 2. The plurality of planned cutting lines 87 are arranged in a lattice structure extending along the first direction X and the second direction Y so as to define the plurality of device regions 86. For example, the plurality of planned cutting lines 87 may be delimited by alignment marks and the like provided inside and/or outside the wafer 81.

The wafer structure 80 in this embodiment includes the mesa portion 11, the MISFET structure 12, the outer contact region 19, the outer well region 20, the field regions 21, the main surface insulating film 25, the sidewall structure 26, the interlayer insulating film 27, the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A, 36B, the source wiring 37, and the upper insulating film 38 formed in each of the device regions 86.

The wafer structure 80 includes the dicing line 41 defined in regions between the plurality of upper insulating films 38. That is, the dicing line 41 extends across the plurality of device regions 86 across the plurality of planned cutting lines 87 so as to expose the plurality of planned cutting lines 87. The dicing line 41 is formed in a lattice structure extending along the plurality of planned cutting lines 87. In this embodiment, the dicing line 41 exposes the interlayer insulating film 27. Of course, in a case where the interlayer insulating film 27 exposes the first wafer main surface 82, the dicing line 41 may expose the first wafer main surface 82.

13A until 13I are cross-sectional views showing an exemplary manufacturing process for the 1 semiconductor device 1A shown in Figure 1. Descriptions of the specific features of each structure shown in each 13A until 13I shown process are omitted or simplified since they are as described above.

With reference to 13A the wafer structure 80 is manufactured (see 11 and 12 ). Next, a first base conductor film 88 to serve as a base of the first gate conductor film 55 and the first source conductor film 67 is formed on the wafer structure 80. The first base conductor film 88 is formed in the form of a film along the interlayer insulating film 27, the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A, 36B, the source wiring 37, and the upper insulating film 38. Preferably, the first base conductor film 88 includes a Ti-based metal film. The first base conductor film 88 may be formed by a sputtering method and/or a vapor deposition method.

Next, a second base conductor film 89 is formed on the first base conductor film 88 to serve as a base of the second gate conductor film 56 and the second source conductor film 68. The second base conductor film 89 covers the interlayer insulating film 27, the gate electrode 30, the source electrode 32, the plurality of gate wirings 36A, 36B, the source wiring 37, and the upper insulating film 38 in a film form with the first base conductor film 88 interposed therebetween. The second base conductor film 89 includes a Cu-based metal film. The second base conductor film 89 can be formed by a sputtering process and/or a vapor deposition process.

Next, with reference to 13B a resist mask 90 having a predetermined pattern is formed on the second base conductor film 89. The resist mask 90 includes a first opening 90a exposing the gate electrode 30 and a second opening 90b exposing the source electrode 32. The first opening 90a exposes a region in which the gate terminal electrode 50 is to be formed in a region on the gate electrode 30. The second opening 90b exposes a region in which the source terminal electrode 60 is to be formed in a region on the source electrode 32.

This step includes a step of reducing adhesion of the resist mask 90 with respect to the second base conductor film 89. The adhesion of the resist mask 90 must be adjusted by adjusting the exposure conditions and/or the baking conditions (baking temperature, time, etc.) after exposure for the resist mask 90. Through this step, a growth start point of the first protrusion portion 53 is formed at a lower end portion of the first opening 90a, and a growth start point of the second protrusion portion 63 is formed at a lower end portion of the second opening 90b.

Next, with reference to 13C on the second base conductor film 89, a third base conductor film 91 is formed to serve as a base of the second gate conductor film 56 and the second source conductor film 68. The third base conductor film 91 is formed in this embodiment by depositing a conductor (a Cu-based metal in this embodiment) in the first opening 90a and the second opening 90b by a plating process (for example, an electroplating process). The third base conductor film 91 is integrated with the second base conductor film 89 within the first opening 90a and the second opening 90b. Through this step, the gate terminal electrode 50 covering the gate electrode 30 is formed. In addition, the source terminal electrode 60 covering the source electrode 32 is formed.

This step includes a step of introducing a plating solution between the second base conductor film 89 and the resist mask 90 at the lower end portion of the first opening 90a. This step also includes a step of introducing the plating solution between the second base conductor film 89 and the resist mask 90 at the lower end portion of the second opening 90b. By this step, a part of the third base conductor film 91 (the gate terminal electrode 50) at the lower end portion of the first opening 90a is drawn into a protrusion shape, and thereby the first protrusion portion 53 is formed. In addition, a part of the third base conductor film 91 (the source terminal electrode 60) at the lower end portion of the second opening 90b is drawn into a protrusion shape, and thereby the second protrusion portion 63 is formed.

Next, with reference to 13D the resist mask 90 is removed. This step exposes the gate connection electrode 50 and the source connection electrode 60 to the outside.

Next, with reference to 13E a portion of the second base conductor film 89 exposed from the gate terminal electrode 50 and the source terminal electrode 60 is removed. An unnecessary portion of the second base conductor film 89 may be removed by an etching process. The etching process may be a wet etching process and/or a dry etching process. Next, a portion of the first base conductor film 88 exposed from the gate terminal electrode 50 and the source terminal electrode 60 is removed. An unnecessary portion of the first base conductor film 88 may be removed by an etching process. The etching process may be a wet etching process and/or a dry etching process.

Next, with reference to 13F , a sealant 92 is applied to the first wafer main surface 82 so as to cover the gate terminal electrode 50 and the source terminal electrode 60. The sealant 92 is to form a base of the sealing insulator 71. The sealant 92 covers a periphery of the gate terminal electrode 50 and a periphery of the source terminal electrode 60, and covers an entire area of the upper insulating film 38, an entire area of the gate terminal electrode 50, and an entire area of the source terminal electrode 60.

The sealant 92 in this embodiment includes the first matrix resin 74, the plurality of first fillers 75, and the plurality of first flexible particles 76 (flexible agent). The plurality of first fillers 75 are added to the first matrix resin 74 such that the ratio of the total cross-sectional area to the unit cross-sectional area is higher than the ratio of the cross-sectional area of the first matrix resin 74 to the unit cross-sectional area. That is, the viscosity of the sealant 92 is increased by the plurality of first fillers 75.

The plurality of first fillers 75 are preferably added to the first matrix resin 74 such that the ratio of the total cross-sectional area to the unit cross-sectional area is not less than 60%. After the step of supplying the sealant 92, the sealant 92 is cured by heating to form the sealing insulator 71. The sealing insulator 71 has the insulating main surface 72 covering the entire area of the gate terminal electrode 50 and the entire area of the source terminal electrode 60.

Next, with reference to 13G the sealing insulator 71 is partially removed. The sealing insulator 71 is ground from the insulating main surface 72 side by a grinding process in this embodiment. The grinding process may be a mechanical polishing process and/or a chemical mechanical polishing process. The insulating main surface 72 is ground until the gate terminal electrode 50 and the source terminal electrode 60 are exposed. This step includes a step of grinding the gate terminal electrode 50 and the source terminal electrode 60. By this step, the insulating main surface 72 is formed, which forms the single grinding surface with the gate terminal electrode 50 (the gate terminal surface 51) and the source terminal electrode 60 (the source terminal surface 61).

Next, with reference to 13H , the wafer 81 is partially removed from the side of the second wafer main surface 83, and the wafer 81 is thinned until the desired thickness is reached. The step of thinning the wafer 81 is performed by an etching process and/or a grinding process. The etching process may be a wet etching process and/or a dry etching process. The grinding process may be a mechanical polishing process and/or a chemical mechanical polishing process.

This step includes a step of thinning the wafer 81 using the sealing insulator 71 as a support member that supports the wafer 81. This enables appropriate handling of the wafer 81. In addition, it is possible to suppress deformation (bending due to thinning) of the wafer 81 with the sealing insulator 71, and therefore the wafer 81 can be appropriately thinned.

For example, when the thickness of the wafer 81 is less than the thickness of the sealing insulator 71, the wafer 81 is further thinned. As another example, in a case where the thickness of the wafer 81 is not less than the thickness of the sealing insulator 71, the wafer 81 is thinned until the thickness of the wafer 81 becomes less than the thickness of the sealing insulator 71. In these cases, the wafer 81 is preferably thinned until a thickness of the second semiconductor region 7 (the semiconductor substrate) becomes less than a thickness of the first semiconductor region 6 (the epitaxial layer).

Of course, the thickness of the second semiconductor region 7 (the semiconductor substrate) cannot be less than the thickness of the first semiconductor region 6 (the epitaxial layer). In addition, the wafer 81 can be thinned until the first semiconductor region 6 is exposed from the second wafer main surface 83. That is, the entire second semiconductor region 7 can be removed.

Next, with reference to 13I the drain electrode 77 is formed covering the second wafer main surface 83. The drain electrode 77 may be formed by a sputtering method and/or a vapor deposition method. Then, the wafer structure 80 and the sealing insulator 71 are cut along the provided cutting lines 87. The wafer structure 80 and the sealing insulator 71 may be cut with a dicing blade (not shown). Through the above steps, the plurality of semiconductor devices 1A are manufactured from the single wafer structure 80.

As described above, the manufacturing method for the semiconductor device 1A includes the step of preparing the wafer structure 80, the step of forming the gate terminal electrode 50 (a source terminal electrode 60), and the step of forming the sealing insulator 71. The wafer structure 80 includes the wafer 81 and the gate electrode 30 (the source electrode 32: the main surface electrode). The wafer 81 has the first wafer main surface 82. The gate electrode 30 (the source electrode 32) is arranged on the first wafer main surface 82.

In the step of forming the gate terminal electrode 50 (a source terminal electrode 60), the gate terminal electrode 50 (the source terminal electrode 60) is formed on the gate electrode 30 (the source electrode 32). In the step of forming the sealing insulator 71, the gate terminal electrode 50 (the source terminal electrode 60) is formed covering a periphery of the gate terminal electrode 50 (the source terminal electrode 60) on the first wafer main surface 82 so that a part of the gate terminal electrode 50 (the source terminal electrode 60) is exposed.

In the step of forming the sealing insulator 71, the gate terminal electrode 50 (the source terminal electrode 60) is formed, which covers the periphery of the gate terminal electrode 50 (the source terminal electrode 60) on the first wafer main surface 82 such that a part of the gate terminals electrode 50 (the source terminal electrode 60). The sealing insulator 71 includes the first matrix resin 74 and the plurality of first fillers 75.

According to the manufacturing method described above, the strength of the sealing insulator 71 can be adjusted with the first matrix resin 74 and the plurality of first fillers 75. In addition, the sealing insulator 71 according to the manufacturing method described above makes it possible to protect the sealing target from external forces and/or moisture. That is, it is possible to protect the sealing target from damage by external forces and/or deterioration by moisture. Thereby, shape errors and deviations in electrical characteristics can be reduced. As a result, it is possible to manufacture the semiconductor device 1A that can improve reliability.

The plurality of first fillers 75 are preferably added to the first matrix resin 74 such that the ratio of the first total cross-sectional area to the unit cross-sectional area is higher than the ratio of the cross-sectional area of the first matrix resin 74 to the unit cross-sectional area. According to the manufacturing method, the mechanical strength of the sealing insulator 71 can be increased and the stress of the sealing insulator 71 due to temperature change can be reduced. This can result in the wafer 81 having less deformation and/or deviation of electrical properties due to the stress of the sealing insulator 71.

In this case, the ratio of the first total cross-sectional area is preferably not less than 60%. According to this structure, the mechanical strength of the sealing insulator 71 can be adequately increased. The ratio of the first total cross-sectional area is preferably not more than 95%. The plurality of first fillers 75 may be each composed of the spherical object and/or the indefinite object. The plurality of first fillers 75 are each preferably composed of the spherical object. The sealing insulator 71 preferably includes the plurality of first fillers 75 having different particle sizes.

The forming step of the sealing insulator 71 preferably includes the supplying step of the sealant 92 and the heat-curing step of the sealant 92. In the supplying step of the sealant 92, the sealant 92 including the first matrix resin 74 composed of the thermosetting resin and the plurality of first fillers 75 are supplied to the first wafer main surface 82. In the heat-curing step of the sealant 92, the sealing insulator 71 is formed by heat-curing the sealant 92.

In this case, the sealant 92 is preferably applied to the main surface 82 of the first wafer so as to cover the entire area of the gate terminal electrode 50 (the source terminal electrode 60). In this case, the step of forming the sealing insulator 71 preferably includes the step of partially removing the sealing insulator 71 until the gate terminal electrode 50 (the source terminal electrode 60) is partially exposed after the step of heat-curing the sealant 92.

The step of forming the gate terminal electrode 50 (the source terminal electrode 60) preferably includes the step of forming the gate terminal electrode 50 (the source terminal electrode 60) thicker than the gate electrode 30 (the source electrode 32). The step of forming the sealing insulator 71 preferably includes the step of forming the sealing insulator 71 thicker than the gate electrode 30 (the source electrode 32).

The manufacturing method for the semiconductor device 1A preferably includes the step of thinning the wafer 81 after the formation step of the sealing insulator 71. According to this manufacturing method, since the stress of the sealing insulator 71 with respect to the wafer 81 can be reduced, the wafer 81 can be appropriately thinned. In this case, the wafer 81 can be thinned by using the sealing insulator 71 as a support member.

The thinning step of the wafer 81 preferably includes the step of thinning the wafer 81 until the thickness becomes smaller than the thickness of the sealing insulator 71. The thinning step of the wafer 81 preferably includes the step of thinning the wafer 81 until it becomes thinner than the gate terminal electrode 50 (source terminal electrode 60). The thinning step of the wafer 81 preferably includes the step of thinning the wafer 81 by the grinding process.

The wafer 81 preferably has the laminated structure including the substrate and the epitaxial layer, and has a first wafer major surface 82 formed by the epitaxial layer. In this case, the thinning step of the wafer 81 may include the step of removing at least a portion of the substrate. For example, the thinning step of the wafer 81 may include the step of thinning the substrate until it becomes thinner than the epitaxial layer. The wafer 81 preferably includes the single crystal of the wide band gap semiconductor.

The formation step of the gate terminal electrode 50 (the source terminal electrode 60) preferably includes the step of forming the second base conductor film 89 (conductor film) covering the first gate electrode 30 (the source electrode 32), the step of forming, on the base conductor film 89, the resist mask 90 exposing the portion of the second base conductor film 89 covering the gate electrode 30 (the source electrode 32), the step of depositing the third base conductor film 91 (conductor) on the portion of the second base conductor film 89 exposed from the resist mask 90, and the step of removing the resist mask 90 after the deposition step of the third base conductor film 91.

The manufacturing method for the semiconductor device 1A preferably includes the step of forming the upper insulating film 38 partially covering the gate electrode 30 (the source electrode 32) before the step of forming the gate terminal electrode 50 (the source terminal electrode 60). In this case, the supplying step of the sealant 92 preferably includes the step of supplying the sealant 92 into an opening portion 95 to cover the gate terminal electrode 50 (the source terminal electrode 60) and the upper insulating film 38.

The step of forming the gate terminal electrode 50 (the source terminal electrode 60) preferably includes the step of forming the gate terminal electrode 50 (the source terminal electrode 60) having the portion directly covering the upper insulating film 38. The step of forming the upper insulating film 38 preferably includes the step of forming the upper insulating film 38 including at least one of the inorganic insulating film 42 and the organic insulating film 43.

In the preparation step of the wafer structure 80, it is preferable to prepare the wafer structure 80 including the wafer 81, the device region 86, the planned cutting lines 87, and the gate electrode 30 (the source electrode 32). The device region 86 is set in the wafer 81 (the first wafer main surface 82). The planned cutting lines 87 are set in the wafer 81 (the first wafer main surface 82) to define the device region 86. The gate electrode 30 (the source electrode 32) is arranged on the first wafer main surface 82 in the device region 86. In this case, the manufacturing method for the semiconductor device 1A preferably includes the step of cutting the wafer 81 and the sealing insulator 71 along the planned cutting lines 87 after the forming step of the sealing insulator 71 (specifically, after the removing step of the sealing insulator 71).

14A to 14C are cross-sectional views showing an exemplary manufacturing process for the 8th semiconductor package 201A shown. Specific features of each structure shown in the 14A to 14C shown steps are as described above and are therefore omitted or simplified.

Regarding 14A the manufacturing method of the semiconductor package 201A is performed after the step of manufacturing the semiconductor device 1A. In the manufacturing method of the semiconductor package 201A, a lead frame 220 is first prepared. The lead frame 220 includes the metal plate 202, the plurality of lead terminals 209, and a frame portion 221 that supports the metal plate 202 and the plurality of lead terminals 209, and is formed into a predetermined shape by press molding or the like.

Next, with reference to 14B the semiconductor device 1A is bonded to the metal plate 202 (the die pad 206) via the conductive adhesive 210. Next, at least one of the lead wires 211 is connected to the lead terminal 209 and the gate terminal electrode 50, and at least one of the lead wires 211 is connected to the lead terminal 209 and the source terminal electrode 60.

Next, with reference to 14C , a molding process based on a mold 222 (a metal mold) is performed. 14C shows an example in which a transfer molding method is used as an example of the molding method. The mold 222 includes a first mold 223 (a lower mold) on one side and a second mold 224 (an upper mold) on the other side. The second mold 224 defines a mold space 225 with the first mold 223.

The lead frame 220 is arranged within the mold 222 so that at least the semiconductor device 1A is positioned within the mold space 225. After the lead frame 220 is arranged, a molding resin 226 including the second matrix resin 216, the plurality of second fillers 217, and the plurality of second flexible particles 218 is supplied to the mold space 225. The plurality of second fillers 217 are added to the second matrix resin 216 so that the ratio of the second total cross-sectional area to the unit cross-sectional area is higher than the ratio of the cross-sectional area of the second matrix resin 216 to the unit cross-sectional area.

That is, the viscosity of the molding resin 226 is increased by the plurality of second fillers 217. The ratio of the second total cross-sectional area is preferably not less than 60%. The second total cross-sectional area is preferably different from the first total cross-sectional area of the plurality of first fillers 75. That is, the ratio of the second total cross-sectional area (the second filler density) is preferably different from the first total cross-sectional area (the first filler density). It is particularly preferable that the second total cross-sectional area exceeds the first total cross-sectional area.

The mold resin 226 seals the metal plate 202, the plurality of lead terminals 209, the semiconductor device 1A, the conductive adhesive 210, and the plurality of lead wires 211 within the mold space 225. After the step of supplying the mold resin 226, the mold resin 226 is cured by heating to form the case body 212. Then, the lead frame 220 is removed from the mold 222, and the metal plate 202 and the plurality of lead terminals 209 are separated from the frame portion 221 together with the case body 212.

The semiconductor package 201A is then manufactured by the process including the above steps. This embodiment illustrates an example in which a transfer molding method is used as an example of the molding method. However, a compression molding method may be used instead of such a transfer molding method.

As described above, the manufacturing method for the semiconductor package 201A includes the step of preparing the semiconductor device 1A and the step of forming the package body 212. The semiconductor device 1A includes the chip 2, the gate electrode 30 (the source electrode 32: the main surface electrode), the gate terminal electrode 50 (the source terminal electrode 60), the sealing insulator 71.

The sealing insulator 71 covers the periphery of the gate terminal electrode 50 (the source terminal electrode 60) on the first main surface 3 so as to expose a part of the gate terminal electrode 50 (the source terminal electrode 60). The sealing insulator 71 includes the first matrix resin 74 and the plurality of first fillers 75. In the step of forming the package body 212, the die pad 206 and the semiconductor device 1A are sealed with the mold resin 226 including the second matrix resin 216 and the plurality of second fillers 217, and accordingly, the package body 212 is formed.

According to the manufacturing method described above, the mechanical strength of the case body 212 can be adjusted with the second matrix resin 216 and the plurality of second fillers 217. According to this manufacturing method, the case body 212 also enables the semiconductor device 1A to be protected from external forces and/or moisture. That is, it is possible to protect the semiconductor device 1A from damage by external forces and/or deterioration by moisture. Thereby, shape errors and deviations in electrical characteristics of, for example, the semiconductor device 1A can be reduced.

On the other hand, the sealing insulator 71 enables the sealing target to be protected from external forces and/or moisture via the package body 212 on the semiconductor device 1A side. That is, it is possible to protect the sealing target from damage by external forces via the package body 212 and/or deterioration by moisture via the package body 212. Thereby, shape errors and deviations in electrical characteristics of, for example, the semiconductor device 1A can be reduced. As a result, it is possible to manufacture the semiconductor package 201A that can improve reliability.

It is preferable that the plurality of first fillers 75 of the first filler density are added to the first matrix resin 74, and that the plurality of second fillers 217 of the second filler density different from the first filler density are added to the second matrix resin 216. It is preferable that the plurality of first fillers 75 are added to the first matrix resin 74 so that the unit cross-sectional area becomes the first total cross-sectional area, and that the plurality of second fillers 217 are added to the second matrix resin 216 so that the unit cross-sectional area becomes the second total cross-sectional area different from the first total cross-sectional area.

In other words, the ratio of the second total cross-sectional area to the unit cross-sectional area is preferably different from the ratio of the first total cross-sectional area to the unit cross-sectional area. According to the above manufacturing methods, the mechanical strength of the package body 212 can be adjusted with respect to the mechanical strength of the semiconductor device 1A. In this case, the ratio of the second total cross-sectional area (the two filler density) is preferably higher than the ratio of the first total cross-sectional area (the first filler density).

According to the plurality of second fillers 217 having the second total cross-sectional area larger than the first total cross-sectional area, the mechanical strength of the package body 212 may be larger than the mechanical strength of the sealing insulator 71. Therefore, the semiconductor device 1A may have reduced deformation and also have reduced detachment from the package body 212. In addition, as the strength of the package body 212 increases, the lead frame 220 (e.g., the die pad 206) may deform less and also detach less from the package body 212.

15 is a plan view showing a semiconductor device 1B according to a second embodiment. Referring to 15 the semiconductor device 1B includes a modified mode of the semiconductor device 1A. Specifically, the semiconductor device 1B includes the source terminal electrode 60 having at least one (in this embodiment, a plurality of) drawer terminal portions 100. Specifically, the plurality of drawer terminal portions 100 are respectively drawn out from the plurality of drawer electrode portions 34A, 34B of the source electrode 32 so as to face the gate terminal electrode 50 in the second direction Y. That is, the plurality of drawer terminal portions 100 sandwich the gate terminal electrode 50 in plan view from both sides of the second direction Y.

As described above, the semiconductor device 1B can achieve the same effects as the semiconductor device 1A. In addition, the semiconductor device 1B is manufactured by a similar manufacturing method as the semiconductor device 1A. Therefore, the manufacturing method for the semiconductor device 1B can achieve the same effects as the manufacturing method for the semiconductor device 1A. The semiconductor device 1B can also be integrated into the semiconductor package 201A. Therefore, the same effects as those of the semiconductor package 201A including the semiconductor device 1A are also achieved with the semiconductor package 201A including the semiconductor device 1B.

16 is a plan view showing a semiconductor device 1C according to a third embodiment. 17 is a cross-sectional view along the 16 shown line XVII-XVII. 18 is a circuit diagram showing an electrical configuration of the 16 semiconductor device 1C shown. Referring to 16 until 18 the semiconductor device 1C has a modified mode of the semiconductor device 1A.

Specifically, the semiconductor device 1C includes the plurality of source terminal electrodes 60 arranged at intervals from each other on the source electrode 32. The semiconductor device 1C in this embodiment includes at least one (in this embodiment, one) source terminal electrode 60 arranged on the body electrode portion 33 of the source electrode 32 and at least one (in this embodiment, a plurality of) source terminal electrodes 60 arranged on the plurality of drawer electrode portions 34A, 34B of the source electrode 32.

The source terminal electrode 60 on the side of the body electrode portion 33 is formed in this embodiment as a main terminal electrode 102 that conducts a drain-source current IDS. The plurality of source terminal electrodes 60 on the sides of the plurality of drawer electrode portions 34A, 34B are each formed in this embodiment as a detection terminal electrode 103 that conducts a monitoring current IM that monitors the drain-source current IDS. Each of the detection terminal electrodes 103 has a smaller area in plan view than the area of the main terminal electrode 102.

One sense terminal electrode 103 is arranged on the first drawer electrode portion 34A and faces the gate terminal electrode 50 in the second direction Y in plan view. The other sense terminal electrode 103 is arranged on the second drawer electrode portion 34B and faces the gate terminal electrode 50 in the second direction Y in plan view. The plurality of sense terminal electrodes 103 therefore enclose the gate terminal electrode 50 from both sides of the second direction Y in plan view.

With reference to 18 in the semiconductor device 1C, a gate drive circuit 106 is to be electrically connected to the gate terminal electrode 50, at least a first resistor R1 is to be electrically connected to the main terminal electrode 102, and at least a second resistor R2 is to be electrically connected to the plurality of sense terminal electrodes 103. The first resistor R1 is configured to conduct the drain-source current IDS generated in the semiconductor device 1C. The second resistor R2 is configured to conduct the monitor current IM whose value is smaller than that of the drain-source current IDS.

The first resistor R1 may be a resistor or a conductive bonding member having a first resistance value. The second resistor R2 may be a resistor or a conductive bonding member having a second resistance value that is greater than the first resistance value. The conductive bonding member may be a circuit board or a conductive wire (e.g., a bonding wire). That is, at least one first bonding wire having the first resistance value may be connected to the main terminal electrode 102.

In addition, at least one second bonding wire having a second resistance value that is larger than the first resistance value may be connected to at least one of the sensing terminal electrodes 103. The second bonding wire may have a smaller line thickness than the line thickness of the first bonding wire. In this case, a bonding area of the second bonding wire with respect to the sensing terminal electrode 103 may be smaller than a bonding area of the first bonding wire with respect to the main terminal electrode 102.

As described above, the semiconductor device 1C achieves the same effects as the semiconductor device 1A. In the manufacturing method of the semiconductor device 1C, the resist mask 90 having the plurality of second openings 90b exposing regions in which the source terminal electrode 60 and the sense terminal electrode 103 are to be formed, respectively, is formed in the manufacturing method of the semiconductor device 1A, and then the same steps as those of the manufacturing method of the semiconductor device 1A are performed. Therefore, the manufacturing method of the semiconductor device 1C achieves the same effects as the manufacturing method of the semiconductor device 1A.

In this embodiment, an example is shown in which the detection terminal electrodes 103 are formed on the drawer electrode portions 34A, 34B, but the arrangement locations of the detection terminal electrodes 103 are arbitrary. Therefore, the detection terminal electrode 103 may be arranged on the body electrode portion 33. In this embodiment, an example in which the detection terminal electrode 103 is applied to the semiconductor device 1A was shown. Of course, the detection terminal electrode 103 may also be applied to the second embodiment.

The semiconductor device 1C may also be integrated into the semiconductor package 201A. In this case, the semiconductor package 201A further includes the lead terminal 209 corresponding to the detection terminal electrode 103 and the lead wires 211 connected to the detection terminal electrode 103 and the lead terminal 209. The same effects as those of the semiconductor package 201A enclosing the semiconductor device 1A are also achieved with the semiconductor package 201A enclosing the semiconductor device 1C.

19 is a plan view showing a semiconductor device 1D according to a fourth embodiment. 20 is a cross-sectional view along the 19 shown line XX-XX. With reference to 19 and 20 the semiconductor device 1D includes a modified mode of the semiconductor device 1A. Specifically, the semiconductor device 1D includes a gap portion 107 formed in the source electrode 32.

The gap portion 107 is formed in the body electrode portion 33 of the source electrode 32. The gap portion 107 penetrates the source electrode 32 so as to expose a part of the interlayer insulating film 27 in a cross-sectional view. In this embodiment, the gap portion 107 extends in a band shape from a portion of a wall portion of the source electrode 32, which is opposite to the gate electrode 30 in the first direction X, toward an inner portion of the source electrode 32.

The gap portion 107 in this embodiment is formed in a band shape and extends in the first direction X. In this embodiment, the gap portion 107 crosses a central portion of the source electrode 32 in the first direction X in plan view. The gap portion 107 has an end portion at a distance inward (toward the gate electrode 30 side) from a wall portion of the source electrode 32 in plan view at a position on the fourth side surface 5D side. Of course, the gap portion 107 may divide the source electrode 32 in the second direction Y.

The semiconductor device 1D includes a gate interwiring 109 that is led out from the gate electrode 30 into the gap portion 107. The gate interwiring 109 has a laminated structure including the first gate conductor film 55 and the second gate conductor film 56 like the gate electrode 30 (the plurality of gate wirings 36A, 36B). The gate interwiring 109 is formed at a distance from the source electrode 32 and extends in a band shape along the gap portion 107 in plan view.

The gate inter-wiring 109 penetrates the interlayer insulating film 27 at an inner portion of the active surface 8 (the first main surface 3) and is electrically connected to the plurality of gate structures 15. The gate inter-wiring 109 may be directly connected to the plurality of gate structures 15 or may be electrically connected to the plurality of gate structures 15 via a conductor film.

The aforementioned upper insulating film 38 in this embodiment includes a gap covering portion 110 covering the gap portion 107. The gap covering portion 110 covers an entire area of the gate interwiring 109 within the gap portion 107. The gap covering portion 110 may be led out from within the gap portion 107 onto the source electrode 32 so as to cover the peripheral edge portion of the source electrode 32.

The semiconductor device 1D in this embodiment includes the plurality of source terminal electrodes 60 arranged at a distance from each other on the source electrode 32. The plurality of source terminal electrodes 60 are each arranged at a distance from the gap portion 107 on the source electrode 32 and face each other in the second direction Y in plan view. The plurality of source terminal electrodes 60 are arranged in this embodiment so that the gap cover portion 110 is exposed.

The plurality of source terminal electrodes 60 in this embodiment are each formed in a quadrangular shape (more specifically, a rectangular shape extending in the first direction X) in plan view. The planar shapes of the plurality of source terminal electrodes 60 are arbitrary, and may each be formed in a polygonal shape other than the quadrangular shape, a circular shape, or an elliptical shape in plan view. The plurality of source terminal electrodes 60 may each include the second protrusion portion 63 formed on the gap cover portion 110 of the upper insulating film 38.

The aforementioned sealing insulator 71 in this embodiment covers the gap portion 107 in a region between the plurality of source terminal electrodes 60. The sealing insulator 71 covers the gap covering portion 110 of the upper insulating film 38 in a region between the plurality of source terminal electrodes 60. That is, the sealing insulator 71 covers the gate intermediate wiring 109 with the upper insulating film 38 interposed therebetween.

In this embodiment, an example was shown in which the upper insulating film 38 has the gap covering portion 110. However, the presence or absence of the gap covering portion 110 is arbitrary, and the upper insulating film 38 may be formed without the gap covering portion 110. In this case, the plurality of source terminal electrodes 60 are formed on the source electrode 32 so as to expose the gate interwiring 109. The sealing insulator 71 directly covers the gate interwiring 109 and electrically insulates the gate interwiring 109 from the source electrode 32. The sealing insulator 71 directly covers a part of the interlayer insulating film 27 exposed in a region between the source electrode 32 and the gate interwiring 109 within the gap portion 107.

As described above, the semiconductor device 1D achieves the same effects as the semiconductor device 1A. In the manufacturing method of the semiconductor device 1D, the wafer structure 80 in which structures corresponding to the semiconductor device 1D are formed in each device region 86 is prepared, and similar steps to those in the manufacturing method of the semiconductor device 1A are performed. Therefore, the manufacturing method of the semiconductor device 1D achieves the same effects as the manufacturing method of the semiconductor device 1A.

In this embodiment, an example was shown in which the gap portion 107, the gate interwiring 109, the gap cover portion 110, etc. are applied to the semiconductor device 1A. Of course, the gap portion 107, the gate interwiring 109, the gap cover portion 110, etc. can also be applied to the second and third embodiments. The semiconductor device 1D can also be integrated into the semiconductor package 201A. Therefore, the same effects as those of the semiconductor package 201A including the semiconductor device 1A are also achieved with the semiconductor package 201A including the semiconductor device 1D.

21 is a plan view showing a semiconductor device 1E according to a fifth embodiment. Referring to 21 the semiconductor device 1E has a mode in which the features (structures having the gate interwiring 109) of the semiconductor device 1D according to the fourth embodiment are combined with the features (structures having the sense terminal electrode 103) of the semiconductor device 1C according to the third embodiment.

With the semiconductor device 1E in such a mode, the same effects as those of the semiconductor device 1A are achieved. Also, the semiconductor device 1E can be integrated into the semiconductor package 201A. Therefore, the same effects as those of the semiconductor package 201A including the semiconductor device 1A are also achieved with the semiconductor package 201A including the semiconductor device 1E.

22 is a plan view showing a semiconductor device 1F according to a sixth embodiment. Referring to 22 the semiconductor device 1F comprises a modified mode of the semiconductor device 1A. Specifically, in the semiconductor device 1F, the gate electrode 30 is arranged in a region along an arbitrary corner portion of the chip 2.

That is, when a first straight line L1 (see two-dot chain line section) crossing the central portion of the first main surface 3 in the first direction X and a second straight line L2 (see two-dot chain line section) crossing the central portion of the first main surface 3 in the second direction Y are set, the gate electrode 30 is arranged at a position offset from both the first straight line L1 and the second straight line L2. The gate electrode 30 in this embodiment is arranged in an area along a corner portion connecting the second side surface 5B and the third side surface 5C in plan view.

The plurality of drawer electrode portions 34A, 34B of the aforementioned source electrode 32 enclose the gate electrode 30 in plan view from both sides of the second direction Y, as in the case of the first embodiment. The first drawer electrode portion 34A is led out from the body electrode portion 33 with a first planar area. The second drawer electrode portion 34B is led out from the body electrode portion 33 with a second planar area smaller than the first planar area. Of course, the source electrode 32 does not have to have the second drawer electrode portion 34B and may only include the body electrode portion 33 and the first drawer electrode portion 34A.

The aforementioned gate terminal electrode 50 is arranged on the gate electrode 30 as in the case of the first embodiment. The gate terminal electrode 50 is arranged in a region along any corner portion of the chip 2 in this embodiment. That is, the gate terminal electrode 50 is arranged at a position offset from both the first straight line L1 and the second straight line L2 in plan view. The gate terminal electrode 50 is arranged in the region along the corner portion connecting the second side surface 5B and the third side surface 5C in plan view in this embodiment.

The aforementioned source terminal electrode 60 in this embodiment has the drawer terminal portion 100 led out to the first drawer electrode portion 34A. The source terminal electrode 60 in this embodiment does not have the drawer terminal portion 100 led out to the second drawer electrode portion 34B. The drawer terminal portions 100 thereby face the gate terminal electrode 50 from a second direction Y side. The source terminal electrode 60 has portions facing the gate terminal electrode 50 from two directions including the first direction X and the second direction Y by having the drawer terminal portion 100.

As described above, the semiconductor device 1F achieves the same effects as the semiconductor device 1A. In the manufacturing method of the semiconductor device 1F, the wafer structure 80 in which patterns corresponding to the semiconductor device 1F are formed in each device region 86 is prepared, and similar steps to those in the manufacturing method of the semiconductor device 1A are performed. Therefore, the manufacturing method of the semiconductor device 1F achieves the same effects as the manufacturing method of the semiconductor device 1A.

The structure in which the gate electrode 30 and the gate terminal electrode 50 are arranged at the corner portion of the chip 2 can be applied to the second to fifth embodiments. Also, the semiconductor device 1F can be integrated into the semiconductor package 201A. Therefore, the same effects as those of the semiconductor package 201A including the semiconductor device 1A are also achieved with the semiconductor package 201A including the semiconductor device 1F.

23 is a plan view showing a semiconductor device 1G according to a seventh embodiment. Referring to 23 the semiconductor device 1G comprises a modified mode of the semiconductor device 1A. Specifically, in the semiconductor device 1G, the gate electrode 30 is arranged in the central portion of the first main surface 3 (the active surface 8) in plan view.

That is, when the first straight line L1 (see two-dot chain line section) crossing the central portion of the first main surface 3 in the first direction X and the second straight line L2 (see two-dot chain line section) crossing the central portion of the first main surface 3 in the second direction Y are set, the gate electrode 30 is arranged to overlap an intersection portion Cr of the first straight line L1 and the second straight line L2. The aforementioned source electrode 32 is formed in a ring shape (specifically, a quadrangular ring shape) around the gate electrode 30 in plan view in this embodiment.

The semiconductor device 1G includes a plurality of gap portions 107A, 107B formed in the source electrode 32. The plurality of gap portions 107A, 107B include a first gap portion 107A and a second gap portion 107B. The first gap portion 107A crosses a portion of the source electrode 32 extending in the first direction X in a region on one side (the side of the first side surface 5A) of the source electrode 32 in the second direction Y. The first gap portion 107A faces the gate electrode 30 in the second direction Y in plan view.

The second gap portion 107B crosses a portion of the source electrode 32 extending in the first direction X in a region on the other side (the second side surface 5B side) of the source electrode 32 in the second direction Y. The second gap portion 107B faces the gate electrode 30 in the second direction Y in plan view. In this embodiment, the second gap portion 107B faces the first gap portion 107A in plan view with the gate electrode 30 interposed therebetween.

The aforementioned first gate wiring 36A is led out from the gate electrode 30 into the first gap portion 107A. Specifically, the first gate wiring 36A has a portion extending in a band shape in the second direction Y within the first gap portion 107A and a portion extending in a band shape in the first direction X along the first side surface 5A (the first connection surface 10A). The aforementioned second gate wiring 36B is led out from the gate electrode 30 into the second gap portion 107B. Specifically, the second gate wiring 36B has a portion extending in a band shape in the second direction Y within the second gap portion 107B and a portion extending in a band shape in the first direction X along the second side surface 5B (the second connection surface 10B).

The plurality of gate wirings 36A, 36B cross (more specifically, cross perpendicularly) the both end portions of the plurality of gate structures 15 as in the case of the first embodiment. The plurality of gate wirings 36A, 36B penetrate the interlayer insulating film 27 and are electrically connected to the plurality of gate structures 15. The plurality of gate wirings 36A, 36B may be directly connected to the plurality of gate structures 15 or may be electrically connected to the plurality of gate structures 15 via a conductor film.

The aforementioned source wiring 37 is led out from a plurality of portions of the source electrode 32 and surrounds the gate electrode 30, the source electrode 32 and the gate wirings 36A, 36B. Of course, the source wiring 37 may be led out from a single portion of the source electrode 32 as in the case of the first embodiment.

The aforementioned upper insulating film 38 includes a plurality of gap covering portions 110A, 110B which, in this embodiment, respectively cover the plurality of gap portions 107A, 107B. The plurality of gap covering portions 110A, 110B include a first gap covering portion 110A and a second gap covering portion 110B. The first gap covering portion 110A covers an entire area of the first gate wiring 36A in the first gap portion 107A. The second gap covering portion 110B covers an entire area of the second gate wiring 36B in the second gap portion 107B. The plurality of gap covering portions 110A, 110B are respectively led out from inside the plurality of gap portions 107A, 107B onto the source electrode 32 to cover the peripheral edge portion of the source electrode 32.

The aforementioned gate terminal electrode 50 is arranged on the gate electrode 30 as in the case of the first embodiment. The gate terminal electrode 50 is arranged in the central portion of the first main surface 3 (the active surface 8) in this embodiment. That is, when the first straight line L1 (see two-dot chain line portion) crossing the central portion of the first main surface 3 in the first direction X and the second straight line L2 (see two-dot chain line portion) crossing the central portion of the first main surface 3 in the second direction Y are set, the gate terminal electrode 50 is arranged so as to overlap the intersection portion Cr of the first straight line L1 and the second straight line L2.

The semiconductor device 1G in this embodiment includes a plurality of source terminal electrodes 60 arranged on the source electrode 32. The plurality of source terminal electrodes 60 are respectively arranged on the source electrode 32 at intervals from the plurality of gap portions 107A, 107B and face each other in the first direction X in plan view. The plurality of source terminal electrodes 60 in this embodiment are arranged so that the plurality of gap portions 107A, 107B are exposed.

The plurality of source terminal electrodes 60 in this embodiment are each formed in a shape of a band extending along the source electrode 32 (more specifically, curved in the shape of the letter C along the gate terminal electrode 50) in plan view. The planar shapes of the plurality of source terminal electrodes 60 are arbitrary and may each be formed as a quadrangular shape, a polygonal shape other than the quadrangular shape, a circular shape, or an elliptical shape. The plurality of source terminal electrodes 60 may each include the second protrusion portion 63 disposed on the gap covering portion 110A, 110B of the upper insulating film 38.

The aforementioned sealing insulator 71 covers the plurality of gap portions 107A, 107B in a region between the plurality of source terminal electrodes 60 in this embodiment. The aforementioned sealing insulator 71 covers the plurality of gap covering portions 110A, 110B in a region between the plurality of source terminal electrodes 60 in this embodiment. That is, the sealing insulator 71 covers the plurality of gate wirings 36A, 36B with the plurality of gap covering portions 110A, 110B disposed therebetween.

In this embodiment, an example was shown in which the upper insulating film 38 has the gap covering portion 110A, 110B. However, the presence or absence of the plurality of gap covering portions 110A, 110B is arbitrary, and the upper insulating film 38 may be formed without the plurality of gap covering portions 110A, 110B. In this case, the plurality of source terminal electrodes 60 are formed on the source electrode 32 so as to expose the gate wirings 36A, 36B.

The sealing insulator 71 directly covers the gate wirings 36A, 36B and electrically insulates the gate wirings 36A, 36B from the source electrode 32. The sealing insulator 71 directly covers a part of the interlayer insulating film 27 exposed from a region between the source electrode 32 and the gate wirings 36A, 36B within the plurality of gap portions 107A, 107B.

As described above, the semiconductor device 1G achieves the same effects as the semiconductor device 1A. In the manufacturing method of the semiconductor device 1G, the wafer structure 80 in which structures corresponding to the semiconductor device 1G are formed in each device region 86 is prepared, and similar steps to those in the manufacturing method of the semiconductor device 1A are performed. Therefore, the manufacturing method of the semiconductor device 1G achieves the same effects as the manufacturing method of the semiconductor device 1A.

The structure in which the gate electrode 30 and the gate terminal electrode 50 are arranged at the central portion of the chip 2 can be applied to the second to sixth embodiments. Also, the semiconductor device 1G can be integrated into the semiconductor package 201A. Therefore, the same effects as those of the semiconductor package 201A including the semiconductor device 1A are also achieved with the semiconductor package 201A including the semiconductor device 1G.

24 is a plan view showing a semiconductor device 1H according to an eighth embodiment. 25 is a cross-sectional view along the 24 shown line XXV-XXV. The semiconductor device 1H includes the aforementioned chip 2. The chip 2 is free of the mesa portion 11 in this embodiment and has the flat first main surface 3. The semiconductor device 1H has an SBD (Schottky Barrier Diode) structure 120 formed as an example of a diode in the chip 2.

The semiconductor device 1H includes an n-type diode region 121 formed in an inner portion of the first main surface 3. The diode region 121 is formed by using a part of the first semiconductor region 6 in this embodiment.

The semiconductor device 1H includes a p-type protection region 122 that separates the diode region 121 from other regions on the first main surface 3. The protection region 122 is formed in a surface layer portion of the first semiconductor region 6 at a distance from a peripheral edge of the first main surface 3. The protection region 122 is formed in a ring shape (square ring shape in this embodiment) around the diode region 121 in plan view in this embodiment. The protection region 122 has an inner end portion on the diode region 121 side and an outer end portion on the peripheral edge side of the first main surface 3.

The semiconductor device 1H includes the aforementioned main surface insulating film 25 that selectively covers the first main surface 3. The main surface insulating film 25 has a diode opening 123 that exposes the diode region 121 and the inner end portion of the protection region 122. The main surface insulating film 25 is formed at a distance inward from the peripheral edge of the first main surface 3 and exposes the first main surface 3 (the first semiconductor region 6) from the peripheral edge portion of the first main surface 3. Of course, the main surface insulating film 25 may cover the peripheral edge portion of the first main surface 3. In this case, the peripheral edge portion of the main surface insulating film 25 may be continuous with the first to fourth side surfaces 5A to 5D.

The semiconductor device 1H includes a first polar electrode 124 (main surface electrode) disposed on the first main surface 3. The first polar electrode 124 is an "anode electrode" in this embodiment. The first polar electrode 124 is disposed at a distance inward from the peripheral edge of the first main surface 3. The first polar electrode 124 is formed quadrangularly along the peripheral edge of the first main surface 3 in plan view in this embodiment. The first polar electrode 124 enters the diode opening 123 from the main surface insulating film 25 and is electrically connected to the first main surface 3 and the inner end portion of the protection region 122.

The first polar electrode 124 forms a Schottky junction with the diode region 121 (the first semiconductor region 6). This forms the SBD structure 120. A planar area of the first polar electrode 124 is preferably not less than 50% of the first main surface 3. More preferably, the planar area of the first polar electrode 124 is not less than 75% of the first main surface 3. The first polar electrode 124 may have a thickness of not less than 0.5 µm and not more than 15 µm.

The first polar electrode 124 may have a laminated structure including a Ti-based metal film and an Al-based metal film. The Ti-based metal film may have a single-layer structure composed of a Ti film or a TiN film. The Ti-based metal film may have a laminated structure including the Ti film and the TiN film laminated in any order. The Al-based metal film is preferably thicker than the Ti-based metal film. The Al-based metal film may include at least one of a pure Al film (Al film with a purity of not less than 99%), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film.

The semiconductor device 1H includes the aforementioned upper insulating film 38 that selectively covers the main surface insulating film 25 and the first polar electrode 124. The upper insulating film 38 has the laminated structure including the inorganic insulating film 42 and the organic insulating film 43 laminated in this order from the chip 2 side as in the case of the first embodiment. The upper insulating film 38 in this embodiment has a contact hole 125 that exposes an inner portion of the first polar electrode 124 and covers a peripheral edge portion of the first polar electrode 124 over an entire circumference in plan view. The contact hole 125 in this embodiment is formed into a square in plan view.

The upper insulating film 38 is formed at a distance inward from the peripheral edge of the first main surface 3 (the first to fourth side surfaces 5A to 5D) and defines the dicing line 41 with the peripheral edge of the first main surface 3. The dicing line 41 is formed in a band shape extending along the peripheral edge of the first main surface 3 in plan view. The dicing line 41 in this embodiment is formed in a ring shape (specifically, a square ring shape) around the inner portion of the first main surface 3 in plan view.

In this embodiment, the dicing line 41 exposes the first main surface 3 (the first semiconductor region 6). Of course, in a case where the main surface insulating film 25 covers the peripheral edge portion of the first main surface 3, the dicing line 41 may expose the main surface insulating film 25. The upper insulating film 38 preferably has a thickness exceeding the thickness of the first polar electrode 124. The thickness of the upper insulating film 38 may be less than the thickness of the chip 2.

The semiconductor device 1H has a terminal electrode 126 arranged on the first polar electrode 124. The terminal electrode 126 is erected in a columnar manner on a portion of the first polar electrode 124 exposed from the contact hole 125. The terminal electrode 126 may have a smaller area in plan view than the area of the first polar electrode 124 and may be arranged on an inner portion of the first polar electrode 124 may be arranged at a distance from the peripheral edge of the first polar electrode 124. The terminal electrode 126 is formed in a polygonal shape (a quadrangular shape in this embodiment) in which the four sides are parallel to the first to fourth side surfaces 5A to 5D in plan view.

The connection electrode 126 has a connection surface 127 and a connection side wall 128. The connection surface 127 extends flat along the first main surface 3. The connection surface 127 can be composed of a ground surface with grinding marks. The connection side wall 128 is located on the upper insulating film 38 (in particular the organic insulating film 43) in this embodiment.

That is, a portion of the terminal electrode 126 is in contact with the inorganic insulating film 42 and the organic insulating film 43. The terminal side wall 128 extends substantially vertically to the normal direction Z. Here, "substantially vertically" includes a mode that extends in the laminate direction while being curved (meandering). The terminal side wall 128 includes a portion facing the first polar electrode 124 with the upper insulating film 38 interposed therebetween. The terminal side wall 128 is preferably composed of a smooth surface without a grinding mark.

The terminal electrode 126 has a protruding portion 129 protruding outward at a lower end portion of the terminal side wall 128. The protruding portion 129 is formed in a region on the side of the upper insulating film 38 (the organic insulating film 43) as an intermediate portion of the terminal side wall 128. The protruding portion 129 extends along the outer surface of the upper insulating film 38 and is formed in a tapered shape in which a thickness gradually decreases in cross-sectional view from the terminal side wall 128 toward the tip portion. The protruding portion 129 therefore has a sharp-edged tip portion having an acute angle. Of course, the terminal electrode 126 may be formed without the protruding portion 129.

The connection electrode 126 preferably has a thickness that is greater than the thickness of the first polar electrode 124. More preferably, the thickness of the connection electrode 126 exceeds the thickness of the upper insulating film 38. The thickness of the connection electrode 126 in this embodiment exceeds the thickness of the chip 2. Of course, the thickness of the connection electrode 126 can be less than the thickness of the chip 2.

The thickness of the connection electrode 126 can be not less than 10 µm and not more than 300 µm. The thickness of the connection electrode 126 is preferably not less than 30 µm. More preferably, the thickness of the connection electrode 126 is not less than 80 µm and not more than 200 µm. The connection electrode 126 preferably has a planar area of not less than 50% of the first main surface 3. More preferably, the connection electrode 126 has a planar area of at least 75% of the first main surface 3.

The terminal electrode 126 has a laminated structure including, in this embodiment, a first conductor film 133 and a second conductor film 134 laminated in this order from the first polar electrode 124 side. The first conductor film 133 may include a Ti-based metal film. The first conductor film 133 may have a single-layer structure composed of a Ti film or a TiN film.

The first conductor film 133 may have a laminated structure including the Ti film and the TiN film laminated in any order. The first conductor film 133 has a thickness smaller than the thickness of the first polar electrode 124. The first conductor film 133 covers the first polar electrode 124 in the form of a film inside the contact hole 125 and is extended in the form of a film onto the upper insulating film 38. The first conductor film 133 forms a part of the protrusion portion 129. The first conductor film 133 may not necessarily be formed and may be omitted.

The second conductor film 134 forms a body of the terminal electrode 126. The second conductor film 134 may include a Cu-based metal film. The Cu-based metal film may be a pure Cu film (Cu film with a purity of not less than 99%) or a Cu alloy film. The second conductor film 134 includes a pure Cu plating film in this embodiment. The second conductor film 134 preferably has a thickness that exceeds the thickness of the first polar electrode 124. More preferably, the thickness of the second conductor film 134 exceeds the thickness of the upper insulating film 38. The thickness of the second conductor film 134 exceeds the thickness of the chip 2 in this embodiment.

The second conductor film 134 covers the first polar electrode 124 with the first conductor film 133 arranged therebetween within the contact opening nition 125 and is led out in the form of a film onto the upper insulating film 38 with the first conductor film 133 interposed therebetween. The second conductor film 134 forms a part of the protrusion portion 129. That is, the protrusion portion 129 has a laminated structure including the first conductor film 133 and the second conductor film 134. The second conductor film 134 has a thickness exceeding the thickness of the first conductor film 133 in the protrusion portion 129.

The semiconductor device 1H includes the aforementioned sealing insulator 71 covering the first main surface 3. The sealing insulator 71 includes the first matrix resin 74, the plurality of first fillers 75, and the plurality of first flexible particles 76 (flexible agent). The sealing insulator 71 covers a periphery of the terminal electrode 126 in this embodiment such that a part of the terminal electrode 126 is exposed on the first main surface 3. Specifically, the sealing insulator 71 exposes the terminal surface 127 and covers the terminal side wall 128. The sealing insulator 71 covers the protrusion portion 129 in this embodiment and faces the upper insulating film 38 with the protrusion portion 129 interposed therebetween. The sealing insulator 71 suppresses the terminal electrode 126 from falling off.

The sealing insulator 71 has a portion that directly covers the upper insulating film 38. The sealing insulator 71 covers the first polar electrode 124 with the upper insulating film 38 interposed therebetween. The sealing insulator 71 covers the dicing line 41 defined by the upper insulating film 38 at the peripheral edge portion of the first main surface 3. The sealing insulator 71 directly covers the first main surface 3 (the first semiconductor region 6) at the dicing line 41 in this embodiment. Of course, in a case where the main surface insulating film 25 is exposed from the dicing line 41, the sealing insulator 71 may directly cover the main surface insulating film 25 at the dicing line 41.

The sealing insulator 71 preferably has a thickness that exceeds the thickness of the first polar electrode 124. More preferably, the thickness of the sealing insulator 71 exceeds the thickness of the upper insulating film 38. The thickness of the sealing insulator 71 in this embodiment exceeds the thickness of the chip 2. Of course, the thickness of the sealing insulator 71 may be less than the thickness of the chip 2. The thickness of the sealing insulator 71 may be not less than 10 µm and not more than 300 µm. The thickness of the sealing insulator 71 is preferably not less than 30 µm. More preferably, the thickness of the sealing insulator 71 is not less than 80 µm and not more than 200 µm.

The sealing insulator 71 has the insulating main surface 72 and the insulating side wall 73. The insulating main surface 72 extends flat along the first main surface 3. The insulating main surface 72 forms a single flat surface with the connection surface 127. The insulating main surface 72 can be composed of a ground surface with grinding marks. In this case, the insulating main surface 72 preferably forms a single ground surface with the connection surface 127.

The insulating side wall 73 extends from the peripheral edge of the insulating main surface 72 toward the chip 2 and is continuous with the first to fourth side surfaces 5A to 5D. The insulating side wall 73 is formed substantially perpendicular to the insulating main surface 72. The angle that the insulating side wall 73 forms with the insulating main surface 72 may be not less than 88° and not more than 92°. The insulating side wall 73 may be composed of a ground surface having grinding marks. The insulating side wall 73 may form a single ground surface with the first to fourth side surfaces 5A to 5D.

The semiconductor device 1H includes a second polar electrode 136 (second main surface electrode) covering the second main surface 4. The second polar electrode 136 is a "cathode electrode" in this embodiment. The second polar electrode 136 is electrically connected to the second main surface 4. The second polar electrode 136 forms an ohmic contact with the second semiconductor region 7 exposed from the second main surface 4. The second polar electrode 136 may cover an entire region of the second main surface 4 so as to be continuous with the peripheral edge of the chip 2 (the first to fourth side surfaces 5A to 5D).

The second polar electrode 136 may cover the second main surface 4 at a distance from the peripheral edge of the chip 2. The second polar electrode 136 is configured such that a voltage of not less than 500 V and not more than 3000 V is to be applied between the terminal electrode 126 and the second polar electrode 136. That is, the chip 2 is configured such that a voltage of not less than 500 V and not more than 3000 V is to be applied between the first main surface 3 and the second main surface 4.

As described above, the semiconductor device 1H includes the chip 2, the first polar electrode 124 (main surface electrode), the terminal electrode 126, and the sealing insulator 71. The chip 2 has the first main surface 3. The first polar electrode 124 is arranged on the first main surface 3 at a distance from the periphery of the first main surface 3. The terminal electrode 126 is arranged on the first polar electrode 124. The sealing insulator 71 covers the periphery of the terminal electrode 126 on the first main surface 3 so that a part of the terminal electrode 126 is exposed. The sealing insulator 71 includes the first matrix resin 74 and the plurality of first fillers 75.

According to this structure, a strength of the sealing insulator 71 can be adjusted by the first matrix resin 74 and the plurality of first fillers 75. Also according to this structure, an object to be sealed can be protected from external forces and moisture by the sealing insulator 71. That is, the object to be sealed can be protected from damage (including peeling) due to external forces and deterioration (including corrosion) due to moisture. In this way, it is possible to prevent shape defects and variations in electrical characteristics. As a result, it is possible to provide the semiconductor device 1H that can improve reliability.

Thus, the semiconductor device 1H can achieve the same effects as the semiconductor device 1A. In the manufacturing method of the semiconductor device 1H, the wafer structure 80 in which structures corresponding to the semiconductor device 1H are formed in each device region 86 is prepared, and similar steps to those in the manufacturing method of the semiconductor device 1A are performed. Therefore, the manufacturing method of the semiconductor device 1H can achieve the same effects as the manufacturing method of the semiconductor device 1A.

27 is a plan view showing a semiconductor package 201B in which the semiconductor device 1H according to the eighth embodiment is to be mounted. The semiconductor package 201B may also be referred to as a "semiconductor module". Referring to 27 Like the semiconductor package 201A, the semiconductor package 201B includes the metal plate 202, the plurality of (two in this embodiment) lead terminals 209, the conductive adhesive 210, the plurality of lead wires 211 (conductive connection members), and the package body 212. The semiconductor package 201B includes the semiconductor device 1H instead of the semiconductor device 1A. Differences from the semiconductor package 201A will be described below.

A plurality of lead terminals 209 are arranged at a distance from the metal plate 202, and the other lead terminals 209 are formed integrally with the die pad 206. The semiconductor device 1H is arranged on the die pad 206 within the package body 212. The semiconductor device 1H is arranged on the die pad 206 in a position where the second polar electrode 136 faces the die pad 206, and is electrically connected to the die pad 206.

The conductive adhesive 210 is disposed between the second polar electrode 136 and the die pad 206 and bonds the semiconductor device 1H to the die pad 206. At least one (four in this embodiment) lead wire 211 is electrically connected to the terminal electrode 126 and the lead terminal 209.

The case body 212 includes the second matrix resin 216, the plurality of second fillers 217, and the plurality of second flexible particles 218 as in the case of the first embodiment. The description given in the first embodiment applies to the description of the second matrix resin 216, the plurality of second fillers 217, and the plurality of second flexible particles 218. Other specific configurations of the case body 212 and the aspect of covering the semiconductor device 1H with the case body 212 are the same as the configuration of the case body 212 and the aspect of covering the semiconductor device 1A with the case body 212 according to the first embodiment, and therefore will not be described.

As described above, the semiconductor package 201B includes the die pad 206, the semiconductor device 1H, and the package body 212. The semiconductor device 1H is arranged on the die pad 206. The semiconductor device 1H includes the chip 2, the first polar electrode 124 (the main surface electrode), the terminal electrode 126, and the sealing insulator 71. The chip 2 has the first main surface 3. The first polar electrode 124 is arranged on the first main surface 3. The terminal electrode 126 is arranged on the first polar electrode 124.

The sealing insulator 71 covers the periphery of the terminal electrode 126 on the first main surface 3 so that a part of the terminal electrode 126 is exposed. The sealing insulator 71 includes the first matrix resin 74 and the plurality of first fillers 75. The case body 212 seals the die pad 206 and the semiconductor device 1H to cover the sealing insulator 71. The package body 212 encloses the second matrix resin 216 and the plurality of second fillers 217.

According to this structure, the mechanical strength of the case body 212 can be adjusted with the second matrix resin 216 and the plurality of second fillers 217. According to the structure, the case body 212 also enables the semiconductor device 1H to be protected from external forces and/or moisture. That is, it is possible to protect the semiconductor device 1H from damage by external forces and/or deterioration by moisture. Thereby, shape errors and deviations in electrical characteristics of, for example, the semiconductor device 1H can be reduced.

On the other hand, the sealing insulator 71 enables the sealing target to be protected from external forces and/or moisture via the package body 212 on the semiconductor device 1H side. That is, it is possible to protect the sealing target from damage by external forces via the package body 212 and/or deterioration by moisture via the package body 212. Thereby, shape errors and deviations in electrical characteristics of, for example, the semiconductor device 1H can be reduced. As a result, it is possible to provide the semiconductor package 201B that can improve reliability.

Below are shown modified examples that can be applied to each embodiment. 27 is a perspective view showing a housing 201C in which the semiconductor device 1A of 1 and the 24 semiconductor device 1H shown are to be incorporated. 28 is an exploded perspective view of the 27 shown housing 201C. 29 is a cross-sectional view along the 27 shown line XXIX-XXIX. The package 201C may be referred to as a "semiconductor package" or a "semiconductor module".

Regarding 27 to 29 the semiconductor package 201C includes a first metal plate 230. The first metal plate 230 integrally includes a first die pad 231 and a first lead terminal 232. The first die pad 231 is formed in a rectangular shape in plan view. The first die pad 231 has a first plate surface 233 on one side, a second plate surface 234 on the other side, and first to fourth plate side surfaces 235A to 235D connecting the first plate surface 233 and the second plate surface 234.

The first plate surface 233 is an arrangement surface for the semiconductor device 1A and the semiconductor device 1H. The first plate side surface 235A and the second plate side surface 235B extend in the first direction X and face each other in the second direction Y. The third plate side surface 235C and the fourth plate side surface 235D extend in the second direction Y and face each other in the first direction X.

The first lead terminal 232 is led out in a band shape extending in the second direction Y from the first plate side surface 235A of the first die pad 231. The first lead terminal 232 is positioned on the first plate side surface 235A side in plan view. The first lead terminal 232 is led out to be positioned higher than the first plate surface 233 of the first die pad 231 (on the opposite side of the second plate surface 234).

The semiconductor package 201C includes a second metal plate 240 arranged at a distance from the first metal plate 230 in the normal direction Z of the first metal plate 230 (the first plate surface 233). The second metal plate 240 includes a second die pad 241 and a second lead terminal 242. The second die pad 241 is arranged at a distance from the first die pad 231 in the normal direction Z so as to face the first die pad 231. The second die pad 241 is formed in a rectangular shape in plan view.

The second die pad 241 has a first plate surface 243 on one side, a second plate surface 244 on the other side, and first to fourth plate side surfaces 245A to 245D connecting the first plate surface 243 and the second plate surface 244. The first plate surface 243 faces the first die pad 231 and serves as a connection surface for electrically connecting to the semiconductor device 1A and the semiconductor device 1H. The first plate side surface 245A and the second plate side surface 245B extend in the first direction X and face each other in the second direction Y. The third plate side surface 245C and the fourth plate side surface 245D extend in the second direction Y and face each other in the first direction X.

The second lead terminal 242 is led out in a band shape extending in the second direction Y from the first plate side surface 245A of the second die pad 241. The second lead terminal 242 is formed at a position extending in the first direction X from the first lead necting terminal 232 is shifted. The second lead terminal 242 is positioned on the second plate side surface 245B side in plan view and is not opposite to the first lead terminal 232 in the normal direction Z in this embodiment. The second lead terminal 242 is drawn to be positioned lower than the first plate surface 243 of the second die pad 241 (on the side of the first die pad 231). The second lead terminal 242 has a length with respect to the second direction Y that is different from a length of the first lead terminal 232.

The semiconductor package 201C includes a plurality (five in this embodiment) of third lead terminals 250 arranged at a distance from the first metal plate 230 and the second metal plate 240. The plurality of third lead terminals 250 are arranged within a region between the first metal plate 230 (the first die pad 231) and the second metal plate 240 (the second die pad 241) on the third plate side surface 235C side of the first metal plate 230 (on the third plate side surface 245C side of the second metal plate 240) in this embodiment.

The plurality of third lead terminals 250 are each formed in a band shape extending in the second direction Y. The plurality of third lead terminals 250 may each have a curved portion recessed toward one side or the other side of the normal direction Z. The plurality of third lead terminals 250 may be arranged arbitrarily. The plurality of third lead terminals 250 are arranged to be positioned collinearly with the first lead terminal 232 in plan view in this embodiment.

The semiconductor package 201C encloses the semiconductor device 1A (a first semiconductor device) disposed on the first metal plate 230 in a region between the first metal plate 230 and the second metal plate 240. Specifically, the semiconductor device 1A is disposed on the first plate surface 233 of the first die pad 231. The semiconductor device 1A is disposed on the third plate side surface 235C of the first die pad 231 in plan view. The semiconductor device 1A is disposed on the first die pad 231 in a position where the drain electrode 77 faces the first die pad 231 and is electrically connected to the first die pad 231.

The semiconductor package 201C encloses the semiconductor device 1H (a second semiconductor device) disposed on the first metal plate 230 at a distance from the semiconductor device 1A in a region between the first metal plate 230 and the second metal plate 240. Specifically, the semiconductor device 1H is disposed on the first plate surface 233 of the first die pad 231. The semiconductor device 1H is disposed on the fourth plate side surface 235D of the first die pad 231 in plan view. The semiconductor device 1H is disposed on the first die pad 231 in a position where the second polar electrode 136 faces the first die pad 231 and is electrically connected to the first die pad 231.

The semiconductor package 201C includes a first conductor spacer 261 (a first conductive connection member) disposed between the semiconductor device 1A and the second metal plate 240, and a second conductor spacer 262 (a second conductive connection member) disposed between the semiconductor device 1H and the second metal plate 240. The first conductor spacer 261 is electrically connected to the source terminal electrode 60 of the semiconductor device 1A and the second die pad 241. The second conductor spacer 262 is disposed between the semiconductor device 1H and the second die pad 241, and is electrically connected to the semiconductor device 1H and the second die pad 241.

The first conductor spacer 261 and the second conductor spacer 262 may each include a metal plate (e.g., a Cu-based metal plate). The second conductor spacer 262 may be integrally formed with the first conductor spacer 261, although it is formed separately from the first conductor spacer 261 in this embodiment.

The semiconductor package 201C includes the first to sixth conductive adhesives 271 to 276. The first to sixth conductive adhesives 271 to 276 may include a solder or a metal paste. The solder may be a lead-free solder. The metal paste may include at least one of Au, Ag, and Cu. The Ag paste may be composed of an Ag sintering paste. The Ag sintering paste is composed of a paste in which nano-sized or micro-sized Ag particles are added to an organic solvent.

The first conductive adhesive 271 is located between the drain electrode 77 and the first die pad 231 and electrically and mechanically bonds the semiconductor device 1A to the first die pad 231. The second conductive adhesive 272 is located between the second polar electrode 136 and the second die pad 241 and electrically and mechanically bonds the semiconductor device 1H to the first die pad 231.

The third conductive adhesive 273 is disposed between the source terminal electrode 60 and the first conductor spacer 261 and electrically and mechanically bonds the first conductor spacer 261 to the source terminal electrode 60. The fourth conductive adhesive 274 is disposed between the terminal electrode 126 and the second conductor spacer 262 and electrically and mechanically bonds the second conductor spacer 262 to the terminal electrode 126.

The fifth conductive adhesive 275 is disposed between the second die pad 241 and the first conductor spacer 261 and electrically and mechanically connects the first conductor spacer 261 to the second die pad 241. The sixth conductive adhesive 276 is disposed between the second die pad 241 and the second conductor spacer 262 and electrically and mechanically connects the second conductor spacer 262 to the second die pad 241.

The semiconductor package 201C includes at least one (in this embodiment, a plurality) of the aforementioned lead wires 211 arranged to electrically connect the gate terminal electrodes 50 of the semiconductor device 1A to at least one (in this embodiment, a plurality) of the third lead terminals 250.

The semiconductor package 201C includes the aforementioned package body 212 having a substantially rectangular parallelepiped shape. The package body 212 seals the first metal plate 230 (the first die pad 231), the second metal plate 240 (the second die pad 241), the semiconductor device 1A, the semiconductor device 1H, the first lead spacer 261, the second lead spacer 262, the first to sixth conductive adhesives 271 to 276, and the plurality of lead wires 211 in this embodiment so that a part of the first lead terminal 232, a part of the second lead terminal 242, and a part of the plurality of third lead terminals 250 are exposed.

The housing body 212 has the first surface 213, the second surface 214 and the first to fourth side walls 215A to 215D as in the case of the first embodiment. The first surface 213 is positioned on the side of the first plate surface 233 of the first metal plate 230. The second surface 214 is positioned on the side of the second plate surface 244 of the second metal plate 240.

The first side wall 215A is positioned on the first plate side surface 235A side of the first metal plate 230 and extends along the first plate side surface 235A. The second side wall 215B is positioned on the second plate side surface 235B side of the first metal plate 230 and extends along the second plate side surface 235B. The third side wall 215C is positioned on the third plate side surface 235C side of the first metal plate 230 and extends along the third plate side surface 235C. The fourth side wall 215D is positioned on the fourth plate side surface 235D side of the first metal plate 230 and extends along the fourth plate side surface 235D.

The package body 212 has, for the structure on the semiconductor device 1A side, a portion that directly covers the first to fourth side surfaces 5A to 5D of the chip 2, a portion that directly covers the insulating main surface 72 of the sealing insulator 71, and a portion that directly covers the straightness of the sealing insulator 71. The package body 212 covers the insulating main surface 72 and the insulating side wall 73 by filling the grinding marks of the insulating main surface 72 and the grinding marks of the insulating side wall 73. The package body 212 also has a portion that directly covers a portion of the gate terminal surface 51 of the gate terminal electrode 50 exposed by the lead wires 211, and a portion that directly covers a portion of the source terminal surface 61 of the source terminal electrode 60 exposed by the lead wires 211.

The package body 212 also has, for the structure on the semiconductor device 1H side, a portion that directly covers the first to fourth side surfaces 5A to 5D of the chip 2, a portion that directly covers the insulating main surface 72 of the sealing insulator 71, and a portion that directly covers the straightness of the sealing insulator 71. The package body 212 covers the insulating main surface 72 and the insulating side wall 73 by filling the grinding marks of the insulating main surface 72 and the grinding marks of the insulating side wall 73. The package body 212 also has a portion that directly covers a portion of the terminal surface 127 of the terminal electrode 126 exposed by the lead wires 211.

The housing body 212 covers the first die pad 231 of the first metal plate 230 and exposes the first lead terminal 232 for the structure on the outside of the semiconductor device 1A and the semiconductor device 1H. The housing body 212 has a portion that directly covers the first plate surface 233 of the first die pad 231 and a portion that covers the first to fourth Plate side surface 235A to 235D of the first die pad 231 is directly covered.

In this embodiment, the package body 212 exposes the second plate surface 234 of the first die pad 231 through the first surface 213. The first surface 213 forms a single flat surface with the second plate surface 234 of the first die pad 231 in this embodiment. Of course, the package body 212 may cover part or all of the second plate surface 234 of the first die pad 231. The package body 212 may also cover the entire area of the first die pad 231.

The package body 212 covers the second die pad 241 of the second metal plate 240 and exposes the second lead terminal 242. The package body 212 has a portion that directly covers the first plate surface 243 of the second die pad 241 and a portion that directly covers the first to fourth plate side surfaces 245A to 245D of the second die pad 241.

In this embodiment, the package body 212 exposes the second plate surface 244 of the second die pad 241 through the second surface 214. The second surface 214 forms a single flat surface with the second plate surface 244 of the second die pad 241 in this embodiment. Of course, the package body 212 may cover part or all of the second plate surface 244 of the second die pad 241. The package body 212 may also cover the entire area of the second die pad 241.

The case body 212 includes the second matrix resin 216, the plurality of second fillers 217, and the plurality of second flexible particles 218 as in the case of the first embodiment. The description given in the first embodiment applies to the description of the second matrix resin 216, the plurality of second fillers 217, and the plurality of second flexible particles 218. Other specific configurations of the case body 212, the aspect of covering the semiconductor device 1A by the case body 212, and the aspect of covering the semiconductor device 1H by the case body 212 are as mentioned above and therefore will not be described.

As described above, according to the semiconductor package 201C, the same effects as those of the semiconductor package 201A and those of the semiconductor package 201B are achieved. This embodiment describes the semiconductor package 201C enclosing the semiconductor device 1A. However, the semiconductor package 201C may also enclose any of the semiconductor devices 1B to 1G according to the second to seventh embodiments instead of the semiconductor device 1A.

This embodiment also illustrates an example in which the source terminal electrode 60 is connected to the first die pad 231 via the first conductor spacer 261. However, the source terminal electrode 60 may be connected to the first die pad 231 not via the first conductor spacer 261 but via the third conductive adhesive 273. This embodiment also illustrates an example in which the terminal electrode 126 is connected to the first die pad 231 via the second conductor spacer 262. However, the terminal electrode 126 may be connected to the first die pad 231 not via the second conductor spacer 262 but via the fourth conductive adhesive 274.

30 is a cross-sectional view showing a modified example of the chip 2 to be applied to each embodiment. In 30 , a mode in which the modified example of the chip 2 is applied to the semiconductor device 1A is shown as an example. However, the modified example of the chip 2 may be applied to any of the second to eighth embodiments. Referring to 30 the semiconductor device 1A does not have the second semiconductor region 7 within the chip 2 and may only have the first semiconductor region 6 within the chip 2.

In this case, the first semiconductor region 6 is exposed from the first main surface 3, the second main surface 4 and the first to fifth side surfaces 5A to 5D of the chip 2. That is, the chip 2 in this embodiment has a single-layer structure which does not have the semiconductor substrate and which is composed of the epitaxial layer. The chip 2 having such a structure is manufactured by completely removing the second semiconductor region 7 (the semiconductor substrate) in the manner described in the above-mentioned 13H shown step.

31 is a cross-sectional view showing a modified example of the sealing insulator 71 to be applied to each embodiment. In 31 , a mode in which the modified example of the sealing insulator 71 is applied to the semiconductor device 1A is shown as an example. However, the modified example of the sealing insulator 71 may be applied to any of the second to tenth embodiments. Referring to 31 the semiconductor device 1A can seal the ation insulator 71 covering an entire area of the upper insulating film 38.

In this case, in the first to seventh embodiments, the gate terminal electrode 50 and the source terminal electrode 60 are formed which are not in contact with the upper insulating film 38. In this case, the sealing insulator 71 may have a portion which directly covers the gate electrode 30 and the source electrode 32. On the other hand, in the eighth embodiment, the terminal electrode 126 is formed which is not in contact with the upper insulating film 38. In this case, the sealing insulator 71 may have a portion which directly covers the first polar electrode 124.

Each of the above embodiments can be implemented in still other embodiments. For example, the features disclosed in the above first to eighth embodiments can be appropriately combined with each other. Therefore, a configuration including at least two features of the features disclosed in the above first to eighth embodiments at the same time can be adopted.

In each of the above embodiments, the chip 2 having the mesa portion 11 has been shown. However, the chip 2 which does not have the mesa portion 11 and whose first main surface 3 extends flat may also be used. In this case, the sidewall structure 26 may be omitted.

In each of the above embodiments, the configurations with the source wiring 37 were shown. However, configurations without the source wiring 37 may also be used. In each of the above embodiments, the trench gate type gate structure 15 controlling the channel within the chip 2 was shown. However, the planar gate type gate structure 15 controlling the channel from the first main surface 3 may also be used.

In each of the above embodiments, the configurations in which the MISFET structure 12 and the SBD structure 120 are formed in the different chips 2 have been shown. However, the MISFET structure 12 and the SBD structure 120 may be formed in different regions of the first main surface 3 in the same chip 2. In this case, the SBD structure 120 may be formed as a return diode of the MISFET structure 12.

In each of the embodiments, the configuration in which the "first conductivity type" is the "n-type" and the "second conductivity type" is the "p-type" has been shown. However, a configuration in which the "first conductivity type" is the "p-type" and the "second conductivity type" is the "n-type" may be used in each of the embodiments. The specific configuration in this case can be obtained by replacing the "n-type" with the "p-type" in the above descriptions and the accompanying drawings and at the same time replacing the "p-type" with the "n-type".

In each of the embodiments, the second semiconductor region 7 has been shown to be of “n-type”. However, the second semiconductor region 7 may be of “p-type”. In this case, an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure 12. In this case, in the above descriptions, the “source” of the MISFET structure 12 is replaced with an “emitter” of the IGBT structure, and the “drain” of the MISFET structure 12 is replaced with a “collector” of the IGBT structure. Of course, in a case where the chip 2 has a single-layer structure composed of the epitaxial layer, in the second semiconductor region 7 of “p-type”, p-type impurities may be introduced into a surface layer portion of the second main surface 4 of the chip 2 (the epitaxial layer) by an ion implantation method.

In each of the embodiments, the first direction X and the second direction Y are defined by the extending directions of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be any directions as long as the first direction X and the second direction Y maintain a relationship in which the first direction X and the second direction Y intersect each other (specifically, intersect perpendicularly). For example, the first direction X may be a direction intersecting the first to fourth side surfaces 5A to 5D, and the second direction Y may be a direction intersecting the first to fourth side surfaces 5A to 5D.

Examples of features taken from the present descriptions and the accompanying drawings are given below. Hereinafter, the alphanumeric characters in parentheses represent the corresponding components in the above embodiments, but are not intended to limit the scope of each paragraph to the embodiments. The "semiconductor device" in the following paragraphs may be replaced by a "wide band gap semiconductor device", a "SiC semiconductor device", a "semiconductor switching device" or a "semiconductor rectifying device" as appropriate.

[A1] A semiconductor device (1A to 1H) comprising: a chip (2) having a main surface (3); a main surface electrode (30, 32, 124) arranged on the main surface (3); a terminal electrode (50, 60, 126) arranged on the main surface electrode (30, 32, 124); and a sealing insulator (71) which includes a first matrix resin (74) and first fillers (75) and which covers a periphery of the terminal electrode (50, 60, 126) on the main surface (3) so as to expose a part of the terminal electrode (50, 60, 126).

[A2] The semiconductor device (1A to 1H) according to A1, wherein the first fillers (75) are introduced into the first matrix resin (74) such that a ratio of the first or its total cross-sectional area (“first total cross-sectional area”) to a unit cross-sectional area (“unit cross-sectional area”) is greater than a ratio of a cross-sectional area of the first matrix resin (74) to the unit cross-sectional area.

[A3] The semiconductor device (1A to 1H) according to A2, wherein the ratio of the first total cross-sectional area is not less than 60%.

[A4] The semiconductor device (lA to 1H) according to A1 or A3, wherein the terminal electrode (50, 60, 126) is thicker than the main surface electrode (30, 32, 124) and wherein the sealing insulator (71) is thicker than the main surface electrode (30, 32, 124).

[A5] The semiconductor device (1A to 1H) according to any one of A1 to A4, wherein the terminal electrode (50, 60, 126) is thicker than the chip (2) and the sealing insulator (71) is thicker than the chip (2).

[A6] The semiconductor device (1A to 1H) according to any one of A1 to A5, wherein the first matrix resin (74) is composed of a thermosetting resin.

[A7] The semiconductor device (1A to 1H) according to any one of A1 to A6, wherein the first fillers (75) are each composed of one or both of a spherical object and an indeterminate object.

[A8] The semiconductor device (1A to 1H) according to A7, wherein the first fillers (75) are each composed of the spherical object.

[A9] The semiconductor device (1A to 1H) according to any one of A1 to A8, wherein the first fillers (75) include at least one of ceramics, oxides and nitrides.

[A10] The semiconductor device (1A to 1H) according to any one of A1 to A9, wherein the sealing insulator (71) includes first fillers (75) having different particle sizes.

[A11] The semiconductor device (1A to 1H) according to any one of A1 to A10, wherein the first fillers (75) each have a particle size of not less than 1 nm and not more than 100 µm.

[A12] The semiconductor device (1A to 1H) according to any one of A1 to A11, wherein the first fillers (75) include fillers (75a) that are thinner than the main surface electrode (30, 32, 124) and fillers (75b, 75c) that are thicker than the main surface electrode (30, 32, 124).

[A13] The semiconductor device (1A to 1H) according to any one of A1 to A12, wherein the terminal electrode (50, 60, 126) has a terminal surface (51, 61, 127) and a terminal side wall (52, 62, 128), and wherein the sealing insulator (71) exposes the terminal surface (51, 61, 127) and covers the terminal side wall (52, 62, 128).

[A14] The semiconductor device (1A to 1H) according to A13, wherein the sealing insulator (71) has an insulating main surface (72) forming a single flat surface with the terminal surface (51, 61, 127).

[A15] The semiconductor device (1A to 1H) according to any one of A1 to A14, wherein the chip (2) has a side surface (5A to 5D) and the sealing insulator (71) has an insulating side wall (73) forming a single flat surface with the side surface (5A to 5D).

[A16] The semiconductor device (1A to 1H) according to any one of A1 to A15, further comprising: an insulating film (38) partially covering the main surface electrode (30, 32, 124), wherein the sealing insulator (71) has a portion directly covering the insulating film (38).

[A17] The semiconductor device (1A to 1H) according to A16, wherein the terminal electrode (50, 60, 126) has a portion directly covering the insulating film (38).

[A18] The semiconductor device (1A to 1H) according to A16 or A17, wherein the insulating film (38) includes at least one of an inorganic insulating film (42) and an organic insulating film (43) or both.

[A19] A semiconductor device (1A to 1H) according to any one of A16 to A18, wherein the insulating film (38) is thicker than the main surface electrode (30, 32, 124) and wherein the sealing insulator (71) is thicker than the insulating film (38).

[A20] The semiconductor device (1A to 1H) according to any one of A16 to A19, wherein the first fillers (75) include fillers (75c) that are thicker than the insulating film (38).

[A21] The semiconductor device (1A to 1H) according to any one of A1 to A20, wherein the chip (2) includes a single crystal of a wide band gap semiconductor.

[A22] The semiconductor device (1A to 1H) according to any one of A1 to A21, wherein the chip (2) includes a single crystal of SiC.

[A23] A semiconductor module (201A, 201B, 201C) comprising: an electrode (206, 231); and the semiconductor device (1A to 1H) according to any one of A1 to A22 arranged on the electrode (206, 231).

[B1] A semiconductor package (201A, 201B, 201C) comprising: a die pad (206, 231); the semiconductor device (1A to 1H) according to any one of A1 to A22 arranged on the die pad (206, 231); and a package body (212) that encloses a second matrix resin (216) and second fillers (217) and that seals the die pad (206, 231) and the semiconductor device (1A to 1H) so as to cover the sealing insulator (71).

[B2] The semiconductor package (201A, 201B, 201C) according to B1, wherein the first fillers (75) are added to the first matrix resin (74) at a first density and the second fillers (217) are added to the second matrix resin (216) at a second density different from the first density.

[B3] The semiconductor package (201A, 201B, 201C) according to B2, wherein the second fillers (217) having the second density higher than the first density are added into the second matrix resin (216).

[B4] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B3, wherein the first fillers (75) are added to the first matrix resin (74) to have a first total cross-sectional area in a unit cross-sectional area, and wherein the second fillers (217) are added to the second matrix resin (216) to have a second total cross-sectional area different from the first total cross-sectional area in the unit cross-sectional area.

[B5] The semiconductor package (201A, 201B, 201C) according to B4, wherein the second fillers (217) are added to the second matrix resin (216) to have the second total cross-sectional area exceeding the first total cross-sectional area.

[B6] The semiconductor package (201A, 201B, 201C) according to B4 or B5, wherein the first fillers (75) are added to the first matrix resin (74) such that a ratio of the first total cross-sectional area to the unit cross-sectional area is higher than a ratio of a cross-sectional area of the first matrix resin (74) to the unit cross-sectional area, and wherein the second fillers (217) are added to the second matrix resin (216) such that a ratio of the second total cross-sectional area to the unit cross-sectional area is higher than a ratio of a cross-sectional area of the second matrix resin (216) to the unit cross-sectional area.

[B7] The semiconductor package (201A, 201B, 201C) according to any one of B4 to B6, wherein the ratio of the first total cross-sectional area is not less than 60% and the ratio of the second total cross-sectional area is not less than 60%.

[B8] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B7, wherein the first matrix resin (74) is composed of a thermosetting resin and wherein the second matrix resin (216) is composed of a thermosetting resin.

[B9] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B8, wherein the first fillers (75) are each composed of a spherical object and/or an indeterminate object, and wherein the second fillers (217) are each composed of a spherical object and/or an indeterminate object.

[B10] The semiconductor package (201A, 201B, 201C) according to B9, wherein the first fillers (75) are each constructed from the spherical object and wherein the second fillers (217) are each constructed from the spherical object.

[B11] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B10, wherein the first fillers (75) include at least one of ceramics, oxides, and nitrides, and wherein the second fillers (217) include at least one of ceramics, oxides, and nitrides.

[B12] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B11, wherein the sealing insulator (71) encloses the first fillers (75) having different particle sizes and the package body (212) encloses the second fillers (217) having different particle sizes.

[B13] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B12, wherein the first fillers (75) each have a particle size of not less than 1 nm and not more than 100 µm and the second fillers (217) each have a particle size of not less than 1 nm and not more than 100 µm.

[B14] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B13, wherein the sealing insulator (71) includes at least one filler fragment (75d) exposed from an outer surface.

[B15] The semiconductor package (201A, 201B, 201C) according to B14, wherein the second matrix resin (216) includes a portion directly covering the filler fragment (75d) on the outer surface of the sealing insulator (71).

[B16] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B15, wherein the sealing insulator (71) includes at least one filler fragment (75d) covered on an outer surface with the first matrix resin (74).

[B17] The semiconductor package (201A, 201B, 201C) according to B16, wherein the second matrix resin (216) includes a portion indirectly covering the filler fragment (75d) with the first matrix resin (74) sandwiched at the outer surface of the sealing insulator (71).

[B18] The semiconductor package (201A, 201B, 201C) according to any one of B14 to B17, wherein the filler fragment (75d) has a broken portion formed along the outer surface of the sealing insulator (71).

[B19] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B18, wherein the second fillers (217) include a second filler (217) whose particle size in each cross section including the sealing insulator (71) and the package body (212) exceeds the maximum particle size of the first fillers (75).

[B20] Semiconductor package (201A, 201B, 201C) according to B19, wherein a maximum particle size of the second fillers (217) is not smaller than 2 times the maximum particle size of the first fillers (75).

[B21] Semiconductor package (201A, 201B, 201C) according to B20, wherein the maximum particle size of the second fillers (217) is not smaller than 5 times the maximum particle size of the first fillers (75).

[B22] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B21, wherein the package body (212) forms with the sealing insulator (71) a gap portion (219a) extending along an outer surface of the sealing insulator (71).

[B23] The semiconductor package (201A, 201B, 201C) according to B22, wherein the gap portion (219a) extends from a region on the sealing insulator (71) to a region on the terminal electrode (50, 60, 126).

[B24] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B21, wherein the package body (212) forms with the terminal electrode (50, 60, 126) a gap portion (219a) extending along an outer surface of the terminal electrode (50, 60, 126).

[B25] The semiconductor package (201A, 201B, 201C) according to any one of B1 to B24, further comprising: a lead terminal (209, 250) arranged at a distance from the die pad (206, 231); and a lead wire (211) connected to the terminal electrode (50, 60, 126) and the lead terminal (209, 250); wherein the package body (212) seals the die pad (206, 231), the lead terminal (209, 250), the semiconductor device (1A to 1H), and the lead wire (211) such that the lead terminal (209, 250) is partially exposed.

[C1] A semiconductor package (201A, 201B, 201C) comprising: a die pad (206, 231); a semiconductor device (1A to 1H) arranged on the die pad (206, 231) and comprising a chip (2) having a main surface (3), a main surface electrode (30, 32, 124) arranged on the main surface (3), a terminal electrode (50, 60, 126) arranged on the main surface electrode (30, 32, 124), and a sealing insulator (71) that includes a first matrix resin (74) and first fillers (75) and covers a periphery of the terminal electrode (50, 60, 126) on the main surface (3) so that a part of the terminal electrode (50, 60, 126) is exposed; and a package body (212) which encloses a second matrix resin (216) and second fillers (217) and which seals the die pad (206, 231) and the semiconductor device (1A to 1H) so as to cover the sealing insulator (71).

[C2] The semiconductor package (201A, 201B, 201C) according to C1, wherein the chip (2) has a laminated structure including a substrate (7) and an epitaxial layer (6), and has the main surface (3) formed by the epitaxial layer (6).

[C3] The semiconductor package (201A, 201B, 201C) according to C2, wherein the first fillers (75) include at least one filler (75c) that is thicker than the substrate (7).

[C4] The semiconductor package (201A, 201B, 201C) according to C2 or C3, wherein the second fillers (217) include at least one filler (217c) that is thicker than the substrate (7).

[C5] The semiconductor package (201A, 201B, 201C) according to any one of C2 to C4, wherein the first fillers (75) include at least one filler (75c) that is thicker than the epitaxial layer (6).

[C6] The semiconductor package (201A, 201B, 201C) according to any one of C2 to C5, wherein the second fillers (217) include at least one filler (217c) that is thicker than the epitaxial layer (6).

[C7] A semiconductor package (201A, 201B, 201C) according to any one of C2 to C6, wherein the epitaxial layer (6) is thicker than the substrate (7).

[C8] The semiconductor package (201A, 201B, 201C) according to C1, wherein the chip (2) has a laminated structure composed of an epitaxial layer (6) and having the main surface (3) formed by the epitaxial layer (6).

[C9] The semiconductor package (201A, 201B, 201C) according to C8, wherein the first fillers (75) include at least a first filler (75c) that is thicker than the epitaxial layer (6).

[C10] The semiconductor package (201A, 201B, 201C) according to C8 or C9, wherein the second fillers (217) include at least one second filler (217c) that is thicker than the epitaxial layer (6).

[C11] The semiconductor package (201A, 201B, 201C) according to any one of C1 to C10, wherein the first fillers (75) include at least one filler (75c) that is thicker than the chip (2).

[C12] The semiconductor package (201A, 201B, 201C) according to any one of C1 to C11, wherein the second fillers (217) include at least one filler (217c) that is thicker than the chip (2).

The aforementioned [C1] is a clause or paragraph which constitutes the aforementioned [B1] which cites the aforementioned [A1] in its own right, and the aforementioned [C2] to [C12] cite the aforementioned [C1]. The aforementioned [A2] to [A22] and the aforementioned [B2] to [B24] may therefore be adapted in their citation formats and/or expressions to be configured to cite the aforementioned [C1] to [C12].

[D1] A manufacturing method for a semiconductor device (1A to 1H), comprising: a step of preparing a wafer structure (80) including a wafer (81) having a main surface (82) and a main surface electrode (30, 32, 124) arranged on the main surface (82); a step of forming a terminal electrode (50, 60, 126) on the main surface electrode (30, 32, 124); and a step of forming a sealing insulator (71) including a first matrix resin (74) and first fillers (75) and covering a periphery of the terminal electrode (50, 60, 126) on the main surface (82) so as to expose a part of the terminal electrode (50, 60, 126).

[D2] A manufacturing method for the semiconductor device (1A to 1H) according to D1, wherein the first fillers (75) are added to the first matrix resin (74) such that a ratio of a first or total cross-sectional area to a unit cross-sectional area is higher than a ratio of a cross-sectional area of the first matrix resin (74) to the unit cross-sectional area.

[D3] A manufacturing method for the semiconductor device (1A to 1H) according to D1 or D2, wherein the ratio of the first total cross-sectional area is not less than 60%.

[D4] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D3, wherein the step of forming the sealing insulator (71) includes: a step of supplying the first matrix resin (74) composed of a thermosetting resin and a sealing agent (92) including the first fillers (75) to the main surface (82); and a step of forming the sealing insulator (71) by thermally curing the sealing agent (92).

[D5] A manufacturing method for the semiconductor device (1A to 1H) according to D4, wherein the step of forming the sealing insulator (71) includes: a step of supplying the sealant (92) to the main surface (82) so as to cover the entire area of the terminal electrode (50, 60, 126); and a step of partially removing the sealing insulator (71) until a part of the terminal electrode (50, 60, 126) is exposed after the step of thermally curing the sealant (92).

[D6] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D5, wherein the step of forming the terminal electrode (50, 60, 126) includes a step of forming the terminal electrode (50, 60, 126) which thicker than the main surface electrode (30, 32, 124), and the step of forming the sealing insulator (71) includes a step of forming the sealing insulator (71) which is thicker than the main surface electrode (30, 32, 124).

[D7] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D6, further comprising: a step of thinning the wafer (81) after the step of forming the sealing insulator (71).

[D8] A manufacturing method for the semiconductor device (1A to 1H) according to D7, wherein the step of thinning the wafer (81) includes a step of thinning the wafer (81) until the wafer (81) has a thickness smaller than the thickness of the sealing insulator (71).

[D9] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D8, wherein the first fillers (75) are each composed of a spherical object and/or an indeterminate object.

[D10] A manufacturing method for the semiconductor device (1A to 1H) according to D9, wherein the first fillers (75) are each composed of the spherical object.

[D11] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D10, wherein the first fillers (75) include at least one of ceramics, oxides and nitrides.

[D12] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D11, wherein the sealing insulator (71) includes the first fillers (75) having different particle sizes.

[D13] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D12, wherein the first fillers (75) each have a particle size of not less than 1 nm and not more than 100 µm.

[D14] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D13, wherein the first fillers (75) include fillers (75a) that are thinner than the main surface electrode (30, 32, 124) and fillers (75d, 75c) that are thicker than the main surface electrode (30, 32, 124).

[D15] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D14, wherein the step of forming the terminal electrode (50, 60, 126) includes: a step of forming a conductor film (89) covering the main surface electrode (30, 32, 124); a step of forming, on the conductor film (89), a mask (90) exposing a portion of the conductor film (89) covering the main surface electrode (30, 32, 124); a step of depositing a conductor (91) on the portion of the conductor film (89) exposed by the mask (90); and a step of removing the mask (90) after the step of depositing the conductor (91).

[D16] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D15, further comprising: a step of preparing the wafer structure (80) including the wafer (81) having the main surface (82) in which a device region (86) and a planned cutting line (87) defining the device region (86) are defined, and the main surface electrode (30, 32, 124) arranged on the main surface (82) in the device region (86); and a step of cutting the wafer (81) along the planned cutting line (87) after the step of forming the sealing insulator (71).

[D17] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D16, further comprising: a step of forming an insulating film (38) partially covering the main surface electrode (30, 32, 124) before the step of forming the terminal electrode (50, 60, 126); wherein the step of forming the sealing insulator (71) includes a step of forming the sealing insulator (71) covering the terminal electrode (50, 60, 126) and the insulating film (38).

[D18] A manufacturing method for the semiconductor device (1A to 1H) according to D17, wherein the step of forming the terminal electrode (50, 60, 126) includes a step of forming the terminal electrode (50, 60, 126) having a portion directly covering the insulating film (38).

[D19] A manufacturing method for the semiconductor device (1A to 1H) according to D17 or D18, wherein the step of forming the insulating film (38) includes a step of forming the insulating film (38) including one of an inorganic insulating film (42) and an organic insulating film (43) or both.

[D20] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D19, wherein the wafer (81) has a laminated structure including a substrate (7) and an epitaxial layer (6), and has the main surface (82) formed by the epitaxial layer (6).

[D21] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D20, wherein the wafer (81) includes a single crystal of a wide band gap semiconductor.

[D22] A manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D21, wherein the wafer (81) includes a single crystal of SiC.

[E1] A manufacturing method for a semiconductor package (201A, 201B, 201C), comprising: a step of arranging the semiconductor device (1A to 1H) manufactured by the manufacturing method for the semiconductor device (1A to 1H) according to any one of D1 to D22 on a die pad (206, 231); and a step of sealing the semiconductor device (1A to 1H) and the die pad (206, 231) with a resin (226) including a second matrix resin (216) and second fillers (217).

[E2] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to E1, wherein the first fillers (75) are added to the first matrix resin (74) at a first density and the second fillers (217) are added to the second matrix resin (216) at a second density different from the first density.

[E3] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to E2, wherein the second fillers (217) are added in the second matrix resin (216) having the second density higher than the first density.

[E4] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to any one of E1 to E3, wherein the first fillers (75) are added to the first matrix resin (74) to have a first total cross-sectional area in a unit cross-sectional area, and wherein the second fillers (217) are added to the second matrix resin (216) to have a second total cross-sectional area different from the first total cross-sectional area in the unit cross-sectional area.

[E5] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to E4, wherein the second fillers (217) are added to the second matrix resin (216) to have the second total cross-sectional area exceeding the first total cross-sectional area.

[E6] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to E4 or E5, wherein the first fillers (75) are added into the first matrix resin (74) such that a ratio of the first total cross-sectional area to the unit cross-sectional area is higher than a ratio of a cross-sectional area of the first matrix resin (74) to the unit cross-sectional area, and wherein the second fillers (217) are added into the second matrix resin (216) such that a ratio of the second total cross-sectional area to the unit cross-sectional area is higher than a ratio of a cross-sectional area of the second matrix resin (216) to the unit cross-sectional area.

[E7] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to any one of E4 to E6, wherein the ratio of the first total cross-sectional area is not less than 60%, and wherein the ratio of the second total cross-sectional area is not less than 60%.

[E8] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to any one of E1 to E7, wherein the first matrix resin (74) is composed of a thermosetting resin and wherein the second matrix resin (216) is composed of a thermosetting resin.

[E9] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to any one of E1 to E8, wherein the first fillers (75) are each composed of a spherical object and/or an indeterminate object, and wherein the second fillers (217) are each composed of a spherical object and/or an indeterminate object.

[E10] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to E9, wherein the first fillers (75) are each composed of the spherical object and wherein the second fillers (217) are each composed of the spherical object.

[E11] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to any one of E1 to E10, wherein the first fillers (75) include at least one of ceramics, oxides and nitrides, and wherein the second fillers (217) include at least one of ceramics, oxides and nitrides.

[E12] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to any one of E1 to E11, wherein the sealing insulator (71) includes the first fillers (75) having different particle sizes, and wherein the package body (212) includes the second fillers (217) having different particle sizes.

[E13] A manufacturing method for the semiconductor package (201A, 201B, 201C) according to any one of E1 to E12, wherein the first fillers (75) each have a particle size of not less than 1 nm and not more than 100 µm and wherein the second fillers (217) each have a particle size of not less than 1 nm and not more than 100 µm.

[F1] A manufacturing method for a semiconductor package (201A, 201B, 201C), comprising: a step of arranging the semiconductor device (1A to 1H) according to any one of A1 to A22 on a die pad (206, 231); and a step of sealing the die pad (206, 231) and the semiconductor device (1A to 1H) with a resin (226) including a second matrix resin (216) and second fillers (217).

The above [F1] is a clause or paragraph resulting from a modification of the expression or wording of the above [E1]. The above [E2] to [E13] may therefore be adapted in their citation formats or references and/or in their expressions or wording so that they are configured to cite or refer to the above [F1].

While embodiments of the present invention have been described in detail above, these are merely specific examples for illustrating the technical content, and the present invention should not be construed as being limited to these specific examples only, and the spirit and scope of the invention are limited only by the appended claims.

LIST OF REFERENCE SIGNS

1A:

semiconductor device

1B

semiconductor device

1C

semiconductor device

1D

semiconductor device

1E

semiconductor device

1F

semiconductor device

1G

semiconductor device

1H

semiconductor device

2

chip

3

First main interface

5A

First page surface

5B

Second side surface

5C

Third page surface

5D

Fourth side surface

6

First semiconductor region (epitaxial layer)

7

Second semiconductor region (substrate)

30

Gate electrode (main surface electrode)

32

Source electrode (main surface electrode)

38

Upper insulation film

42

Inorganic insulating film

43

Organic insulating film

50

Gate connection electrode

51

Gate connection surface

52

Gate connector side panel

60

Source connection electrode

61

Source connection surface

62

Source connector side panel

71

Sealing insulator

72

Main insulating surface

73

Insulating side wall

74

First matrix resin

75

First filler

75a

First small size filler

75b

First medium size filler

75c

First large size filler

75d

Filler fragment

80

Wafer structure

81

Wafer

82

First wafer main surface

86

Fixture area

87

Planned cutting line

89

Second base conductor film

90

Resist mask

91

Third Base Ladder Film (Ladder)

92

Sealants

124

First polar electrode or first pole forming electrode (main surface electrode)

126

Connection electrode

127

Connection surface

128

Connection side wall

201A

Semiconductor housing

201B

Semiconductor housing

201C

Semiconductor housing

206

Die-Pad

209

Line connection

211

Conductor wire

212

Housing body

216

Second matrix resin

217

Second filler

217a

Second filler small size

217b

Second medium size filler

217c

Second filler large size

219a

Gap section

231

First Die Pad

250

Third line connection

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions.

Cited patent literature

• JP2021181321 [0001]

Claims (20)

A semiconductor package comprising: a die pad; a semiconductor device disposed on the die pad and having a chip with a main surface, a main surface electrode disposed on the main surface, a terminal electrode disposed on the main surface electrode, and a sealing insulator that includes a first matrix resin and first fillers and covers a periphery of the terminal electrode on the main surface to expose a part of the terminal electrode; and a package body that includes a second matrix resin and second fillers and that seals the die pad and the semiconductor device to cover the sealing insulator. Semiconductor housing according to Claim 1 wherein the first fillers are added to the first matrix resin at a first density and wherein the second fillers are added to the second matrix resin at a second density that is different from the first density. Semiconductor housing according to Claim 2 wherein the second fillers are added to the second matrix resin at a second density that is higher than the first density. Semiconductor package according to one of the Claims 1 until 3 wherein the first fillers are added to the first matrix resin to have a first total cross-sectional area in a unit cross-sectional area, and wherein the second fillers are added to the second matrix resin to have a second total cross-sectional area different from the first total cross-sectional area in the unit cross-sectional area. Semiconductor housing according to Claim 4 wherein the second fillers are added to the second matrix resin to have the second total cross-sectional area exceeding the first total cross-sectional area. Semiconductor housing according to Claim 4 or 5 , wherein the first fillers are added to the first matrix resin such that a ratio of the first total cross-sectional area to the unit cross-sectional area is higher than a ratio of a cross-sectional area of the first matrix resin to the unit cross-sectional area, and wherein the second fillers are added to the second matrix resin such that a ratio of the second total cross-sectional area to the unit cross-sectional area is higher than a ratio of a cross-sectional area of the second matrix resin to the unit cross-sectional area. Semiconductor package according to one of the Claims 4 until 6 , wherein a ratio of the first total cross-sectional area is not less than 60% and wherein a ratio of the second total cross-sectional area is not less than 60%. Semiconductor package according to one of the Claims 1 until 7 , wherein the first matrix resin is composed of a thermosetting resin and wherein the second matrix resin is composed of a thermosetting resin. Semiconductor package according to one of the Claims 1 until 8th , wherein the first fillers are each composed of a spherical object and/or an indeterminate object and wherein the second fillers are each composed of a spherical object and/or an indeterminate object. Semiconductor housing according to Claim 9 , wherein the first fillers are each constructed from the spherical object and wherein the second fillers are each constructed from the spherical object. Semiconductor package according to one of the Claims 1 until 10 wherein the first fillers include at least one of ceramics, oxides and nitrides, and wherein the second fillers include at least one of ceramics, oxides and nitrides. Semiconductor package according to one of the Claims 1 until 11 , wherein the sealing insulator includes the first fillers having different particle sizes, and wherein the housing body includes the second fillers having different particle sizes. Semiconductor package according to one of the Claims 1 until 12 , wherein the first fillers each have a particle size of not less than 1 nm and not more than 100 µm, and wherein the second fillers each have a particle size of not less than 1 nm and not more than 100 µm. Semiconductor package according to one of the Claims 1 until 13 , where the terminal electrode is thicker than the main surface electrode and wherein the sealing insulator is thicker than the main surface electrode. Semiconductor package according to one of the Claims 1 until 14 , wherein the terminal electrode is thicker than the chip and wherein the sealing insulator is thicker than the chip. Semiconductor package according to one of the Claims 1 until 15 wherein the terminal electrode has a terminal surface and a terminal sidewall, and wherein the sealing insulator has an insulating main surface forming a single flat surface with the terminal surface and covering the terminal sidewall. Semiconductor package according to one of the Claims 1 until 16 , wherein the chip has a side surface and wherein the sealing insulator has an insulating sidewall forming a single flat surface with the side surface. Semiconductor package according to one of the Claims 1 until 17 wherein the semiconductor device further includes an insulating film partially covering the main surface electrode, and wherein the sealing insulator has a portion directly covering the insulating film. Semiconductor package according to one of the Claims 1 until 18 , where the chip encloses a single crystal of a wide band gap semiconductor. Semiconductor package according to one of the Claims 1 until 19 , further comprising: a lead terminal arranged at a distance from the die pad; and a lead wire connected to the terminal electrode and the lead terminal, wherein the package body seals the die pad, the lead terminal, the semiconductor device, and the lead wire to partially expose the lead terminal.