DE112022003469T5 - INTRODUCTION AND DETECTION OF PARITY ERRORS FOR THE SELF-TEST OF A UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER - Google Patents

Abstract

A UART includes a transmit register, a receive register, a virtual remappable pin, a parity error checking circuit to evaluate the contents of the receive register for a parity error, and control logic to determine the contents of the transmit register. The content includes underlying data and a parity bit based on that data. The control logic routes the content to the receive register via the first virtual remappable pin. The control logic shall cause modified content to be provided to the receive register before all content in the receive register is received. The modified content shall cause a parity error. The modified content shall have different underlying data or a different parity bit than the contents of the transmit register. The control logic shall determine whether the parity error checking circuit detected the parity error.

Description

PRIORITY

This application claims priority to Indian Application No. 202111030809, filed on July 9, 2021. The present application relates to electronic communications, and more particularly to the introduction and detection of parity errors in a single universal asynchronous receiver/transmitter (UART).

FIELD OF INVENTION

The present application relates to electronic communications and, in particular, to the introduction and detection of parity errors in a single universal asynchronous receiver/transmitter (UART).

BACKGROUND

UARTs are used to implement various communication protocols between electronic devices. UARTs can be used for serial communication. The transmission of data through a UART can be framed by start and stop bits to facilitate timing between UARTs on different devices.

Different errors can occur during data transmission between UARTs. Such errors can be caused, for example, by noise in the transmitting device, transmission medium, receiving device, or by a misconfiguration of any of these elements. One such error can be a parity error. A parity error can arise when a data bit changes value during transmission. A parity error can be detected by a parity check. A parity check can be performed in part by evaluating a parity bit. The parity bit can be an indication of whether in a given frame the total number of bits with a certain value - for example, zero or one - is even or odd. The parity bit can be set by the transmitting UART based on the data to be sent and inserted into or appended to the data frame. The receiving UART can calculate what the parity bit should look like based on the actual data received and then compare the calculated parity bit with the parity bit received by the transmitting UART. If the calculated parity bit does not match the received parity bit, a parity error occurs.

Inventors of examples of the present disclosure have found that testing of UART circuits, devices, and modules often utilizes two or more such UART circuits, devices, or modules. Data is generated by one such UART and received by the other UART. To test correctness of operation, such as detecting parity errors, a parity error may be artificially created. However, by using a separate UART circuit, device, or UART module, which in turn may be located on a different microcontroller or system than the original UART circuit, device, or module, inventors of examples of the present disclosure have found that this dependence on another UART circuit, device, or module may introduce additional errors. These additional errors may include false positives or false negatives when testing the parity error capabilities of the UART. For example, data may be sent from a transmitting UART to a receiving UART. Test mechanisms in the sending UART may cause a parity error, for example, by swapping a bit of the data to be sent. However, this error may go undetected if, for example, another bit of the data to be sent is swapped by noise in the transmission medium or the receiving UART. During a test or validation of the UARTs, it may appear that the parity error check is working properly, when in fact that parity error check is not working properly. Furthermore, it may not be clear whether the parity error check of the sending UART is not working properly, the parity error check of the receiving UART is not working properly, or whether there is noise in the sending UART, transmission medium, or receiving UART. Inventors of examples of the present disclosure have found that the examples of the present disclosure address one or more of these issues.

COMPILATION

A UART includes a transmit register, a receive register, a virtual remappable pin, a parity error checking circuit to evaluate the contents of the receive register for a parity error, and control logic to determine the contents of the transmit register. The contents must include underlying data and a parity bit based on the underlying data. The control logic routes the contents of the transmit register to the receive register via the virtual remappable pin. The control logic shall store the entire contents of the transmit register in the receive register before receiving the entire contents of the transmit register. cause modified content to be provided to the receive register. The modified content shall cause a parity error. The modified content shall have different underlying data or a different parity bit than the contents of the transmit register. The control logic shall determine whether the parity error checking circuit has detected the parity error.

BRIEF DESCRIPTION OF THE DRAWINGS

• 1 is an illustration of an example system for introducing and detecting parity errors in a UART in accordance with examples of the present disclosure.
• 2 is a timing diagram of the generation of parity check information according to examples of the present disclosure.
• 3 is a timing diagram of the introduction of a parity error into the generation of parity check information according to examples of the present disclosure.
• 4 is an illustration of an example method for introducing and detecting parity errors in a UART according to examples of the present disclosure.

DETAILED DESCRIPTION

Examples of the present disclosure may include a UART. The UART may include a transmit register, a receive register, a virtual remappable pin, a parity error checking circuit, and control logic. The UART may operate in a normal mode and a test mode. In normal mode, the UART may send or receive data on behalf of other elements that use the UART to communicate, such as a system or microcontroller in which the UART is included or integrated. In a test mode, the UART may perform a self-test to verify that the parity error checking circuit is functioning properly. The operating mode may be controlled by the control logic.

The transmit register and the receive register may comprise any suitable mechanism for storing information, such as a hardware register, volatile memory, or non-volatile memory. The transmit register and the receive register may each be located local to the UART, as opposed to a general purpose register for a larger microcontroller in which the UART is integrated or implemented. The transmit register may comprise information to be transmitted by the UART. For example, data for the transmit register may be provided by elements of a system that uses the UART for communication in normal mode. Such data may be provided by control logic in test mode, for example. The receive register may comprise information received by the UART. For example, data for the receive register may be provided by other elements of a system that communicate with the UART in normal mode, such as another UART. Such data may be provided by test circuitry, for example, as described below in test mode.

The virtual remappable pin may be implemented in any suitable manner. In one example, the virtual remappable pin may be implemented by a software-controlled interconnect matrix. The matrix may be implemented entirely within the UART, or within the UART and a larger system in which the UART resides, such as a microcontroller. The virtual remappable pin may be programmable via control logic. The control logic may, in turn, make programmatic calls to other parts of the system to set the virtual remappable pin. The virtual remappable pin may be programmable to interconnect two ports of the UART or the system in which the UART is implemented. The virtual remappable pin may be used, for example, to interconnect TX and RX ports, or to interconnect an RX port to a transmit-ready port.

The parity error checking circuit may serve to evaluate the contents of the receive register for a parity error. The parity error checking circuit may evaluate the parity of the contents of the receive register against an expected parity. The expected parity may be calculated by a parity error checking circuit based on the data contents. In normal mode, when contents are placed in a transmit register and sent to another UART, the parity bit may be correctly set. The contents of the transmit may become corrupted during transmission and therefore the contents received in the receive register may fail the parity error check. In test mode, the control logic may artificially induce a parity error, as described below, which should be detected by the parity error checking circuit. The test mode can thus test whether the parity error checking circuit is functioning correctly.

The control logic may be used in a test mode to determine or set contents of the transmit register. The contents may include underlying data and a parity bit based on the underlying data. The control logic may be operable in a test mode to direct the contents of the transmit register to the receive register via the virtual remappable pin. The control logic may be operable in a test mode to cause modified contents to be provided to the receive register prior to the entire contents of the transmit register being received in the receive register. The modified contents may cause a parity error. The modified contents may have different underlying data or a different parity bit than the contents of the transmit register. The control logic may be operable in a test mode to determine whether the parity error checking circuit has detected the parity error.

The control logic and parity error checking circuitry may be implemented in any suitable manner, such as analog circuitry, digital circuitry, an application specific integrated circuit, a field programmable gate array, reconfigurable or programmable hardware, instructions for execution by a processor, or any suitable combination thereof.

In combination with any of the above examples, the control logic can be used to provide modified contents to the receive register before the entire contents of the transmit register are received at the receive register by passing a known signal to the receive register through the virtual remappable pin.

In combination with one of the examples above, the known signal can be a constant value.

In combination with one of the above examples, the constant value can correspond to an expected value of a stop bit.

In combination with any of the above examples, the content may include the stop bit and the control logic may be operable to provide modified content to the receive register. The modified content may include setting different underlying data or different parity bits of the transmit register and setting the expected value of the stop bit by applying the known signal.

In combination with one of the above examples, the known signal can be a clear-to-transmit signal.

In combination with any of the above examples, the known signal may be a data terminal ready signal.

In combination with any of the above examples, the control logic can be used to provide modified content to the receive register by switching input signals to the receive register from the contents of the transmit register to the known signal.

In combination with any of the above examples, the control logic can be used to provide modified content to the receive register by remapping the virtual remappable pin from the contents of the transmit register to a known signal.

In combination with any of the above examples, the control logic may be used to provide modified content to the receiving register by selectively forwarding inputs to the receiving register.

In combination with any of the above examples, the control logic may be operable to output an error signal to indicate that the parity error was not detected based on the determination that the parity error checking circuit did not detect the parity error. Any suitable error signal may be used.

Examples of the present disclosure may include a microcontroller. The microcontroller may include one of the UARTs of the above examples.

1 is an illustration of an example system 100 for introducing and detecting parity errors in a UART, such as a single UART, according to examples of the present disclosure. The system 100 may be implemented in any suitable context, such as in a controller, a microcontroller, a chip, an integrated circuit, a system on a chip, an application specific integrated circuit, a field programmable gate array, a computer, a mobile device, or other suitable electronic device. In the example of 1 the system 100 can be implemented by a microcontroller.

The system 100 may include a UART 116. The UART 116 may be implemented by analog circuits, digital circuits, instructions for execution by a processor, or any suitable combination thereof. The system 100 may include more instances of UART 116 than shown. However, a single such UART 116 may be configured to introduce and detect a parity error. In the case of multiple instances of UART 116, each of the multiple instances of UART 116 may introduce and detect a corresponding parity error.

The system 100 may include any suitable external ports, such as the TX port 130, the RX port 118, and a Ready to Send (RTS) port 134, to provide communication to or from the UART 116. The RTS port 134 may be a logic low port such that an RTS signal is "true" when it has a zero or other logic low value. Such ports 130, 118, 134 may be implemented by any suitable electrical connection. In various examples, the ports 130, 118, 134 may be external connections of a chip, board, die, or other package of the UART 116. The ports 130, 118, 134 may be configured to provide communication between the UART 116 and other instances of UARTs in other devices.

The system 100 may include any other suitable type and number of elements. For example, the system 100 may include a processor 102 communicatively coupled to a memory 104. The memory 104 may include instructions that, when loaded and executed by the processor 102, may implement software to be executed by the system 100. The system 100 may include a system bus 106. The system bus 106 may be configured to facilitate communication between the processor 102 and other parts of the system 100, such as the UART 116.

In one example, UART 116 may be a peripheral of a microcontroller of system 100. Such a peripheral may perform tasks on behalf of processor 102 and system 100. The tasks may be initiated by a command, user input, software, or other operation of processor 102. Once initiated, such tasks may be performed by the peripheral independently of processor 102. Thus, processor 102 may offload tasks to such peripherals. When a task is completed or other appropriate criteria exist for processor 102 or software executing thereon to take further action, the peripheral may, for example, generate an interrupt to processor 102. Other possible peripherals of system 100 may include, for example, counters 108, digital-to-analog converters 110, analog-to-digital converters 112, or I2C communication circuitry 114, but in some examples may not include counters 108, digital-to-analog converters 110, analog-to-digital converters 112, or I2C communication circuitry 114.

The UART 116 may include control logic 132. The control logic 132 may be implemented by analog circuitry, digital circuitry, an application specific integrated circuit, a field programmable gate array, reconfigurable or programmable hardware, instructions for execution by a processor, or any suitable combination thereof. The control logic 132 may be configured to direct and control operations of the UART 116 to introduce parity errors as described in the present disclosure.

UART 116 may include a receive register such as RXREG 126. RXREG 126 may be configured to store one or more bits of information, including content data to be received, frame information, or error information such as parity bits, received at UART 116 via RX port 118. The data received at RX port 118 may be received by another instance of a UART. Data in RXREG 126 may be read and used by any suitable part of system 100, such as control logic 132.

UART 116 may include a transmit register such as TXREG 128. TXREG 128 may be configured to store one or more bits of information, including content data to be transmitted, frame information, or error information such as parity bits, to be sent by UART 116 over TX port 130. The data to be stored in TXREG 128 and sent over TX port 130 may be generated by any suitable part of system 100, such as control logic 132, software executing on processor 102, or another peripheral of system 100.

In one example, the UART 116 may be configured to introduce a parity error by utilizing the resources available in the UART 116. The UART 116 may be configured to introduce a parity error without using an additional instance of a UART.

In one example, UART 116 may include or have access to one or more virtual remappable pins. For ease of discussion, a single virtual remappable pin is described herein, with the understanding that more than one virtual remappable pin may be provided. Such a virtual remappable pin may be configured to provide connections between or within a particular peripheral device. of system 100, such as UART 116. The virtual remappable pin may be implemented, for example, through a switch structure within UART 116 or between UART 116 and other elements of system 100. In one example, the virtual remappable pin may be implemented through a software-controlled interconnect matrix. The matrix may be implemented entirely within UART 116 or within UART 116 and a larger system in which UART 116 resides, such as a microcontroller. The virtual remappable pin may be programmable via control logic 132. Control logic 132 may, in turn, make programmatic calls to other parts of the system to set the virtual remappable pin. The virtual remappable pin may be programmable, for example, to electrically connect two ports of UART 116 or system 100. The virtual remappable pin can be used, for example, to connect TX and RX ports or registers together, or an RX port or register with a clear to transmit signal. For example, the UART 116 can have a remappable pin RP1 120. RP1 120 is shown outside the UART 116 for demonstration purposes as if it were physical pins. In addition, 1 Two illustrations of the remappable pin RP1 120 are shown for ease of reading. The single instance of the remappable pin RP1 120 is shown as a separate instance to show the equivalent routing of signals to or from the pins to be remapped, even though it is a single instance. The control logic 130 may be configured to route two or more signals to the same remappable pin. This may result in two or more signals being connected. This may be done within the UART 116 or within the system 100. The routing of signals through the remappable pin RP1 120 may be performed programmatically by the control logic 130 by assigning and reassigning the remappable pin RP1 120. However, for illustrative purposes, the ability of control logic 130 to route signals via remappable pin RP1 120 can be illustrated as switch 124.

Parity information for the data to be sent to TX port 130 may be stored in TXREG 128. The parity information may be set according to a designed parity scheme for UART 116. Any suitable parity information may be used. For example, a parity bit may be used. In another example, the parity bit may be set to a one if the data to be sent has an odd number of ones, and the parity bit may be set to a zero if the data to be sent has an even number of ones. The examples shown in the present disclosure may follow this scheme. In other examples, the parity bit may be set to a zero if the data to be sent has an odd number of ones, and the parity bit may be set to a one if the data to be sent has an even number of ones.

Parity information may be set or checked by any suitable portion of the UART 116. For example, the UART 116 may include a parity error checking circuit 136. The parity error checking circuit 136 may be implemented by analog circuits, digital circuits, and instructions for execution by a processor, or any suitable combination thereof. In one example, the parity error checking circuit 136 may be configured to examine and evaluate contents of TXREG 128 and set a parity bit in TXREG 128 based on the underlying data to be transmitted by TXREG 128. In another example, the parity bit may instead be set by other suitable portions of the UART 116, such as a source of the contents of TXREG 128. In addition, the parity error checking circuit 136 may be configured to examine and evaluate contents of RXREG 126 and evaluate whether a parity error has occurred. Parity error checking circuit 136 may be configured to read the underlying data of RXREG 126 as it was actually received and calculate a parity bit corresponding to that underlying data. Parity error checking circuit 136 may be configured to compare such calculated parity bit with the parity bit actually received in RXREG 126. If the parity bits do not match, a parity error may have occurred. UART 116 may take appropriate corrective action. If the parity bits do match, no parity error has occurred and UART 116 may then continue to process information in RXREG 126.

During a normal operating mode in which the parity error checking capabilities of the UART 116 are not to be tested, the remappable pin RP1 120 may not be in the 1 The remappable pin RP1 120 may instead be unassigned or absent and UART 116 may be configured to forward contents of TXREG 128 to TX port 130. The parity information for the data in TXREG 128 to be sent to TX port 130 may be calculated and stored in TXREG 128 or otherwise communicated with the data sent to TX port 130. The data may be sent from TX port 130 to other entities (not shown) connected to TX port 130, such as another UART. Additionally, UART 116 may be configured to pass content from RX port 118 to RXREG 126. In one example, RX port 118 is connected directly to an input of RXREG 126. Parity information for the data received in RXREG 126 may be calculated by parity error checking circuit 136 as discussed above and compared to the parity information received with the data received in RXREG 126. If the parity information matches, no parity error may be detected. If the parity information does not match, a parity error may be detected. If a parity error is detected, appropriate corrective action may be taken. This may include, for example, requesting the sender of the information - for example, another UART - to resend the data or notifying a user or software entity of the system 100.

During normal operation mode, an RTS signal may be forwarded by control logic 132 to RTS port 134. The RTS signal may be part of a handshaking scheme (along with a Clear-to-Send (CTS) message). The RTS signal may signal to other UART instances (not shown) that UART 116 is ready to send. In the example of system 100, a logic low signal may indicate that UART 116 is ready to send, while a logic high signal may indicate that UART 116 is not ready to send.

The control logic 132 may be configured to switch the UART 116 between test and normal modes. During a test mode, the control logic 132 may be configured to determine exemplary test content to be used in TXREG 128. The control logic 132 may make this decision by generating the test content or evaluating the content in TXREG 128, which may have been provided by another entity.

During a test mode, control logic 132 may be configured to selectively forward contents of TXREG 128 to RXREG 126 via remappable pin RP1 120. Control logic 132 may be configured to perform such forwarding in any suitable manner. Control logic 132 may be configured to selectively forward different contents to RXREG 126 to cause modified contents to be provided to RXREG 126 compared to the original contents of TXREG 128. The modified contents may be provided to RXREG 126 before the entire original contents of TXREG 128 are provided to RXREG 126, i.e., a portion of the entire original contents of TXREG 128 may not be provided to RXREG 126 and instead the portion may be replaced with modified content. The modified contents may be designed to cause a parity error in RXREG 126. The modified contents may have a different parity bit than originally in TXREG 128, or different underlying data than originally in TXREG 128, or both.

In one example, during the transfer of contents from TXREG 128, the remappable pin RP1 120 may be reprogrammed to route the RTS signal to the input of RXREG 126 before all of the original contents of TXREG 128 are provided to RXREG 12. This process is symbolically represented as a switch 124 in 1 . The control logic 132 may be configured to selectively apply either the RTS signal output to RXREG 126 via the remappable pin RP1 120 or the contents of TXREG 128 to RXREG 126 via the remappable pin RP1 120. The selective application may be accomplished by reprogramming RP1 120 from connecting TXREG 128 and RXREG 126 to connecting the RTS signal output of the control logic 130 and RXREG 126. Reprogramming RP1 120 to connect the RTS signal output of control logic 130 and RXREG 126 may result in bits being swapped and inserted or otherwise manipulated to artificially create a parity error in the contents of RXREG 126.

Any suitable bit in the transmission of information in a frame between TXREG 128 and RXREG 126 may be modified by control logic 132 to artificially create a parity error. For example, a bit in the underlying data that had a logic low value in the contents of TXREG 128 may be modified to a logic high value. In another example, a bit in the underlying data that had a logic high value in the contents of TXREG 128 may be modified to a logic low value. In these examples, the underlying data in the contents of TXREG 128 may have caused a particular parity bit to be set, and the action of control logic 132 to artificially change a bit of that underlying data should cause the parity calculation of RXREG 126 to be inconsistent with the parity bit transmitted. If parity error checking circuit 136 is functioning properly, it may detect that parity error. The control logic 132 may be configured to determine whether the parity error was correctly detected by the parity error checking circuit 136.

In yet another example, the parity bit itself, which had a logic low value in the contents of TXREG 128, may be modified to a logic high value by control logic 132 to verify the operation of parity error checking circuit 136. In yet another example, the parity bit itself, which had a logic high value in the contents of TXREG 128, may be modified to a logic low value by control logic 132 to verify the operation of parity error checking circuit 136. In these examples, the underlying data in the contents of TXREG 128 may have caused a particular parity bit value to be set, and the action of control logic 132 to artificially change this value should cause the parity calculation of parity error checking circuit 136 to not match the parity bit transmitted. If parity error checking circuit 136 is functioning properly, it may detect this parity error. The control logic 132 may be configured to determine whether the parity error was correctly detected by the parity error checking circuit 136.

The control logic 132 may be configured to use any suitable source of information to set the incorrect value for the parity bit provided to RXREG 126 via the remappable pin RP1 120. In one example, the control logic 132 may be configured to provide the RTS signal as a source of information to set the incorrect value for the parity bit provided to RXREG 126 via the remappable pin RP1 120. The RTS signal may be logic low, as discussed above, when UART 116 is being read to send data. However, because UART 116 is in a test mode, the RTS signal may be logic high, indicating that UART 116 is not ready to send data. Thus, in test mode, the control logic 132 may utilize the state of the RTS signal to send a logic high value to RXREG 126. Although the use of the RTS signal is described as being to generate a parity error in the contents of RXREG 126, any suitable signal may be used.

An RTS signal can be used because its value is known to be a logic high when data is not ready to be sent because test mode is enabled. This logic high value corresponds to the value for an expected stop bit, which would also be a logic high. Thus, the RTS signal can reliably have a logic high value in test mode and be successfully applied to modify the underlying data or parity bit of the contents of TXREG 128 as received by RXREG 126. By aligning such a modified value (e.g., the RTS signal) as received by RXREG 126 so that it is the same value expected for a stop bit, a second modification to make the modified value match the expected value of the stop bit is performed. Without the expected value of the stop bit, for example, provided by the RTS signal, the parity error checking circuit 136 may not attempt to check the parity of the contents of RXREG 126 because another transmission error may be caused by an incorrect stop bit value and prevent the parity check. As stated above, when using an RTS signal, any suitable known signal may be used. The suitable known signal may be a constant value for the duration of the application of the known signal to RXREG 126 instead of contents transmitted by TXREG 128 and have a value corresponding to the expected value of the stop bit. For example, a data terminal ready signal may be used instead of an RTS signal. A known signal may be inverted, if necessary, to correspond to an expected value of a stop bit.

The test mode may be used according to any suitable criteria. For example, the test mode may be performed when the system 100 is started, at regular intervals, as part of a larger diagnostic test, or at the request of a user or the system's software.

2 is a timing diagram of the generation of parity check information according to examples of the present disclosure. The diagrams in 2 can reflect a correct information frame with a correct parity bit as tested during a test mode. The 2 may reflect the contents of TXREG 128, which may be generated, for example, by control logic 132 or another suitable portion of system 100.

A known data sequence may be used. For example, the sequence "00110000" may be used. In this data sequence, there may be an even number of "1" values. Therefore, and for the purposes of this example, a parity bit of "1" may be applied to the data sequence. The data contents are shown in diagram 202. The contents of TXREG 128 may be passed to the remappable pin RP1 120 according to the timing shown. A parity bit and a stop bit may both be "1" values.

Diagram 204 may illustrate values for the RTS signal. The RTS signal may be generated by the control logic 132. In other examples, a Data Terminal Ready (DTR) signal may be used.

Diagram 206 may illustrate values received from RXREG 126. This may be the originally transmitted content of diagram 202.

Diagram 208 can illustrate the timing at which data is sampled at RXREG 126. As shown, data may be sampled every 2 microseconds.

Test mode can start at 0 microseconds. At about 1 microsecond, the RTS signal can be logic high, indicating that the UART 116 is not ready to send data in normal mode. RXREG 126 can be reset. Sampling can start at 2 microseconds.

At 4 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 6 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 8 microseconds, the value 1 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 10 microseconds, the value 1 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 12 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 14 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 16 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 18 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

If the value of the parity bit is not modified by the control logic 132 (as in 2 the case), after 20 microseconds the value 1 can be read from TXREG 128, output to the remappable pin RP1 120 and entered into RXREG 126.

At 22 microseconds, a stop bit with a logic high value may be received, which terminates a data frame received at RXREG 126. The parity bit may then be compared with the received content by parity error checking circuit 136. In the example of 2 the parity bit is correct. The control logic 132 can check the results of the parity error checking circuit 136.

3 is a timing diagram of the introduction of a parity error into the generation of parity check information according to examples of the present disclosure.

A known data sequence may be used. For example, the sequence "00110000" may be used. In this data sequence, there may be an even number of "1" values and therefore, for the purposes of this example, a parity bit of "1" may be applied to the data sequence. The data content is shown in diagram 302. A parity bit and a stop bit may both be "1" values.

Diagram 304 may illustrate values for the RTS signal. The RTS signal may be generated by the control logic 132.

Diagram 306 may represent values received from RXREG 126. This may be the contents of diagram 302 interrupted by the application of the RTS signal in place of part of the contents of TXREG 128.

Diagram 308 can illustrate the timing at which data is sampled at RXREG 126. As shown, data may be sampled every 2 microseconds.

Test mode can start at 0 microseconds. At about one microsecond, the RTS signal can be logic high, indicating that the UART 116 is not ready to send data. RXREG 126 can be reset. Test sampling can start at 2 microseconds.

At 4 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 6 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 8 microseconds, the value 1 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 10 microseconds, the value 1 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 12 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 14 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 16 microseconds, the value 0 can be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126.

At 18 microseconds, control logic 132 may be configured to provide modified content to RXREG 126. Control logic 132 may do this by remapping remappable pin RP1 120 to connect RXREG 126 and the RTS signal shown in diagram 304. At 18 microseconds, the value 1 from the RTS signal may be transferred through remappable pin RP1 120 so that it is the input of RXREG 126. This may replace the value 0 of TXREG 128. In one example, as shown, remappable pin RP1 120 may be remapped to TXRED 128 and RXREG 126 after bit sampling 308 samples the bit for the 18 microsecond time slot. At 20 microseconds, a value of 1 may be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126. At 22 microseconds, a stop bit value of 1 may be read from TXREG 128, output to the remappable pin RP1 120, and input to RXREG 126, thereby terminating a data frame received at RXREG 126. The parity bit may then be compared to the received content by the parity error check circuit 136. In the example of 3 the parity bit is incorrect. The control logic 132 may check the results of the parity error checking circuit 136 and confirm that the parity error checking circuit 136 has detected a parity error.

At 22 microseconds, a stop bit with a high logic value may be received, which terminates a data frame received at RXREG 126. The parity bit may then be compared with the received content by parity error checking circuit 136. In the example of 2 the parity bit is incorrect. The parity bit had a value of one, but the data at 18 microseconds was flipped, changing the parity of the data received at RXREG 126. Control logic 132 may check the results of parity error checking circuit 136 to determine if this parity error is correctly identified.

In another example, the RTS signal may still be mapped to the remappable pin RP1 120 (and thus connected to RXREG 126) at 20 microseconds and 22 microseconds, which with the sample data and parity information may also result in an incorrect parity bit received from RXREG 126 for the actual data received. The control logic 132 may check the results of the parity error checking circuit 136 and confirm that the parity error checking circuit 136 detected a parity error. In another example, the RTS signal may still be mapped to the remappable pin RP1 120 (and thus connected to RXREG 126) at 20 microseconds, but at 22 microseconds the remappable pin RP1 120 may be remapped to TXREG 128 and RXREG 126, which with the sample data and parity information may similarly result in RXREG 126 receiving an incorrect parity bit for the actual data received. The control logic 132 may check the results of the parity error checking circuit 136 and confirm that the parity error checking circuit 136 detected a parity error.

4 is an illustration of an example method 400 for introducing and detecting parity errors in a UART, ie, in a single UART, according to examples of the present disclosure.

The method 400 may be performed by any suitable mechanism, for example by the system of 1-3 and in particular by the control logic 132 and the parity error checking circuit 136. The method 400 may have more or fewer steps than in 4 In addition, various certain steps of the method 400 may be repeated, omitted, skipped, executed in a different order, in parallel, or recursively.

At 405 a UART can be initialized.

At 410, it may be determined whether the UART is to operate in a normal mode or a test mode. The decision to enter test mode may be made by a user of the UART on demand, periodically, at startup, or on another suitable basis. If the UART is to operate in normal mode, method 400 may continue to 415. Otherwise, if the UART is to operate in test mode, method 400 may continue to 430.

At 415, data can be transmitted from the UART to another UART or data can be received at the UART from another UART. Data to be transmitted can be stored in the TXREG. Received data can be stored in the RXREG. Received data can be checked for parity. The parity bit received in the RXREG can be evaluated against the underlying data frame that was also received in the RXREG.

At 420, it may be determined if there is a parity bit error. If not, method 400 may return to 410. If yes, method 40 may continue to 425.

At 425, any appropriate corrective action may be taken for a parity bit, such as generating an error signal, generating a warning, or requesting that the frame be retransmitted by the sending UART. Method 400 may return to 410.

At 430, a remappable pin may be mapped between the TXREG and the RXREG so that the output of the TXREG is passed to the RXREG. A countdown may begin to an appropriate time to switch the application of the TXREG to the RXREG to the application of a known signal such as an RTS signal to the RXREG. The countdown may be monitored by, for example, a timer with clock signals or a software counter. The switching to cause modified contents to be passed to the RXREG may be performed before the entire contents of the TXREG are received at the RXREG.

At 435, it may be determined whether the application of the remappable pin is toggled to cause modified content to be passed to the RXREG. If so, method 400 may continue to 440. Otherwise, method 400 may repeat 435 for one or more additional clock cycles.

At 440, the remappable pin can be remapped to apply a known signal to the RXREG, which can match an expected value of the stop bit (e.g., an RTS signal or DTR signal).

At 445, the system can wait for a stop bit to be passed to RXREG.

At 450, contents of the RXREG may be evaluated with respect to a parity bit of the RXREG. A parity of the received data may be calculated and compared with received parity information. It may be determined whether a parity error was detected. If so, method 400 may continue to 460. Otherwise, method 400 may continue to 455.

At 455, it may be determined that the parity error checking circuit that performed 450 is not functioning properly. Any appropriate corrective action may be taken, such as warning a user of the UART. Process 400 may return to 410.

At 460, it may be determined that the parity error checking circuit that performed 450 is functioning properly. Process 400 may return to 410.

Although examples have been described above, other variations and examples may be made from this disclosure without departing from the spirit and scope of these examples.

Claims (23)

A universal asynchronous receiver/transmitter (UART), comprising: a transmit register containing information to be transmitted by the UART; a receive register to receive information received by the UART; a virtual remappable pin; a parity error checking circuit to evaluate the contents of the receive register for a parity error; and control logic to: determine the contents of the transmit register, wherein the contents are to include underlying data and a parity bit based on the underlying data; forward the contents of the transmit register to the receive register via the virtual remappable pin. cause modified contents to be provided to the receive register prior to receiving the entire contents of the transmit register in the receive register, cause the modified contents to cause a parity error, cause the modified contents to have different underlying data or a different parity bit than the contents of the transmit register; and determine whether the parity error checking circuit has detected the parity error. UART to Claim 1 , wherein the control logic causes modified contents to be provided to the receive register before the entire contents of the transmit register are received at the receive register by passing a known signal to the receive register via the virtual remappable pin. UART to Claim 2 , where the known signal is a constant value. UART to Claim 3 , where the constant value is equal to an expected value of a stop bit. UART to Claim 4 , where: the contents comprise the stop bit; and the control logic is to cause modified contents to be provided to the receive register, including setting other underlying data or other parity bit of the transmit register and setting the expected value of the stop bit by asserting the known signal. UART according to one of the Claims 2 until 5 , where the known signal is a ready-to-transmit signal. UART according to one of the Claims 2 until 5 , where the known signal is a data terminal ready signal. UART according to one of the Claims 2 until 7 , wherein the control logic is to cause modified contents to be provided to the receive register by switching input signals to the receive register from the contents of the transmit register to the known signal. UART according to one of the Claims 2 until 7 , where the control logic is to cause modified contents to be provided to the receive register by remapping the virtual remappable pin from the contents of the transmit register to a known signal. UART according to one of the Claims 1 until 9 , where the control logic is to cause modified contents to be provided to the receiving register by selectively forwarding inputs to the receiving register. UART according to one of the Claims 1 until 10 wherein the control logic is to output an error signal to indicate that the parity error was not detected based on the determination that the parity error checking circuit did not detect the parity error. Microcontroller that provides a universal asynchronous receiver/transmitter (UART) according to one of the Claims 1 until 11 having. A method comprising, in a universal asynchronous receiver/transmitter (UART): determining contents of a transmit register, the transmit register containing information to be transmitted by the UART, the contents to include underlying data and a parity bit based on the underlying data; directing the contents of the transmit register to a receive register via a virtual remappable pin, prior to receiving the entire contents of the transmit register in the receive register, causing modified contents to be provided to the receive register, the modified contents having different underlying data or a different parity bit than the contents of the transmit register, the modified contents to cause a parity error; and determining whether a parity error checking circuit has detected a parity error in the receive register. Procedure according to Claim 13 which comprises providing modified contents to the receive register prior to receiving the entire contents of the transmit register at the receive register by passing a known signal to the receive register via the virtual remappable pin. Procedure according to Claim 14 , where the known signal is a constant value. Procedure according to Claim 15 , where the constant value is equal to an expected value of a stop bit. Procedure according to Claim 16 , wherein: the contents comprise the stop bit; and the method comprises causing modified contents to be provided to the receiving register and the expected value of the stop bit is set by applying the known signal. Method according to one of the Claims 14 until 17 , where the known signal is a ready-to-transmit signal. Method according to one of the Claims 14 until 17 , where the known signal is a data terminal ready signal. Method according to one of the Claims 14 until 19 which comprises providing modified contents to the receive register by switching input signals to the receive register from the contents of the transmit register to the known signal. Method according to one of the Claims 13 until 20 which comprises providing modified contents to the receive register by remapping the virtual remappable pin from the contents of the transmit register to a known signal. Method according to one of the Claims 13 until 20 , which comprises providing modified content to the receiving register by selectively forwarding inputs to the receiving register. Method according to one of the Claims 13 until 22 which comprises, based on the determination that the parity error checking circuit did not detect the parity error, outputting an error signal to indicate that the parity error was not detected.

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