DE112021000823T5 - TRANSISTOR DRIVER CIRCUIT - Google Patents

Abstract

A transistor driver circuit is provided that drives a transistor to be driven and has a configuration that includes a controller that performs controlling to cause a change in a circuit parameter over time that contributes to a rise time or a fall time of the transistor to be driven.

Description

technical field

The invention disclosed in the present specification relates to a transistor driver circuit.

State of the art

It is well known that in a transistor such as a MOSFET (a MOS transistor), during the switching operation of the transistor, EMI (electromagnetic interference) noise due to a high-frequency component of an output voltage (Vds (drain-source voltage) in the case of the MOSFET) of the Transistor can occur.

The known switching characteristics of such a transistor include a rise time tr and a fall time tf of an output voltage of the transistor. For example, if the transistor is as in 10 shown around a MOSFET, the rise time tr is defined as the time it takes Vds to rise from 10% to 90% and the fall time tf is defined as the time it takes Vds to rise from 90% to 10% to fall.

The EMI noise increases when the rise time tr and fall time tf are short, and decreases when the rise time tr and fall time tf are long. At the same time, the switching loss is reduced as the rise time tr and fall time tf are decreased, and increased as the rise time tr and fall time tf are increased. This balances EMI noise and switching losses (power dissipation).

citation list

patent literature

Patent Document 1: JP-A-2014-165890

Summary of the Invention

Technical task

Patent Document 1 discloses a load drive control device intended to reduce both EMI noise and switching loss. In Patent Document 1 described above, a capacitance is connected to an input side of a pre-driver that drives an NMOS transistor, and is charged or discharged such that an output voltage of the pre-driver varies, and the NMOS Transistor is turned on and off by pre-driver output voltage to get linear rising and falling gradients of Vds of NMOS transistor. Accordingly, it is possible to reduce the power dissipation at the time of turning on/off the NMOS transistor to a minimum dissipation amount required for a high-frequency range characteristic of EMI noise and hence switching loss and EMI noise to reduce.

However, Patent Document 1 described above has a disadvantage that the rise time tr and the fall time tf of the transistor each occur uniformly in time, so the achieved effect of reducing EMI noise and switching loss may be insufficient.

In view of the circumstances described above, an object of the invention disclosed in the present specification is to provide a transistor driving circuit capable of reducing EMI noise while suppressing an increase in switching loss.

the solution of the problem

An aspect of the invention disclosed in the present specification is a transistor driver circuit that drives a transistor to be driven and includes a controller that performs control to cause a circuit parameter associated with a rise time or a fall time of the contributes to be driven transistor is changed over time (a first configuration).

Also, in the first configuration described above, the circuit parameter may be a current supplied to a control terminal of the transistor to be driven (a second configuration).

Moreover, in the second configuration described above, a pre-driver including a first transistor portion through which the current flows may be further provided, and the controller may cause an on-resistance of the first transistor portion to vary with time (a third configuration).

Moreover, in the third configuration described above, the first transistor section may include a plurality of first transistors connected in parallel between an application terminal (also: application terminal) of a power supply voltage and the control terminal, and the controller may cause the number of parallel-connected first transistors being in an activated state and the plurality of first Transistors can be turned on and off, varied with time (a fourth configuration).

Moreover, in the fourth configuration described above, each of the first transistors may be a PMOS transistor, and the pre-driver may include a first switch arranged between a gate signal application terminal and a gate of each of the first transistors, and a second switch , which is arranged between the gate and a source of each of the first transistors (a fifth configuration).

Also, in the first configuration described above, the circuit parameter may be a current drawn from a control terminal of the transistor to be driven (a sixth configuration).

Moreover, in the sixth configuration described above, a pre-driver including a second transistor section through which the current flows may be further provided, and the controller may cause an on-resistance of the second transistor section to be varied with time (a seventh configuration).

Furthermore, in the seventh configuration described above, the second transistor section may include a plurality of second transistors connected in parallel between the control terminal and a reference potential application terminal, and the controller may cause the number of the second transistors connected in parallel located in are in an activated state and can be turned on/off by the plurality of second transistors is varied with time (an eighth configuration).

Also, in the eighth configuration described above, each of the second transistors may be an NMOS transistor, and
the pre-driver may include a third switch arranged between an application terminal of a gate signal and a gate of each of the second transistors, and a fourth switch arranged between the gate and a source of each of the second transistors (a ninth configuration).

Also, in the first configuration described above, the circuit parameter may be a feedback capacitance of the transistor to be driven (tenth configuration).

In addition, in the tenth configuration described above, the controller can cause the number of feedback capacitances connected in parallel, including a first feedback capacitance as a parasitic capacitance of the transistor to be driven and an activated one of at least one second feedback capacitance different from the first feedback capacitance, to vary with time becomes (an eleventh configuration).

Furthermore, in the eleventh configuration described above, the controller may control a fifth switch for toggling between activated and deactivated states of the at least one second feedback capacitance (a twelfth configuration).

Moreover, in the third configuration described above, the first transistor portion may include a PMOS transistor, and the controller may cause a power supply voltage of the pre-driver to be varied over time (a thirteenth configuration).

Moreover, in the thirteenth configuration described above, the power supply voltage may be a boot voltage generated by a bootstrap (a fourteenth configuration).

Moreover, in the fourteenth configuration described above, the controller may cause a voltage applied to an anode of a diode included in the bootstrap to be varied with time (a fifteenth configuration).

Another aspect of the invention disclosed in the present specification is a switching circuit including the transistor driving circuit of any of the configurations described above and the transistor to be driven (a sixteenth configuration).

In the sixteenth configuration described above, the transistor to be controlled may be an NMOS transistor (seventeenth configuration).

Moreover, the seventeenth configuration described above may include a low potential side NMOS transistor connected in series with the high potential side transistor to be controlled (an eighteenth configuration).

Another aspect of the invention disclosed in the present specification is a switched-mode power supply circuit incorporating the circuitry of any of the configurations described above.

Advantageous Effects of the Invention

With the transistor driver circuit described in this specification, it is possible to reduce EMI noise while suppressing an increase in switching loss.

character list

• 1 12 is a view showing a configuration of a DC/DC converter according to an exemplary embodiment of the present invention.
• 2 12 is a view showing a partial configuration of a transistor driving circuit according to a first embodiment of the present invention.
• 3 12 is a view showing a partial configuration of a transistor driving circuit according to a second embodiment of the present invention.
• 4 14 is a view showing a partial configuration of a transistor driving circuit according to a third embodiment of the present invention.
• 5 12 is a view showing a partial configuration of a transistor driving circuit according to a fourth embodiment of the present invention.
• 6 14 is a view showing a configuration of a DC/DC converter according to a fifth embodiment of the present invention.
• 7 12 is a view showing a configuration of a DC/DC converter according to a sixth embodiment of the present invention.
• 8th 14 is a view showing a configuration of a DC/DC converter according to a seventh embodiment of the present invention.
• 9 Fig. 12 shows an example of the result of an FFT analysis performed on a ripple waveform of an input voltage.
• 10 Fig. 12 is a diagram for explaining the rise and fall time of a MOSFET.

Description of the embodiments

An exemplary embodiment according to the invention is described below with reference to the accompanying drawing figures.

<DC/DC converter configuration>

1 12 is a view showing a configuration of a DC/DC converter 10 according to the exemplary embodiment of the present invention. The DC/DC converter 10 is a buck converter that down-converts an input voltage Vin to generate an output voltage Vout.

As in 1 As shown, the DC/DC converter 10 comprises a switching circuit 5, an inductor L1, an output capacitor C1, a boot capacitor Cb and a diode D1.

The switching circuit 5 comprises a transistor driver circuit 1, an NMOS transistor M1 and an NMOS transistor M2. The NMOS transistor M1 and the NMOS transistor M2 are switching-controlled by the transistor driving circuit 1. FIG.

The NMOS transistor M1 and the NMOS transistor M2 are connected in series between an application terminal of the input voltage Vin and an application terminal of a ground potential to form a bridge. Specifically, a drain of the NMOS transistor M1 is connected to the input voltage Vin application terminal. A source of the NMOS transistor M1 is connected to a drain of the NMOS transistor M2 at a node Nsw. A source of the NMOS transistor M2 is connected to the ground potential terminal. That is, the NMOS transistor M1 is a high-side transistor on the high potential side, and the NMOS transistor M2 is a low-side transistor on the low potential side.

One end of inductor L1 is connected to node Nsw. The other end of the inductor L1 is connected to one end of the output capacitor C1. The other end of the output capacitor C1 is connected to a ground potential application terminal. The output voltage Vout is generated at one end of the output capacitor C1.

The NMOS transistor M1 and the NMOS transistor M2 are complementarily switched such that when one of them is in an on-state, the other is in an off-state. Such a complementary switch drive also includes a case where a dead time is provided during which both are placed in the off state in order to prevent a through current from occurring, for example.

One end of boot capacitor Cb is connected to node Nsw. The other end of the boot capacitor Cb is connected to a cathode of the diode D1. A supply voltage Vcc is applied to the anode of the diode D1. The boot capacitor Cb and the diode D1 form a bootstrap 6. A boot voltage Vboot is generated at a node Nb where the diode D1 is connected to the boot capacitor Cb.

The transistor driver circuit 1 includes a controller 2, a pre-driver 3, and a pre-driver 4. The pre-driver 3 causes the boot voltage Vboot to be applied to a gate of the NMOS Tran sistor M1 is applied to bring the NMOS transistor M1 into the on-state, and causes a switching voltage Vsw generated at the node Nsw to be applied to the above-described gate to turn the NMOS transistor M1 into the off-state bring.

The pre-driver 4 causes a power supply voltage Vreg to be applied to a gate of the NMOS transistor M2 to turn the NMOS transistor M2 into the on-state, and causes the ground potential to be applied to the gate described above, to turn off the NMOS transistor M2.

In a case where the NMOS transistor M1 is in the off-state and the NMOS transistor M2 is in the on-state, the boot capacitor Cb is charged with the power supply voltage Vcc through the diode D1, and the boot voltage Vboot = Vcc - Vf (Vf: forward voltage of diode D1) is established. Thereafter, when the NMOS transistor M1 is in the on-state while the NMOS transistor M2 is in the off-state, the boot voltage Vboot = Vin + Vcc - Vf is established, and the pre-driver 3 causes the Boot voltage Vboot is applied to the gate of the NMOS transistor M1 to turn the NMOS transistor M1 on.

The controller 2 controls the driving of the pre-driver 3 and the pre-driver 4.

<First Embodiment>

A transistor driving circuit 1 according to a first embodiment will now be described. 2 12 is a view showing an internal configuration of a pre-driver 3 in the transistor drive circuit 1 according to the first embodiment. Here, an NMOS transistor M1 is referred to as a transistor to be driven.

the inside 2 The illustrated pre-driver 3 comprises PMOS transistors 31A, 31B and 31C, an NMOS transistor 32 and switches SW1 to SW4. As for the number of PMOS transistors used, there is no limitation to three PMOS transistors 31A, 31B and 31C, and the number may be four or more, for example.

The PMOS transistors 31A, 31B and 31C are connected in parallel between an application terminal of a boot voltage Vboot and a node N3. Specifically, the respective sources of the PMOS transistors 31A, 31B and 31C are connected to the boot voltage application terminal Vboot. The respective drains of PMOS transistors 31A, 31B and 31C are connected to node N3.

The node N3 is connected to a gate (a control terminal) of the NMOS transistor M1 and to a drain of the NMOS transistor M32. A source of the NMOS transistor 32 is connected to a node Nsw.

An output terminal of a controller 2 for outputting a gate signal G1 is directly connected to each of the respective gates of the PMOS transistor 31A and the NMOS transistor 32 . In addition, the switch SW1 is arranged between the above-described output terminal of the controller 2 and a gate of the PMOS transistor 31B. The switch SW2 is arranged between the above-described output terminal of the controller 2 and a gate of the PMOS transistor 31C.

The switch SW3 is arranged between the gate and source of the PMOS transistor 31B. The switch SW4 is arranged between the gate and source of the PMOS transistor 31C.

The controller 2 controls turning on/off of the switches SW1 to SW4.

The controller 2 causes the gate signal G1 of a high level to be applied to each of the gates of the PMOS transistor 31A and the NMOS transistor 32 to turn the PMOS transistor 31A into an off state and the NMOS transistor 32 into an on-state. On the other hand, the controller 2 causes the gate signal G1 of a low level to be applied to each of the gates of the PMOS transistor 31A and the NMOS transistor 32 to turn the PMOS transistor 31A into the on state and the NMOS transistor 32 to the off state.

In addition, when the PMOS transistor 31B is activated, the controller 2 brings the switch SW1 into an on-state and the switch SW3 into an off-state. As a result, the PMOS transistor 31B is turned on and off based on a level of the gate signal G1. On the other hand, when the PMOS transistor 31B is deactivated, the controller 2 brings the switch SW1 into the off-state and the switch SW3 into the on-state. As a result, the PMOS transistor 31B has a gate-source voltage Vgs of 0 V and is thus brought into the off state.

In addition, when the PMOS transistor 31C is activated, the controller 2 brings the switch SW2 to the on-state and the switch SW4 to the off-state. As a result, the PMOS transistor 31C is turned on based on the level of the gate signal G1 switched on and off. On the other hand, when the PMOS transistor 31C is deactivated, the controller 2 brings the switch SW2 into the off-state and the switch SW4 into the on-state. As a result, the PMOS transistor 31C has a voltage Vgs of 0 V and is thus brought into the off state.

The PMOS transistor 31A and an activated one of the PMOS transistors 31B and 31C are related to the NMOS transistor 32 such that when one of them is in the on-state, the other is brought into the off-state.

A current is supplied from the application terminal (a node Nb) of the boot voltage Vboot to the gate of the NMOS transistor 31A in the on state and an activated one of the PMOS transistors 31B and 31C which is in the on state. Transistor M1 is supplied, and thus the NMOS transistor M1 is turned on. Also, a current is drawn from the gate of the NMOS transistor M1 via the NMOS transistor 32 which is in the on-state, so that the NMOS transistor M1 is turned off.

The controller 2 causes the number of parallel-connected transistors that are activated and can be turned on and off to vary with time among the PMOS transistors 31A, 31B, and 31C.

More specifically, if, for example, an on/off operation of the NMOS transistor M1 is defined as a switching operation, then during a first predetermined number of switching operations the PMOS transistors 31B and 31C are turned off, during a subsequent second predetermined number of switching operations PMOS transistor 31B is enabled while PMOS transistor 31C is off, during a subsequent third predetermined number of switching operations PMOS transistors 31B and 31C are enabled, during a subsequent further second predetermined number of switching operations PMOS transistor 31B is switched is enabled while PMOS transistor 31C is turned off, and during a subsequent further first predetermined number of switching operations PMOS transistors 31B and 31C are turned off. In this case, the number of paralleled transistors that are activated changes from 1 to 2 to 3 to 2 to 1.

Accordingly, an on-resistance Ron between the application terminal of the boot voltage Vboot and the node N3 is caused to vary with time, and thus a current supplied to the gate of the NMOS transistor M1 can be caused to vary with time. Consequently, a rise time tr (a rise time tr of Vds) of the NMOS transistor M1 is time-distributed, and thus it is possible to reduce EMI noise while suppressing an increase in switching loss. The current described above corresponds to a circuit parameter that contributes to the rise time tr of the MOS transistor M1.

In particular, in a case where the transistor driving circuit 1 is used in a vehicle, it can be expected to reduce EMI noise in a high-frequency band (100 MHz or higher) equal to or higher than an FM band, where further suppression of EMI noise is required as specified in the vehicle equipment standards. This effect can be similarly obtained also in the following embodiments.

<Second embodiment>

Next, a transistor driving circuit 1 according to a second embodiment will be described. 3 12 is a view showing an internal configuration of a pre-driver 3 in the transistor drive circuit 1 according to the second embodiment. Here, an NMOS transistor M1 is referred to as a transistor to be driven.

the inside 3 The illustrated pre-driver 3 comprises a PMOS transistor 31, NMOS transistors 32A, 32B and 32C, and switches SW11 to SW14. As for the number of NMOS transistors used, there is no limitation to three NMOS transistors 32A, 32B and 32C, and the number may be four or more, for example.

The PMOS transistor 31 is connected between an application terminal of a boot voltage Vboot and a node N3. Specifically, a source of the PMOS transistor 31 is connected to the application terminal of the boot voltage Vboot. A drain of PMOS transistor 31 is connected to node N3. Node N3 is connected to a gate of NMOS transistor M1.

NMOS transistors 32A, 32B and 32C are connected in parallel between node N3 and a node Nsw. In particular, the respective drains of NMOS transistors 32A, 32B and 32C are connected to node N3. The respective sources of NMOS transistors 32A, 32B and 32C are connected to node Nsw. The node Nsw is an application terminal for a switching voltage Vsw as a reference potential.

An output terminal of a controller 2 for outputting a gate signal G1 is directly connected to each of the respective gates of the PMOS transistor 31 and the NMOS transistor 32A. In addition, the switch SW11 is arranged between the above-described output terminal of the controller 2 and a gate of the NMOS transistor 32B. The switch SW12 is arranged between the above-described output terminal of the controller 2 and a gate of the NMOS transistor 32C.

The switch SW13 is arranged between the gate and source of the NMOS transistor 32B. The switch SW14 is arranged between the gate and source of the NMOS transistor 32C.

The controller 2 controls turning on/off of the switches SW11 to SW14.

The controller 2 causes the gate signal G1 of a high level to be applied to each of the gates of the PMOS transistor 31 and the NMOS transistor 32A to turn the PMOS transistor 31 into an off state and the NMOS transistor 32A into an on-state. On the other hand, the controller 2 causes the gate signal G1 to be applied to each of the gates of the PMOS transistor 31 and the NMOS transistor 32A with a low level to turn the PMOS transistor 31 into the on state and the NMOS transistor 32A to the off state.

In addition, when the NMOS transistor 32B is activated, the controller 2 brings the switch SW11 into an on-state and the switch SW13 into an off-state. As a result, driving of the NMOS transistor 32B is performed based on a level of the gate signal G1. On the other hand, when the NMOS transistor 32B is deactivated, the controller 2 brings the switch SW11 into the off-state and the switch SW13 into the on-state. As a result, the NMOS transistor 32B has a voltage of 0 V and is thus brought into the off state.

In addition, when the NMOS transistor 32C is activated, the controller 2 brings the switch SW12 to the on-state and the switch SW14 to the off-state. As a result, the driving of the NMOS transistor 32C is performed based on the level of the gate signal G1. On the other hand, when the NMOS transistor 32C is deactivated, the controller 2 brings the switch SW12 into the off-state and the switch SW14 into the on-state. As a result, the NMOS transistor 32C has a voltage of 0 V and is thus brought into the off state.

The NMOS transistor 32A and an activated one of the NMOS transistors 32B and 32C are related to the PMOS transistor 31 such that when one of them is in the on-state, the other is brought into the off-state.

A current is supplied from the application terminal of the boot voltage Vboot to the gate of the NMOS transistor M1 in the on state via the PMOS transistor 31, and thus the NMOS transistor M1 is turned on. In addition, a current is drawn from the gate of the NMOS transistor M1 via the NMOS transistor 32A which is in the on state and an enabled one of the NMOS transistors 32B and 32C which is in the on state, and thus is the NMOS transistor M1 turns off.

The controller 2 causes the number of parallel-connected transistors that are activated and can be turned on and off to vary with time among the NMOS transistors 32A, 32B and 32C.

More specifically, if, for example, an on/off operation of the NMOS transistor M1 is defined as a switching operation, then during a first predetermined number of switching operations, the NMOS transistors 32B and 32C are turned off, during a subsequent second predetermined number of switching operations NMOS transistor 32B is enabled while NMOS transistor 32C is off, during a subsequent third predetermined number of switching operations NMOS transistors 32B and 32C are enabled, during a subsequent further second predetermined number of switching operations NMOS transistor 32B is switched is enabled while NMOS transistor 32C is turned off, and during a subsequent further first predetermined number of switching operations NMOS transistors 32B and 32C are turned off. In this case, the number of paralleled transistors that are activated changes from 1 to 2 to 3 to 2 to 1.

Accordingly, an on-resistance Ron between the node N3 and the node Nsw is varied with time, and thus a current drawn from the gate of the NMOS transistor M1 can be varied with time. Consequently, a fall time tf (a fall time tf of Vds) of the NMOS transistor M1 is time-distributed, and in this way it is possible to reduce EMI noise while suppressing an increase in switching loss. The current described above corresponds to a circuit parameter that contributes to the fall time tf of the NMOS transistor M1.

<Third embodiment>

Next, a transistor driving circuit 1 according to a third embodiment described. 4 14 is a view showing an internal configuration of a pre-driver 4 in the transistor drive circuit 1 according to the third embodiment. Here, an NMOS transistor M2 is referred to as a transistor to be driven.

the inside 4 The illustrated pre-driver 4 comprises PMOS transistors 41A, 41B and 41C, an NMOS transistor M42 and switches SW21 to SW24. As for the number of PMOS transistors used, there is no limitation to three PMOS transistors 41A, 41B and 41C, and the number may be four or more, for example.

The pre-driver 4 according to this embodiment has a configuration similar to the configuration described above ( 2 ) of the pre-driver 3 according to the first embodiment, wherein the PMOS transistors 41A, 41B and 41C of this embodiment correspond to the PMOS transistors 31A, 31B and 31C of the first embodiment, respectively, the NMOS transistor 42 of this embodiment corresponds to the NMOS transistor 32 corresponds to the first embodiment, and the switches SW21 to SW24 of this embodiment correspond to the switches SW1 to SW4 of the first embodiment, respectively.

This embodiment differs from the first embodiment in the following aspects. That is, the respective drains of the PMOS transistors 41A, 41B and 41C are connected to an application terminal of a power supply voltage Vreg. A node N4, at which the respective drains of the PMOS transistors 41A, 41B and 41C are connected to a drain of the NMOS transistor 42, is connected to a gate of the NMOS transistor M2. A source of the NMOS transistor 42 is connected to a ground potential application terminal.

Similarly to the first embodiment, a controller 2 performs on/off control of the switches SW21 to SW24 to switch between on and off states of the PMOS transistors 41B and 41C. Based on a level of a gate signal G2 output from an output terminal of the controller 2, on/off driving of the PMOS transistor 41A and an activated one of the PMOS transistors 41B and 41C is performed. Based on the level of the gate signal G2, the NMOS transistor 42 is also turned on and off. The PMOS transistor 41A and an activated one of the PMOS transistors 41B and 41C are related to the NMOS transistor 42 such that when one of them is in an on-state, the other is brought into an off-state .

Similarly to the first embodiment, the controller 2 causes the number of parallel-connected transistors that are activated and can be turned on and off to be time-varied among the PMOS transistors 41A, 41B and 41C.

Accordingly, an on-resistance Ron between the application terminal of the power supply voltage Vreg and the node N4 is made to vary with time, and thus a current supplied to the gate of the NMOS transistor M2 can be made to vary with time. Consequently, a rise time tr (a rise time tr of Vds) of the NMOS transistor M2 is distributed in time, and thus it is possible to reduce EMI noise while suppressing an increase in switching loss.

<Fourth embodiment>

Next, a transistor driving circuit 1 according to a fourth embodiment will be described. 5 14 is a view showing an internal configuration of a pre-driver 4 in the transistor drive circuit 1 according to the fourth embodiment. Here, an NMOS transistor M2 is referred to as a transistor to be driven.

the inside 5 The illustrated pre-driver 4 comprises a PMOS transistor 41, NMOS transistors 42A, 42B and 42C, and switches SW31 to SW34. As for the number of NMOS transistors used, there is no limitation to three NMOS transistors 42A, 42B and 42C, and the number may be four or more, for example.

The pre-driver 4 according to this embodiment has a configuration similar to the configuration described above ( 3 ) of the pre-driver 4 according to the second embodiment, wherein the PMOS transistor 41 of this embodiment corresponds to the PMOS transistor 31 of the second embodiment, the NMOS transistors 42A, 42B and 42C of this embodiment correspond to the NMOS transistors 32A, 32B and 32C, respectively correspond to the second embodiment, and the switches SW31 to SW34 of this embodiment correspond to the switches SW11 to SW14 of the second embodiment, respectively.

This embodiment differs from the second embodiment in the following points. That is, a drain of the PMOS transistor 41 is connected to an application terminal of a power supply voltage Vreg. A node N4, at which the drain of the PMOS transistor 41 is connected to the drains of the NMOS transistors 42A, 42B and 42C, is connected to a gate of the NMOS transistor sisters M2 connected. The respective sources of the NMOS transistors 42A, 42B and 42C are connected to an application terminal of a ground potential (a reference potential).

Similarly to the second embodiment, a controller 2 performs on/off control of switches SW31 to SW34 to switch between activated and deactivated states of NMOS transistors 42B and 42C. Based on a level of a gate signal G2 output from an output terminal of the controller 2, on/off driving of the NMOS transistor 42A and an activated one of the NMOS transistors 42B and 42C is performed. Also, the PMOS transistor 41 is turned on and off based on the level of the gate signal G2. The NMOS transistor 42A and an activated one of the NMOS transistors 42B and 42C are related to the PMOS transistor 41 such that when one of them is in an on-state, the other is brought into an off-state .

Similarly to the second embodiment, the controller 2 causes the number of parallel-connected transistors that are activated and can be turned on and off to be time-varied among the NMOS transistors 42A, 42B, and 42C.

Accordingly, an on-resistance Ron between the node N4 and the ground potential application terminal is caused to vary with time, and thus a current drawn from the gate of the NMOS transistor M2 can be caused to vary with time. Consequently, a fall time tf (a fall time tf of Vds) of the NMOS transistor M2 is time-distributed, and thus it is possible to reduce EMI noise while suppressing an increase in switching loss.

<Fifth embodiment>

Next, a fifth embodiment will be described. 6 14 is a view showing a DC/DC converter 10 having a configuration of a switching circuit 5 according to the fifth embodiment. Here, an NMOS transistor M1 is referred to as a transistor to be driven.

As in 6 1, circuit 5 according to this embodiment includes feedback capacitance Cgd1, which is a parasitic capacitance between a gate and a drain of NMOS transistor M1, and feedback capacitances Cgd2 and Cgd3 connected between the gate and drain of NMOS transistor M1 . As for the number of feedback capacitances other than the parasitic capacitance connected between the gate and drain of the NMOS transistor M1, there is no limitation to the two feedback capacitances Cgd2 and Cgd3, and the number may be three or more, for example.

One end of each of the feedback capacitances Cgd2 and Cgd3 is directly connected to the gate of the NMOS transistor M1. The other end of each of the feedback capacitances Cgd2 and Cgd3 is connected to the drain of the NMOS transistor M1 via a corresponding one of the switches S1 and S2.

A controller 2 controls turning on/off of the switches S1 and S2. When switches S1 and S2 are in an on state, feedback capacitances Cgd2 and Cgd3 are activated, and when switches S1 and S2 are in an off state, feedback capacitances Cgd2 and Cgd3 are deactivated.

In this embodiment, the controller 2 causes the number of parallel-connected and activated feedback capacitances between the gate and the drain of the NMOS transistor M1 among the feedback capacitances Cgd1, Cgd2 and Cgd3 to change with time.

More specifically, if for example an on/off operation of the NMOS transistor M1 is defined as a switching operation, then during a first predetermined number of switching operations the feedback capacitances Cgd2 and Cgd3 are deactivated, during a subsequent second predetermined number of switching operations the feedback capacitance is Cgd2 activated while the feedback capacitance Cgd3 is deactivated, during a subsequent third predetermined number of switching operations the feedback capacitances Cgd2 and Cgd3 are enabled, during a subsequent further second predetermined number of switching operations the feedback capacitance Cgd2 is enabled while the feedback capacitance Cgd3 is blocked, and during a subsequent further first predetermined number of switching processes, the feedback capacitances Cgd2 and Cgd3 are blocked. In this case, the number of feedback capacitances connected in parallel and activated changes from 1 to 2 to 3 to 2 to 1.

Accordingly, the feedback capacitance between the gate and the drain of the NMOS transistor M1 is caused to vary with time such that a rise time tr and a fall time tf of the NMOS transistor M1 are spread over time, and it is thus possible to reduce EMI noise , while suppressing an increase in switching loss. The feedback capacitance described above corresponds to a circuit para meter that contributes to the rise time tr and fall time tf of the NMOS transistor M1.

<Sixth embodiment>

Next, a sixth embodiment will be described. 7 14 is a view showing a DC/DC converter 10 having a configuration of a switching circuit 5 according to the sixth embodiment. Here, an NMOS transistor M2 is referred to as a transistor to be driven.

As in 7 1, circuit 5 according to this embodiment includes feedback capacitance Cgd11, which is a parasitic capacitance between a gate and a drain of NMOS transistor M2, and feedback capacitances Cgd12 and Cgd13 connected between the gate and drain of NMOS transistor M2 . As for the number of feedback capacitances other than the parasitic capacitance connected between the gate and drain of the NMOS transistor M2, there is no limitation to the two feedback capacitances Cgd12 and Cgd13, and the number may be three or more, for example.

One end of each of the feedback capacitances Cgd12 and Cgd13 is directly connected to the gate of the NMOS transistor M2. The other end of each of the feedback capacitances Cgd12 and Cgd13 is connected to the drain of the NMOS transistor M2 via a corresponding one of the switches S11 and S12.

A controller 2 controls turning on/off of the switches S11 and S12. When switches S11 and S12 are in an on state, feedback capacitances Cgd12 and Cgd13 are activated, and when switches S11 and S12 are in an off state, feedback capacitances Cgd2 and Cgd3 are deactivated.

In this embodiment, the controller 2 causes the number of feedback capacitances connected in parallel between the gate and the drain of the NMOS transistor M2 among the feedback capacitances Cgd11, Cgd12 and Cgd13 to change with time.

More specifically, if for example an on/off operation of the NMOS transistor M2 is defined as a switching operation, then during a first predetermined number of switching operations the feedback capacitances Cgd12 and Cgd13 are deactivated, during a subsequent second predetermined number of switching operations the feedback capacitance is Cgd12 activated while the feedback capacitance Cgd13 is deactivated, during a subsequent third predetermined number of switching operations the feedback capacitances Cgd12 and Cgd13 are enabled, during a subsequent further second predetermined number of switching operations the feedback capacitance Cgd12 is enabled while the feedback capacitance Cgd13 is blocked, and during a subsequent further first predetermined number of switching processes, the feedback capacitances Cgd12 and Cgd13 are blocked. In this case, the number of feedback capacitances connected in parallel and activated changes from 1 to 2 to 3 to 2 to 1.

Accordingly, the feedback capacitance between the gate and the drain of the NMOS transistor M2 is caused to vary with time such that a rise time tr and a fall time tf of the NMOS transistor M2 are spread over time, and it is thus possible to reduce EMI noise , while suppressing an increase in switching loss.

<Seventh Embodiment>

8th 12 is a view showing the configuration of a DC/DC converter 10 according to a seventh embodiment. Here, an NMOS transistor M1 is referred to as a transistor to be driven. in the in 8th In the illustrated DC/DC converter 10, the switches Sw1 to Sw3 are arranged in a bootstrap 6.

The switch Sw1 is arranged between an application terminal of a predetermined power supply voltage Vcc1 and an anode of a diode D1. The switch Sw2 is arranged between an application terminal of a predetermined power supply voltage Vcc2 and the anode of the diode D1. The switch Sw3 is arranged between an application terminal of a predetermined power supply voltage Vcc3 and the anode of the diode D1. A magnitude relationship between the power supply voltages Vcc1 to Vcc3 is expressed by Vcc1<Vcc2<Vcc3, for example. The number of power supply voltages is not limited to three power supply voltages Vcc1 to Vcc3, but may be four or more, for example.

A controller 2 controls turning on/off of the switches Sw1 to Sw3.

In this embodiment, a pre-driver 3 includes a PMOS transistor 31 and an NMOS transistor 32. A node Nb is connected to a source of the PMOS transistor 31 so that a boot voltage Vboot is applied to the source.

In this embodiment, the controller 2 causes the boot voltage Vboot to change over time at the time of turning on the NMOS transistor M1.

More specifically, for example, if an on/off operation of the NMOS transistor M1 is defined as a switching operation, during a first predetermined number of switching operations, the switch Sw1 is brought into an on state while the switches Sw2 and Sw3 are brought into an off -state, during a subsequent second predetermined number of switching operations the switch Sw2 is placed in the on-state while the switches Sw1 and Sw3 are placed in the off-state, during a subsequent third predetermined number of switching operations the switch Sw3 is placed in the on state while switches Sw1 and Sw2 are placed in the off state, during a subsequent further second predetermined number of switching operations switch Sw2 is placed in the on state while switches Sw1 and Sw3 are placed in the off -State are brought, and during a subsequent further first predetermined number of switching operations Switch Sw1 is placed in the on state while switches Sw2 and Sw3 are placed in the off state.

Accordingly, the boot voltage Vboot changes from Vin + Vcc1 - Vf to Vin + Vcc2 - Vf to Vin + Vcc3 - Vf to Vin + Vcc2 - Vf to Vin + Vcc1 - Vf at the time of turning on the NMOS transistor M1.

Here, an on-resistance Ron of the PMOS transistor 31 is a function of Vgs of the PMOS transistor 31, and when the boot voltage Vboot changes with time, the on-resistance Ron of the PMOS transistor 31 also changes with time. Consequently, a current supplied to a gate of the NMOS transistor M1 via the PMOS transistor 31 varies, and thus a rise time tr of the NMOS transistor M1 is distributed in time. Accordingly, it is possible to reduce EMI noise while suppressing an increase in switching loss.

In this embodiment, the boot voltage Vboot is varied such that the on-resistance of the NMOS transistor M1 also changes. However, for example, when the boot voltage Vboot varies sinusoidally, it is possible to obtain a value corresponding to an average value of a sine wave as an average value of the on-resistance of the NMOS transistor M1.

In addition, with respect to a power supply voltage Vreg applied to a pre-driver 4, the controller 2 may time-vary the power supply voltage Vreg at the time of turning on an NMOS transistor M2. Accordingly, a rise time tr of the NMOS transistor M2 can be time-distributed.

<To the FFT analysis>

9 13 is a left diagram showing an example of a ripple voltage waveform included in the input voltage Vin in the DC/DC converter 10 ( 1 ) is generated in a case where the input voltage Vin = 12V and the output voltage Vout = 5V. The input voltage Vin is supplied from an unillustrated battery, and an unillustrated capacitor is connected to an output terminal of the battery.

As in the left illustration of 9 As shown, the capacitor described above is discharged when the NMOS transistor M1 is turned on to lower the input voltage Vin. Then, when the NMOS transistor M1 is turned off, the capacitor described above is charged to increase the input voltage Vin. These operations are repeatedly performed so that a 500 kHz waveform having an amplitude of 200 mV is generated in a ripple of the input voltage Vin. Also, at this time, when the NMOS transistor M1 is turned on, the noise Ns1 is generated, while when the NMOS transistor M1 is turned off, the noise Ns2 is generated. The noise Ns1 has a waveform of 130 MHz with an amplitude of 120 mV.

9 Fig. 12 shows, in a right panel, a result of FFT (fast Fourier transform) analysis of the waveform shown in the left panel. As in the right representation of 9 shown, a spectrum value at 500 kHz is -25.4 dB and a spectrum value at 130 MHz is -71.6 dB.

As in the left illustration of 9 shown, the 500 kHz waveform has an amplitude of 200 mV, and thus an effective value thereof is expressed by 200 mV/(2×√2) = 70.7 mV, so that a spectrum value expressed by 20× log (70.7 mV) = -23 dB is expressed, which is essentially the same as that shown in the right-hand plot of 9 result shown matches. However, the 130MHz waveform has an amplitude of 120mV, so an RMS value thereof is expressed by 120mV/(2× √2) = 42.4mV, and one obtains a spectral value expressed by 20X log(42, 4 mV) = -27 dB is expressed, which is inconsistent with that shown in the right-hand representation of 9 result shown matches.

As in the left illustration of 9 As shown, the noise Ns1 at 130MHz occurs five times within an FFT range of up to 10µs during a period expressed by 1/130MHz × 5 = 38ns. Consequently, the probability of its occurrence is expressed by 38ns/10µs = 0.0038 = -48.4dB. Accordingly, a spectral value in terms of occurrence probability is expressed by -27dB + (-48dB) = -75dB, which is basically the same as that shown in the right-hand graph of 9 result shown matches.

As a result, the rise time tr and the fall time tf are time-distributed as in the foregoing, thereby reducing the likelihood of noise occurring at the same frequency, so that the spectral value of the noise can be reduced.

<Other modifications>

While the foregoing has described the embodiments of the present invention, various changes can be made to the embodiments without departing from the gist of the present invention.

For example, the foregoing may be implemented in any combination as long as there are no inconsistencies.

Furthermore, in the switching circuit 5 in each of the above embodiments, a PMOS transistor can be used in place of the NMOS transistor M1 on the high side. In this case, it suffices to use a voltage lower than the input voltage Vin as the power supply voltage of the pre-driver 3, so there is no need to generate the power supply voltage of the pre-driver 3 by bootstrap or the like.

In addition, the transistor driving circuit of the present invention is not limited to a buck-type DC/DC converter and is also applicable to switching power supply circuits including various types of DC/DC converters such as e.g. B. boost converter, boost and buck converter, non-isolated and isolated DC / DC converter and a DC / AC converter (an inverter), and further to other types of circuits than power supply circuits.

In addition, a transistor that is driven by the transistor driving circuit of the present invention is not limited to a MOSFET and may be an IGBT, for example.

Industrial Applicability

The invention disclosed in the present specification can be used to drive different types of transistors.

Reference List

1

Transistor driver circuit

2

steering

3

pre-driver

4

pre-driver

5

circuit

6

Bootstrap

10

DC/DC converter

M1, M2

NMOS transistor

L1

inductor

C1

output capacitor

cb

boat capacitor

D1

diode

31A to 31C

PMOS transistor

32

NMOS transistor

SW1 to SW4

Switch

31

PMOS transistor

32A to 32C

NMOS transistor

SW11 to SW14

Switch

41A to 41C

PMOS transistor

42

NMOS transistor

SW21 to SW24

Switch

41

PMOS transistor

42A to 42C

NMOS transistor

SW31 to SW34

Switch

Cgd1 to Cgd3

feedback capacitance

S1, S2

Switch

Cgd11 to Cgd13

feedback capacitance

S11, S12

Switch

Sw1 to Sw3

Switch

QUOTES INCLUDED IN DESCRIPTION

This list of the documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• JP2014165890A [0005]

Claims (19)

Transistor driver circuit driving a transistor to be driven, the transistor driver circuit comprising: a controller that performs controlling to cause a change in a circuit parameter over time that contributes to a rise time or a fall time of the transistor to be driven. transistor driver circuit claim 1 , where the circuit parameter is a current supplied to a control terminal of the transistor to be driven. transistor driver circuit claim 2 , further comprising: a pre-driver including a first transistor portion through which the current flows, wherein the controller causes an on-resistance of the first transistor portion to vary over time. transistor driver circuit claim 3 wherein the first transistor portion includes a plurality of first transistors connected in parallel between a power supply voltage application terminal and the control terminal, and the controller causes a plurality of parallel-connected first transistors that are in an activated state and from the plurality of first Transistors can be switched on and off to vary in time. transistor driver circuit claim 4 wherein each of the first transistors is a PMOS transistor, and the pre-driver comprises: a first switch arranged between an application terminal of a gate signal and a gate of each of the first transistors; and a second switch arranged between the gate and a source of each of the first transistors. transistor driver circuit claim 1 , where the circuit parameter is a current drawn from a control terminal of the transistor to be driven. transistor driver circuit claim 6 , further comprising: a pre-driver including a second transistor portion through which the current flows, wherein the controller causes an on-resistance of the second transistor portion to vary over time. transistor driver circuit claim 7 , wherein the second transistor section includes a plurality of second transistors connected in parallel between the control terminal and a reference potential application terminal, and the controller causes a number of parallel-connected second transistors that are in an activated state and from the plurality of second transistors can be switched on and off to vary in time. transistor driver circuit claim 8 wherein each of the second transistors is an NMOS transistor, and the pre-driver comprises: a third switch arranged between an application terminal of a gate signal and a gate of each of the second transistors; and a fourth switch arranged between the gate and a source of each of the second transistors. transistor driver circuit claim 1 , where the circuit parameter is a feedback capacitance of the transistor to be driven. transistor driver circuit claim 10 wherein the controller causes a number of feedback capacitances connected in parallel to vary in time, including a first feedback capacitance as a parasitic capacitance of the transistor to be driven and an activated one of at least one second feedback capacitance different from the first feedback capacitance. transistor driver circuit claim 11 , wherein the controller controls a fifth switch for switching between activated and deactivated states of the at least one second feedback capacitance. transistor driver circuit claim 3 , wherein the first transistor portion includes a PMOS transistor, and the controller causes a supply voltage of the pre-driver to change over time. transistor driver circuit Claim 13 , where the supply voltage is a boot voltage generated by a bootstrap. transistor driver circuit Claim 14 , wherein the controller causes a voltage applied to an anode of a diode in the bootstrap to vary with time. A circuit comprising: the transistor driver circuit of any one of Claims 1 until 15 ; and the transistor to be controlled. circuit after Claim 16 , where the transistor to be controlled is an NMOS transistor. circuit after Claim 17 1 . further comprising: a low potential side NMOS transistor connected in series with the high potential side transistor to be controlled. Switched mode power supply circuitry comprising: the circuitry of any one of Claims 16 until 18 .

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