DE112020000748B4 - Adresserzeugung zur hochleistungsverarbeitung von vektoren - Google Patents

Adresserzeugung zur hochleistungsverarbeitung von vektoren Download PDF

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Publication number
DE112020000748B4
DE112020000748B4 DE112020000748.0T DE112020000748T DE112020000748B4 DE 112020000748 B4 DE112020000748 B4 DE 112020000748B4 DE 112020000748 T DE112020000748 T DE 112020000748T DE 112020000748 B4 DE112020000748 B4 DE 112020000748B4
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Prior art keywords
data vector
vector
binary data
memory
log
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DE112020000748.0T
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German (de)
English (en)
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DE112020000748T5 (de
Inventor
Jan van Lunteren
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
DE112020000748.0T 2019-05-10 2020-05-01 Adresserzeugung zur hochleistungsverarbeitung von vektoren Active DE112020000748B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/408,575 2019-05-10
US16/408,575 US10996949B2 (en) 2019-05-10 2019-05-10 Address generation for high-performance vector processing
PCT/IB2020/054137 WO2020229933A1 (en) 2019-05-10 2020-05-01 Address generation for high-performance vector processing

Publications (2)

Publication Number Publication Date
DE112020000748T5 DE112020000748T5 (de) 2021-10-28
DE112020000748B4 true DE112020000748B4 (de) 2022-11-17

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Application Number Title Priority Date Filing Date
DE112020000748.0T Active DE112020000748B4 (de) 2019-05-10 2020-05-01 Adresserzeugung zur hochleistungsverarbeitung von vektoren

Country Status (6)

Country Link
US (1) US10996949B2 (https=)
JP (1) JP7386901B2 (https=)
CN (1) CN113767371B (https=)
DE (1) DE112020000748B4 (https=)
GB (1) GB2598250B (https=)
WO (1) WO2020229933A1 (https=)

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GB201907382D0 (en) * 2019-05-24 2019-07-10 Univ Southampton Computer-implemented method for creating encoded data for use in a cognitive computing system, as well as cognitive processing unit and cognitive computing
US11435941B1 (en) * 2020-06-24 2022-09-06 Amazon Technologies, Inc. Matrix transpose hardware acceleration
US11636569B1 (en) * 2020-09-23 2023-04-25 Amazon Technologies, Inc. Matrix transpose hardware acceleration
US20220129270A1 (en) * 2020-10-23 2022-04-28 Marvell Asia Pte Ltd Method and system for topk operation
CN114327639B (zh) * 2021-12-29 2025-07-22 深圳鲲云信息科技有限公司 基于数据流架构的加速器、加速器的数据存取方法及设备
CN115422098B (zh) * 2022-02-15 2023-08-29 摩尔线程智能科技(北京)有限责任公司 基于扩展页表的gpu访存自适应优化方法及装置
FR3133459B1 (fr) * 2022-03-11 2024-03-22 Commissariat Energie Atomique Générateur d’adresses pour un calculateur à architecture de type « instruction unique, données multiples »
JP2023154162A (ja) * 2022-04-06 2023-10-19 国立大学法人九州工業大学 演算処理装置
CN115148272B (zh) * 2022-06-30 2025-05-16 长鑫存储技术有限公司 存储器地址确定方法与电子设备
CN116089323A (zh) * 2023-02-24 2023-05-09 北京信而泰科技股份有限公司 表项生成方法及装置
CN116910770B (zh) * 2023-09-13 2023-12-19 中国海洋大学 一种基于密度的固件基址识别系统及方法

Citations (3)

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US7793038B2 (en) 2007-06-26 2010-09-07 International Business Machines Corporation System and method for programmable bank selection for banked memory subsystems
US20160275013A1 (en) 2015-03-18 2016-09-22 International Business Machines Corporation Programmable memory mapping scheme with interleave properties
US9705532B2 (en) 2013-03-15 2017-07-11 Arris Enterprises Llc Parallel low-density parity check (LDPC) accumulation

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JPH0769896B2 (ja) * 1988-11-07 1995-07-31 富士通株式会社 ベクトル処理システム
US5276902A (en) * 1988-11-07 1994-01-04 Fujitsu Limited Memory access system for vector data processed or to be processed by a vector processor
JP4240610B2 (ja) * 1998-11-27 2009-03-18 株式会社日立製作所 計算機システム
US6604166B1 (en) 1998-12-30 2003-08-05 Silicon Automation Systems Limited Memory architecture for parallel data access along any given dimension of an n-dimensional rectangular data array
US6453380B1 (en) * 1999-01-23 2002-09-17 International Business Machines Corporation Address mapping for configurable memory system
US8341332B2 (en) * 2003-12-02 2012-12-25 Super Talent Electronics, Inc. Multi-level controller with smart storage transfer manager for interleaving multiple single-chip flash memory devices
US6430672B1 (en) * 2000-07-17 2002-08-06 International Business Machines Corporation Method for performing address mapping using two lookup tables
CN101069211A (zh) 2004-11-23 2007-11-07 高效存储技术公司 分页存储器及其智能存储器区段的交错寻址的多次缩略的方法和装置
US7398362B1 (en) * 2005-12-09 2008-07-08 Advanced Micro Devices, Inc. Programmable interleaving in multiple-bank memories
US8397010B1 (en) * 2007-04-16 2013-03-12 Juniper Networks, Inc. Convenient, flexible, and efficient management of memory space and bandwidth
CN101645005A (zh) * 2008-08-06 2010-02-10 中国人民解放军信息工程大学 基于多维可变描述表的处理器结构与指令系统表示方法
US9262174B2 (en) * 2012-04-05 2016-02-16 Nvidia Corporation Dynamic bank mode addressing for memory access
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Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
US7793038B2 (en) 2007-06-26 2010-09-07 International Business Machines Corporation System and method for programmable bank selection for banked memory subsystems
US9705532B2 (en) 2013-03-15 2017-07-11 Arris Enterprises Llc Parallel low-density parity check (LDPC) accumulation
US20160275013A1 (en) 2015-03-18 2016-09-22 International Business Machines Corporation Programmable memory mapping scheme with interleave properties

Also Published As

Publication number Publication date
CN113767371A (zh) 2021-12-07
CN113767371B (zh) 2023-04-14
GB2598250A (en) 2022-02-23
US20200356367A1 (en) 2020-11-12
WO2020229933A1 (en) 2020-11-19
GB202117077D0 (en) 2022-01-12
JP2022531786A (ja) 2022-07-11
DE112020000748T5 (de) 2021-10-28
US10996949B2 (en) 2021-05-04
JP7386901B2 (ja) 2023-11-27
GB2598250B (en) 2022-07-06

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