DE112019007118T5 - Semiconductor module parallel connection and semiconductor module interconnection substrate - Google Patents

Abstract

A semiconductor module parallel circuit (1) has: a plurality of power semiconductor modules (10); and a multilayer substrate (100) connecting the plurality of power semiconductor modules (10), each of the power semiconductor modules (10) comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate (100) comprising: an external connection terminal; first signal terminal connection patterns connected to the first signal terminals of the power semiconductor modules (10); and second signal terminal connection patterns connected to the second signal terminals of the power semiconductor modules (10) and inductances of the gate line for the plurality of power semiconductor modules (10) from the external connection terminal to the first signal terminal connection pattern and from the second signal terminal connection pattern to the external connection terminal are equal to each other .

Description

area

The present invention relates to a semiconductor module parallel circuit and a semiconductor module interconnection substrate.

background

A technique for driving parallel connected semiconductor switching elements is known from, for example, Patent Literature 1. Patent Literature 1 discloses that twisted cables that are a gate line to two IGBTs are laid adjacent to connection lines so that electromotive forces generated in the twisted pair cables are generated and polarities thereof are substantially equal to each other and gate-emitter voltages of the individual elements are substantially equal to each other, thereby providing balanced currents to flow through the individual elements.

List of citations

Patent literature

Patent Literature 1: Japanese Patent Application Laid-Open No. H9-261948

Brief description

Technical problem

In recent years, the susceptibility to the influence of inductance has increased with an increase in the speed of switching. Patent Literature 1 does not allow the influence of inductance. When a difference in inductance occurs between semiconductor elements, an imbalance occurs in the amount of current flowing through individual semiconductor elements. When such an imbalance occurs in the current flowing through the semiconductor elements, a larger amount of current flows in one of the semiconductor elements, resulting in a shortened life of the semiconductor.

the solution of the problem

A semiconductor module parallel connection of a first invention comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of the gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other.

A semiconductor module parallel connection of a second invention comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first Power semiconductor module is connected to the second signal connection for the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and a length of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and a length of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other.

A semiconductor module connection substrate of a third invention comprises: an external connection terminal; a first signal terminal connection pattern for a first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is provided for connection to a first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is provided for connection to a second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for a second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is provided for connection to a second signal terminal of the second power semiconductor module, wherein an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first Power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are the same to each other.

Advantageous Effects of the Invention

A semiconductor module parallel circuit according to the first invention comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other. As a result, it is possible to find an imbalance in the flow between the To reduce semiconductor modules, and a shortening of the life of the semiconductor modules to reduce.

A semiconductor module parallel circuit according to the second invention comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and a length of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and a length of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other. As a result, it is possible to reduce an imbalance in current between the semiconductor modules and shorten the life of the semiconductor elements.

A semiconductor module connection substrate according to the third invention comprises: an external connection terminal; a first signal terminal connection pattern for a first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is provided for connection to a first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is provided for connection to a second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for a second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is provided for connection to a second signal terminal of the second power semiconductor module, wherein an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first Power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are the same to each other. As a result, it is possible to reduce an imbalance in current between the semiconductor modules and reduce a shortening of the life of the semiconductor modules.

Figure list

• 1 Fig. 13 is a view showing a semiconductor module parallel connection according to a first embodiment.
• 2 FIG. 13 is a schematic diagram of the semiconductor module parallel connection according to the first embodiment.
• 3 FIG. 13 shows a plan view of a package that houses a semiconductor module according to the first embodiment.
• 4th FIG. 13 shows a schematic diagram of the semiconductor module according to the first embodiment.
• 5 Fig. 13 is a view showing a multilayer substrate according to the first embodiment.
• 6th Fig. 13 is a view showing a wiring pattern on the multilayer substrate according to the first embodiment.
• 7th Fig. 13 is a view showing a wiring pattern on the multilayer substrate according to the first embodiment.
• 8th Fig. 13 is a view showing a semiconductor module parallel connection in a second embodiment.
• 9 Fig. 13 is a view showing a multilayer substrate according to the second embodiment.
• 10 FIG. 13 shows a schematic view of the semiconductor module parallel connection according to the second embodiment.
• 11th Fig. 13 is a view showing a gate drive current in the semiconductor module parallel circuit according to the second embodiment.
• 12th Fig. 13 is a view showing a semiconductor module parallel connection in a third embodiment.
• 13th Fig. 13 is a view showing a multilayer substrate according to the third embodiment.
• 14th FIG. 13 shows a schematic view of the semiconductor module parallel connection according to the third embodiment.
• 15th Fig. 13 is a view showing a semiconductor module parallel connection in a fourth embodiment.
• 16 Fig. 13 is a view showing a multilayer substrate according to the fourth embodiment.
• 17th FIG. 13 shows a schematic view of the semiconductor module parallel connection according to the fourth embodiment.
• 18th Fig. 13 is a view showing a semiconductor module parallel connection in a fifth embodiment.
• 19th Fig. 13 is a view showing a multilayer substrate according to the fifth embodiment.
• 20th FIG. 13 shows a schematic view of the semiconductor module parallel connection according to the fifth embodiment.
• 21 FIG. 13 is a view showing a gate drive current in the semiconductor module parallel circuit according to the fifth embodiment.

Description of embodiments

First embodiment

1 Fig. 13 is a view showing a semiconductor module parallel connection 1 represents according to a first embodiment. The semiconductor module parallel connection 1 comprises a semiconductor module 10-1 , a semiconductor module 10-2 and a multilayer substrate 100 on. The multilayer substrate 100 is immediately above the semiconductor module 10-1 and the semiconductor module 10-2 arranged and physically secured by a fastener 50 fixed. The semiconductor module 10-1 and the semiconductor module 10-2 are electrically parallel to each other through the multilayer substrate 100 connected. In the following description, the semiconductor modules 10-1 and 10-2 referred to as semiconductor modules 10, where the semiconductor modules 10-1 and 10-2 do not have to be distinguished from one another. The semiconductor module 10 is, for example, a power semiconductor module.

When used for a three-phase two-stage inverter circuit, define the semiconductor module 10-1 and the semiconductor module 10-2 for example a U-phase leg of the three-phase two-stage inverter circuit.

2 FIG. 13 is a schematic diagram of the semiconductor module parallel connection according to the first embodiment. The semiconductor module 10-1 and the semiconductor module 10-2 are each surrounded by a broken line.

The semiconductor module 10-1 comprises a semiconductor element 30-1 and a semiconductor element 40-1 which are connected in series with each other, and a source terminal of the semiconductor element 30-1 and a drain terminal of the semiconductor element 40-1 are connected to each other.

The semiconductor module 10-2 comprises a semiconductor element 30-2 and a semiconductor element 40-2 which are connected in series with each other, and a source terminal of the semiconductor element 30-2 and a drain terminal of the semiconductor element 40-2 are connected to each other.

A gate connector 11-1 of the semiconductor element 30-1 of the semiconductor module 10-1 , a gate connector 11-2 of the semiconductor element 30-2 of the semiconductor module 10-2 and a first connection terminal 71-1 an external connection port 61 of the multilayer substrate are electrically connected to each other. A sample source connector 13-1 of the semiconductor element 30-1 of the semiconductor module 10-1 , a sample source connector 13-2 of the semiconductor element 30-2 of the semiconductor module 10-2 and a second connection terminal 72-1 of the external connection port 61 of the multilayer substrate are electrically connected to each other. The gate connector 11-1 of the semiconductor element 30-1 of the semiconductor module 10-1 can be used as a first signal port 11-1 and the gate terminal 11-2 of the semiconductor element 30-2 of the semiconductor module 10-2 can be used as a first signal port 11-2 are designated. The sample source connector 13-1 of the semiconductor element 30-1 of the semiconductor module 10-1 can be used as a second signal connection 13-1 and the sample source terminal 13-2 of the semiconductor element 30-2 of the semiconductor module 10-2 can be used as a second signal connection 13-2 are designated. The first signal connection 11-1 of the semiconductor element 30-1 of the semiconductor module 10-1 and the first signal port 11-2 of the semiconductor element 30-2 of the semiconductor module 10-2 each have a gate potential. The second signal connector 13-1 of the semiconductor element 30-1 of the semiconductor module 10-1 and the second signal terminal 13-2 of the semiconductor element 30-2 of the semiconductor module 10-2 each have a source potential.

A gate connector 12-1 of the semiconductor element 40-1 of the semiconductor module 10-1 , a gate connector 12-2 of the semiconductor element 40-2 of the semiconductor module 10-2 and a first connection terminal 71-2 an external connection port 62 of the multilayer substrate are electrically connected to each other. A sample source connector 14-1 of the semiconductor element 40-1 of the semiconductor module 10-1 , a sample source connector 14-2 of the semiconductor element 40-2 of the semiconductor module 10-2 and a second connection terminal 72-2 of the external connection port 62 of the multilayer substrate are electrically connected to each other. The gate connector 12-1 of the semiconductor element 40-1 of the semiconductor module 10-1 can be used as a third signal port 12-1 and the gate terminal 12-2 of the semiconductor element 40-2 of the semiconductor module 10-2 can be used as a third signal port 12-2 are designated. The sample source connector 14-1 of the semiconductor element 40-1 of the semiconductor module 10-1 can be used as a fourth signal port 14-1 and the sample source terminal 14-2 of the semiconductor element 40-2 of the semiconductor module 10-2 can be used as a fourth signal port 14-2 are designated. The third signal port 12-1 of the semiconductor element 40-1 of the semiconductor module 10-1 and the third signal port 12-2 of the semiconductor element 40-2 of the semiconductor module 10-2 each have a gate potential. The fourth signal connector 14-1 of the semiconductor element 40-1 of the semiconductor module 10-1 and the fourth signal connector 14-2 of the semiconductor element 40-2 of the semiconductor module 10-2 each have a source potential.

A drain connection of the semiconductor element 30-1 of the semiconductor module 10-1 and a drain terminal of the semiconductor element 30-2 of the semiconductor module 10-2 are connected to each other and connected to a DC bus on a high potential side (not shown).

A source terminal of the semiconductor element 40-1 of the semiconductor module 10-1 and a source terminal of the semiconductor element 40-2 of the semiconductor module 10-2 are connected to each other and connected to a DC bus on a low potential side (not shown).

3 shows a plan view of an assembly 20th that houses a semiconductor module 10 according to the first embodiment. Although not in 3 shown, the assembly 20th the semiconductor element 30-1 and the semiconductor element 40-1 connected in series. As in 3 are main connections 10P , Main connections 10N and main connections 10AC on a surface side of the assembly 20th provided. Two main connections 10P resting on a longitudinal one-end section of the assembly 20th are arranged in a direction orthogonal to the longitudinal direction. Two main connections 10N that are closer to a central portion of the assembly 20th are provided as the main ports 10P , are in the direction orthogonal to the longitudinal direction of the assembly 20th arranged. Anyone from the main line 10P and the main connection 10N is not limited to two in number. Anyone from the main line 10P and the main connection 10N can be one, three or more. Three main connections 10AC attached to the longitudinal other-end portion of the assembly 20th are arranged in the direction orthogonal to the longitudinal direction. The number of main ports 10AC is not limited to three. The number of main ports 10AC can be one or two, or four or more.

The main connections 10P each define a direct current positive terminal P in the semiconductor module 10, the main terminals 10N each define a DC negative terminal N in the semiconductor module 10 and the main terminals 10AC each define an alternating current connection AC in the semiconductor module 10.

A first signal connection 11th , a second signal connection 13th , a third signal connector 12th and a fourth signal connector 14th are between the main connections 10N and the main connections 10AC provided. In other words, are the first signal port 11th , the second signal connector 13th , the third signal port 12th and the fourth signal connector 14th between the DC terminals and the AC terminals provided. The second signal connector 13th and the first signal port 11th are from one side of the main connection 10AC along one side in the longitudinal direction of the assembly 20th arranged. In addition, there is the third signal connection 12th and the fourth signal connector 14th from the side of the main connection 10AC along the other side in the longitudinal direction of the assembly 20th provided.

The first signal connection 11th , the second signal connector 13th , the third signal connector 12th and the fourth signal connector 14th are with the multilayer substrate 100 connected.

4th FIG. 10 shows a schematic diagram of the semiconductor module 10 according to the first embodiment. The semiconductor module 10 has a semiconductor element 30th on that with the main connection 10P connected, and a semiconductor element 40 on that with the main connection 10N connected is. The semiconductor element 30th and the semiconductor element 40 are connected in series and an electrical connection point between them is to the main connector 10AC connected.

The semiconductor element 30th has a drain connection D1 on, the one with the main connection 10P connected to a source terminal S1 on, the one with the main connection 10AC is connected, the first signal connection 11th and the second signal terminal 13th . The drain connection has a drain potential, the source connection has a source potential and the first signal connection 11th has a gate potential.

The semiconductor element 40 has a drain connection D2 on, the one with the main connection 10AC connected to a source terminal S2 on, the one with the main connection 10N is connected, the third signal terminal 12th and the fourth signal terminal 14th . The drain connection has a drain potential, the source connection has a source potential and the third signal connection 12th has a gate potential.

In each of the semiconductor elements 30th and the semiconductor element 40 a transistor element and a diode element are connected in parallel to each other. Depending on characteristics of a load, for example, in a case of a resistive load, the connection of each diode element may be omitted.

In the first embodiment, a MOSFET is illustrated as a transistor element, but the transistor element is not limited to the MOSFET, and any other device that is switchable between a low resistance state and a high resistance state according to an electrical signal can be applied. For example, a transistor element such as an IGBT or a bipolar transistor can be used. In a case where the transistor element is an IGBT, the “drain connection” is to be replaced with a “collector connection”, the “source connection” is to be replaced with an “emitter connection” and the “sensing source connection” is closed replace with a "sampling emitter connector". Silicon (Si), silicon carbide (SiC), gallium nitride (GaN) and the like can be used as materials of the transistor elements and diode elements that make up the semiconductor elements 30th and 40 define.

5 Fig. 10 shows a plan view of the multilayer substrate 100 , the one for the parallel connection of the semiconductor modules 1 is used according to the first embodiment. In 5 exhibits the multilayer substrate 100 a plurality of layers. In 5 is a first layer, which is a visible layer, and is referred to as a front surface. A layer that is a visible layer and is located on a side opposite the front surface is referred to as a back surface. The first layer and a second layer can be invisible layers.

The external connection port 61 and the external connection port 62 are on the front surface of the multilayer substrate 100 attached. The external connection port 61 and the external connection port 62 are connected to an external connection circuit (not shown). The external connection ports 61 and 62 are on the front face in 5 attached, but can be attached to the rear surface. The external connection ports 61 and 62 can be integrated with each other.

First signal connector connection pattern 111-1 and 111-2 , second signal terminal connection pattern 113-1 and 113-2 , third signal terminal connection pattern 112-1 and 112-2 and fourth signal terminal connection pattern 114-1 and 114-2 are designed as a pattern. The third signal terminal connection patterns 112-1 and 112-2 and the fourth signal terminal connection patterns 114-1 and 114-2 are not shown.

The first signal port connection patterns 111-1 and 111-2 , the second signal terminal connection pattern 113-1 and 113-2 , the third signal terminal connection pattern 112-1 and 112-2 and the fourth signal terminal connection patterns 114-1 and 114-2 are each electrically connected to a back surface pattern through a through hole.

The first signal port connection pattern 111-1 , the second signal terminal connection pattern 113-1 , the third signal terminal connection pattern 112-1 and the fourth Signal port connection pattern 114-1 are patterns for connecting to the first signal connection 11-1 , the second signal connection 13-1 , the third signal connector 12-1 or the fourth signal connection 14-1 of the semiconductor module 10-1 .

The first signal port connection pattern 111-2 , the second signal terminal connection pattern 113-2 , the third signal terminal connection pattern 112-2 and the fourth signal terminal connection pattern 114-2 are patterns for connecting the first signal terminal 11-2 , the second signal connection 13-2 , the third signal connection 12-2 or the fourth signal connection 14-2 of the semiconductor module 10-2 .

Next, a description will be given of connecting the semiconductor module in parallel 10-1 and the semiconductor module 10-2 through the multilayer substrate 100 the parallel connection of the semiconductor modules 1 made according to the first embodiment.

6th Fig. 13 is a view showing an example in which the first signal terminal connection patterns 111-1 and 111-2 in the multilayer substrate 100 are connected to each other. In 6th is a direction that is from the external connection port 61 of the multilayer substrate 100 extending to each semiconductor module, defined as an X-direction, a direction extending from the back surface to the front surface of the multilayer substrate is defined as a Z-direction (not shown) and a direction orthogonal to the X-direction and the Z- Direction is defined as a Y direction. In 6th are the first signal port connection patterns 111-1 and 111-2 and the external connection port 61 connected or wired. The first signal port connection patterns 111-1 and 111-2 share a common line from the external connection port 61 to a point S. The line branches from the point S into a connection to the first signal terminal connection pattern 111-1 and the first signal terminal connection pattern 111-2 away. This means that the point S is a junction point. For two semiconductor modules, the point S can be a midpoint of the line between the first signal terminal connection patterns 111-1 and 111-2 being. With the line laid out as described above, a line length is from the external connection port 61 to the first signal terminal connection pattern 111-1 and a line length from the external connection port 61 to the first signal terminal connection pattern 111-2 can be equal to each other. In 6th is the line from the external connection port 61 to the first signal terminal connection patterns formed in the same layer of the multilayer substrate 100 , but need not be formed in the same layer. Different layers of the multilayer substrate 100 can be used. For example, the wiring may be from the external connection port 61 to point S and the wiring between 111-1 and 111-2 will be in different layers.

Descriptions and illustrations of the third signal terminal connection patterns 112-1 and 112-2 are similar to that of the first signal terminal connection pattern 111-1 and 111-2 and are therefore left out.

7th Fig. 13 is a view showing an example in which the second signal terminal connection patterns 113-1 and 113-2 in the multilayer substrate 100 are connected to each other. In 7th is a direction that is from the external connection port 61 of the multilayer substrate 100 from extending to each semiconductor module is defined as an X-direction, a direction extending from the back surface to the front surface of the multilayer substrate is defined as a Z-direction (not shown), and a direction orthogonal to the X-direction and the Z. -Direction is defined as a Y-direction. In 7th are the second signal terminal connection patterns 113-1 and 113-2 and the external connection port 61 connected or wired. The second signal port connection patterns 113-1 and 113-2 share a common line from the external connection port 61 to a point T. The line branches off from the point T into connection with the second signal terminal connection pattern 113-1 and the second signal terminal connection pattern 113-2 . This means that point T is a junction point. For two semiconductor modules, the point T is a midpoint of the line between the second signal terminal connection patterns 113-1 and 113-2 . With the lines laid out as described above, a line length from the external connection terminal 61 to the second signal terminal connection pattern 113-1 and a line length from the external connection port 61 to the second signal terminal connection pattern 113-2 be equal to each other. In 7th is the line from the external connection port 61 to the second signal terminal connection patterns in the same layer of the multilayer substrate 100 formed, but need not be formed in the same layer. Different layers of the multilayer substrate 100 can be used. For example, lines from the external connection port 61 to the point T and the line between 113-1 and 113-2 be in different layers.

Descriptions and illustrations of the fourth signal terminal connection patterns 114-1 and 114-2 are similar to those of the first signal terminal connection patterns 113-1 and 113-2 and are therefore left out.

The wiring involved in the combination of the lines from the external connection port 61 to the first signal connection of the semiconductor module 10-1 and lines from the second signal terminal of the semiconductor module 10-1 to the external connection port 61 are referred to as gate interconnection or gate line.

The gate interconnection for the semiconductor element 30-1 of the semiconductor module 10-1 is a combination of the lines from the external connection port 61 to the first signal terminal connection pattern 111-1 and lines from the second signal terminal connection pattern 113-1 to the external connection port 61 .

Similarly, those who have a combination of the line from the external connection port 61 to the first signal connection of the semiconductor module 10-2 and lines from the second signal connection of the semiconductor module 10-2 to the external connection port 61 are referred to as a gate interconnection. The gate interconnection for the semiconductor element 30-2 of the semiconductor module 10-2 is a combination of the lines from the external connection port 61 to the first signal terminal connection pattern 111-2 and lines from the second signal terminal connection pattern 113-2 to the external connection port 61 .

With the external connection terminal, the first signal terminal connection pattern and the second signal terminal connection pattern configured as described above, a length of the gate wiring for the semiconductor element can be determined 30-1 of the semiconductor module 10-1 and a length of the gate wiring for the semiconductor element 30-2 of the semiconductor module 10-2 be the same. Since the length of the gate interconnection or gate line for the semiconductor element 30-1 of the semiconductor module 10-1 and the length of the gate interconnection or gate line for the semiconductor element 30-2 of the semiconductor module 10-2 can be equal to each other, it is possible an imbalance in current between the semiconductor element 30-1 and the semiconductor element 30-2 to reduce.

A line inductance of the gate line or gate interconnection for the semiconductor element 30-1 of the semiconductor module 10-1 and a line inductance for the gate line or gate interconnection for the semiconductor element 30-2 of the semiconductor module 10-2 can be equal to each other. Because the line inductance of the gate line for the semiconductor element 30-1 of the semiconductor module 10-1 and the line inductance of the gate line for the semiconductor element 30-2 of the semiconductor module 10-2 may be equal to each other, it is possible to find an imbalance in current between the semiconductor element 30-1 and the semiconductor element 30-2 to reduce.

Although not described, the gate wiring is for the semiconductor element 40-1 of the semiconductor module 10-1 and the gate line or gate circuit for the semiconductor element 40-2 of the semiconductor module 10-2 designed in the same way as described above, so that a line inductance of the gate interconnection for the semiconductor element 40-1 of the semiconductor module 10-1 and a line inductance for the gate line of the semiconductor element 40-2 of the semiconductor module 10-2 can be equal to each other. As a result, it is possible to have an imbalance in current between the semiconductor element 40-1 and the semiconductor element 40-2 to reduce.

Line inductances, which are a source of voltage drops, provide equal amounts of voltage drops caused by the individual line inductances if the line inductances are equal to one another, so that current flows through the line can be equal to one another.

In the first embodiment, if there is an imbalance in current between the semiconductor modules to such an extent that it has substantially no influence, the lengths of the lines are regarded as equal to each other. Similarly, if there is an imbalance in current between the semiconductor modules to such an extent that it has essentially no influence, the inductances of lines are considered to be equal to each other.

The gate line that is in the multilayer substrate 100 as described above, designed to reduce an imbalance in current between the semiconductor modules can be achieved in a smaller number of layers.

It is preferable for line patterns or for circuit patterns to have essentially the same widths when forming the gate line in the multilayer substrate 100 as described above. In the multilayer substrate 100 According to the first embodiment, a distance in the Z direction between the external connection terminal and the first signal terminal connection pattern, preferably short, and a distance in the Z direction between the external connection terminal and the second signal terminal connection pattern is preferably short. That is, the external connection terminal and the first signal terminal connection patterns, and the external connection terminal and the second signal terminal connection patterns preferably have lines designed such that wiring patterns overlap when the multilayer substrate 100 is viewed in the positive direction of the Z direction. With the lines or interconnections laid out as described above, it is possible to achieve a configuration that is less susceptible to noise. The above description is made as one in which two semiconductor modules are arranged in parallel, but a similar configuration can be applied when three or more semiconductor modules are arranged in parallel. In the above description, the line lengths from the branch point (point S) to the first signal terminal connection patterns of the two semiconductor modules are equal to each other, and the line lengths from the branch point (point T) to the second signal terminal connection patterns of the two semiconductor modules are equal to each other. In a case of three semiconductor modules, similarly, the line lengths from the branch point to the first signal terminal connection patterns of the three semiconductor modules are equal to each other, and the line lengths from the branch point to the second signal terminal connection patterns of the three semiconductor modules are equal to each other. As a result, the individual gate line lengths for the three semiconductor modules can be identical to each other. Since the individual gate line lengths for the three semiconductor modules are equal to each other, it is possible to reduce an imbalance in current among the three semiconductor elements. The above description is made as an example in which the junction points are used for the wiring from the external connection terminal to the first signal terminal connection patterns of the semiconductor modules and the wiring from the external connection terminal to the second signal terminal connection patterns of the semiconductor modules, but it is not limited thereto. The lines from the external connection terminal to the first signal terminal connection patterns of the semiconductor modules and the line from the external connection terminal to the second signal terminal connection patterns of the semiconductor modules can be configured without using the branch points. Even in that case, the individual gate line lengths are equal to each other, which makes it possible to reduce an imbalance in current among the three semiconductor elements.

The semiconductor module parallel connection according to the first embodiment includes: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate connecting a plurality of the power semiconductor modules, each of the power semiconductor modules including: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module with the first signal terminal of the first Power semiconductor module is connected; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, which makes it possible to have an imbalance in the flow to reduce between the semiconductor modules.

The semiconductor module parallel connection according to the first embodiment includes: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate connecting a plurality of the power semiconductor modules, each of the power semiconductor modules including: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and a length of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and a length of the gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, making it possible to create an imbalance in the flow between the hal to reduce conductor modules, and a shortening of the life of the semiconductor modules to reduce.

In the semiconductor module parallel connection according to the first embodiment, the gate line length for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and the gate line length for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, thereby making it possible to reduce the imbalance in current between the semiconductor modules.

In the semiconductor module parallel connection according to the first embodiment, the line from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and the line from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module are formed in a first layer of the multilayer substrate, and the line from the second Signal terminal connection patterns for the first power semiconductor module to the external connection terminal and the line from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are formed in a second layer of the multilayer substrate, whereby it is possible to reduce an imbalance in current between the semiconductor modules.

The semiconductor module connection substrate according to the first embodiment includes: an external connection terminal; a first signal terminal connection pattern for a first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is provided for connection to a first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is provided for connection to a second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for a second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, the second signal terminal connection pattern for the second power semiconductor module being provided for connection to a second signal terminal of the second power semiconductor module, and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first Power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are the same to each other, which makes it possible to use a U Reduce the current balance between the semiconductor modules.

Second embodiment

A parallel connection of the semiconductor module 10-1 and the semiconductor module 10-2 through a Multilayer substrate 200 a semiconductor module parallel circuit 2 in a second embodiment are described.

8th Fig. 13 is a view showing a configuration of the semiconductor module parallel connection 2 represents, the two semiconductor modules are arranged in parallel to each other.
9 Fig. 13 is a view showing the multilayer substrate 200 the parallel connection of the semiconductor modules 2 in the second embodiment. 10 Fig. 13 is a schematic view of a cross section of the multilayer substrate 200 the 9 along a line A-A '. In 10 is a direction that is from the external connection port 61 of the multilayer substrate 200 extending to each semiconductor module is defined as an X direction, a direction extending from a back surface to a front surface of the multilayer substrate is defined as a Z direction, and a direction is orthogonal to the X direction and the Z direction defined as a Y direction (not shown). The multilayer substrate 200 is formed into three layers: a first layer 201 ; a second layer 202 ; and a third layer 203 . In the X direction is a coordinate position of the external connection terminal 61 fixed to 0. In the Z direction is a coordinate position of the third layer 203 of the multilayer substrate 200 in contact with the semiconductor modules 10-1 and 10-2 set to 0. The first layer is defined as a front surface and the third layer is defined as a back surface. The first layer and the third layer can be invisible layers. The semiconductor module 10-1 and the semiconductor module 10-2 are arranged in parallel with each other in the X direction, and the semiconductor module 10-1 and the semiconductor module 10-2 are closer to the external connection port from one side in this order 61 arranged.

In 10 a solid line indicates a wire from the external connection port 61 to the first signal terminal connection pattern, and a broken line indicates a line from the second signal terminal connection pattern to the external connection terminal 61 on. The first signal port connection patterns 111-1 and 111-2 and the second signal terminal connection patterns 113-1 and 113-2 are in the third shift 203 of the multilayer substrate 200 designed for the purpose of connection and the individual signal connections for the individual semiconductor modules.

The one on the first shift 201 of the multilayer substrate 200 The line formed is referred to as the gate return line, the line in the second layer 202 is referred to as the gate forward line and the one in the third layer 203 formed line is referred to as output line. The gate forward line is to the external connection terminal 61 connected. The gate forward line is connected to the gate return line. The gate return line is with the first signal terminal connection patterns 111-1 and 111-2 connected. The line from the gate return line to the first signal terminal connection pattern 111-1 is not connected to the gate forward line. Similarly, the gate return is from the first signal terminal connection patterns 111-2 not connected to the gate forward line. A position in the X direction where the gate return line and the first signal terminal connection pattern 111-2 are connected to each other is closer to the external connection port 61 with respect to the X direction as a position in the X direction where the gate forward line and the gate return line are connected to each other. In other words, the gate lead is that in the second layer 202 is formed connected to the gate return line, which is in the first layer 201 is formed, and the gate return line is connected to the first signal terminal connection pattern 111-2 connected at the position offset in a direction opposite to the X direction from the position where the gate lead included in the second layer 202 is formed connected to the gate return line that is in the first layer 201 is trained.

The position in the X direction where the gate return and the first signal terminal connection pattern 111-2 are connected to each other is referred to as junction point Q.

The second signal port connection patterns 113-1 and 113-2 are connected to the output line. A position in the X direction where the second signal terminal connection pattern 113-1 connected to the output line is closer to the external connection port 61 with respect to the X direction as a position in the X direction where the second signal terminal connection pattern 113-2 is connected to the output line. The output line is with the external connection port 61 connected.

The position in the X direction where the second signal terminal connection pattern 113-1 connected to the output line is referred to as a connection point P.

When a line length from the external connection port 61 to the first signal terminal connection pattern 111-1 denoted by Len1g and a line length from the second signal terminal connection pattern 113-1 to the external connection port 61 denoted by Lenls, a line length Len1 is the gate line from the semiconductor module 10-1 Len1g + Len1s. Similarly, if a line length from the external connection port 61 to the first signal terminal connection pattern 111-2 denoted by Len2g and a line length from the second signal terminal connection pattern 113-2 to the external connection port 61 is denoted by Len2s, a line length Len2 is the gate line of the semiconductor module 10-2 Len2g + Len2s. In the second embodiment, the gate line is formed in such a way that the gate line length (line length Len1) for the first power semiconductor module is from the external connection terminal 61 to the first signal connection connection pattern for the first power semiconductor module and from the second signal connection connection pattern for the first power semiconductor module to the external connection connection, and the gate line length (line length Len2) for the second power semiconductor module from the external connection connection to the first signal connection connection pattern for the second power semiconductor module and from the second signal connection connection pattern for the second power semiconductor module to the external connection terminal are equal to one another (Len1 = Len2). This means that the gate line is designed in such a way that a line inductance that is in the gate line for the semiconductor module 10-1 is generated and a line inductance in the gate line for the semiconductor module 10-2 is generated are equal to each other. Note that, for example, the first power semiconductor module is the semiconductor module 10-1 and the second power semiconductor module is the semiconductor module 10-2 is.

In 10 Len1g is a line length of a line from the external connection port 61 to the first signal terminal connection pattern 111-1 . Len1s is a line length of a combination of a line from the second signal terminal connection pattern 113-1 to the connection point P and a line from the connection point P to the external connection terminal 61 . Len2g is a line length for a combination of a line from the external connection port 61 to the branch point Q and a line from the branch point Q to the first signal terminal connection pattern 111-2 . Len2s is a line length of one line from the second signal terminal connection pattern 113-2 to the external connection port 61 .

In the second embodiment, the line is designed as described above in such a way that the line length of the gate line for the semiconductor module 10-1 and the line length of the gate line for the semiconductor module 10-2 can be equal to each other. This means that the gate line is designed in such a way that Len1 = Len2 is true. The line inductance that is in the gate line for the semiconductor module 10-1 is generated, and the line inductance that is in the gate line for the semiconductor module 10-2 generated can be equal to each other.

Next, a gate drive current is determined in the semiconductor module parallel circuit 2 described. A power input from the external connection port 61 flows through the gate forward line that is in the second layer 202 of the multilayer substrate 200 and then through the gate return that is in the first layer 201 of the multilayer substrate 200 is trained. Next, at the gate return branch point Q, the current branches by current flows in the first signal terminal connection pattern 111-1 and the first signal terminal connection pattern 111-2 provide.

One of the branched gate drive currents flows to the first signal terminal 11-1 of the semiconductor module 10-1 via the first signal terminal connection pattern 111-1 , and similarly the other flows to the first signal terminal 11-2 of the semiconductor module 10-2 via the first signal terminal connection pattern 111-2 .

Next, a current output flows from the second signal terminal 13-1 of the semiconductor module 10-1 into the output line of the multilayer substrate 200 via the second signal terminal connection pattern 113-1 . Similarly, a current output flows from the second signal terminal 13-2 of the semiconductor module 10-2 into the output line of the multilayer substrate 200 via the second signal terminal connection pattern 113-2 . The current output from the second signal port connection pattern 113-2 merges with the power output from the second signal terminal connection pattern 113-1 at the connection point P on the output line. The merged stream is from the external connection port 61 issued.

Stromeingaben an die ersten Signalanschlüsse der Halbleitermodule 10-1 und 10-2 können genähert werden wie in der Gleichung (2) nachstehend. $$\text{I1g}=\text{I2g}=\text{Ig}$$

Nachstehende Formel (3) ist von den Formeln (1) und (2) abgeleitet. $${\text{Ig}}_{12}=2\text{Ig}$$

Aus den Formeln (2) und (3), sind die Ströme I1g und I2g, die an dem Abzweigungspunkt Q abgezweigt sind und davon durch die Gate-Rückleitung fließen jeweils 1/2 des Stroms Ig₁₂, der durch die Gate-Hinleitung fließt. Mit anderen Worten ist der Strom Ig₁₂, der durch die Gate-Hinleitung fließt, ein Strom (2Ig), das Doppelte des Stroms Ig (I1g, I2g) ist, der an dem Abzweigungspunkt Q abgezweigt ist und davon wegfließt. 11th Fig. 13 is a view showing a gate drive current flowing through each layer of the multilayer substrate 200 flows. When a current flowing through the gate forward line is denoted by Ig ₁₂ , a current flowing from the branch point Q to the first signal terminal connection pattern 111-1 flows through I1g and is a current flowing from the junction point Q to the first signal terminal connection pattern 111-2 flows through I2g, the following equation (1) applies. $${\text{Ig}}_{\text{12th}}=\text{I1g}+\text{I2g}$$

Current inputs to the first signal connections of the semiconductor modules 10-1 and 10-2 can be approximated as in equation (2) below. $$\text{I1g}=\text{I2g}=\text{Ig}$$

The following formula (3) is derived from formulas (1) and (2). $${\text{Ig}}_{\mathrm{12th}}=2\text{Ig}$$

From formulas (2) and (3), the currents I1g and I2g which are branched at the junction point Q and flow therefrom through the gate return line are each 1/2 of the current Ig ₁₂ flowing through the gate forward line. In other words, the current Ig ₁₂ flowing through the gate forward line is a current (2Ig) that is twice the current Ig (I1g, I2g) that is branched off at the junction point Q and flows away therefrom.

Stromausgaben von den zweiten Signalanschlüssen der Halbleitermodule 10-1 und 10-2 wie in Formel (5) genähert werden. $$\text{I1s}=\text{I2s}=\text{Is}$$

Nachstehende Formel (6) ist von den Formeln (4) und (5) abgeleitet. $${\text{Is}}_{12}=\text{2Is}$$

Aus den Formeln (5) und (6) sind die Ströme I1s und I2s, die durch die Ausgangsleitung fließen, bevor sie sich an dem Verbindungspunkt P vereinigen, jeweils 1/2 des Stroms Is₁₂, der durch die Ausgangsleitung fließt. Mit anderen Worten ist der Strom Is₁₂, der durch die Ausgangsleitung fließt, ein Strom (2Is), der das Doppelte des Stroms Is (I1s, I2s) ist, der vor dem Vereinigen an dem Verbindungspunkt P fließt.Next, when a current flowing through the output _{line is denoted by IS 12} , a current is that from the second signal terminal connection pattern 113-2 flows through denoted I2s, and a current flowing from the second signal terminal connection pattern 113-1 flows is denoted by I1s, then the following formula (4) applies. $$\text{I1s}+\text{I2s}={\text{Is}}_{\mathrm{12th}}$$

Current outputs from the second signal connections of the semiconductor modules 10-1 and 10-2 as approximated in formula (5). $$\text{I1s}=\text{I2s}=\text{Is}$$

The following formula (6) is derived from formulas (4) and (5). $${\text{Is}}_{\mathrm{12th}}=\text{2Is}$$

From formulas (5) and (6), the currents I1s and I2s flowing through the output line before joining at the junction point P are each 1/2 of the current Is ₁₂ flowing through the output line. In other words, the current Is ₁₂ flowing through the output line is a current (2Is) that is twice the current Is (I1s, I2s) flowing at the connection point P before merging.

The current (Ig) flowing from the junction point Q to the first signal connection of the semiconductor module 10-1 flows and the current (Is) that flows from the second signal connection to the semiconductor module 10-2 flows at the connection point P may be equal to each other. This means that an amount of voltage drop in the line that extends from the junction point Q to the first signal terminal of the semiconductor module 10-1 and an amount of voltage drop in the line extending from the second signal terminal to the semiconductor module 10-2 extending to the connection point P may be equal to each other.

In the second embodiment, a current flows which is the sum of the gate currents flowing through the first signal terminals of the semiconductor modules 10-1 and 10-2 flow through the gate lead in the multilayer substrate 200 is designed such that the line inductances of the gate interconnection for the semiconductor module 10-1 and the gate line for the semiconductor module 10-2 can be equal to each other.

As the line inductance of the gate line for the semiconductor module 10-1 and the line inductance for the gate line for the semiconductor module 10-2 can be equal to each other, it is possible to reduce an imbalance in current generated between the semiconductor modules when the semiconductor modules are driven in parallel.

It is preferable to adapt wiring patterns to have substantially the same width when forming the gate wiring in the multilayer substrate 200 .

In the second embodiment, the line to the first signal connections of the semiconductor modules is in the two layers of the multilayer substrate 200 designed such that the gate line lengths for the semiconductor modules can be equal to one another.

In the second embodiment, if there is an imbalance in current between the semiconductor modules to such an extent that it has substantially no influence, the lengths of the lines are considered to be equal to each other. Similarly, if there is an imbalance in current between the semiconductor modules to such an extent that it has essentially no influence, the inductances of the line are considered to be equal to each other.

Although not described, the gate lines are for the semiconductor element 40-1 of the semiconductor module 10-1 and the gate line for the semiconductor element 40-2 of the semiconductor module 10-2 in the same manner as discussed above, such that a line inductance of the gate line for the semiconductor element 40-1 of the semiconductor module 10-1 and a line inductance of the gate line for the semiconductor element 40-2 of the semiconductor module 10-2 can be equal to each other. As a result, it is possible to suffer from an imbalance in current between the semiconductor element 40-1 and the semiconductor element 40-2 to reduce.

In the second embodiment, the gate return is in the first layer 201 of the multilayer substrate 200 and the output line is in the third layer 203 of the multilayer substrate 200 educated. Alternatively, the Output line in the first layer 201 of the multilayer substrate 200 be formed and the gate return line can be in the third layer 203 of the multilayer substrate 200 be trained.

In the semiconductor module parallel connection according to the second embodiment, the line from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and the line from the external connection terminal to the first signal terminal connection pattern of the second power semiconductor module are in the first layer 201 and the third layer 202 of the multilayer substrate, thereby making it possible to reduce an imbalance in current between the semiconductor modules.

Third embodiment

The above-described first and second embodiments give an example in which two semiconductor modules are arranged in parallel with each other. A third embodiment, which will be described below, gives an example in which three semiconductor modules are arranged in parallel with each other. 12th Fig. 13 is a view showing a configuration of a semiconductor module parallel connection 3 represents in which three semiconductor modules are arranged in parallel to each other. The semiconductor modules 10-1 and 10-2 and a semiconductor module 10-3 are arranged in parallel. The third embodiment differs from the first and the second embodiment in that the semiconductor module 10-3 is added. The semiconductor modules 10-1 , 10-2 and 10-3 are with a multilayer substrate 300 connected and driven in parallel.

13th Fig. 13 is a view showing the multilayer substrate 300 the parallel connection of the semiconductor modules 3 in the third embodiment. In 13th the multilayer substrate differs 300 among the multilayer substrates in the first and second embodiments in that a first signal terminal connection pattern 111-3 , a second signal terminal connection pattern 113-3 , a third signal terminal connection pattern 112-3 and a fourth signal terminal connection pattern 114-3 that come with the semiconductor module 10-3 are connected, are formed.

The first signal port connection pattern 111-3 , the second signal terminal connection pattern 113-3 , the third signal terminal connection pattern 112-3 and the fourth signal terminal connection pattern 114-3 are patterns for connecting to the first signal connector 11-1 , the second signal connection 13-1 , the third signal connector 12-1 or the fourth signal connection 14-1 of the semiconductor module 10-3 .

14th Fig. 13 is a schematic view of a cross section of the multilayer substrate 300 the 13th along a line B-B '. In 14th is a direction extending from the external connection port 61 of the multilayer substrate 300 extending to each semiconductor module, defined as an X direction, is a direction extending from a rear surface to a front surface of the multilayer substrate 300 is defined as a Z direction, and a direction orthogonal to the X direction and the Z direction is defined as a Y direction (not shown). The multilayer substrate 300 is made up of three layers: a first layer 301 ; a second layer 302 ; and a third layer 303 . An interlayer removal between the first layer 301 and the second layer 302 and an interlayer removal between the second layer 302 and the third layer 303 are designed to be equal to each other. In the X direction is a coordinate position of the external connection terminal 61 fixed to 0. In the Z direction is a coordinate position of the third layer 303 of the multilayer substrate 300 fixed to 0. The first layer is defined as a front surface and the third layer is defined as a back surface. The first layer and the third layer can be invisible layers. The semiconductor modules 10-1 , 10-2 and 10-3 are arranged in parallel to each other in the X direction and the semiconductor module 10-1 , the semiconductor module 10-2 and the semiconductor module 103 are closer to the external connection terminal from one side in this order 61 arranged.

In 14th a solid line indicates a wire from the external connection port 61 to the first signal terminal connection pattern, and a broken line indicates a line from the second signal terminal connection pattern to the external connection terminal 61 on. The first signal port connection patterns 111-1 , 111-2 and 111-3 and the second signal terminal connection patterns 113-1 , 113-2 and 113-3 are in the third shift 303 of the multilayer substrate 300 designed for the purpose of connection to individual signal connections for the individual semiconductor modules.

The line or interconnection that is in the first layer 301 of the multilayer substrate 300 is formed is referred to as the gate return line, which is in the second layer 302 formed line or interconnection is referred to as gate forward line, and one in the third layer 303 formed line or interconnection is referred to as an output line. The gate forward line is to the external connection terminal 61 connected. The gate forward line is connected to the gate return line. The gate return line is with the first signal terminal connection patterns 111-1 , 111-2 and 111-3 connected. The line from the gate return line to the first signal terminal connection pattern 111-1 is not connected to the gate forward line. Similarly, the lines are from the gate return line to the first signal terminal connection pattern 111-2 and the lines from the gate return line to the first signal terminal connection pattern 111-3 not connected to the gate forward line. A position in the X direction where the gate return line and the first signal terminal connection pattern 111-3 are connected to each other is closer to the external connection port 61 with respect to the X direction as a position in the X direction where the gate forward line and the gate return line are connected to each other. In other words, the gate lead is that in the second layer 302 is formed connected to the gate return line, which is in the first layer 301 is formed, and the gate return line is connected to the first signal terminal connection pattern 111-3 connected at the position offset in a direction opposite to the X direction from the position where the gate lead included in the second layer 302 is formed connected to the gate return line that is in the first layer 301 is trained. A position in the X direction where the gate return line and the first signal terminal connection pattern 111-2 are connected to each other is closer to the external connection port 61 in terms of the X direction as the position in the X direction where the gate return line and the first signal terminal connection pattern 111-3 are connected to each other.

The position in the X direction where the gate return and the first signal terminal connection pattern 111-3 are connected to each other is referred to as junction point Q1. The position in the X direction where the gate return and the first signal terminal connection pattern 111-2 are connected to each other is referred to as junction point Q2.

The second signal port connection patterns 113-1 , 113-2 and 113-3 are connected to the output line. A position in the X direction where the second signal terminal connection pattern 113-2 connected to the output line is closer to the external connection port 61 with respect to the X direction as a position in the X direction where the second signal terminal connection pattern 113-3 is connected to the output line. A position in the X direction where the second signal terminal connection pattern 113-1 connected to the output line is closer to the external connection port 61 with respect to the X direction as a position in the X direction where the second signal terminal connection pattern 113-2 is connected to the output line. The output line is with the external connection port 61 connected.

The position in the X direction where the second signal terminal connection pattern 113-2 connected to the output line is referred to as a connection point P1, and the position in the X direction where the second signal terminal connection pattern 113-1 connected to the output line is referred to as a connection point P2.

When a line length from the external connection port 61 to the first signal terminal connection pattern 111-1 is denoted by Len1g and a line length from the second signal terminal connection pattern 113-1 to the external connection port 61 denoted by Len1s, is a line length Len1 of a gate line for the semiconductor module 10-1 Len1g + Len1s. Similarly, if a line length from the external connection port 61 to the first signal terminal connection pattern 111-2 denoted by Len2g and a line length from the second signal terminal connection pattern 113-2 to the external connection port 61 denoted by Len2s, a line length Len2 is a gate line for the semiconductor module 10-2 Len2g + Len2s. Similarly, if a line length from the external connection port 61 to the first signal terminal connection pattern 111-3 is denoted by Len3g and a line length from the second signal terminal connection pattern 113-3 to the external connection port 61 denoted by Len3s, is a line length Len3 of a gate line for the semiconductor module 10-3 Len3g + Len3s.

In the third embodiment, the gate line is formed such that the gate line length (line length Len1) for the first power semiconductor module from the external connection terminal 61 to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal 61 , the gate line length (line length Len2) for the second power semiconductor module from the external connection terminal 61 to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal 61 , and the gate line length (line length Len3) for a third power semiconductor module from the external connection terminal 61 to the first signal terminal connection pattern for the third power semiconductor module and from the second signal terminal connection pattern for the third power semiconductor module to the external connection terminal 61 are the same to each other (Len1 = Len2 = Len3). This means that the gate line is designed in such a way that the line inductances that are in the gate line for the semiconductor module 10-1 and the gate line for the semiconductor module 10-2 are generated, and a line inductance that is in the gate line for the semiconductor module 10-3 is generated are equal to each other.

It is preferable to adjust the wiring patterns to have substantially the same widths when forming the gate wiring in the multilayer substrate 300 .

In 14th Len1g is a line length of a line from the external connection port 61 to the first signal terminal connection pattern 111-1 . Len1s is a line length of a combination of a line from the second signal terminal connection pattern 113-1 to the connection point P2 and a line from the connection point P2 to the external connection terminal 61 . Len2g is a line length of a combination of a line from the external connection port 61 to the branch point Q2 and a line from the branch point Q2 to the first signal terminal connection pattern 111-2 . Len2s is a line length of a combination of a line from the second signal terminal connection pattern 113-2 to the connection point P1 and a line from the connection point P1 to the external connection terminal 61 . Len3g is a line length of a combination of a line from the external connection port 61 to the branch point Q1 and a line from the branch point Q1 to the first signal terminal connection pattern 111-3 . Len3s is a line length of one line from the second signal terminal connection pattern 113-3 to the external connection port 61 .

In the third embodiment, the line is designed as described above in such a way that the line length of the gate line for the semiconductor module 10-1 , the line length of the gate line for the semiconductor module 10-2 and the line length for the gate line of the semiconductor module 10-3 can be equal to each other. This means that the gate line is designed in such a way that Len1 = Len2 = Len3 is true. As the gate line lengths of the semiconductor modules 10-1 , 10-2 and 10-3 can be equal to each other, it is possible to reduce an imbalance in current generated among the semiconductor modules when the semiconductor modules are driven in parallel.

In the third embodiment, the line lengths are the gate interconnection for the semiconductor module 10-1 , the line length for the gate line of the semiconductor module 10-2 and the line length for the gate line of the semiconductor module 10-3 equal to each other, such that the amount of voltage drops due to the line inductances can be equal to each other, thereby making it possible to reduce an imbalance in current generated among the semiconductor modules when the semiconductor modules are driven in parallel.

In the third embodiment, the wiring of the first signal terminals of the semiconductor modules is in the two layers of the multilayer substrate 300 designed such that the gate line lengths of the semiconductor modules can be equal to one another.

In the third embodiment, if there is an imbalance in current among the semiconductor modules to such an extent that it has substantially no influence, the lengths of a line length are considered to be equal to each other. Similarly, if there is an imbalance in current among the semiconductor modules to such an extent that it has essentially no influence, the inductances of lines are considered to be equal to each other.

In the third embodiment, the gate return is in the first layer 301 of the multilayer substrate 300 and the output line is in the third layer 303 of the multilayer substrate 300 educated. Alternatively, the output line can be in the first layer 301 of the multilayer substrate 300 may be formed, and the gate return line may be in the third layer 303 of the multilayer substrate 300 be trained.

The semiconductor module parallel circuit according to the third embodiment includes: a first power semiconductor module; a second power semiconductor module; a third power semiconductor module; and a multilayer substrate that interconnects a plurality of the power semiconductor modules, each of the power semiconductor modules including: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first Signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module; a first signal terminal connection pattern for the third power semiconductor module, wherein the first signal terminal connection pattern for the third power semiconductor module is connected to the first signal terminal of the third power semiconductor module; and a second signal terminal connection pattern for the third power semiconductor module, wherein the second signal terminal connection pattern for the third power semiconductor module is connected to the second signal terminal of the third power semiconductor module, and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal, and an inductance of a Gate line for the third power semiconductor mod ul from the external connection terminal to the first signal terminal connection pattern for the third power semiconductor module and from the second signal terminal connection pattern for the third power semiconductor module to the external connection terminal are equal to each other, thereby making it possible to reduce an imbalance in current among the semiconductor modules.

Fourth embodiment

A fourth embodiment as described below gives an example in which interlayer distances of a multilayer substrate are equal to each other. A description will be made of an example in which two semiconductor modules are arranged in parallel. 15th Fig. 13 is a view showing a semiconductor module parallel connection 4th of the fourth embodiment. 16 Fig. 13 is a view showing a multilayer substrate 400 the parallel connection of the semiconductor modules 4th in the fourth embodiment. 17th Fig. 13 is a schematic view of a cross section of the multilayer substrate 400 the 16 along a line C-C '. A basic configuration and each wire connection are similar to those in the second embodiment. The fourth embodiment differs from the second embodiment in points that will be described. In the multilayer substrate 400 the 17th is an interlayer removal between a first layer 401 and a second layer 402 and an interlayer removal between the second layer 402 and a third layer 403 designed to be equal to each other. That is, an interlayer distance between the layer having a gate return line formed therein and the layer having a gate return line formed therein and an interlayer distance between the layer having the gate return line formed therein and the layer having the output line formed therein are formed equal to each other.

The interlayer distance between the layer having the gate return formed therein and the layer having the gate return formed therein and the interlayer distance between the layer having the gate return formed therein and the layer having the Having output line formed therein, are formed equal to one another, such that the influence of mutual inductances can be reduced.

Auf ähnliche Weise kann ein Spannungsabfall aufgrund einer Leitungsinduktivität der dritten Schicht 403 durch nachstehende Formel (8) ausgedrückt werden. $$\Delta \text{V3}=\text{L3}\times \left({\text{di}}_{\text{L3}}/\text{dt}\right)-\text{M23}\times \left({\text{di}}_{\text{L3}}/\text{dt}\right)-\text{M}13\times \left({\text{di}}_{\text{L3}}/\text{dt}\right)$$

L1 repräsentiert eine Selbstinduktivität der ersten Schicht 401, L3 repräsentiert eine Selbstinduktivität der dritten Schicht 403, M13 repräsentiert eine gegenseitige Induktivität zwischen der ersten Schicht 401 und der zweiten Schicht 402, M23 repräsentiert eine gegenseitige Induktivität zwischen der zweiten Schicht 402 und der dritten Schicht 403, M13 repräsentiert eine gegenseitige Induktivität zwischen der ersten Schicht 401 und der dritten Schicht 403, di_L1/dt repräsentiert ein Zeitdifferential eines durch die erste Schicht 401 fließenden Stroms und di_L3/dt repräsentiert ein Zeitdifferential eines durch die dritte Schicht 403 fließenden Stroms.A voltage drop due to a line inductance of the first layer 401 can be expressed by the following formula (7). $$\mathrm{<figure-callout\; id="1"\; label="\Delta \; V"\; filenames="DE112019007118T5\_0021.png,DE112019007118T5\_0023.png"\; state="\{\{state\}\}">\Delta </figure-callout>}\text{V}1=\text{L1}\times \left({\text{di}}_{\text{L.}1}/\text{German}\right)-\text{M12}\times \left({\text{di}}_{\text{L.}1}/\text{German}\right)-\text{M.}\mathrm{13th}\times \left({\text{di}}_{\text{L.}1}/\text{German}\right)$$

Similarly, a voltage drop due to line inductance of the third layer 403 can be expressed by the following formula (8). $$\Delta \text{V3}=\text{L3}\times \left({\text{di}}_{\text{L3}}/\text{German}\right)-\text{M23}\times \left({\text{di}}_{\text{L3}}/\text{German}\right)-\text{M.}\mathrm{13th}\times \left({\text{di}}_{\text{L3}}/\text{German}\right)$$

L1 represents a self inductance of the first layer 401 , L3 represents a self inductance of the third layer 403 , M13 represents mutual inductance between the first layer 401 and the second layer 402 , M23 represents mutual inductance between the second layer 402 and the third layer 403 , M13 represents mutual inductance between the first layer 401 and the third layer 403 , di _L1 / dt represents a time differential of one through the first layer 401 flowing current and di _L3 / dt represents a time differential of one through the third layer 403 flowing stream.

Da eine Entfernung zwischen dem ersten Signalverbindungsmuster 111-1 und dem ersten Signalverbindungsmuster 111-2 und eine Entfernung zwischen dem zweiten Signalverbindungsmuster 113-1 und dem zweiten Signalverbindungsmuster 113-2 dazu ausgebildet gleich zueinander zu sein, sind eine Leitungslänge in der ersten Schicht 401 und eine Leitungslänge in der dritten Schicht 403 gleich zueinander, und daher gilt nachstehende Formel (10) . $$\text{L1}=\text{L3}=\text{L}$$

Da ein Strom, der durch die erste Schicht 401 fließt und ein Strom, der durch die dritte Schicht 403 fließt, gleich zueinander sind, gilt nachstehende Formel (11). $${\text{di}}_{\text{L}1}/\text{dt}={\text{di}}_{\text{L3}}/\text{dt}=\text{di}/\text{dt}$$

Aus den Formeln (7) bis (11) sind die Spannungsabfälle aufgrund der Leitungsinduktivitäten der ersten Schicht 401 und der dritten Schicht 403 durch Formeln (12) und (13) wie nachstehend ausgedrückt. $$\Delta \text{V}1=\text{L}\times \left(\text{di}/\text{dt}\right)-\text{M}\times \left(\text{di}/\text{dt}\right)-\text{M}13\times \left(\text{di}/\text{dt}\right)$$

$$\Delta \text{V3}=\text{L}\times \left(\text{di}/\text{dt}\right)-\text{M}\times \left(\text{di}/\text{dt}\right)-\text{M}13\times \left(\text{di}/\text{dt}\right)$$

Es kann aus den Formeln (12) und (13) erkannt werden dass die Spannungsabfälle aufgrund der Leitungsinduktivitäten der ersten Schicht 401 und der dritten Schicht 403 gleich zueinander sind.In the fourth embodiment, since the interlayer removal between the first layer 401 and the second layer 402 and the interlayer distance between the second layer 402 and the third layer 403 are designed to be equal to each other, the following formula (9) applies. $$\text{M.}\mathrm{12th}=\text{M.}23=\text{M.}$$

Da is a distance between the first signal connection pattern 111-1 and the first signal connection pattern 111-2 and a distance between the second signal connection pattern 113-1 and the second signal connection pattern 113-2 designed to be equal to one another are a line length in the first layer 401 and a line length in the third layer 403 equal to each other, and therefore formula (10) below holds. $$\text{L1}=\text{L3}=\text{L.}$$

Because a stream that runs through the first layer 401 flows and a current that passes through the third layer 403 flows are equal to each other, the following formula (11) applies. $${\text{di}}_{\text{L.}1}/\text{German}={\text{di}}_{\text{L3}}/\text{German}=\text{di}/\text{German}$$

From formulas (7) to (11) are the voltage drops due to the line inductances of the first layer 401 and the third layer 403 by formulas (12) and (13) as expressed below. $$\mathrm{<figure-callout\; id="1"\; label="\Delta \; V"\; filenames="DE112019007118T5\_0021.png,DE112019007118T5\_0023.png"\; state="\{\{state\}\}">\Delta </figure-callout>}\text{V}1=\text{L.}\times \left(\text{di}/\text{German}\right)-\text{M.}\times \left(\text{di}/\text{German}\right)-\text{M.}\mathrm{13th}\times \left(\text{di}/\text{German}\right)$$

$$\Delta \text{V3}=\text{L.}\times \left(\text{di}/\text{German}\right)-\text{M.}\times \left(\text{di}/\text{German}\right)-\text{M.}\mathrm{13th}\times \left(\text{di}/\text{German}\right)$$

It can be seen from formulas (12) and (13) that the voltage drops due to the line inductances of the first layer 401 and the third layer 403 are equal to each other.

In the fourth embodiment, the interlayer distance is between the first layer 401 and the second layer 402 and the interlayer distance between the second layer 402 and the third layer 403 designed to be equal to each other, so that the influence of the mutual inductances can be reduced. Since the influence of the mutual inductances can be reduced, a line inductance of the gate line for the semiconductor module 10-1 and a line inductance of a gate line for the semiconductor module 10-2 be equal to each other. As the line inductance in the gate line for the semiconductor module 10-1 and the line inductance for the gate line for the semiconductor module 10-2 can be equal to each other, the amounts of voltage drops due to the line inductances can be equal to each other, and it is possible to reduce an imbalance in current generated between the semiconductor modules when the semiconductor modules are driven in parallel.

Although the fourth embodiment described above gives an example in which two semiconductor modules are arranged in parallel with each other, the influence of mutual inductances can be similarly reduced even in a case where three semiconductor modules are arranged.

In the fourth embodiment, if there is an imbalance in current between the semiconductor modules to such an extent that it has substantially no influence, the lengths of the lines are considered to be equal to each other. Similarly, the inductances of the lines are considered to be equal to each other if there is an imbalance in current between semiconductor modules to such an extent that it has essentially no influence.

Fifth embodiment

A fifth embodiment is an embodiment in which the influence of a line inductance is further reduced. The fifth embodiment, which will be described below, gives an example in which three semiconductor modules are arranged in parallel with each other. 18th Fig. 13 is a view showing a semiconductor module parallel connection 5 according to the fifth embodiment. 19th Fig. 13 is a view showing a multilayer substrate 500 the parallel connection of the semiconductor modules 5 in the fifth embodiment.

20th Fig. 13 is a schematic view of a cross section of the multilayer substrate 500 in 19th along a line D-D '. A basic configuration and each wire connection are similar to those in the third embodiment. The fifth embodiment differs from the third embodiment in points that will be described. For convenience of description, a position of a gate return line in the X direction corresponding to a position of the first signal terminal connection pattern will be described 111-1 in the X direction is referred to as a branch point Q3. A position of the output line in the X direction corresponding to a position of the second signal terminal connection pattern 113-3 in the X direction, is referred to as a connection point P3.

In the gate return that is in a first layer 501 of the multilayer substrate 500 According to the fifth embodiment, a wiring pattern from the junction point Q1 to the junction point Q2 is formed to have a width greater than a width of a wiring pattern from the junction point Q2 to the junction point Q3. In the output line, which is in a third layer 503 of the multilayer substrate 500 is formed to have a line pattern from the connection point P1 to the connection point P2 to have a width larger than a width of a line pattern from the connection point P3 to the connection point P1.

A gate drive current in the semiconductor module parallel circuit 5 is described. A power input from the external connection port 61 flows through a gate forward that is in a second layer 502 of the multilayer substrate 500 and then through the gate return line that is in the first layer 501 of the multilayer substrate 500 is trained. Next, the current in the gate return branches by current flows in the first signal terminal connection patterns 111-1 , 111-2 and 111-3 provide.

One of the branched gate drive currents flows to the first signal terminal of the semiconductor module 10-1 via the first signal terminal connection pattern 111-1 . In a similar manner, another one of the branched gate drive currents to the first signal connection of the semiconductor module 10-2 via the first signal terminal connection pattern 111-2 and the other of the branched gate drive currents flows to the first signal terminal of the semiconductor module 10-3 via the first signal terminal connection pattern 111-3 . The gate drive current branched at the gate return branch point Q1 flows to the first signal terminal connection pattern 111-3 . The gate drive current branched at the gate return branch point Q2 flows to the first signal terminal connection pattern 111-2 .

Next, a current output flows from the second signal terminal of the semiconductor module 10-1 into the output line of the multilayer substrate 500 via the second signal terminal connection pattern 113-1 . In a similar way, a current output flows from the second signal terminal of the semiconductor module 10-2 into the output line of the multilayer substrate 500 via the second signal terminal connection pattern 113-2 . A current output from the second signal connection of the semiconductor module 10-3 flows into the output line of the multilayer substrate 500 via the second signal terminal connection pattern 113-3 . The current output from the second signal port connection pattern 113-3 merges with the power output from the second signal terminal connection pattern 113-2 at the connection point P1 of the output line or converges with this. The power outputs from the second signal port connection pattern 113-2 and the second signal terminal connection pattern 113-3 run on the power output from the second signal terminal connection pattern 113-1 at the connection point P2 of the output line. The merged streams at the connection point P2 are from the external connection port 61 issued.

Stromeingänge bzw. Stromeingaben zu den ersten Signalanschlüssen der Halbleitermodule 10-1, 10-2 und 10-3 können wie nachsehend in der Formel (15) genähert werden. $$\text{I1g}=\text{I2g}=\text{I3g}=\text{Ig}$$

Formel (16) wie nachstehend, ist von den Formeln (14) und (15) abgeleitet. $${\text{Ig}}_{123}=3\text{Ig}$$

Aus den voranstehenden Formeln (15) und (16) ist der in der Gate-Rückleitung von dem Abzweigungspunkt Q2 zu dem ersten Signalanschlussverbindungsmuster 111-1 fließende Strom Ig. Ein von dem Abzweigungspunkt Q1 zu dem Abzweigungspunkt Q2 fließender Strom ist 2Ig. 21 Fig. 13 is a view showing a gate drive current flowing through each layer of the multilayer substrate 500 flows. When a current flowing through the gate forward line is denoted by Ig ₁₂₃ , a current flowing from the branch point Q2 to the first signal terminal connection pattern 111-1 , denoted by I1g, flows a current flowing from the branch point Q2 to the first signal terminal connection pattern 111-2 is denoted by I2g, and a current flowing from the branch point Q2 to the first signal terminal connection pattern 111-3 is denoted by I3g, the following formula (14) is true. $${\text{Ig}}_{123}=\text{I1g}+\text{I2g}+\text{Ig3}$$

Current inputs or current inputs to the first signal connections of the semiconductor modules 10-1 , 10-2 and 10-3 can be approximated as shown in formula (15). $$\text{I1g}=\text{I2g}=\text{I3g}=\text{Ig}$$

Formula (16) as below is derived from formulas (14) and (15). $${\text{Ig}}_{123}=3\text{Ig}$$

From the above formulas (15) and (16), that is in the gate return line from the branch point Q2 to the first signal terminal connection pattern 111-1 flowing stream Ig. A current flowing from the branch point Q1 to the branch point Q2 is 2Ig.

Stromausgaben von den zweiten Signalanschlüssen der Halbleitermodule 10-1, 10-2 und 10-3 können wie nachsehend in der Formel (18) genähert werden. $$\text{I1s}=\text{I2s}=\text{I3s}=\text{Is}$$

Nachstehende Formel (19) ist von den Formeln (17) und (18) abgeleitet. $${\text{Is}}_{123}=3\text{Is}$$

Aus den Formeln (18) und (19) ist ein in der Ausgangsleitung von dem zweiten Signalanschlussverbindungsmuster 113-3 zu dem Verbindungspunkt P1 fließender Strom Is. Ein von dem Verbindungspunkt P1 zu dem Verbindungspunkt P2 fließender Strom 2Is.Next, when a current flowing through the output _{line is denoted by IS 123} , a current output flowing from the second signal terminal connection pattern 113-3 is output, denoted by I3s, a current flowing from the second signal terminal connection pattern 113-2 is output, denoted by I2s, and a current output or a current output from the second Signal port connection pattern 113-1 is denoted by I1s, the following formula (17) applies. $$\text{I1s}+\text{I2s}+\text{I3s}={\text{Is}}_{123}$$

Current outputs from the second signal connections of the semiconductor modules 10-1 , 10-2 and 10-3 can be approximated as below in formula (18). $$\text{I1s}=\text{I2s}=\text{I3s}=\text{Is}$$

The following formula (19) is derived from formulas (17) and (18). $${\text{Is}}_{123}=3\text{Is}$$

Of the formulas (18) and (19), one is in the output line from the second signal terminal connection pattern 113-3 Current Is flowing to the connection point P1. A current 2Is flowing from the connection point P1 to the connection point P2.

From the above description, a current in the gate return line is current Ig flowing from the branch point Q2 to the branch point Q3. The current flowing from the branch point Q1 to the branch point Q2 is 2Ig. The current flowing from the branch point Q1 to the branch point Q2 is approximately twice the current flowing from the branch point Q2 to the branch point Q3. In the gate return, there occurs a difference in the time-differentiated amount of the current in the line from the junction point Q1 to the junction point Q2 and the line from the junction point Q2 to the junction point Q3. Similarly, in the output line, the current flowing from the connection point P1 to the connection point P2 is Is. A current flowing from the connection point P3 to the connection point P1 is 2Is. The current flowing from the connection point P1 to the connection point P2 is approximately twice the current flowing from the connection point P3 to the connection point P1. In the output line, there occurs a difference in the time-differentiated amount of current between the line from the connection point P1 to the connection point P2 and the line from the connection point P3 to the connection point P1. There is a difference in the time-differentiated amount of current in the line.

L repräsentiert eine Selbstinduktivität einer Leitung und di/dt repräsentiert eine zeitdifferenzierte Menge des Stroms. Wie aus Formel (20) erkannt werden kann, resultiert eine unterschiedliche zeitdifferenzierte Menge von Strom in einer unterschiedlichen Spannungsabfallmenge.In the fourth embodiment described, a voltage drop amount of the line is expressed by the product of a self-inductance of the line and a time-differentiated amount of the current, as shown in Formula (20) below. To simplify the description, the influence of the mutual inductances is not taken into account here. $$\Delta \text{V}=\text{L.}\times \left(\text{di}/\text{German}\right)$$

L represents a self-inductance of a line and di / dt represents a time-differentiated amount of the current. As can be seen from formula (20), a different time-differentiated amount of current results in a different amount of voltage drop.

In the gate return of the multilayer substrate 500 According to the fifth embodiment, the wiring pattern from the junction point Q1 to the junction point Q2 is formed to have a width greater than a width of the wiring pattern from the junction point Q2 to the junction point Q3. Increasing the line pattern width can reduce the line's self-inductance. This means that the line from the junction point Q1 to the junction point Q2 has a lower self-inductance than the line from the junction point Q2 to the junction point Q3.

As can be seen from the formula (20), the self-inductance of the line is given by a first term on the right side of the formula (20) and the time-differentiated amount of current is given by a second term on the right side of the formula (20) specified. The line from the junction point Q1 to the junction point Q2 provides a larger second term on the right-hand side of the formula (20) than the line from the junction point Q2 to the junction point Q3. However, since the width of the wiring pattern from the junction point Q1 to the junction point Q2 is larger than the width of the wiring pattern from the junction point Q2 to the junction point Q3, the first term on the right side of the formula (20) can be reduced.

The foregoing applies to the output line in a similar manner. The line from the connection point P1 to the connection point Q2 represents a larger second term on the right side of the formula (20) than the line from the connection point P3Q2 to the connection point P1. However, because the width of the line pattern from the connection point P1 to the Connection point P2 is larger than the width of the wiring pattern from the connection point P3 to the connection point P1, the first term on the right side of the formula (20) can be reduced.

In the fifth embodiment, the self-inductance of the line and the time-differentiated amount of current are taken into account, thereby making it possible to reduce the difference in the amount of voltage drop due to the inductance of the line.

In the fifth embodiment, because the voltage drop amounts of the gate line in the semiconductor module 10-1 and the gate line of the semiconductor module 10-2 can be equal to each other, it is possible to reduce an imbalance in current generated between the semiconductor modules when the semiconductor modules are driven in parallel.

In the fifth embodiment, if there is an imbalance in current between the semiconductor modules to such an extent that it has substantially no influence, the line inductances are regarded as equal to each other.

Note that in the present invention, the respective embodiments can be freely combined, or the embodiments can be appropriately modified or omitted within the scope of the invention.

List of reference symbols

1, 2, 3, 4, 5

Semiconductor module parallel connection;

10-1

Semiconductor module;

10-2

Semiconductor module;

10-3

Semiconductor module;

10P

first main connection;

10N

second main connection;

10AC

third main connection;

11, 11-1, 11-2, 12, 12-1, 12-2

first signal connection;

13, 13-1, 13-2, 14, 14-1, 14-2

second signal connection;

20th

Module;

30, 30-1, 30-2

first semiconductor element;

40, 40-1, 40-2

second semiconductor element;

50

Fastener;

61, 62

External connection port;

71-1, 71-2

first connection terminal;

72-1, 72-2

second connection terminal;

100, 200, 300, 400, 500

Multilayer substrate;

111-1, 111-2, 111-3, 112-1, 112-2, 112-3

first signal terminal connection pattern;

113-1, 113-2, 113-3, 114-1, 114-2, 114-3

second signal terminal connection pattern;

201, 301, 401, 501

first layer;

202, 302, 402, 502

second layer;

203, 303, 403, 503

third layer;

D1, D2

Drain connector;

S1, S2

Source connector.

Claims (8)

Semiconductor module parallel connection, comprising: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of the gate line for the second power semiconductor module from the external connection terminal to the The first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are identical to one another. Semiconductor module parallel connection, with: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, wherein each of the power semiconductor modules has: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal connection which is connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and a length of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and a length of the gate line for the second power semiconductor module from the external connection terminal to the The first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are identical to one another. Semiconductor module parallel connection according to Claim 1 or 2 , wherein a line from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and a line from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module are formed in a first layer of the multilayer substrate, and a line from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal and a line from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are formed in a second layer of the multilayer substrate. Semiconductor module parallel connection according to Claim 3 wherein the line from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and the line from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module are formed in a third layer of the multilayer substrate. Semiconductor module parallel connection, comprising: a first power semiconductor module; a second power semiconductor module; a third power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal which is connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module; a first Signal terminal connection pattern for the third power semiconductor module, wherein the first signal terminal connection pattern for the third power semiconductor module is connected to the first signal terminal of the third power semiconductor module; and a second signal terminal connection pattern for the third power semiconductor module, wherein the second signal terminal connection pattern for the third power semiconductor module is connected to the second signal terminal of the third power semiconductor module, and an inductance of the gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal connection connection pattern for the first power semiconductor module to the external connection connection, an inductance of the gate line for the second power semiconductor module from the external connection connection to the first signal connection connection pattern for the second power semiconductor module and from the second signal connection connection pattern for the second power semiconductor module to the external connection connection, and an inductance of the Gate line for the third power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the third power semiconductor module and from the second signal terminal connection pattern for the third power semiconductor module to the external connection terminal are equal to each other. Semiconductor module parallel connection, with: a first power semiconductor module; a second power semiconductor module; a third power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, wherein each of the power semiconductor modules has: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal connection which is connected to a source potential of the power semiconductor switching element, wherein the multilayer substrate comprises: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for the second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module; a first signal terminal connection pattern for the third power semiconductor module, wherein the first signal terminal connection pattern for the third power semiconductor module is connected to the first signal terminal of the third power semiconductor module; and a second signal terminal connection pattern for the third power semiconductor module, wherein the second signal terminal connection pattern for the third power semiconductor module is connected to the second signal terminal of the third power semiconductor module, and a length of the gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, a length of a gate line for the second power semiconductor module from the external connection terminal to the first Signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal and a length of a gate line for the third power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the third power semiconductor module and from the second signal terminal connection pattern for the third power semiconductor module to the External connection ports are equal to each other. Semiconductor module interconnection substrate, comprising: an external connection terminal; a first signal terminal connection pattern for a first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is provided for connection to a first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is provided for connection to a second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for a second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern is provided for the second power semiconductor module for connection to a second signal terminal of the second power semiconductor module, wherein an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the The first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are identical to one another. Semiconductor module interconnection substrate, comprising: an external connection terminal; a first signal terminal connection pattern for a first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is provided for connection to a first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module, wherein the second signal terminal connection pattern for the first power semiconductor module is provided for connection to a second signal terminal of the first power semiconductor module; a first signal terminal connection pattern for a second power semiconductor module, wherein the first signal terminal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal terminal connection pattern for the second power semiconductor module, wherein the second signal terminal connection pattern for the second power semiconductor module is provided for connection to a second signal terminal of the second power semiconductor module, wherein a length of a gate line for the first power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the first power semiconductor module and from the second signal terminal connection pattern for the first power semiconductor module to the external connection terminal, and a length of a gate line for the second power semiconductor module from the external connection terminal to the first signal terminal connection pattern for the second power semiconductor module and from the second signal terminal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other.

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