DE112019004935T5 - CYCLE RECOVERY DEVICE AND METHOD FOR EQUALIZED SYSTEMS - Google Patents

Abstract

The present invention relates to clock extraction in systems subject to severe intersymbol interference. In particular, the invention presents an apparatus and a method for clock recovery for a receiver. The timing recovery apparatus includes an adaptive equalizer configured to equalize a digital received signal and a timing recovery circuit configured to recover timing information from the equalized digital received signal. The apparatus further comprises a calculation circuit configured to: calculate a first phase characteristic of a first set of equalizer coefficients, calculate an initial phase characteristic of an initial set of equalizer coefficients, calculate a first phase shift parameter which is a phase shift between the first and the initial Phase characteristic, calculate a first set of corrected equalizer coefficients based on the first set of equalizer coefficients and the first phase shift parameter, and update the first set of equalizer coefficients.

Description

TECHNICAL AREA

The present invention relates to clock extraction in systems affected by severe intersymbol interference. In particular, the invention presents an apparatus and a method for clock recovery for a receiver. The timing recovery apparatus and method can be used for an equalized system, for example a receiver with an adaptive equalizer. The clock recovery device and the method are able to perform a clock recovery (TR) after the adaptive equalizer.

BACKGROUND

The next generation of ultra-high-speed, short-range fiber links will use small, cheap, and low-power transceivers. All of these requirements are mainly due to the limited space in data centers. The transceivers should support intra and inter data center connections from a few hundred meters to several tens of kilometers.

The preferred solution is to transmit 100+ Gbit / s per wavelength, which is a major challenge when a very inexpensive solution is required. The coherent approach is ruled out because it requires high performance and expensive equipment. Therefore, intensity modulation (IM) and direct detection methods (DD) are preferred. The sophisticated on-off keying modulation format, which is widely used in non-coherent systems, has also been explored for applications with speeds of 100+ Gbit / s per wavelength. However, such a solution would require expensive, high bandwidth optics and electronics. To overcome this disadvantage, advanced modulation formats supported by digital signal processing (DSP) have been investigated as an alternative technology to support 100-G. The most promising candidates are duobinary pulse amplitude modulation (DB-PAM-n), discrete multi-tone modulation (DMT), and carrierless amplitude and phase modulation (CAP). All of the above methods provide similar performance in IM-DD systems. However, the DB-PAM formats are more attractive because they require a simple DSP.

Optical transceivers used in data centers use very cheap components such as direct modulated lasers (DML) and electro-absorption modulators (EML). DSP consumption and latency are very critical and only basic DSP functions are implemented in real products. The power of the optical signal is nearly proportional to the electrical signal that modulates the laser.

10 shows a conventional IM-DD-PAM transmission system in this regard. Forward error correction (FEC) is required at higher data rates. These codes are often standardized, but they can also be proprietary. After the bits output by the FEC have been mapped into a PAM signal, the PAM signal can be pre-equalized to improve performance. A digital-to-analog converter (DAC) outputs an analog electrical signal that is often amplified by a modulator driver (MD). The EML / DML optical output signal can suffer from Chromatic Dispersion (CD) over longer connections. Therefore, dispersion compensation fibers (DCF) or dispersion compensation modules (DCM) are used in some systems to compensate for the CD. A photodetector / diode (PDet) detects the optical signal on the receiver side. The PDet output is proportional to the power of the optical signal. The PDet output is amplified using a transimpedance amplifier (TIA). PDet and TIA can be integrated into optical receiver assemblies (ROSA), which can contain an automatic gain control circuit (AGC) to adapt the electrical signal to an analog-digital input (ADC) if electronic equalization is used. The receiver can use a feed-forward equalizer (FFE), a decision-feed-back equalizer (DFE), a maximum likelihood sequence estimator (MLSE), or combine some of them in the receiver. FFE suffers from noise amplification, DFE from error multiplication, while MLSE is the best and most complex solution. In the end, hard FECs are usually used after the PAM demapper.

11 Figure 3 shows a simplified Rx block diagram with TR blocks. The AGC block monitors signal power fluctuations and generates an almost constant signal swing that fits into the ADC input range. In this way, the ADC is used effectively. The equalizer recovers signals that suffer from noise and intersymbol interference (ISI). Before the equalizer is activated, however, the local oscillator must be synchronized to the input signal, ie to the transmit oscillator responsible for the data clock. These two oscillators need to be synchronized. Small phase deviations are allowed, as it is impossible to follow the transmitter clock source perfectly. The clock extraction is made possible by a phase detector (PD), which outputs the information whether the sampling clock is faster or slower. Since this information is noisy and suffers from pattern-dependent noise, noise from amplifiers, component imperfections, etc., the clock information must be filtered before it reaches the receiver oscillator, which is often implemented as a voltage controlled oscillator (VCO).

$$z\left(k\right)=y\left(k\right)+n\left(k\right)={\displaystyle \sum _{j=-n}^{n}x\left(k-j\right)h\left(j\right)+n\left(k\right)}$$

Clock information can be derived from the ADC output signal. The TR block includes PD, low pass filter and VCO. The VCO clock phase can be adjusted with a circuit for sampling phase adjustment (SPA). The sampling phase optimization can also be supported by the FEC decoder, which provides a number of FEC input errors (number of corrected errors). The best sampling phase should minimize this number. IM-DD transmission systems can, as in 12th can be modeled. The transmitted signal x is modified by the system transfer function H, which can be approximated by a linear system. In general the system is non-linear. The output signal is a convolution of the signal x and the system impulse response h: $$y\left(k\right)={\displaystyle \sum _{j=-n}^{n}x\left(k-j\right)H\left(j\right)}$$

$$z\left(k\right)=y\left(k\right)+n\left(k\right)={\displaystyle \sum _{j=-n}^{n}x\left(k-j\right)H\left(j\right)+n\left(k\right)}$$

The ISI spreads the input signal over 2n + 1 symbol intervals. As a rule, the transfer function behaves like a low-pass filter, whereby high-frequency components can be strongly attenuated. An additive noise n also interferes with the signal x. The TR block receives a signal that suffers from ISI and noise. TR designers expect noise, and practical TR solutions are less sensitive to noise under the given working conditions. For example, a pre-FEC BER is directly related to the amount of noise the system can tolerate. However, in systems that use advanced equalization techniques to cope with ISI caused by severe bandwidth limitations of the optical and electrical components, the received signal contains insufficient timing information. In such systems all known practical TR schemes fail because the frequency content around the Nyquist frequency is very pure.

In digital communication systems, the heart of every receiver is a clock recovery circuit that extracts frequency and phase from the incoming data and forces a local clock source to control the sampling rate and phase of the ADC. Several phase detectors (PD) have been proposed for digital systems.

All PDs have in common that the characteristics of a clock error detector (PD output over symbol interval) are very similar to the sine function. An exception is a so-called “bang-bang” PD, which has a timing error detector characteristic (TEDC) that is sinusoidal in the presence of noise.

wobei T das Symbolintervall, x das Eingangssignal, τ der Abtastzeitpunkt (zwischen o und T), E der Erwartungswert und * die konjugiert komplexe Operation ist. Die quadrierte Gardner-PD (SGPD) erbringt gute Leistungen in FTN-Systemen und kann beschrieben werden durch: $$\begin{array}{l}TEDC\left(\tau \right)=E\left[y\left(kT-\frac{T}{2}+\tau \right)\left(y\left(kT+\tau \right)-y\left(kT-T+\tau \right)\right)\right],\\ y=xx*\end{array}$$

Another conventional PD works with one sample per symbol. Other PDs are used with double oversampling. A conventional, so-called Gardner-PD TEDC can e.g. B. for complex signals can be described as: $$T\mathrm{E.}\mathrm{D.}\mathrm{C.}\left(\tau \right)=\mathrm{E.}\left[real\left(x\left(kT-\frac{\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="DE112019004935T5\_0013.png,DE112019004935T5\_0014.png"\; state="\{\{state\}\}">T</figure-callout>}}{2}+\tau \right)\right)\left(x*\left(kT+\tau \right)-x*\left(kT-T+\tau \right)\right)\right]$$

where T is the symbol interval, x is the input signal, τ is the sampling time (between o and T), E is the expected value and * is the complex conjugate operation. Gardner Squared PD (SGPD) performs well in FTN systems and can be described by: $$\begin{array}{l}T\mathrm{E.}\mathrm{D.}\mathrm{C.}\left(\tau \right)=\mathrm{E.}\left[y\left(kT-\frac{\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="DE112019004935T5\_0013.png,DE112019004935T5\_0014.png"\; state="\{\{state\}\}">T</figure-callout>}}{2}+\tau \right)\left(y\left(kT+\tau \right)-y\left(kT-T+\tau \right)\right)\right],\\ y=xx*\end{array}$$

1. 1. Der Taktton ist sehr schwach und der TR arbeitet mit einer hohen Wahrscheinlichkeit von Taktverschiebungen.
2. 2. Der Taktton verschwindet und die Taktextraktion ist unmöglich.
3. 3. Der TEDC hat keine Nulldurchgänge. Die Taktextraktion ist unmöglich, weil es keinen Gleichgewichtspunkt gibt.
4. 4. Der TEDC hat mehrere Gleichgewichtspunkte und Aufhängungsbereiche. Dies führt zu Zyklusverschiebungen und langer Erfassung.
5. 5. Der TEDC hat einen Gleichstromanteil (asymmetrischer TEDC). Dies erhöht die Wahrscheinlichkeit von Zyklusverschiebungen und macht den TR instabil.

In many implementations, clock extraction is done before the equalizer (see 13th ). This works when the ISI isn't that serious. In any case, the TR jitter is smaller if ISI is not taken into account (only noise is taken into account). So it is always better to have the signal only with noise. The mean ISI corrupts the time information and can be tolerated in some systems. However, this approach cannot work in systems with strong ISI because the ISI clock degradation is too high, so that:

1. 1. The clock tone is very weak and the TR operates with a high probability of clock shifts.
2. 2. The beat disappears and beat extraction is impossible.
3. 3. The TEDC has no zero crossings. The clock extraction is impossible because there is no point of equilibrium.
4. 4. The TEDC has several points of equilibrium and suspension areas. This leads to cycle shifts and long acquisition.
5. 5. The TEDC has a direct current component (asymmetrical TEDC). This increases the likelihood of cycle shifts and makes the TR unstable.

The main conclusion, therefore, is that in severe ISI scenarios, the TR should be performed after the equalizer. This can be relaxed by using the TR equalizer which is much simpler than the main equalizer.

In other words: To improve the clock performance, the signal should be equalized before the TR. If a static equalizer were implemented before the TR block - as in 14 (a) shown - the TR would work best on static channels. However, the channel changes its properties over time and the equalizer must follow the channel changes. Therefore, an adaptive equalizer would be desirable - as in 14 (b) shown. The adaptive equalizer can be a non-linear feed-forward equalizer, such as e.g. B. a Volterra filter. The adaptive equalizer varies the taps to keep track of channel changes. This also changes the sampling phase of the TR.

But the in 14 (a) and (b) approaches shown - ie the simple provision of TR after the equalizer - not because the equalizer and TR try to compensate for the phase shifts caused by both blocks. The sampling phase varies as in 14 (c) shown. This leads to the equalizer taps migrating in one direction. After a while, the central tap is no longer in the middle of the impulse response. This leads to a poorer performance of the equalizer. It also leads to TR instability. The worst scenario occurs when the clock is practically lost and the sampling phase wanders freely over many unit intervals in a short period of time. In this case the equalizer still follows the sample phase fluctuations, but the equalizer taps are wrong and the eye diagram is skewed with a BER of almost 0.5.

Therefore, a simple implementation of TR after equalization is not possible.

SUMMARY

In view of the above problems and disadvantages, embodiments of the present invention aim to improve upon current implementations. One aim is to provide an apparatus and method that enable the implementation of TR after equalization. The performance of the device and the method should be high and the TR should be stable. The device and the method should be usable in scenarios with a high ISI.

1. 1. Der Takt wird nach der Entzerrung abgeleitet, d. h. nach einem adaptiven Entzerrer, der den durch ISI verursachten Jitter verringert.
2. 2. Die Taktschwankungen sind viel kleiner als die Schwankungen, die durch den vor dem Entzerrer abgeleiteten Takt verursacht werden.
3. 3. Ein Takt mit geringem Jitter verbessert die Leistung des Entzerrers, da der Entzerrer keine großen Abtastphasenschwankungen verfolgen muss, die durch Eigenjitter verursacht werden.
4. 4. Der Entzerrer kann Kanalvariationen, die durch Systeminstabilitäten und Kanalunvollkommenheiten verursacht werden, leichter nachführen.
5. 5. Der Entzerrer wird nicht durch schnellen deterministischen Jitter beeinträchtigt, der von der TR-Schleife verfolgt werden kann, die viel schneller ist als die Aktualisierungsgeschwindigkeit des Entzerrers.
6. 6. Die Ausführungsformen der Erfindung sind sowohl in nicht-kohärenten als auch in kohärenten Systemen, z. B. Empfängern, anwendbar.

The object is achieved by the embodiments of the invention as described in the attached independent claims. Advantageous embodiments of the present invention are further defined in the dependent claims. Embodiments of the invention are generally based on clock derivation after an adaptive equalizer in, for example, PAM-n transmission systems which are severely impaired by ISI caused by bandwidth limitations of the electrical and optical components of the system. The embodiments of the invention are also based on recalculating the taps to enable the TR after equalization, and thereby have the following advantages:

1. 1. The clock is derived after the equalization, ie after an adaptive equalizer that reduces the jitter caused by ISI.
2. 2. The clock fluctuations are much smaller than the fluctuations caused by the clock derived before the equalizer.
3. 3. A clock with low jitter improves the performance of the equalizer because the equalizer does not have to track large sample phase fluctuations caused by self-jitter.
4. 4. The equalizer can more easily track channel variations caused by system instabilities and channel imperfections.
5. 5. The equalizer is not affected by fast deterministic jitter that can be tracked by the TR loop, which is much faster than the equalizer's update rate.
6. 6. The embodiments of the invention are applicable in both non-coherent and coherent systems, e.g. B. Recipients, applicable.

A first aspect of the invention provides a timing recovery apparatus for a receiver, the apparatus comprising: an adaptive equalizer configured to equalize a digital received signal, a timing recovery circuit configured to extract timing information from the equalized digital received signal recovers, and a calculation circuit configured to calculate a first phase characteristic of a first set of equalizer coefficients currently set in the adaptive equalizer, an initial phase characteristic of an initial set of equalizer coefficients, calculated previously at initialization in the adaptive equalizer, calculated a first phase shift parameter indicative of a phase shift between the first and initial phase characteristics, a first set of corrected equalizer coefficients based on the er calculates the first set of equalizer coefficients and the first phase shift parameter, and updates the first set of equalizer coefficients with the first set of corrected equalizer coefficients in the adaptive equalizer.

Due to the calculation circuit of the timing recovery device of the first aspect and the particular calculation it performs, namely for updating the equalizer coefficients in the adaptive equalizer, a very stable TR after equalization is made possible. The timing recovery device is therefore suitable for use in systems with high ISI without affecting TR performance. Channel changes can be more easily tracked and the TR can be performed very quickly. The device can, for example, advantageously be used in a coherent receiver. In one form of implementation of the first aspect, the calculation circuit is further configured to: calculate a second set of equalizer coefficients from the first set of corrected equalizer coefficients based on channel changes tracked by the adaptive equalizer and an adaptive algorithm.

In one form of implementation of the first aspect, the adaptive algorithm is a mean square algorithm.

In one form of implementation of the first aspect, the calculation circuit is further configured to: calculate a second phase characteristic of the second set of equalizer coefficients, calculate a second phase shift parameter indicating a phase shift between the second phase characteristic and the first phase characteristic or the initial phase characteristic, a second Calculate set of corrected equalizer coefficients based on the second set of equalizer coefficients and the second phase shift parameter, and update the first set of corrected equalizer coefficients with the second set of corrected equalizer coefficients in the adaptive equalizer.

In one form of implementation of the first aspect, the equalizer coefficients are coefficients for taps of the adaptive equalizer, and a set of equalizer coefficients includes an equalizer coefficient for each tap of the adaptive equalizer.

In one embodiment of the first aspect, the calculation circuit is configured to: calculate a set of corrected equalization coefficients which is further based on a calibration parameter, in particular a time-varying calibration parameter. The calibration parameter improves the BER and the stability of the device.

In one form of implementation of the first aspect, the calculation circuit is configured to: calculate the calibration parameter based on the first phase shift parameter or the second phase shift parameter.

In one form of implementation of the first aspect, the calculation circuit is configured to: calculate a phase shift characteristic of a set of equalizer coefficients based on a Fast Fourier transform of the equalizer coefficients in the set of equalizer coefficients.

In an embodiment of the first aspect, the calculation circuit is further configured to: perform an inverse FFT on a set of corrected equalizer coefficients before updating the equalizer coefficients in the adaptive equalizer.

A second aspect of the invention provides a receiver, in particular a coherent receiver, with a clock recovery device according to the first aspect or one of its forms of implementation.

In an embodiment of the second aspect, the receiver further comprises: an analog-to-digital converter, ADC, configured to convert an analog received signal into the digital received signal, the clock recovery device configured to provide the recovered clock information to the ADC.

The receiver of the second aspect enjoys the advantages and effects provided by the timing recovery apparatus of the first aspect.

A third aspect of the invention provides a timing recovery method for a receiver, the method comprising: adaptive equalization of a digital received signal, recovery of timing information from the equalized digital received signal, calculation of a first phase characteristic curve of a first set of currently set equalization coefficients, calculation of an initial phase characteristic curve an initial set of equalizer coefficients previously set during the initialization, calculating a first phase shift parameter indicating a phase shift between the first and the initial phase characteristic, calculating a first set of corrected equalizer coefficients on the basis of the first set of equalizer coefficients and the first phase shift parameter, and updating the first set of equalizer coefficients with the first set of corrected equalizer coefficients.

In an embodiment of the third aspect, the method further comprises calculating a second set of equalizer coefficients from the first set of corrected equalizer coefficients based on tracked channel changes and an adaptive algorithm, calculating a second phase characteristic of the second set of equalizer coefficients, calculating a second phase shift parameter which is a phase shift between the second phase characteristic and the first phase characteristic or the initial phase characteristic, calculating a second set of corrected equalizer coefficients based on the second set of equalizer coefficients and the second phase shift parameter, and updating the first set of corrected equalizer coefficients with the second set of corrected equalizer coefficients.

In one form of implementation of the third aspect, the adaptive algorithm is a mean square algorithm.

In one form of implementation of the third aspect, the equalizer coefficients are coefficients for taps of an adaptive equalizer for adaptively equalizing the received digital signal, and a set of equalizer coefficients contains an equalizer coefficient for each tap of the adaptive equalizer.

In one embodiment of the third aspect, the method further comprises: calculating a set of corrected equalization coefficients on the basis of a calibration parameter, in particular a time-variable calibration parameter.

In one embodiment of the third aspect, the method further comprises: calculating the calibration parameter based on the first phase shift parameter or the second phase shift parameter.

In an embodiment of the third aspect, the method further comprises: calculating a phase shift characteristic of a set of equalizer coefficients based on a Fast Fourier transform of the equalizer coefficients in the set of equalizer coefficients.

In one embodiment of the third aspect, the method further comprises: performing an inverse FFT on a set of corrected equalizer coefficients before updating the equalizer coefficients.

The method of the third aspect and its forms of implementation achieve the same advantages and effects as described for the clock recovery device of the first aspect.

It should be noted that all devices, elements, units and means described in the present application can be implemented in software or hardware elements or any combination thereof. All steps carried out by the various units described in the present application, as well as the functionalities which are described in order to be carried out by the various units, are to be understood such that the respective unit is adapted or configured to the respective To carry out steps and functionalities. Even though the following description of certain embodiments does not reproduce a certain functionality or a certain step to be performed by external entities in the description of a certain detailed element of that entity that performs that particular step or functionality, it should it will be clear to a person skilled in the art that these methods and functionalities can be implemented in corresponding software or hardware elements or any combination thereof.

Figure list

• 1 zeigt eine Taktrückgewinnungsvorrichtung gemäß einer Ausführungsform der Erfindung.
• 2 zeigt einen Empfänger gemäß einer Ausführungsform der Erfindung.
• 3 zeigt Start-Entzerrer-Abgriffe.
• 4 zeigt Entzerrerabgriffe.
• 5 zeigt eine Entzerrer-Phasenkennlinie.
• 6 zeigt einen Phasenverschiebungsparameter ps im Symbolintervall T.
• 7 zeigt einen Entzerrer-Abgriffsverlauf.
• 8 zeigt in (a) einen Phasenverschiebungsparameter ps und eine TR-Phase einer herkömmlichen Taktrückgewinnungsvorrichtung und zeigt in (b) einen Phasenverschiebungsparameter ps und eine TR-Phase einer Taktrückgewinnungsvorrichtung gemäß einer Ausführungsform der Erfindung.
• 9 zeigt ein Verfahren gemäß einer Ausführungsform der Erfindung.
• 10 zeigt ein IM-DD-PAM-Übertragungssystem.
• 11 zeigt grundlegende Rx-Blöcke einschließlich TR-Blöcke.
• 12 zeigt TR in Systemen mit ISI und Rauschen.
• 13 zeigt TR vor einem Entzerrer.
• 14 zeigt in (a) TR nach einem statischen Entzerrer, zeigt in (b) TR nach einem adaptiven Entzerrer, und zeigt in (c) TR-Abtastphasenschwankungen nach einem adaptiven Entzerrer.

The above-described aspects and embodiments of the present invention are set forth in the following description of specific embodiments with reference to the accompanying drawings, in which:

• 1 shows a clock recovery device according to an embodiment of the invention.
• 2 Figure 3 shows a receiver according to an embodiment of the invention.
• 3 shows start equalizer taps.
• 4th shows equalizer taps.
• 5 shows an equalizer phase characteristic.
• 6th shows a phase shift parameter ps in the symbol interval T.
• 7th Figure 11 shows an equalizer tap history.
• 8th shows in (a) a phase shift parameter ps and a TR phase of a conventional clock recovery device and shows in (b) a phase shift parameter ps and a TR phase of a clock recovery device according to an embodiment of the invention.
• 9 shows a method according to an embodiment of the invention.
• 10 shows an IM-DD-PAM transmission system.
• 11 shows basic Rx blocks including TR blocks.
• 12th shows TR in systems with ISI and noise.
• 13th shows TR in front of an equalizer.
• 14th shows in (a) TR after a static equalizer, shows in (b) TR after an adaptive equalizer, and shows in (c) TR sample phase fluctuations after an adaptive equalizer.

DETAILED DESCRIPTION OF THE EMBODIMENTS

1 shows a timing recovery device 100 according to an embodiment of the invention which is suitable for a receiver, for example a coherent receiver. The clock recovery device 100 includes an adaptive equalizer 101 , which is designed to equalize a digital received signal x, comprises a timing recovery (TR) circuit 102, which is designed to recover clock information from the equalized digital received signal y, and comprises a calculation circuit 103 .

The calculation circuit 103 is configured in particular to have a first phase characteristic 105 - referred to as a (k) - to calculate a first set of equalizer coefficients w (k) 104 that are currently in the adaptive equalizer 101 are set. It is also configured to have an initial phase characteristic 107 - referred to as a (o) - to calculate an initial set of equalizer coefficients previously used during initialization in the adaptive equalizer 101 was discontinued. It is then configured to have a first phase shift parameter 106 - referred to as ps - which indicates a phase shift between the first and the initial phase characteristics a (o) and a (k), and a first set of corrected equalizer coefficients 1038 - denoted as w '(k) - based on the first set of equalizer coefficients w (k) and the first phase shift parameter ps. Then it is configured to match the first set of equalizer coefficients w (k) with the first set of corrected equalizer coefficients w '(k) in the adaptive equalizer 101 to update.

The equalizer coefficients are generally coefficients for taps of the adaptive equalizer 101 , and a set of equalizer coefficients comprises one equalizer coefficient per each tap of the adaptive equalizer 101 .

The adaptive equalizer 101 the device 100 of 1 can start with w (o) equalizer coefficients with the initial phase characteristic a (o). Then new equalizer coefficients w (k) can be derived for the equalizer taps, e.g. B. after several updates. The first phase characteristic a (k) of the new coefficients is obtained. The ps value is then calculated from a (o) and a (k). The ps value is used to calculate the corrected (ie re-centered) equalizer coefficients w '(k). The coefficients w '(k) then replace the old coefficients that were used in the adaptive equalizer 101 be used. This from the device 100 carried out procedure is z. B. in receivers 200 , especially in coherent receivers. In the latter case the signals x and y can be complex. The coefficients of the equalizer taps can be either real or complex.

2 shows schematically parts of a receiver 200 according to one embodiment of the invention, wherein the recipient 200 the clock recovery device 100 out 1 includes. Recipient 200 also includes an ADC 201 that is configured to convert an analog received signal into the digital received signal x (that into the clock recovery device 100 is fed), the clock recovery device 100 is further configured, the recovered clock information, ie the output of the TR circuit 102 , to the ADC 201 to deliver.

The following is done in the timing recovery device 100 or in the recipient 200 , especially in the arithmetic unit 103 , performed procedures explained in more detail. In the following only real signals are considered, but the same analyzes and procedures can easily be applied to complex signals.

The equalizer 101 uses a start channel model (see 3 ) and tracks channel changes. The taps - ie the equalizer coefficients of the taps - of the equalizer 101 can be updated with various adaptive algorithms. The following is a linear equalizer 101 with n taps, denoted by their coefficients w. The real signal x before the equalizer 101 is equalized and the equalizer output is defined by: $$y\left(k\right)={\displaystyle \sum _{j=0}^{n-1}x\left(k-j\right)w\left(j\right)}$$

für das reale Eingangssignal, wobei ein Vektor w die Entzerrerkoeffizienten für die Abgriffe darstellt, ein Vektor x das Signal vor dem Entzerrer enthält und e der Entzerrerfehler ist, der die Differenz zwischen dem Ausgangssignal und dem nächstliegenden Signalpegel ist. Der Parameter µ definiert eine Aktualisierungsgeschwindigkeit. Größere µ-Werte ermöglichen die Verfolgung schneller Kanaländerungen, während kleinere µ-Werte eine bessere Leistung bieten. Sehr große µ-Werte können zur Instabilität des Entzerrers führen. Große µ-Werte sind bei zeitvariablen Kanälen zu bevorzugen und können das in 1 oder 2 dargestellte System sehr schnell in den instabilen Bereich bringen.The equalizer taps 101 can be updated, e.g. B. by a decision-driven least mean square algorithm defined by $$w\left(k+1\right)=w\left(k\right)+\mu Xe$$

for the real input signal, where a vector w represents the equalizer coefficients for the taps, a vector x contains the signal before the equalizer and e is the equalizer error, which is the difference between the output signal and the closest signal level. The parameter µ defines an update speed. Larger µ values enable faster channel changes to be tracked, while smaller µ values provide better performance. Very large µ values can lead to instability of the equalizer. Large µ values are preferable for time-variable channels and can do this in 1 or 2 Bring the system shown into the unstable area very quickly.

The channel response, represented by the tap coefficients wi, i = o, 1, ..., n-1, provide information about the equalizer phase and amplitude in the frequency domain. The start channel model, ie the initial equalization coefficients, are denoted by w (o). The Fourier transform of the channel response represented by w (o) is W (o). That is, W (o) = fft (w (o)). The coefficients in the frequency domain are W (i), i = o, 1, ..., n-1. The coefficients can be represented by amplitude and phase (polar shape) so they can be written as W (i) = | W (j) | exp (yes (i)). For the in 4th A phase transfer function represented by a (o) can be calculated from the channel response (w (o)) shown. This is in 5 shown.

With a parallel implementation, several symbols can be processed at the same time. For example, a CMOS clock can cover M = 64 symbols. This means that 64 equalizers can work in parallel. The equalizer taps are recalculated 64 times, but can only be used in the equalizer after they have been calculated. When new taps are available, they can be used in the equalizer 101 be used. The coefficients of the new equalizer taps are denoted by W (k). Now there is a new phase characteristic a (k) and the old, original a (o). Each of them has n values. If n is even, then a (j) = - a (n-j + 1). The coefficients can be written as a (o, j). The phase shift due to new coefficients can be calculated using the phase shift parameter: $$ps\left(k\right)=1/\left(k2-\mathrm{<figure-callout\; id="1"\; label="k"\; filenames="DE112019004935T5\_0013.png,DE112019004935T5\_0014.png"\; state="\{\{state\}\}">k</figure-callout>}1+1\right){\displaystyle \sum _{j=k1}^{k2}\left(a\left(\mathrm{0,}j\right)-a\left(k,j\right)\right)}$$

The phase shift is in 6th shown. It changes over time and the center taps move to the right. As they approach the limits of the equalizer, the central taps are at the end of the filter. This case is in 7th shown. In this situation, the equalizer produces a lot of errors and becomes unstable. The phase shift parameter ps can be calculated using the filter taps in the time domain (wi, i = o, 1, ..., n-1): $$ps={\displaystyle \sum _{j=k1}^{k2}\left(f\left(\mathrm{0,}j\right)w2\left(\mathrm{0,}j\right)-f\left(k,j\right)w2\left(k,j\right)\right)}$$

The simplest implementation uses f (o, j) = f (k, j) = j. However, these coefficients can be optimized for best performance. The optimization can only take place around the central tap. So z. B. only f of the five most important taps can be optimized. The optimal value provides the smallest sampling phase fluctuations.

$$f=\mathrm{0,1,}\dots ,\frac{n}{2},-\frac{n}{2}+\mathrm{1,}-\frac{n}{2}+\mathrm{2,}\dots ,-\mathrm{2,}-1.$$

The TR phase would conventionally try to follow the sample phase changes caused by the equalizer. This is in 8 (a) shown. However, this ends as mentioned earlier. In order to prevent the sampling phase drift, the arithmetic circuit calculates 103 the equalizer tap coefficients new, e.g. B. by: $$\mathrm{W.}\text{'}\left(j\right)=\mathrm{W.}\left(j\right)\text{exp}\left(-j\mathrm{4th}\pi f\left(j\right)\left(ps-\delta \right)/n\right)$$

$$f=\mathrm{0.1,}...,\frac{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE112019004935T5\_0013.png,DE112019004935T5\_0014.png"\; state="\{\{state\}\}">n</figure-callout>}}{2},-\frac{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE112019004935T5\_0013.png,DE112019004935T5\_0014.png"\; state="\{\{state\}\}">n</figure-callout>}}{2}+\mathrm{1,}-\frac{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="DE112019004935T5\_0013.png,DE112019004935T5\_0014.png"\; state="\{\{state\}\}">n</figure-callout>}}{2}+\mathrm{2,}...,-\mathrm{2,}-1.$$

The optional parameter δ helps to improve BER and system stability. This parameter can be set during calibration and changed over time to improve device performance. In addition, after a while, a (o) can be replaced by the current FFE taps. The new tap coefficients W '(j) can be used directly in the frequency domain equalizer. They can be transferred to the time domain with w "= ifft (W ') and used in the time domain equalizer. The equalizer 101 and the TR circuit 102 are stable in this case, which is visualized in FIG. 8 (b). TR fluctuations are caused only by the intrinsic jitter, and the fluctuations of the equalizer are caused by noise and the update factor µ.

The TR update speed is much faster than the equalizer update 101 . In the case of fast, deterministic jitter, the TR circuit follows 101 the jitter fluctuations. The equalizer 101 is not influenced by jitter as the taps are always re-centered. That means the equalizer 101 cannot track phase changes.

1. 1. Setzen der Koeffizienten der Start-Entzerrerabgriffe (Startkanalmodell).
2. 2. Berechnen der Startkanalmodell-Phasenkennlinie 107.
3. 3. Erfassen eines Taktes. Der TR ist stabil, aber verrauscht.
4. 4. Berechnen des neue Kanalmodells (Entzerrer-Abgriffkoeffizienten 104).
5. 5. Berechnen der Phasenkennlinie 105 des neuen Kanalmodells.
6. 6. Berechnen eines Phasenverschiebungsparameter 106, der durch das neue Kanalmodell verursacht wird.
7. 7. Neuberechnen der neuen Entzerrerkoeffizienten 104, indem die neuen Abgriffe um die berechnete Phasenverschiebung verschieben werden, um die korrigierten Entzerrerkoeffizienten 1038 zu erhalten.
8. 8. Nach der Erfassung des Kanals periodisches Ersetzen des Startkanalmodells durch das aktuelle Kanalmodell. Optionales Ändern des Parameters δ um die durch diese Ersetzung eingeführte Verschiebung.

One from the device 100 or the recipient 200 The algorithm carried out can be summarized in the following steps:

1. 1. Set the coefficients of the start equalizer taps (start channel model).
2. 2. Calculate the starting channel model phase characteristic 107 .
3. 3. Acquisition of a cycle. The TR is stable but noisy.
4. 4. Compute the new channel model (equalizer tap coefficients 104 ).
5. 5. Calculate the phase characteristic 105 of the new channel model.
6. 6. Compute a phase shift parameter 106 caused by the new channel model.
7. 7. Recalculate the new equalizer coefficients 104 by shifting the new taps by the calculated phase shift by the corrected equalizer coefficients 1038 to obtain.
8. 8. After the channel has been recorded, the start channel model is periodically replaced by the current channel model. Optionally changing the parameter δ by the shift introduced by this replacement.

9 shows a procedure 900 according to one embodiment of the invention. The procedure 900 can from the device 100 of 1 or the recipient 200 of 2 be performed.

The procedure 900 includes one step 901 the adaptive equalization of a digital received signal. This can be done by the adaptive equalizer 101 be performed. The method further comprises a step 902 for the recovery of clock information from the equalized digital received signal. This can be done from the TR circuit 102 be performed. The method also includes further steps performed by the calculation circuit 103 can be performed, namely: one step 903 for calculating a first phase characteristic 105 a first set of equalizer coefficients 104 that are currently set (e.g. in the adaptive equalizer 101 ), one step 904 for calculating an initial phase characteristic 107 an initial set of equalizer coefficients that were previously set during initialization (e.g. in the adaptive equalizer 101 ), one step 905 for calculating a first phase shift parameter 106 , which is a phase shift between the first and the initial phase characteristic 105 and 107 indicating a step 9036 for computing a first set of corrected equalizer coefficients 1038 based on the first set of equalizer coefficients 104 and the first phase shift parameter 1036 and one step 907 for updating the first set of equalizer coefficients 104 with the first set of corrected equalizer coefficients 108 .

The present invention has been described in connection with various embodiments as examples and implementations. However, other embodiments may be understood and carried out by those skilled in the art having the claimed invention based on the drawings, this disclosure, and the independent claims. In both the claims and the description, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “to” does not exclude a plurality. A single element or another unit can fulfill the functions of several units or objects listed in the claims. The mere fact that certain measures are recited in the mutually different dependent claims does not mean that a combination of these measures cannot be used in an advantageous embodiment.

Claims (13)

A clock recovery device (100) for a receiver, the device (100) comprising: an adaptive equalizer (101) configured to equalize a digital received signal, a clock recovery circuit (102) configured to equalize clock information from the recovers digital received signal, and a calculation circuit (103) configured to: Calculating a first phase characteristic (105) of a first set of equalizer coefficients (104) currently set in the adaptive equalizer (101), calculating an initial phase characteristic (107) of an initial set of equalizer coefficients previously used in the initialization in the adaptive equalizer (101), calculating a first phase shift parameter (106) which indicates a phase shift between the first and the initial phase characteristic (105, 107), calculating a first set of corrected equalizer coefficients (108) on the basis of the first set of equalizer coefficients ( 104) and the first phase shift parameter (106), and updating the first set of equalizer coefficients (104) with the first set of corrected equalizer coefficients (108) in the adaptive equalizer (101). Device (100) according to Claim 1 wherein the calculation circuit (103) is further configured to: calculate a second set of equalizer coefficients from the first set of corrected equalizer coefficients (108) based on channel changes tracked by the adaptive equalizer (101) and an adaptive algorithm. Device (100) according to Claim 2 , where: the adaptive algorithm is a mean square algorithm. Device (100) according to Claim 2 or 3 wherein the calculation circuit (103) is further configured to: calculate a second phase characteristic of the second set of equalizer coefficients, calculate a second phase shift parameter that indicates a phase shift between the second phase characteristic and the first phase characteristic (105) or the initial phase characteristic (107) second set of corrected equalizer coefficients based on the second set of equalizer coefficients and the second phase shift parameter, and updating the first set of corrected equalizer coefficients (108) with the second set of corrected equalizer coefficients in the adaptive equalizer (101). Device (100) according to one of the Claims 1 to 4th wherein: equalizer coefficients are coefficients for taps of the adaptive equalizer (101), and a set of equalizer coefficients includes an equalizer coefficient for each tap of the adaptive equalizer (101). Device (100) according to one of the Claims 1 to 5 wherein the calculation circuit (103) is configured to: calculate a set of corrected equalizer coefficients further on the basis of a calibration parameter, in particular a time-varying calibration parameter. Device (100) according to Claim 6 wherein the calculation circuit (103) is configured to: calculate the calibration parameter based on the first phase shift parameter (106) or the second phase shift parameter. Device (100) according to one of the Claims 1 to 7th wherein the calculation circuit (103) is configured to: calculate a phase shift characteristic of a set of equalizer coefficients based on a Fast Fourier transform of the equalizer coefficients in the set of equalizer coefficients. Device (100) according to one of the Claims 1 to 8th wherein the calculation circuit (103) is further configured to: perform an inverse FFT on a set of corrected equalizer coefficients prior to updating the equalizer coefficients in the adaptive equalizer (101). Receiver (200), in particular a coherent receiver, which has a clock recovery device (100) according to one of the Claims 1 to 9 includes. Receiver (200) after Claim 10 , further comprising: an analog-to-digital converter, ADC, (201) configured to convert an analog received signal into the digital received signal, wherein the clock recovery device (100) is configured to provide the recovered clock information to the ADC (201). A clock recovery method (900) for a receiver, the method (900) comprising: adaptive equalization (901) of a digital received signal, Recovery (902) of clock information from the equalized digital received signal, Calculating (903) a first phase characteristic (105) of a first set of currently set equalizer coefficients (104), Calculating (904) an initial phase characteristic (107) of an initial set of equalizer coefficients which were previously set during initialization, Calculating (905) a first phase shift parameter (106) which indicates a phase shift between the first and the initial phase characteristic curve (105, 107), Calculating (906) a first set of corrected equalizer coefficients (108) based on the first set of equalizer coefficients (104) and the first phase shift parameter (106), and Updating the first set of equalizer coefficients (104) with the first set of corrected equalizer coefficients (108). Method (900) according to Claim 12 , further comprising: calculating a second set of equalizer coefficients from the first set of corrected equalizer coefficients (108) based on tracked channel changes and an adaptive algorithm calculating a second phase characteristic of the second set of equalizer coefficients, calculating a second phase shift parameter indicating a phase shift between the second phase characteristic and the first phase characteristic (105) or the initial phase characteristic (107), calculating a second set of corrected equalizer coefficients based on the second set of equalizer coefficients and the second phase shift parameter, and updating the first set of corrected equalizer coefficients (108) with the second set of corrected equalizer coefficients.

Images