DE112018007923T5 - Doherty amplifier - Google Patents

Abstract

A housing (1) contains a first and a second input port (2, 3) which are adjacent to one another, and a first and a second output port (4, 5) which are adjacent to one another. Within the housing (1) between the first input connection (2) and the first output connection (4) are a first input matching circuit (6), a first delay circuit (7), a second input matching circuit (8), a first amplifier (9) and a first output matching circuit (10) sequentially connected. Within the housing (1) between the second input connection (3) and the second output connection (5) are a third input matching circuit (11), a second amplifier (12), a second output matching circuit (13), a second delay circuit (14) and a third output matching circuit (15) sequentially connected. Outside the housing (1), first to fourth matching circuits (16-19) are connected to the first input connection (2), the second input connection (3), the first output connection (4) and the second output connection (5), respectively.

Description

area

The present disclosure relates to a Doherty amplifier having two amplifiers in one housing.

background

In mobile communications, a transmission power amplifier is typically required to have high efficiency and low distortion. Further, in recent years, in order to support high-speed, large-capacity communication, a modulation wave signal having a high PAPR (Peak Average Power Ratio) has been used. If a signal with a high PAPR is amplified with a power amplifier, in order to meet distortion standards, the power amplifier is allowed to operate at a low average output power obtained by providing a back-off to a saturated output power. Since a back-off amount is typically inversely related to an efficiency, a high efficiency cannot be expected in a case where a high PAPR is used. Amplifiers called Doherty amplifiers, which can solve this problem, are widely used mainly in communication base stations.

In the Doherty amplifier, a main amplifier biased to class AB or class B and a peak amplifier biased to class C are synthesized in parallel using a λ / 4 line. The λ / 4 line is positioned at an output of one of the amplifiers. The λ / 4 line is also positioned at an input of the other amplifier. Since the two amplifiers operate in a similar manner and are synthesized in phase when a large signal is input, characteristics similar to the characteristics of a 2-synthesized amplifier are exhibited, and a large saturation output can be realized become. When a small signal is fed in, however, since only the main amplifier works and the λ / 4 line connected to the output side of the main amplifier functions as an impedance inverter, a high degree of efficiency can be obtained through a high load impedance. Therefore, the Doherty amplifier can realize a high efficiency in a wide output power range.

Since the Doherty amplifier uses two amplifiers, it is desirable to put the two amplifiers in one case in order to reduce a size. If the entire Doherty amplifier is integrated, however, it is difficult to fine-tune characteristics. It is therefore desirable to accommodate the two amplifiers and only part of the matching circuits in one housing and to provide an adjustable part outside the housing. However, electromagnetic coupling between adjacent input ports or between adjacent output ports affects device characteristics. This is considered to be the case as compared with a case where the Doherty amplifier is constructed with two sets of semiconductor devices in which an amplifier is housed in a case and a distance between terminals is reduced Signal passing between adjacent terminals has a phase difference of 90 degrees. Although a method in which an electrical shield is provided inside a case is proposed to address this problem, a reduction in size due to a size of the electrical shield is limited. It is also proposed that all components with the exception of a dividing circuit and a synthesis circuit of the Doherty amplifier be accommodated in one housing (see, for example, PTL 1).

List of quotes

Patent literature

[PTL 1] JP 2005-303771 A

Summary

Technical problem

Although it is possible to suppress electromagnetic coupling by housing all components except a dividing circuit and a synthesis circuit in one case, there is a problem that it is difficult to fine-tune characteristics as described above.

The present invention has been made to solve the problem as described above, and an object of the present invention is to obtain a Doherty amplifier which enables fine adjustment of characteristics to be easily performed while suppressing electromagnetic coupling .

Solution to the problem

A Doherty amplifier according to the present disclosure includes: a housing having first and second input terminals that are adjacent to each other and first and second output terminals that are are adjacent to each other contains; a first input matching circuit, a first delay circuit, a second input matching circuit, a first amplifier, and a first output matching circuit sequentially connected between the first input terminal and the first output terminal within the housing; a third input matching circuit, a second amplifier, a second output matching circuit, a second delay circuit, and a third output matching circuit sequentially connected between the second input terminal and the second output terminal within the housing; first to fourth matching circuits connected to the first input terminal, the second input terminal, the first output terminal and the second output terminal, respectively, outside the housing; a dividing circuit which is provided outside the housing, divides an input signal equally into two signals and feeds the two signals to the first and second input terminals via the first and second matching circuits, respectively; and a synthesis circuit provided outside the case and synthesizes signals input from the first and second output terminals through the third and fourth matching circuits into a signal.

Advantageous Effects of the Invention

In the present disclosure, since the delay circuits are integrated into the housing, it is possible to establish phases between the input terminals and between output terminals to be the same. In this way, it is possible to suppress electromagnetic coupling occurring in a small case. Furthermore, it is possible to easily fine-tune characteristics of the Doherty amplifier on the matching circuits outside the housing.

Figure list

• 1 FIG. 13 is a view illustrating a Doherty amplifier according to Embodiment 1. FIG.
• 2 FIG. 13 is a plan view illustrating a package of a Doherty amplifier according to Embodiment 1. FIG.
• 3 FIG. 13 is a cross-sectional diagram illustrating the housing of the Doherty amplifier according to Embodiment 1. FIG.
• 4th FIG. 13 is a view illustrating impedance transformation of an output matching circuit of the second amplifier according to Embodiment 1. FIG.
• 5 Fig. 13 is a circuit diagram illustrating a Doherty amplifier according to the comparative example.
• 6th Fig. 13 is a view illustrating a calculation result of a drain efficiency of the Doherty amplifier according to the comparative example.
• 7th Fig. 13 is a view illustrating a calculation result of a gain of the Doherty amplifier according to the comparative example.
• 8th FIG. 12 is a view illustrating a calculation result of a drain efficiency of the Doherty amplifier according to Embodiment 1. FIG.
• 9 FIG. 12 is a view illustrating a calculation result of a gain of the Doherty amplifier according to Embodiment 1. FIG.
• 10 Fig. 13 is a view illustrating a result obtained by calculating an influence of the distance between terminals on the saturation output.
• 11 Fig. 13 is a view illustrating a result obtained by calculating a saturation output of the Doherty amplifier according to Embodiment 1 while changing the electrical length of the delay circuit.
• 12th FIG. 13 is an equivalent circuit diagram illustrating the inside of a case of a Doherty amplifier according to Embodiment 2. FIG.
• 13th FIG. 13 is a plan view illustrating a layout inside the case of the Doherty amplifier according to Embodiment 2. FIG.
• 14th FIG. 13 is a view illustrating impedance transformation of an output matching circuit of a second amplifier according to Embodiment 2. FIG.
• 15th FIG. 13 is a view illustrating a Doherty amplifier according to Embodiment 3. FIG.
• 16 FIG. 13 is an equivalent circuit diagram illustrating the inside of the case of the Doherty amplifier according to Embodiment 3. FIG.
• 17th FIG. 13 is a view illustrating impedance transformation of the output matching circuit of the first amplifier according to Embodiment 3. FIG.
• 18th FIG. 13 is a view illustrating impedance transformation of the output matching circuit of the second amplifier according to Embodiment 3. FIG.

Description of embodiments

A Doherty amplifier according to the embodiments of the present disclosure will be described with reference to the drawings. The same components are denoted by the same symbols, and their repeated description can be omitted.

Embodiment 1

1 FIG. 13 is a view illustrating a Doherty amplifier according to Embodiment 1. FIG. One housing 1 includes a first and a second input port 2 and 3 adjacent to each other and first and second output terminals 4th and 5 that are adjacent to each other.

Inside the case 1 are between the first input port 2 and the first output terminal 4th a first input matching circuit 6th , a first delay circuit 7th , a second input matching circuit 8th , a first amplifier 9 and a first output matching circuit 10 sequentially connected. Inside the case 1 are between the second input port 3 and the second output terminal 5 a third input matching circuit 11 , a second amplifier 12th , a second output matching circuit 13th , a second delay circuit 14th and a third output matching circuit 15th sequentially connected.

The first amplifier 9 and the second amplifier 12th are for example GaN-HEMTs. The first amplifier 9 is preloaded to class AB or class B. The second amplifier 12th is preloaded to class C. The second input matching circuit 8th or the like are connected to a gate of the first amplifier 9 connected, and the first output matching circuit 10 is to a drain of the first amplifier 9 connected. The third input matching circuit 11 is to a gate of the second amplifier 12th connected, and the second output matching circuit 13th or the like are connected to a drain of the second amplifier 12th connected.

Outside the case 1 are first to fourth matching circuits 16 to 19th with the first input port 2 , the second input port 3 , the first output port 4th or the second output connection 5 connected. The first and second matching circuits 16 and 17th may include gate bias circuits. The third and fourth matching circuits 18th and 19th may include drain bias circuits.

Outside the case 1 are also a dividing circuit 20th and a synthesis circuit 21st intended. The dividing circuit 20th divides an input signal equally into two signals in phase and feeds the respective signals via the first and the second matching circuit 16 and 17th into the first and second input ports 2 and 3 a. The dividing circuit 20th is a Wilkinson division circuit with microstrip lines 22 and 23, the characteristic impedance of which is 70.71 Ω and an electrical length of 1/4 of a wavelength λ of an input signal, and a resistance 24 of 100 Ω.

The synthesis circuit 21st synthesized from the first and second output terminals 4th and 5 via the third and fourth matching circuit 18th and 19th signals fed into a signal. The matching circuit 25 and a load 26 are connected to an output of the synthesis circuit 21st connected. A resistance value of the load 26 is typically 50 Ω. The matching circuit 25 is a microstrip line whose characteristic impedance is 35.36 Ω and which has an electrical length of 1/4 of a wavelength λ of an input signal.

Circuits within the housing 1 are constructed with, for example, a metal structure formed on a resin substrate whose relative permittivity is between 3 and 4 and whose thickness is between approximately 20 to 30 mils, and SMD (Surface Mount Device) components. Matching circuits within the housing 1 are constructed with an inductance of a bonding wire, an MIM (metal-insulator-metal) capacitor or a microstrip line, which is formed on a dielectric substrate whose relative permittivity is between 30 and 300. The first and second delay circuits 7th and 14th are microstrip lines formed on a dielectric substrate whose relative permittivity is between 30 and 300.

2 FIG. 13 is a plan view illustrating a package of a Doherty amplifier according to Embodiment 1. FIG. 3 FIG. 13 is a cross-sectional diagram illustrating the housing of the Doherty amplifier according to Embodiment 1. FIG. The first amplifier 9 , the second amplifier 12th or the like are mounted on a heat sink 27. The first and second input ports 2 and 3 , the first and the second output port 4th and 5 and the heat sink 27 are fixed with a molding material 28. Of the housing 1 however, it is not limited to a molded case and may be a ceramic case.

The first to third input matching circuits 6th , 8th and 11 and the first and the second Matching circuit 16 and 17th are designed so that signals in gates of the first amplifier 9 and the second amplifier 12th can be fed in without being reflected when a large signal is fed in. The first to third output matching circuits 10 , 13th and 15th and the third and fourth matching circuits 18th and 19th are designed so that an impedance of an output side, of drains of the first amplifier 9 and the second amplifier 12th seen from an optimal load impedance becomes Zopt. Zopt is typically determined by a load-pull calculation or load-pull evaluation of a transistor and becomes a load at a load at which a saturation efficiency becomes a maximum, a load at which an efficiency of a power load becomes a maximum at which a saturation output becomes a maximum, or the like is established.

An impedance of an input side from an output end of the first input matching circuit 6th seen from a first impedance Z _S1 at a frequency of an input signal. An impedance of an output side from an input end of the third output matching circuit 15th From a perspective, a second impedance is Z _L1 at a frequency of an input signal. Z _S1 and Z _L1 have no imaginary part. The characteristic impedance of the first delay circuit 7th is the same as Z _S1 . The characteristic impedance of the second delay circuit 14th is the same as Z _L1 . Because the first delay circuit 7th and the second delay circuit 14th Delaying only one phase without changing the impedance need the first delay circuit 7th and the second delay circuit 14th be connected to a circuit with an impedance that has no imaginary part.

A matching circuit from the drain of the first amplifier 9 for synthesis circuit 21st is designed so that a passband phase becomes 90 degrees + 180 x N degrees (where N is a natural number) at a frequency of an input signal. There is also a matching circuit from the drain of the second amplifier 12th for synthesis circuit 21st designed so that a passband phase becomes 0 degrees + 180 x M (M is a natural number) at a frequency of an input signal. Here, a case will be described in which N = 0 and M = 1. By designing the matching circuits in this way, an impedance to a small signal becomes on the second amplifier side 12th , from the synthesis circuit 21st from an open point of view. Furthermore, a load impedance becomes when the signal of the first amplifier is small 9 set up at an impedance twice as high as that at a large signal.

4th Fig. 13 is a view showing impedance transformation of an output matching circuit of the second amplifier according to the embodiment 1 illustrated. The impedance is from 50 Ω to Z _L1 in the third output matching circuit 15th and the fourth matching circuit 19th transformed. The second delay circuit 14th is connected to a position where an impedance _{becomes that Z L1} having no imaginary part, and is constructed with a microstrip line having an electrical length of 1/4 of a wavelength λ of a signal at a characteristic impedance Z _L1 . The first delay circuit 7th is also connected to a position where an impedance _{becomes the impedance Z S1} , which similarly has no imaginary part, and is constructed with a microstrip line having an electrical length of 1/4 of a wavelength λ of a signal at the characteristic impedance Z _S1 .

Then, effects of the present embodiment will be described in comparison with a comparative example. 5 Fig. 13 is a circuit diagram illustrating a Doherty amplifier according to the comparative example. In the comparative example are the first delay circuit 7th and the second delay circuit 14th outside the case 1 intended. A characteristic impedance of the microstrip line of the first delay circuit 7th and the second delay circuit 14th is 50 Ω. Therefore, a phase difference of 90 degrees occurs between the first and second input terminals 2 and 3 or between the first and the second output port 4th and 5 of the housing 1 on. Accordingly, an influence due to an interference between paths is great.

6th Fig. 13 is a view illustrating a calculation result of a drain efficiency of the Doherty amplifier according to the comparative example. 7th Fig. 13 is a view illustrating a calculation result of a gain of the Doherty amplifier according to the comparative example. A thick line indicates a case where a distance between terminals is 1 mm, and a thin line indicates a case where a distance between terminals is 100 mm. In the comparative example, there is a decrease in the saturation output power and a decrease in the efficiency during a back-off due to a decrease in the distance between the terminals. 8th FIG. 13 is a view illustrating a drain efficiency calculation result of the Doherty amplifier according to Embodiment 1. FIG. 9 FIG. 12 is a view illustrating a calculation result of a gain of the Doherty amplifier according to Embodiment 1. FIG. It can be understood that in Embodiment 1, characteristics do not deteriorate even if the distance between the connections decreases to 1 mm.

10 Fig. 13 is a view illustrating a result obtained by calculating an influence of the distance between terminals on the saturation output. A horizontal axis indicates the distance between connectors. A vertical axis indicates a relative change in the saturation output based on a saturation output at the inter-terminal distance of 100 mm at which electromagnetic coupling between terminals can be ignored. In the comparative example, it can be understood that if the distance between terminals becomes smaller than about 10 mm, a decrease in saturation output can be seen, and if the distance between terminals is several millimeters, a saturation output greatly decreases. Meanwhile, in Embodiment 1, even if the distance between terminals is 1 mm, a saturation output decreases only slightly.

11 Fig. 13 is a view illustrating a result obtained by calculating a saturation output of the Doherty amplifier according to Embodiment 1 while changing the electrical length of the delay circuit. A horizontal axis gives electrical lengths of the first delay circuit 7th and the second delay circuit 14th which are normalized with an electrical length of 1/4 of an input signal. In a manner similar to a typical Doherty amplifier, the electrical lengths of the first delay circuit 7th and the second delay circuit 14th cannot be exactly λ / 4, and if the electrical lengths are within a range of 1/4 ± 20% of a wavelength λ of the input signal, similar effects can be expected.

As described above, in the present embodiment, since the delay circuits are incorporated in the package, it is possible to make phases between the input terminals and between output terminals of the package equal. In this way, it is possible to suppress electromagnetic coupling occurring in a small case. Furthermore, it is possible to easily fine-tune characteristics of the Doherty amplifier on the matching circuits outside the housing.

Embodiment 2

12th Fig. 13 is an equivalent circuit diagram showing the interior of a case of a Doherty amplifier according to an embodiment 2 illustrated. 13th Fig. 13 is a plan view showing a layout of the interior of the case of the Doherty amplifier according to the embodiment 2 illustrated. In contrast to Embodiment 1, the first delay circuit 7th and the second delay circuit 14th built with lumped parameters instead of microstrip lines. Inductors 29 to 36 are constructed with bonding wires. Capacitors 37 to 40 are parallel plate capacitors or the like constructed with an MIM capacitor formed on a semiconductor substrate or a metal structure and a heat sink on a dielectric substrate.

A T-type circuit that uses the capacitor 40 between two inductors 35 and 36 connected in series is shunted, corresponds to the second delay circuit 14th in embodiment 1. 14th FIG. 13 is a view illustrating impedance transformation of an output matching circuit of a second amplifier according to Embodiment 2. FIG. This T-type circuit does not contribute to an impedance transformation and is designed so that only one passband phase is delayed by 90 degrees. In a similar fashion, a T-type circuit corresponds to that of the capacitor 37 between two inductors 29 and 30th connected in series is shunted to the first delay circuit 7th .

While in Embodiment 1, the first delay circuit 7th and the second delay circuit 14th are constructed with high-dielectric-constant substrates, in Embodiment 2, the first delay circuit 7th and the second delay circuit 14th built with concentrated parameters. Therefore, circuit sizes of the first delay circuit 7th and the second delay circuit 14th can be scaled down more easily. As in 13th Also illustrated are the first amplifier 9 and the second amplifier 12th mounted in different positions with respect to a signal travel direction. Therefore, it is possible to suppress interference between bonding wires as well as interference between input terminals and between output terminals.

Embodiment 3

15th FIG. 13 is a view illustrating a Doherty amplifier according to Embodiment 3. FIG. In the present embodiment are inside the housing 1 between the first input port 2 and the first output terminal 4th the first input matching circuit 41 , the first amplifier 9 and the first output matching circuit 42 sequentially connected. Inside the case 1 are between the second Input connector 3 and the second output terminal 5 the second input matching circuit 43 , the second amplifier 12th and the second output matching circuit 44 sequentially connected.

An electrical length from the first input port 2 to the first amplifier 9 is longer than an electrical length from the second input terminal within a range of 1/4 ± 20% of a wavelength λ of an input signal 3 to the second amplifier 12th . Therefore, a pass band phase of the first input matching circuit becomes 41 with respect to a passband phase of the second input matching circuit 43 delayed by 90 degrees.

One electrical length from the second repeater 12th to the second output port 5 is longer than an electrical length from the first amplifier within a range of 1/4 ± 20% of a wavelength λ of an input signal 9 to the first output connection 4th . Therefore, a pass band phase of the second output matching circuit becomes 44 with respect to a pass band phase of the first output matching circuit 42 delayed by 90 degrees.

The second output matching circuit 44 and the fourth matching circuit 19th are designed so that an impedance of an output, from a drain end of the second amplifier 12th seen, in a manner similar to Embodiment 1, an optimal load impedance Zopt becomes. However, the second output matching circuit carries 44 contributes to an impedance transformation and is designed so that a passband phase with respect to the first output matching circuit 42 delayed by 90 degrees. The first input matching circuit 41 and the second input matching circuit 43 are also designed similarly.

16 FIG. 13 is an equivalent circuit diagram illustrating the inside of the case of the Doherty amplifier according to Embodiment 3. FIG. The first input matching circuit 41 includes inductors 45 to 47, a capacitor 48 and a microstrip line 49. The second input matching circuit 43 includes inductors 50 and 51 and a capacitor 52. The first output matching circuit 42 includes an inductor 53. The second output matching circuit 44 includes inductors 54 and 55 and a microstrip line 56.

17th FIG. 13 is a view illustrating impedance transformation of the output matching circuit of the first amplifier according to Embodiment 3. FIG. 18th FIG. 13 is a view illustrating impedance transformation of the output matching circuit of the second amplifier according to Embodiment 3. FIG. An impedance of the first amplifier 9 and the second amplifier 12th is transformed from 50 Ω to Zopt in each case. Note that a phase in the microstrip line 56 at the second output matching circuit 44 delayed by 90 degrees. This similarly occurs in the first input matching circuit 41 on. Therefore, in a manner similar to Embodiment 1, phases of signals between input terminals and between output terminals become the same. Note that if there is a difference in passband phase between the first output matching circuit 42 and the second output matching circuit 44 Is 90 degrees and a difference of a passband phase between the first input matching circuit 41 and the second input matching circuit 43 90 degrees, similar effects in circuits other than in 16 illustrated circuits can be obtained.

During the first delay circuit 7th and the second delay circuit 14th in Embodiment 1 do not contribute to an impedance transformation, carry the first input matching circuit 41 and the second output matching circuit 44 in the present embodiment contributes to an impedance transformation. Therefore, in addition to the effects of Embodiment 1, since it is possible to enable transformation of an impedance to be performed in multiple stages, broadband characteristics can be expected.

List of reference symbols

1

Casing;

2

first input port;

3

second input port;

4th

first output terminal;

5

second output port;

6th

first input matching circuit;

7th

first delay circuit;

8th

second input matching circuit;

9

first amplifier;

10

first output matching circuit;

11

third input matching circuit;

12th

second amplifier;

13th

second output matching circuit;

14th

second delay circuit;

15th

third output matching circuit;

16

first matching circuit;

17th

second matching circuit;

18th

third matching circuit;

19th

fourth matching circuit;

20th

Dividing circuit;

21

Synthesis circuit;

29, 30, 35, 36

Inductor;

37, 40

Capacitor;

41

first input matching circuit;

42

first output matching circuit;

43

second input matching circuit;

44

second output matching circuit

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• JP 2005303771 A [0005]

Claims (5)

Doherty amplifier, comprising: a housing including first and second input ports adjacent to each other and first and second output ports adjacent to each other; a first input matching circuit, a first delay circuit, a second input matching circuit, a first amplifier, and a first output matching circuit sequentially connected between the first input terminal and the first output terminal within the housing; a third input matching circuit, a second amplifier, a second output matching circuit, a second delay circuit, and a third output matching circuit sequentially connected between the second input terminal and the second output terminal within the housing; first to fourth matching circuits connected to the first input terminal, the second input terminal, the first output terminal and the second output terminal, respectively, outside the housing; a dividing circuit provided outside the housing, dividing an input signal equally into two signals, and feeding the two signals to the first and second input terminals via the first and second matching circuits, respectively; and a synthesis circuit provided outside the case and synthesizes signals input from the first and second output terminals through the third and fourth matching circuits into a signal. Doherty amplifier after Claim 1 , wherein an impedance of an input side viewed from an output end of the first input matching circuit is a first impedance at a frequency of the input signal, an impedance of an output side viewed from an input end of the third output matching circuit is a second impedance at the frequency of the input signal, the first and second impedances have no imaginary part, a characteristic impedance of the first delay circuit is the same as the first impedance, a characteristic impedance of the second delay circuit is the same as the second impedance, and electrical lengths of the first and second delay circuits are within a range 1/4 ± 20% of a wavelength of the input signal. Doherty amplifier after Claim 2 wherein the first and second delay circuits are microstrip lines. Doherty amplifier after Claim 2 wherein each of the first and second delay circuits is a circuit to which a capacitor is shunted between two series-connected inductors. Doherty amplifier, comprising: a housing including first and second input ports adjacent to each other and first and second output ports adjacent to each other; a first input matching circuit, a first amplifier, and a first output matching circuit sequentially connected between the first input terminal and the first output terminal within the housing; a second input matching circuit, a second amplifier, and a second output matching circuit sequentially connected between the second input terminal and the second output terminal within the housing; first to fourth matching circuits connected to the first input terminal, the second input terminal, the first output terminal and the second output terminal, respectively, outside the housing; a dividing circuit provided outside the housing, dividing an input signal equally into two signals, and feeding the two signals to the first and second input terminals via the first and second matching circuits, respectively; and a synthesis circuit which is provided outside the housing and synthesizes signals input from the first and second output terminals via the third and fourth matching circuits into a signal, wherein an electrical length from the first input terminal to the first amplifier is within a range of 1/4 ± 20% of a wavelength of the input signal longer than an electrical length from the second input terminal to the second amplifier, and an electrical length from the second amplifier to the second output terminal within a range of 1/4 ± 20% of the wavelength of the input signal is longer than an electrical length from the first amplifier to the first output terminal.

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