DE112017005105B4 - Devices and methods for frequency tuning of rotary traveling wave oscillators - Google Patents

Abstract

A rotary traveling wave oscillator (RTWO) (15, 30, 60, 70, 80, 400, 600, 1500) comprising:a first RTWO ring (601, 602, 603, 604);a plurality of segments (100) positioned around the first RTWO ring and comprising a plurality of tuning capacitors (92) selectable to control an oscillation frequency of the RTWO; anddecoding circuitry configured to control the selection of the plurality of tuning capacitors based on one or more frequency tuning codes, the selection of the plurality of tuning capacitors being quantized across the plurality of segments;wherein the decoding circuitry comprises a plurality of local decoders (402), each configured to control a number of selected capacitors for a corresponding segment of the plurality of segments, and a plurality of tuning decoders (404) configured to control the plurality of local decoders (402) based on the one or more frequency tuning codes.

Description

Area of Revelation

Embodiments of the invention relate to electronic systems and in particular to rotary traveling-wave oscillators (RTWOs).

background

Rotary traveling wave oscillators (RTWOs) can be used in a variety of applications including, for example, telecommunications systems, optical networks, and/or chip-to-chip communications. For example, an RTWO can be used in a frequency synthesizer to generate an output clock signal having a controlled phase and frequency relationship to a reference clock signal.

US 2010/0 066 416 A1 discloses a digitally controlled oscillator, a frequency synthesizer and a radio communication device.

US 2012/0 133 445 A1 discloses an electronic pulse generator and oscillator.

US 2013/0 093 523 A1 discloses a digitally controlled oscillator device and a high frequency signal processing device.

Summary of Revelation

The claimed subject matter is defined in the independent claims. Advantageous further developments are described in the dependent claims.

According to one aspect, an RTWO is provided. The RTWO includes an RTWO ring having a first transmission line conductor and a second transmission line conductor configured to guide a traveling wave, and a plurality of segments disposed around the RTWO ring. Additionally, a first segment of the plurality of segments includes a pair of metal stubs including a first metal stub electrically connected to the first transmission line conductor and a second metal stub electrically connected to the second transmission line conductor, and one or more capacitor tuning banks electrically connected to the pair of metal stub conductors and operable to control an oscillation frequency of the RTWO.

In some embodiments, the first segment further comprises a TDC latch electrically connected between the first metal stub and the second metal stub and operable to detect passage of the traveling wave.

In a number of embodiments, the first metal stub and the second metal stub have substantially the same length.

According to various embodiments, the first metal stub and the second metal stub each have a length of at least a factor of 0.05 of a wavelength of the traveling wave.

In some embodiments, the first metal stub and the second metal stub each have a length of at least about 25 μm.

According to a number of embodiments, the first segment further comprises a first tap buffer having an input electrically connected to the first metal stub and a second tap buffer having an input electrically connected to the second metal stub.

In several embodiments, the first segment further comprises a regeneration circuit electrically connected between the first metal stub and the second metal stub and configured to provide energy to the traveling wave to compensate for a loss of the differential transmission line.

In various embodiments, each of the plurality of segments includes a plurality of tuning capacitor banks operable to provide an LSB tuning resolution of 50 kHz/LSB or less and a tuning range of 4 GHz or more.

In some embodiments, the one or more capacitor tuning banks include a fine tuning capacitor bank electrically connected between the first metal stub and the second metal stub and a coarse tuning capacitor bank electrically connected between the first metal stub and the second metal stub. According to a number of embodiments, the one or more capacitor tuning banks further include a PVT tuning capacitor bank electrically connected between the first metal stub and the second metal stub.

In various embodiments, each of the segments includes a TDC latch and the RTWO further includes a clock distribution tree and a reference clock buffer configured to provide a reference clock signal to the TDC latch of each of the segments via the clock distribution tree.

According to another aspect, a PLL is provided. The PLL includes a PLL core configured to generate one or more frequency tuning codes, and an RTWO including a ring having a first transmission line conductor and a second transmission line conductor configured to guide a traveling wave, and a plurality of segments disposed around the ring. Each of the segments includes a pair of metal stubs including a first metal stub electrically connected to the first transmission line conductor and a second metal stub electrically connected to the second transmission line conductor, and one or more capacitor tuning banks electrically connected to the pair of metal stubs and operable to control an oscillation frequency of the RTWO based on the one or more frequency tuning codes.

In some embodiments, the first metal stub and the second metal stub each have a length of at least a factor of 0.05 of a wavelength of the traveling wave.

In various embodiments, the RTWO is designed to function both as a digitally controlled oscillator and as a time-to-digital converter in the PLL.

In a number of embodiments, the one or more capacitor tuning banks include a fine tuning capacitor bank and a coarse tuning capacitor bank, and the one or more frequency tuning codes include a coarse tuning code and a fine integer tuning code.

According to another aspect, an RTWO is provided. The RTWO comprises at least one RTWO ring, a plurality of segments positioned around the at least one RTWO ring, and a segment decoding system. Each of the plurality of segments comprises one or more configurable circuits, and the segment decoding system is electrically connected to the plurality of segments and is configured to control writing of configuration data to the one or more configurable circuits based on a segment address signal.

In some embodiments, each of the plurality of segments is individually addressable via the segment address signal.

In various embodiments, the segment decoding system comprises a plurality of segment decoders, each of which is connected to a corresponding segment of the plurality of segments.

In several embodiments, the RTWO further comprises a serial interface configured to provide a segment data signal and the segment address signal to the segment decoding system. In a number of embodiments, the segment decoding system is configured to select a segment of the plurality of segments based on a value of the segment address signal and to write a plurality of bits of the segment data signal to the selected segment. According to some embodiments, the segment decoding system is configured to write the plurality of bits of the segment data signal to the selected segment in a plurality of clock cycles over one or more wires having a fewer number than the plurality of bits. In various embodiments, the segment decoding system is configured to select a segment of the plurality of segments based on a value of the segment address signal and to write a plurality of bits of the segment data signal to the selected segment. sensignal and read one or more bits from the selected segment. In a number of embodiments, the serial interface comprises a local SPI.

In some embodiments, the one or more configurable circuits include a regeneration circuit, a latch, a tuning capacitor, and/or a tap buffer.

In various embodiments, the configuration data is operable to control a bias current, a resistance value, a capacitance value, and/or a transistor width of the one or more configurable circuits.

According to another aspect, an RTWO is provided. The RTWO includes a first RTWO ring, a plurality of segments positioned around the first RTWO ring and including a plurality of tuning capacitors selectable to control an oscillation frequency of the RTWO, and a decoding circuit operable to control a selection of the plurality of tuning capacitors based on one or more frequency tuning codes. The selection of the plurality of tuning capacitors is quantized across the plurality of segments.

In some embodiments, the decoding circuit includes a plurality of local decoders, each configured to control a number of selected capacitors for a corresponding segment of the plurality of segments, and a plurality of tuning decoders configured to control the plurality of local decoders based on the one or more frequency tuning codes.

In a number of embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the decoding circuit is implemented such that a selection of one or more tuning decoders is dynamically selected in response to a given value of the fine frequency tuning code. In various embodiments, the decoding circuit is implemented such that a sequence of selecting each of the plurality of tuning decoders for a first ramp of the fine frequency tuning code relative to a second ramp of the fine frequency tuning code is different. In various embodiments, the selection sequence rotates through a plurality of different selection sequences. According to various embodiments, the selection sequence is selected randomly or pseudorandomly.

In several embodiments, the decoding circuit is implemented such that a selection of one or more tuning capacitors is dynamically selected in response to a given value of the one or more frequency tuning codes.

In some embodiments, the first RTWO ring has multiple sides and the decoding circuit is further configured to adjust a number of selected tuning capacitors for each side of the RTWO ring. According to various embodiments, the decoding circuit is implemented such that the number of selected tuning capacitors per side of the RTWO ring is at most one tuning capacitor for each value of the one or more frequency tuning codes.

In various embodiments, the RTWO further comprises a second RTWO ring locked to the first RTWO ring, and the decoding circuit separately controls a number of selected capacitors of the first RTWO ring and the second RTWO ring. According to a number of embodiments, the decoding circuit is further configured to adjust a number of selected tuning capacitors for the first and second RTWO rings. According to some embodiments, the decoding circuit is implemented such that a number of selected tuning capacitors per RTWO ring is at most one tuning capacitor for each value of the one or more frequency tuning codes.

In a number of embodiments, the plurality of tuning capacitors comprises a plurality of coarse tuning capacitors, a plurality of fine tuning capacitors, and/or a plurality of PVT tuning capacitors.

In several embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code and the decoding circuit is further configured to receive an offset code operable to adjust a value of the fine frequency tuning codes to provide a capacity adjustment at a particular segment of the plurality of segments. In various embodiments, the offset code is configured to provide a dynamic capacity adjustment for the plurality of segments while the RTWO is operable to linearize the RTWO.

According to another aspect, a PLL with fine frequency tuning resolution is provided. The PLL includes a PLL core configured to generate one or more frequency tuning codes and an RTWO. The RTWO includes a first RTWO ring, a plurality of segments positioned around the first RTWO ring and including a plurality of tuning capacitors selectable to control an oscillation frequency of the RTWO, and a decoding circuit operable to control a selection of the plurality of tuning capacitors based on the one or more frequency tuning codes. The selection of the plurality of tuning capacitors is quantized across the plurality of segments.

In various embodiments, the decoding circuit includes a plurality of local decoders, each configured to control a number of selected capacitors for a corresponding segment of the plurality of segments, and a plurality of tuning decoders configured to control the plurality of local decoders based on the one or more frequency tuning codes.

In some embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, wherein the decoding circuit is implemented such that a selection of one or more tuning decoders is dynamically selected in response to a given value of the fine frequency tuning code. In several embodiments, the decoding circuit is implemented such that a sequence of selecting each of the plurality of tuning decoders is different for a first ramp of the fine frequency tuning code relative to a second ramp of the fine frequency tuning code.

In a number of embodiments, the PLL further comprises a second RTWO ring locked to the first RTWO ring, and the decoding circuit controls a number of selected capacitors of the first RTWO ring and the second RTWO ring separately. In various embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, and the decoding circuit is further configured to receive an offset code operable to provide capacitance adjustment to a particular segment of the plurality of segments by adjusting a value of the fine frequency tuning code.

In some embodiments, the PLL core is configured to control the value of the offset code to dynamically change a capacity of the plurality of segments to linearize the RTWO.

In a number of embodiments, the frequency step size of the RTWO corresponds to a frequency change resulting from a selection of a tuning capacitor of a segment.

According to another aspect, an RTWO is provided. The RTWO includes a first RTWO ring, a plurality of segments positioned around the first RTWO ring and including a plurality of tuning capacitors selectable to control an oscillation frequency of the RTWO, and a decoding circuit including a plurality of local decoders each configured to control a number of selected tuning capacitors in a respective one of the plurality of segments. Additionally, a plurality of input codes for the plurality of local decoders are separately controllable.

In some embodiments, the decoding circuit further comprises a plurality of tuning decoders configured to control the plurality of input codes based on one or more frequency tuning codes.

In a number of embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code, and the decoding circuit is implemented such that a selection of one or more tuning decoders is dynamically selected in response to a given value of the fine frequency tuning code.

In several embodiments, the RTWO further comprises a second RTWO ring locked to the first RTWO ring, and the decoding circuit controls a number of selected capacitors of the first RTWO ring and the second RTWO ring separately.

According to some embodiments, the one or more frequency tuning codes comprise a fine frequency tuning code and the decoding circuit is further configured to receive an offset code operable to provide capacity adjustment at a particular segment of the plurality of segments by adjusting a value of the fine frequency tuning code.

Short description of the drawings

• 1 is a schematic diagram of an all-digital phase-locked loop (ADPLL) according to one embodiment.
• 2 is an example of a phase noise versus offset frequency plot for an implementation of the ADPLL of 1 .
• 3 is a schematic representation of an implementation of a rotary traveling wave oscillator (RTWO).
• 4 shows an implementation of segmented voting for an RTWO.
• 5 is a schematic representation of an implementation of an RTWO with superimposed transit waveforms of a traveling wave.
• 6A is a schematic representation of an embodiment of an RTWO with segments having metal stubs.
• 6B is a schematic representation of one embodiment of a clock distribution tree for an RTWO.
• 7 is a schematic representation of an embodiment of an RTWO segment with metal stubs.
• 8A until 8R show an RTWO tuning capacitor sequence for process, voltage, and temperature tuning (PVT tuning) according to one embodiment.
• 9A until 9J show an RTWO tuning capacitor sequence for fine integer tuning according to an embodiment.
• 10 shows an embodiment of an RTWO with segmented decoding.
• 11 shows an embodiment of voting decoders for a multi-ring RTWO.
• 12 shows an embodiment of an RTWO voting decoder.
• 13A-1 and 13A-2 show an embodiment of a dynamic element matching for the segment selection of an RTWO.
• 13B-1 and 13B-2 show another embodiment of dynamic element matching for segment selection of an RTWO.
• 13C-1 and 13C-2 show another embodiment of dynamic element matching for segment selection of an RTWO.
• 14 shows an embodiment of an RTWO with segmented digital addressing.
• 15 shows various embodiments of programmable segment circuits.
• 16 shows an embodiment of an RTWO-based PLL system.

Detailed description of embodiments

The following detailed description of certain embodiments presents various descriptions of specific embodiments of the invention. However, the invention may be embodied in many different ways as defined and covered by the claims. In this description, reference is made to the drawings, in which like reference characters may designate identical or functionally similar elements. It is to be understood that elements shown in the figures are not necessarily drawn to scale. Furthermore, it is to be understood that certain Embodiments may include more elements than shown in a drawing and/or a subset of the elements shown in a drawing. Furthermore, some embodiments may include any suitable combination of features from two or more drawings.

As will be appreciated by those skilled in the art, a rotating traveling wave oscillator (RTWO) may include a differential transmission line connected in a ring with an odd number of one or more crossovers and a plurality of regeneration circuits electrically connected along a path of the differential transmission line. In addition, each crossover may reverse the polarity of a wave propagating along the differential transmission line and the regeneration circuits may add energy to the wave to compensate for the losses of the differential transmission line. Additional details of RTWOs may be as described in the US Patent No. 6556089 entitled “ELECTRONIC CIRCUITRY”, which issued on April 29, 2003, and which is hereby incorporated by reference in its entirety.

Apparatus and methods for RTWOs are provided herein.

According to a first aspect, an RTWO comprises a differential transmission line interconnected in a ring and a plurality of segments distributed around the ring. The segments comprise metal stubs extending from the differential transmission line of the RTWO. The metal stubs provide access to additional design resources for tuning capacitors and other circuits of the RTWO segments while allowing the length of the RTWO ring to be relatively short. Thus, the metal stubs do not prevent the RTWO from operating at a relatively high oscillation frequency, e.g. 10 GHz or more, while providing connectivity to tuning capacitors that tune the oscillation frequency of the RTWO over a wide tuning range and/or provide a fine frequency step size. In certain implementations, the RTWO is tunable using coarse and fine tuning capacitors to provide a wide tuning range, temperature tracking, and wide bandwidth frequency ramps, for example ramps up to about 1 GHz at 10 GHz.

According to a second aspect, a distributed quantized scheme is provided for tuning a frequency of the RTWO. The RTWO has multiple segments distributed around the ring of the RTWO, and the segments include tuning capacitors and other circuitry. The distributed quantized frequency tuning is used to control the tuning capacitors in the RTWO segments using separately controllable code values, thereby improving the frequency step size or resolution of the RTWO. In configurations with multiple RTWO rings coupled together to reduce phase noise, the distributed quantized frequency tuning may be used to separately adjust the tuning capacitors across multiple RTWO rings coupled together, e.g., an RTWO configuration with 4 coupled rings. By implementing the RTWO with distributed quantized frequency tuning, a relatively fine frequency resolution is achieved, for example, a least significant bit (LSB) tuning resolution of 50 kHz/LSB or less and a relatively wide tuning range, for example, 4 GHz or more. The distributed quantized scheme can be used for a variety of tuning modes, including coarse tuning, fine tuning, and process, voltage, and temperature (PVT) tuning.

According to a third aspect, a segmented decoding scheme for RTWO frequency tuning codes is provided to reduce decoding complexity. The segmented decoding scheme may operate using a combination of global and local decoding for the frequency tuning codes from a PLL (phase locked loop) core to reduce the number of wires or conductors between the PLL core and the RTWO by a relatively large factor, for example a factor of 10 or more.

According to a fourth aspect, a dynamic element balancing scheme is provided to linearize the fine-tuning gain characteristics of the RTWO. For example, dynamic element balancing may be used to reduce or eliminate the periodicity of a fixed sequence of segment selection used in the segmented decoding scheme for the RTWO. By reducing or eliminating the periodicity in the selection of the segment sequence, unwanted spurious frequency components may be attenuated. In contrast, a fixed sequence of selecting RTWO segments may degrade spectral integrity because spurious frequency components are generated due to the nonlinearity of the fine-tuning characteristics of the RTWO.

According to a fifth aspect, a segmented digital addressing scheme is provided to individually control parameters of RTWO segments. In certain implementations, a serial interface communicates with the segments via segment decoders that operate with shared or common wires to reduce routing density. The controllable parameters may include, but are not limited to, presets (e.g., a bias current level) of the amplifiers used in the regeneration circuits of the RTWO, presets of a sampling latch of the RTWO (e.g., for a time-to-digital converter function), and/or providing a segment-specific capacitance adjustment to provide a linearity correction. Thus, the settings of a particular RTWO segment may be selected to provide adjustments or corrections for linearity or other operating characteristics, thereby improving performance.

The teachings herein can be used to provide a number of advantages. According to one example, an RTWO-based all-digital phase-locked loop (ADPLL) operates with a relatively wide frequency tuning range and/or fine frequency tuning resolution. In addition, the RTWO-based ADPLL can operate with superior robustness to maintain lock during process, temperature, and/or voltage variations.

The RTWOs herein can have relatively low phase noise. According to one example, an RTWO with four coupled rings achieves a single sideband (SSB) phase noise of -121 dBc/Hz at 8.8 GHz.

The RTWOs herein can also be implemented in a relatively compact area and have relatively low power dissipation. According to one example, an RTWO with four coupled rings consumes less than about 190 mW when operating at about 0.9 V and occupies an area of less than about 1.2 mm ² .

The RTWOs herein may also have a relatively wide tuning range. According to one example, an RTWO is tunable over a frequency range greater than 3 GHz, for example between about 8.8 GHz and 12 GHz for a four coupled ring implementation.

The wide tuning range can provide a number of advantages. For example, an RTWO can be used in a PLL that can remain locked over a wide range of temperature variations. For example, the RTWO can be calibrated to the extreme end of an operating temperature range and the PLL loop can remain locked as the temperature varies to the opposite end of the temperature range. According to one example, the RTWO is calibrated at a lower end of a temperature range, for example -40°C, and the PLL remains locked as the temperature is gradually increased to an upper end of the temperature range, for example 125°C. According to another example, the RTWO is calibrated at the upper end of the temperature range and the PLL remains locked as the temperature is gradually decreased to the lower end of the temperature range. In such examples, the RTWO can utilize, for example, 40% or less of the RTWO's fine tuning range in response to the change in operating temperature.

When used in a PLL, the RTWO can provide a relatively low amount of jitter in the output clock. In an example implementation, an ADPLL achieved root mean square (RMS) jitter of about 240 fs or less over the tuning range of the RTWO when operating between about 1 kHz and 100 MHz in a temperature range of about -40 °C to about 125 °C.

Example of a fully digital phase-locked loop with a rotary traveling wave oscillator

In certain configurations herein, an all-digital phase locked loop (ADPLL) is provided that includes a rotary traveling wave oscillator (RTWO). The ADPLL may be used in a variety of applications including, but not limited to, telecommunications, chip-to-chip communications, and/or automatic test equipment. According to one example, the ADPLL generates an output clock signal with a wide variety of frequency ramp profiles and/or rates.

In contrast, an analog PLL with charge pumps may suffer from supply voltage variations, a narrow tuning voltage range and/or variations in loop dynamics. These disadvantages may be exacerbated in implementations with relatively small geometry processes, such as fine-line CMOS processes. Although an ADPLL architecture has a can offer a number of advantages, the teachings herein are also applicable to RTWOs used in other electronic systems, such as analog PLLs that use RTWOs.

In certain implementations, an ADPLL includes an RTWO that functions as both a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC). Implementing the RTWO to provide a variety of functions improves the compactness of a design because the RTWO is used for multiple purposes.

By using an RTWO in the ADPLL, a low figure of merit (FOM) can be achieved. The superior FOM is achieved in part by a fine resolution of the TDC of the RTWO.

Although the RTWOs described herein may be used in ADPLLs, an RTWO implemented according to the teachings described herein may be used in a wide range of electronic systems and applications.

1 is a schematic diagram of an ADPLL 10 according to one embodiment. The ADPLL 10 includes a fractional accumulator 1, a digital filter 2, a combined digitally controlled oscillator (DCO) and time-to-digital converter (TDC) 4, a counter 5, counter latches 6, a multiplier 7, a subtraction block 11, and an addition block 12. The combined DCO and TDC 4 includes an RTWO 15 and TDC latches 16.

As it is in 1 As shown, the ADPLL 10 includes the fractional accumulator 1 which accumulates a digital tuning word or code N _freq at the rate of a reference clock signal CLK _REF . The digital tuning code N _freq may be used to control an output frequency of the ADPLL 10. In the illustrated embodiment, the subtraction block 11 generates, for each cycle of the reference clock signal CLK _REF, a difference signal based on a difference between an output of the fractional accumulator 1 and a number of DCO clocks NUM_DCO generated in part by the RTWO 15. The number of DCO clocks NUM_DCO corresponds to a digital code represented in integer and fractional form.

As it is in 1 As shown, the RTWO 15 and the TDC latches 16 function to generate a fractional number of DCO clocks FRAC_DCO, which the summation block 12 combines with an integer number of DCO clocks INT_DCO to generate the number of DCO clocks NUM_DCO. Specifically, the RTWO 15 generates K clock phases that are provided to the TDC latches 16. The TDC latches 16 process the K clock phases from the RTWO 15 based on the timing of the reference clock signal CLK _REF to determine the fractional number of DCO clocks FRAC_DCO. The K clock phases have the same oscillation frequency but different phases. In one embodiment, the RTWO outputs 64 or more phases to the TDC latches 16. However, other implementations are possible.

Although the TDC latches 16 are shown as a separate block from the RTWO 15, in certain implementations the TDC latches 16 are integrated into a design of the RTWO 15, for example into the design of the RTWO segments.

With further reference to 1 the RTWO 15 outputs a DCO clock signal CLK _DCO , which in certain implementations may correspond to one of the K clock phases. In the illustrated embodiment, the DCO clock signal CLK _DCO serves as an input to the multiplier 7, which multiplies the DCO clock signal CLK _DCO by a multiplication factor M to produce an output clock signal CLK _OUT . The inclusion of the multiplier 7 increases the flexibility of the ADPLL 10 by extending a frequency range over which the output clock signal CLK _OUT can be controlled. For example, the multiplier 7 can be used to control the output clock signal CLK _OUT to frequencies greater than a maximum oscillation frequency of the RTWO 15, and thus can serve as a frequency multiplier.

According to one example, an RTWO is multiplied by a multiplication factor M. According to another example, a multiplier is omitted.

As it is in 1 As shown, the DCO clock signal CLK _DCO is provided to the integer counter 5 which operates in combination with the counter latches 6 to generate the integer number of DCO cycles INT_DCO. In the illustrated embodiment, the integer counter 5 counts a number of cycles of the DCO clock signal CLK _DCO . For example, the integer counter 5 may be loaded with an initial value of 1 and thereafter increment by 1 for each cycle of the DCO clock signal CLK _DCO .

The difference signal generated by the subtraction block 11 is filtered by the digital filter 2. In addition, the filtered difference signal is used in this embodiment to tune the RTWO 15 with both an integer digital tuning code INT and a fractional digital tuning code F.

The RTWO 15 from 1 is tuned by the integer digital tuning code INT and the fractional digital tuning code F to change the fundamental oscillation frequency of the RTWO. In certain implementations, the RTWO 15 may use additional tuning, including, for example, coarse tuning and/or process, voltage, and temperature (PVT) tuning.

Accordingly, in certain implementations, the fractional digital tuning code F provides fine fractional tuning of the RTWO 15 and the integer digital tuning code INT provides fine integer tuning.

The RTWO 15 may be implemented to include one or more features disclosed herein. In one embodiment, the RTWO 15 is implemented with distributed quantized tuning, segmented decoding, dynamic element matching, segmented digital addressing, and/or metal stub segments.

ADPLL 10 illustrates an example of an electronic system that may include an RTWO implemented in accordance with the teachings herein. However, the RTWOs described herein may be used in a wide variety of electronic systems, including, but not limited to, a variety of data converters and/or frequency synthesizers.

2 is an example of a graph 20 in which for an implementation of the ADPLL 10 of 1 Phase noise is plotted against the offset frequency.

The graph 20 contains a first curve 21 of intrinsic DCO phase noise for the combined DCO and TDC 4, a second curve 22 of TDC phase noise for the combined DCO and TDC 4 and a third curve 23 of the total ADPLL phase noise.

As it is in 2 As shown, the RTWO TDC and DCO functions essentially dominate the ADPLL phase noise at low frequency and high frequency offsets, respectively.

Although an example graph of the phase noise for the offset frequency in 2 As shown, other phase noise offset frequency characteristics are possible.

3 is a schematic representation of an implementation of an RTWO 30. The RTWO 30 comprises a differential transmission line having a first conductor 31 and a second conductor 32. As shown in 3 As shown, the differential transmission line 31, 32 is connected in a closed loop or ring and the differential transmission line has a crossover 33 to provide a reversal for a traveling wave propagating around the ring. The RTWO 30 of 3 further comprises a plurality of segments 35, each of which has a regeneration circuit.

The illustrated RTWO 30 includes one crossover and thirty-two regeneration circuits, each implemented using series-connected inverters in this example. However, other configurations are possible, including, for example, configurations using a different number of crossovers, more or fewer segments, more or fewer regeneration circuits, and/or regeneration circuits implemented in other ways. Furthermore, the RTWO 30 may include other circuitry, including, but not limited to, tuning capacitors, latches, buffers, and/or other circuitry in the segments 35.

As it is in 3 As shown, the differential transmission line of the RTWO is connected in a closed loop and folded at each of the four corners. However, the differential transmission line of the RTWO may be implemented in other ways, including, for example, different implementations of folding and/or routing the conductors 31, 32. For example, the teachings herein are applicable not only to RTWOs implemented using rectangular or square rings, but also to RTWOs having differently shaped transmission lines. Although the RTWO illustrated has four sides, the teachings herein are applicable to RTWOs having more or fewer sides, as well as to RTWOs having curved rings.

In the illustrated embodiment, the RTWO 30 includes segments 35, each including a regeneration circuit, that are distributed at substantially regular intervals around the differential transmission line. Evenly distributing the regeneration circuits helps maintain a uniform differential transmission line characteristic impedance and a substantially constant wave speed. Although each segment 35 includes a pair of series-connected inverters, the teachings herein are applicable to segments having other numbers of regeneration circuits and/or other implementations of the regeneration circuits.

In the illustrated embodiment, the RTWO 30 is divided into 8 segments per side. Since each of the conductors 31, 32 provides a clock signal phase, the 32 illustrated segments 35 operate with a total of 64 clock signal phases. However, other implementations are possible.

The oscillation frequency fosc of the RTWO 30 is based on a speed of a traveling wave propagating along the transmission line divided by a total length or distance the wave travels in one cycle. In certain implementations, the oscillation frequency fosc of the RTWO 30 is given by Equation 1 below, where v _p is the wave phase velocity, I is the length of the transmission line loop or ring, L _TL is the transmission line inductance, and C _TL is the transmission line capacitance. $${ƒ}_{OSC}=\frac{v_p}{2l}=\frac{1}{2\sqrt{L_{TL}{C}_{TL}}}$$

In certain configurations herein, segments of an RTWO (e.g., segments 35 of RTWO 30) include one or more tuning capacitors having a capacitance that is digitally controllable to adjust an oscillation frequency of the RTWO.

It can be difficult to meet RTWO specifications in terms of tuning range and frequency tuning step size. Such challenges can be exacerbated in configurations where the RTWO is specified to operate at a relatively high oscillation frequency. For example, an RTWO with a relatively high oscillation frequency may have a relatively short transmission line loop and thus may be constrained by available design resources such as available transistor active areas and/or metal routing channels.

For example, the RTWO 30 in the ADPLL 10 can be 1 However, in certain applications it may be desirable for the ADPLL 10 to operate at a relatively high oscillation frequency fosc (e.g. 10 GHz or more), with a relatively wide tuning range (e.g. 625 MHz or more) and with a relatively fine tuning resolution (e.g. 200 kHz or less).

4 shows an implementation of a segmented tuning for an RTWO. The segmented tuning contains the PVT tuning (in this example 3 bits), the coarse tuning (in this example 7 bits), the fine integer tuning (in this example 31 bits) and the fine fractional tuning (in this example 7 bits).

As it is in 4 As shown, PVT tuning is controlled by a PVT tuning code with a value in the range of 0 to N _pvt , coarse tuning is controlled by a coarse tuning code with a value in the range of 0 to N _coarse , fine integer tuning is controlled by a fine integer tuning code with a value in the range of 0 to N _finei , and fine fractional tuning is controlled by a fine fractional tuning code with a value in the range of 0 to N _finef .

Although a specific implementation of segmented voting is shown, the RTWOs herein may be implemented with a wide range of segmented voting schemes, including, but not limited to, segmentations using more or fewer bits and/or more or fewer voting codes.

As shown in Box 41 of 4 As shown, the RTWO can operate at an oscillation frequency given by equation 2 below, where f _rtwo is the oscillation frequency of the RTWO when all tuning capacitors are deselected, n _pvt is the selected value of the PVT tuning, Δf _pvt,isb is the PVT LSB frequency resolution (e.g. 16 MHz), n _coarse is the selected value of the coarse tuning, Δf _coarse,lsb is the coarse LSB frequency resolution (e.g. 9 MHz), n _finei is the selected value of the fine integer tuning, Δf _fine,lsb is the fine integer LSB frequency resolution (e.g. 200 kHz), n _finef is the selected value of the fine fractional tuning, and Δf _{finef,lsb is} the fine fractional LSB frequency resolution (e.g. 200 kHz). $${ƒ}_{Osc}={ƒ}_{rtwO}+n_{pvt}\ast \mathrm{\Delta }{ƒ}_{pvt,lsb}+n_{cOarse}\ast \mathrm{\Delta }{ƒ}_{cOarse,lsb}+n_{einei}\ast \mathrm{\Delta }{ƒ}_{einei,lsb}+n_{einee}\ast \mathrm{\Delta }{ƒ}_{einee,lsb}$$

Implementing an RTWO using segmented tuning can reduce a number of tuning capacitors per segment in the RTWO design. For example, for specifications with a tuning range of 625 MHz and a tuning resolution of 200 kHz, an RTWO implemented with equal-sized tuning capacitors and without segmentation can have about 12 bits and 2 ¹² = 4096 tuning capacitors per segment in addition to tuning capacitors for PVT variations. In view of the design resource constraints, interconnecting and controlling this number of tuning capacitors per segment would not be feasible. In contrast, an RTWO using segmented tuning of 4 used to meet these specifications with approximately 38 tuning capacitors per segment for coarse and fine integer tuning, 3 tuning capacitors per segment for PVT variations, and an additional 7 tuning capacitors connected to the RTWO ring for fine fractional tuning.

The selection of values for the segmented tuning can be provided in different ways. According to one example, a PVT code is first selected to smooth out the PVT fluctuations. After that, a coarse tuning code can be selected. In addition, both fine integer and fine fractional tuning codes can be controlled in a loop (for example by the ADPLL 10 of 1 ). Accordingly, resolution of the fine fractional tuning capacitor bank can control an overall frequency resolution of the RTWO. Thus, providing segmentation can offer the benefits of both fine frequency tuning resolution and a reduced number of tuning capacitors per segment.

In certain implementations, an RTWO is tuned to a target frequency by first selecting a value of the PVT tuning code, second selecting a value of the coarse tuning code, and finally selecting values of the fine integer tuning code and the fine fractional tuning code via a PLL loop (for example, the ADPLL 10 of 1 ). For example, an algorithm can be used to select a value of the PVT tuning code that provides a frequency step equal to n _pvt *Δf _pvt,lsb . The selected PVT code can be larger or smaller than the initial PVT code N _pvt,start . Next, for this selected PVT code, the algorithm is run again, starting with a starting coarse tuning code N _coarse,start and selects a coarse tuning code that provides a frequency step equal to n _coarse *Δf _coarse,lsb . The selected coarse tuning code can be larger or smaller than the initial PVT code N _pvt,start . After that, the ADPLL loop is closed and via the loop feedback of the ADPLL the correct fine integer code and fine fractional code are achieved to tune the RTWO to the correct frequency.

In certain implementations, an RTWO has multiple segments distributed around the ring of the RTWO. In addition, each of the segments of the RTWO has a PVT tuning capacitor bank, a coarse tuning capacitor bank, and a fine integer tuning capacitor bank. In certain implementations, an RTWO has one instantiation of a fine fractional tuning capacitor bank and multiple instantiations of fine integer tuning capacitor banks, coarse tuning capacitor banks, and PVT tuning capacitor banks. However, other implementations are possible.

5 is a schematic representation of an implementation of an RTWO 60 with superimposed transit waveforms of a traveling wave. The RTWO 60 comprises a differential transmission line having a first conductor 31, a second conductor 32 and a crossover 33. The RTWO 60 further comprises a plurality of segments 65, each having a TDC latch.

Although a specific RTWO implementation is shown, the teachings herein are applicable to RTWO implemented in a variety of ways. Although the illustrated segments 65 are each shown as a TDC latch, the segments 65 include additional circuitry that is not shown in the figures for clarity. 5 are omitted.

The illustrated RTWO 60 operates as a time-to-digital converter (TDC). The time-to-digital conversion function is provided by delaying the traveling wave propagating around the RTWO ring. For example, the illustrated RTWO 60 is divided into thirty-two segments 65. In addition, an RTWO cycle occurs when a traveling wave propagating along the RTWO transmission line passes through each of the segments 65 twice.

For example, during operation, the traveling wave makes one lap around the transmission line and completes half of an RTWO cycle (180° of phase) by passing through all of the segments 65. After reversing, the wave passes through each of the segments 65 again to complete a second lap around the transmission line and complete the RTWO cycle (360° of phase).

As it is in 5 As shown, the traveling wave experiences a fixed time delay at each segment 65 of the RTWO. The time delay of the wave at a segment corresponds to a time-to-digital conversion resolution that is approximately half the RTWO period divided by a number of segments 65.

Accordingly, a number of segments 65 may be selected to control a resolution of an RTWO providing a time-to-digital conversion function.

According to an example, an RTWO operates with a period of approximately 1/10 GHz, has 32 segments and has a corresponding time-to-digital conversion resolution Δt _tdc of approximately 1.56 ps.

In the illustrated configuration, each of the segments 65 includes a TDC latch used to sample the RTWO phases at a frequency of a reference clock signal CLK _REF . In addition, the reference clock signal CLK _REF of the reference clock signal is provided to the TDC latches of the segments 65 via a clock conductor 66, which is connected as a ring in this example.

With reference to 3-5 and Equation 1, the RTWO oscillation frequency is based on a length of the RTWO loop or ring. To provide a high oscillation frequency RTWO, a relatively short transmission line loop is desired. However, to provide a wide frequency tuning range and fine frequency tuning resolution, a relatively large number of tuning capacitors are desired. In addition, a large number of segments are desired to provide a fine resolution time-to-digital conversion function.

Accordingly, there is a complex trade-off between RTWO frequency characteristics (e.g., oscillation frequency, tuning range, and/or frequency step size) and the implementation of RTWO segments (e.g., number of segments, design of segments, and/or switching of segments).

Example of rotary traveling wave oscillators with metal stubs

Segments of an RTWO may include a variety of circuits, including, for example, regeneration circuits (e.g., maintenance amplifiers), tuning capacitors, latches, buffers, and/or other circuits. In order to achieve a sufficient tuning range, according to a first example, each RTWO segment may include multiple tuning capacitor banks, for example, three or more tuning capacitor banks, as previously described with reference to 4 has been discussed. According to a second example, the segments of an RTWO include TDC latches to provide time-to-digital conversion. According to a third example, the RTWO segments each include at least one tap buffer (e.g., a non-inverting or inverting buffer) used to obtain or extract a clock signal of a particular phase from the ring of the RTWO.

Although it is desirable for the segments of an RTWO to have a large number of circuits and/or circuits of relatively large size, the RTWO may be limited by available design resources such as available active areas and/or routing traces. If additional design resources are provided by increasing the length of the RTWO segments this may undesirably increase the length of the RTWO ring, which in turn reduces the oscillation frequency of the RTWO.

In certain configurations herein, an RTWO includes segments with metal stubs extending from the RTWO's differential transmission line. The metal stubs provide connection opportunities to additional design resources. For example, the segment designs may be relatively wide (e.g., in a first dimension that is substantially perpendicular to a local portion of the RTWO's transmission line) and may include tuning capacitors and other circuitry connected to the metal stubs. However, the segment designs have a relatively short length (e.g., in a second dimension that is substantially parallel to a local portion of the RTWO's transmission line) such that the RTWO's transmission line loop is relatively short to provide a high oscillation frequency of, for example, 10 GHz or more.

Accordingly, the metal stubs extend from the differential transmission line of the RTWO to connect to tuning capacitors and/or other circuits that enable implementation of a wide tuning range, a fine frequency step size, a high oscillation frequency, and/or provide the RTWO with additional functionality such as time-to-digital conversion functionality and/or segment programmability.

6A is a schematic representation of an embodiment of an RTWO 70 having segments comprising metal stubs. The RTWO 70 comprises a differential transmission line having a first conductor 31, a second conductor 32 and a crossover 33. The RTWO 70 further comprises a plurality of segments 75.

In the illustrated embodiment, the RTWO 70 has one crossover segment and thirty-two segments. However, other configurations are possible, such as configurations using a different number of crossovers and/or more or fewer segments. Additionally, in the illustrated embodiment, the differential transmission line of the RTWO is connected in a closed loop and folded at each of the four corners. However, the differential transmission line of the RTWO may be implemented in other ways, including, for example, other implementations of folding and/or routing the conductors 31, 32. For example, the teachings herein are applicable not only to RTWOs implemented using rectangular or square loops, but also to RTWOs with differently shaped transmission lines. Although the illustrated RTWO 70 has four sides, the teachings herein are applicable to RTWOs having more or fewer sides.

In the illustrated embodiment, the RTWO 70 includes segments 75 each having a first metal stub 81 and a second metal stub 82 extending from the first conductor 31 and the second conductor 32, respectively. The first and second metal stub 81, 82 are used to provide local clock phase signals from the RTWO's differential transmission line to the circuits of the segments 75.

In the illustrated embodiment, each segment 75 includes a TDC latch 91, tuning capacitors 92, and a regeneration circuit 93 that operate using both a clock signal phase from the first conductor 31 and a clock signal phase from the second conductor 32. However, other implementations are possible. Although the regeneration circuit 93 is shown as being connected between the first and second conductors 31, 32 of the RTWO ring, according to another example, it is connected between the first and second metal stub lines 81, 82. In the illustrated embodiment, each segment 75 includes a first tap buffer 94 that taps the first conductor 31 to obtain a first clock signal phase and a second tap buffer 95 that taps the second conductor 32 to obtain a second clock signal phase.

Although a specific implementation of the segment circuit arrangement in 6A As shown, other implementations of the segment circuitry are possible, including configurations with more or fewer circuits and/or different circuits. For example, in another embodiment, a first set and a second set of tuning capacitors are connected to the first and second conductors 31, 32, respectively. In yet another embodiment, the segments comprise circuitry that provides segment programmability.

By incorporating the first and second metal stub lines 81, 82 extending from the differential transmission line 31, 32 of the RTWO, the segments 75 of the RTWO can be implemented with a wide design that provides an active area and design resources suitable for the segment circuit arrangement. In addition, the RTWO has a differential transmission line 31, 32 in a relatively short loop and thus the RTWO 70 has a relatively high oscillation frequency.

In one embodiment, an RTWO has a total loop length of less than 7500 µm and the stub length of the first and second metal stub lines 81, 82 is at least 25 µm each. With respect to the 6A The rectangular loop shown has the RTWO from 6A for example, a first length L _RING-X of less than about 1875 µm and a second length L _RING-Y of less than about 1875 µm.

The stub length may be expressed as a fraction of a wavelength of the traveling wave of the RTWO. In one embodiment, the first and second metal stub lines 81, 82 each have a length of at least about 0.05 λ, where λ is the wavelength of the RTWO. As those skilled in the art will appreciate, the wavelength of an RTWO may be expressed as a ratio of the wave phase velocity of the RTWO to the oscillation frequency of the RTWO, or v _p /f _osc .

In one embodiment, segments 75 have a length of less than about 25 µm and a width of at least about 25 µm.

In one embodiment, an RTWO has at least 1 segment per 25 µm loop.

6B is a schematic representation of an embodiment of a clock distribution tree 87 for an RTWO 80. The RTWO 80 comprises a differential transmission line connected in a loop and comprising a first conductor 31, a second conductor 32 and a crossover 33. The RTWO 80 further comprises segments 85 and a reference clock buffer 86. For clarity of the figures, the circuit arrangement of the segments 85 in 6B not shown.

As it is in 6B As shown, reference clock buffer 86 provides a reference clock signal to each of segments 85. Reference clock buffer 86 provides the reference clock signal to clock distribution tree 87, which distributes the reference clock signal to each of segments 85. Clock distribution tree 87 may be used to provide the reference clock signal to TDC latches and/or other circuits of segments 85 that operate using the reference clock signal.

The illustrated clock distribution tree 87 is implemented using branching such that a length of a clock conductor from an output of the reference clock buffer 86 to each segment 85 is substantially equal. Implementing the clock distribution tree 87 in this manner helps to substantially equalize a time at which the reference clock signal reaches the TDC latches and/or other circuits of the segments 85.

Further details of the RTWO 80 from 6B may be similar to those described previously.

7 is a schematic representation of an embodiment of an RTWO segment 100 with metal stubs. The RTWO segment 100 is connected to a first transmission line conductor 101 and a second transmission line conductor 102 of a ring of an RTWO.

For the sake of clarity of the figures, 7 only a portion of the first transmission line conductor 101 and the second transmission line conductor 102 is shown. However, the first transmission line conductor 101 and the second transmission line conductor 102 operate as a portion of a differential transmission line of an RTWO connected in a ring.

The RTWO segment 100 of 7 comprises a PVT tuning capacitor bank 111, a coarse tuning capacitor bank 112, a fine tuning capacitor bank 113, a regeneration circuit 115, a TDC latch 117, a first tap buffer 118a, a second tap buffer 118b, a first metal stub 131, and a second metal stub 132.

The PVT tuning capacitor bank 111 includes selectable capacitors used to compensate for process, temperature and/or voltage variations. In addition, the coarse tuning capacitor bank 112 includes selectable capacitors used to provide the coarse tuning of the oscillation frequency of the RTWO. Further, the fine tuning capacitor bank 113 includes selectable capacitors used to provide fine tuning of the oscillation frequency of the RTWO. The tuning capacitor banks may be implemented using any suitable tunable capacitor structure, including, but not limited to, banks of parallel capacitor elements that are digitally selectable via switches.

Although an example of an RTWO segment with three tuning capacitor banks in 7 As shown, the teachings herein are applicable to RTWOs tuned using more or fewer capacitor banks.

In the illustrated embodiment, the PVT tuning capacitor bank 111 operates using a three-bit PVT tuning code, the coarse tuning capacitor bank 112 operates using a seven-bit coarse tuning code, and the fine tuning capacitor bank 113 operates using a thirty-one-bit fine tuning code. Although a specific example of bit widths is shown, the teachings herein are applicable to tuning with a wide variety of bit widths. Accordingly, other implementations are possible. In certain implementations, the fine tuning capacitor bank 113 is controlled via a PLL feedback loop. For example, the fine integer tuning code may be controlled by a digital filter of a PLL.

The illustrated RTWO segment 100 further includes the TDC latch 117, which is used to detect the passage of a traveling wave propagating along the first and second transmission line conductors 101, 102. For example, the outputs of the TDC latches around the RTWO ring can be processed to produce a digital representation of times at which the traveling wave passes through various positions around the loop. The output of the TDC latches can be used, for example, to determine a fractional number of clock cycles elapsed.

As it is in 7 As shown, the TDC latch 117 receives a reference clock signal CLK _REF . In certain implementations, the reference clock signal CLK _REF is distributed via a clock distribution tree, such as the clock distribution tree 87 of 6B delivered to RTWO segment 100.

In the illustrated embodiment, the first tap buffer 118a and the second tap buffer 118b are implemented using inverters. The first tap buffer 118a and the second tap buffer 118b are used to generate clock signal phases that are separated by approximately 180°. By providing tap buffers along various positions along the RTWO ring, a set of clock signals of desired phases can be obtained. Although 7 represents a configuration in which inverters are used to provide a tap, an RTWO may have tap buffer circuits implemented in a variety of ways.

In the illustrated embodiment, the regeneration circuit 115 includes a first inverter 116a and a second inverter 116b. In addition, an input of the first inverter 116a is electrically connected to an output of the second inverter 116b and an output of the first inverter 116a is electrically connected to an input of the second inverter 116b. However, an RTWO segment may include regeneration circuits implemented in other ways.

The first and second metal stub lines 131, 132 provide local clock phases from the RTWO loop to the circuitry of the RTWO segment 100. Using the first and second metal stub lines 131, 132, the length of the RTWO segment 100 can be relatively short, which in turn results in a relatively short RTWO ring and a correspondingly high RTWO oscillation frequency.

In certain configurations herein, an RTWO segment includes a routing channel 133 that is used to provide passage of routing lanes through the RTWO segment.

As it is in 7 As shown, the first and second metal stub lines 131, 132 provide connections from the first transmission line conductor 101 and the second transmission line conductor 102, respectively, to circuitry of the RTWO segment 100. For example, the first and second metal stub lines 131, 132 connect the ring of the RTWO to tuning capacitors and other circuitry of the RTWO segment 100.

The first and second metal stubs 131, 132 provide a capacitive load that acts as part of the characteristic impedance _{Zo of} the transmission line. In certain implementations, the metal stubs may be implemented with approximately equal length and may be distributed at substantially even intervals around the ring of the RTWO. Although the stubs for each segment are shown to be substantially identical, in other configurations the stubs may be implemented differently for one or more of the segments. According to one example, the design rules of the process restrict the layout of the transistors to one direction, and the stubs along the top and bottom sides of an RTWO are implemented differently than stubs on the left and right sides of the RTWO.

As it is in 7 As shown, the first metal stub 131 is connected to the first transmission line conductor 101 (e.g., via a via) and extends from the first transmission line conductor 131 to provide connections to the circuitry of the RTWO segment 100. In the illustrated embodiment, the first metal stub 131 is connected to a first terminal of the PVT tuning capacitor bank 111, to a first terminal of the coarse tuning capacitor bank 112, to a first terminal of the fine tuning capacitor bank 113, to an input of the first tap buffer 118a, and to a first input of the TDC latch 117. In the illustrated embodiment, an end portion of the first metal stub 131 bends before being connected to the first input of the TDC latch 117. Other implementations are possible.

With continued reference to 7 the second metal stub 132 is connected to the second transmission line conductor 102 (e.g., via a via). After an initial curve or bend, the second metal stub 132 extends from the second transmission line conductor 102 to provide connections to the circuitry of the RTWO segment 100. In the illustrated embodiment, the second metal stub 132 is connected to a second terminal of the PVT tuning capacitor bank 111, to a second terminal of the coarse tuning capacitor bank 112, to a second terminal of the fine tuning capacitor bank 113, to an input of the second tap buffer 118b, and to a second input of the TDC latch 117. Other implementations are possible.

In one embodiment, the first metal stub 101 and the second metal stub 102 each have a length (including bends) of at least about 25 µm. According to one example, the stubs 101, 102 have a length of about 95 µm, which corresponds to about 6% of a wavelength (or 0.06 λ) of an RTWO operating at 10 GHz.

As it is in 7 As shown, the transmission line conductors 101, 102 of the RTWO ring have a width W and are spaced apart by a distance S. The width W and the distance S may have any suitable value, e.g. W = 12 µm and S = 8 µm.

In certain implementations, the transmission line conductors 101, 102 are positioned on different metal layers relative to the metal stubs 131, 132. According to one example, the transmission line conductors 101, 102 of the differential transmission line of the RTWO are implemented on two or more adjacent upper metal layers (e.g., a stack of metal-8 and metal-9) and the stubs are implemented on a lower metal layer (e.g., metal-7). As those skilled in the art will appreciate, a lower metal layer is closer to a semiconductor substrate relative to an upper metal layer.

As in 7 shown is a floor plan design 120 of the RTWO segment 100. The floor plan design 120 includes a PVT tuning capacitor bank design 121, a coarse tuning capacitor bank design 122, a fine tuning capacitor bank design 123, a regeneration amplifier design 125, a TDC latch design 127, a tap buffer design 128, and a decoupling capacitor design 129.

The PVT tuning capacitor bank design 121 corresponds to a boundary of an active region (e.g., transistor designs and/or capacitor sizes) of the PVT tuning capacitor bank 111, the coarse tuning capacitor bank design 122 corresponds to a boundary of an active region of the coarse tuning capacitor bank 112, and the fine tuning capacitor bank design 123 corresponds to a boundary of the active region of the fine tuning capacitor bank 113. Furthermore, the tap buffer design 128 corresponds to a boundary of the active region of the tap buffers 118a, 118b, and the TDC latch design 127 corresponds to a boundary of the active region of the TDC latch 117. In addition, the regeneration amplifier design 125 of a boundary of the active area for the inverters 116a, 116b and the decoupling capacitor design 129 of a boundary of the active area of a decoupling capacitor between power supply and ground for the regeneration circuit 115.

In one embodiment, the RTWO segment 100 has a length S _L of less than about 25 μm and a width S _W of at least about 25 μm. In certain implementations, the RTWO segment 100 has a width that is greater than the length so that numerous segments can be distributed around the RTWO ring while maintaining a relatively short RTWO conductor loop length and a corresponding high oscillation frequency.

In one embodiment, an RTWO has at least 1 segment per 25 µm loop.

Although a specific implementation of an RTWO segment circuit arrangement and floor plan design has been described above, the teachings herein are applicable to a variety of RTWO segment implementations.

Example of distributed quantized frequency tuning

Segments of an RTWO include one or more tuning capacitor banks to provide control of the oscillation frequency of the RTWO. For example, an RTWO segment may include a PVT tuning capacitor bank, a coarse tuning capacitor bank, and/or a fine tuning capacitor bank.

The tuning capacitor banks may be controlled across the RTWO segments using common tuning code values. For example, a PVT tuning capacitor bank of each segment may be controlled using a common PVT tuning code. Similarly, a coarse tuning capacitor bank of each RTWO segment may be controlled using a common coarse tuning code and a fine tuning capacitor bank of each RTWO segment may be controlled using a common fine tuning code.

When tuning capacitor banks are controlled in this manner, the RTWO segments each provide substantially the same amount of tuning capacitance, and the value of the tuning capacitance can be controlled by incrementing or decrementing the tuning capacitance code to achieve a desired RTWO oscillation frequency. In such configurations, the tuning capacitance values of the segments change in lockstep.

Although implementing the RTWO segments in this way can provide the RTWO with a well-controlled and uniform transmission line characteristic impedance, implementing the RTWO segments in this way results in a relatively poor step size for frequency tuning. For example, in an RTWO implemented with N segments, the step size of the LSB capacitance of the RTWO corresponds to an LSB tuning capacitance of a segment multiplied by N segments. According to an example, the LSB tuning capacitance in each of the 32 segments is 18.5 fF, and the step size of the LSB capacitance of the RTWO corresponds to 32 * 18.5 fF because all 32 segments switch together. If the frequency step size is 16 MHz due to the individual LSB tuning capacitances, then the LSB frequency step size of the RTWO is 32 × 16 MHz, which is a relatively large value of 512 MHz.

However, a relatively large frequency step size may be unsuitable for high-performance RTWOs, such as RTWOs that provide digitally controlled oscillations and time-to-digital conversion functions in high-speed applications.

Although a size of LSB capacitors in each segment can be reduced by a factor of N to provide a finer LSB capacitance step size, reducing the capacitance in this way may be impractical. For example, limitations in processing technology and/or design rules may restrict a minimum geometry of devices and/or structures and thus it may be impossible to match capacitors with relatively small capacitance values.

In certain configurations herein, a distributed quantized scheme is provided for tuning a frequency of an RTWO. The RTWO has segments distributed around the ring of the RTWO and the segments include tuning capacitors, regeneration circuits, and other circuits. Distributed quantized frequency tuning is used to control the tuning capacitors in the RTWO segments using separately controllable code values, thereby improving the step size or resolution of the RTWO frequency. In addition, in configurations with multiple RTWO rings that are locked together to reduce phase noise, distributed quantized frequency tuning can be used to separately adjust the tuning capacitors across multiple RTWO rings that are coupled together. Therefore, distributed quantized tuning can be used not only across segments of one RTWO ring, but also across segments of two or more RTWO rings.

Therefore, instead of controlling the tuning capacitor bank of each segment with a common tuning code, at least some of the tuning capacitors are quantized across segments. This means that tuning capacitors of the RTWO segments can be activated individually and corresponding tuning capacitors do not have to be switched on simultaneously across different segments. This means that the RTWO operates with a finer frequency step size for frequency tuning.

8A until 8R show an RTWO tuning capacitor sequence for PVT tuning according to an embodiment.

The RTWO tuning sequence shows an RTWO annotated to show the number of active PVT tuning capacitors in a particular segment as the tuning code value is incremented starting with a lowest value of a PVT code. For clarity of description, the lowest value of the PVT code is selected from zero and corresponds to the smallest value of the PVT tuning capacitance. However, a tuning code can be implemented in a variety of ways.

The RTWO tuning sequence is illustrated in the context of an RTWO with 32 segments, each having a PVT tuning capacitor bank for compensating for temperature, process, and/or supply voltage variations. Additionally, the PVT tuning capacitor bank in this example is 3 bits, resulting in 96 tuning capacitors for PVT compensation. Although a specific example is provided with 32 segments and 96 tuning capacitors, the teachings herein are applicable to a variety of RTWOs, including, but not limited to, RTWOs with fewer segments and/or more or fewer tuning capacitors.

Although it is described in the context of PVT voting, the distributed quantized voting scheme of 8A until 8R be used for other types of RTWO tuning capacitor banks, including for example coarse and/or fine tuning.

8A shows a first PVT tuning configuration 201 with PVT code 0, where all PVT tuning capacitors are turned off.

8B shows a second PVT tuning configuration 202 in which the PVT code relative to the first PVT tuning configuration 201 of 8A is incremented. As in 8B As shown, incrementing the tuning capacitor code to a value of 1 causes the tuning capacitor of a segment to be activated.

Activating a tuning capacitor one segment at a time results in a relatively small change in frequency step size. For example, a capacitance change ΔC along the RTWO ring corresponds to an LSB tuning capacitance C _LSB of the tuning capacitor bank of the segment. Thus, a frequency change Δf of the RTWO corresponds to the LSB frequency step f _LSB of the LSB tuning capacitance C _LSB . In an example, if an LSB tuning capacitor has a value of 18.5 fF and a corresponding frequency step size of 16 MHz, the LSB tuning capacitance of the RTWO is about 18.5 fF and the frequency step size of the RTWO is about 16 MHz.

In 8C a third PVT tuning configuration 203 is shown for incrementing the PVT code to 2. In the example shown, the tuning capacitor of a segment eight positions away from the first segment is activated. This in turn causes approximately twice the LSB capacitance change (2 * C _LSB ) and approximately twice the frequency step change (e.g., 2 * f _LSB ).

In 8D a fourth PVT tuning configuration 204 is shown for incrementing the PVT code to 3. As shown in 8D As shown, a third segment positioned eight segments away from the second segment is incremented by 1, causing approximately three times the LSB capacitance change (3 * C _LSB ) and approximately three times the frequency hopping change (e.g., 3 * f _LSB ).

As shown in 8E to 8Q, the algorithm can be repeated. 8E shows a fifth PVT tuning configuration 205 where the PVT code is 4. 8F shows a sixth PVT tuning configuration 206 where the PVT code is 5. 8G shows a seventh PVT tuning configuration 207 where the PVT code is 6. 8H shows an eighth PVT tuning configuration 208 where the PVT code is 7. 8I shows a ninth PVT tuning configuration 209 where the PVT code is 8. 8J shows a tenth PVT tuning configuration 210 where the PVT code is 9. 8K shows an eleventh PVT tuning configuration 211 where the PVT code is 10. 8L shows a twelfth PVT tuning configuration 212 where the PVT code is 11. 8M shows a thirteenth PVT tuning configuration 213 where the PVT code is 12. 8N shows a fourteenth PVT tuning configuration 214 where the PVT code is 13. 8O shows a fifteenth PVT tuning configuration 215 where the PVT code is 14. 8P shows a sixteenth PVT tuning configuration 216 where the PVT code is 15. 8Q shows a seventeenth PVT tuning configuration 217 where the PVT code is 16.

As it is in 8Q As shown, half of the segments have one capacitor activated. As the PVT code continues to increment, additional capacitors can be activated in a similar manner as previously described.

In 8R An eighteenth PVT tuning configuration 218 is shown in which the PVT code is 32 and each segment has one activated capacitor.

The sequence in which the tuning capacitors of the RTWO segments around the RTWO loop are activated may be chosen to reduce or minimize the imbalance of the RTWO due to the distribution of segment selection around the ring. In one embodiment, the RTWO has a rectangular design and one segment on each of the lower (e.g., southern), left (e.g., western), upper (e.g., northern), and right (e.g., eastern) sides of the ring is selected for PVT in a sequence of four consecutive PVT codes, for example, PVT codes 1 through 4.

In certain implementations, the sequence is selected such that the next selected capacitor in a code sequence is on a different side of the RTWO than the last selected capacitor.

In the example shown, when incrementing PVT codes 1 to 4, the selected capacitors are equidistant (e.g. 32/4 = 8 segments apart). For PVT codes 5 to 8, an additional segment is selected at the midpoint of the south, west, north and east sides. The selected segments in this case are equidistant (3 segments) from the segments selected for PVT codes 1 to 4 and equidistant (8 segments) from each other.

The tuning sequence of selecting segments around the RTWO ring continues for codes 9 to 16, with the segments for PVT codes 9 to 16 being equidistant (1 segment) from the segments selected for PVT codes 5 to 8 and equidistant (8 segments) from each other.

This selection algorithm is continued for PVT codes 17 to 32, eventually selecting one capacitor from each segment for code 32.

In certain implementations, when PVT code 32 is reached, the segment selection sequence is repeated and the segment selected for PVT code 1 is selected for PVT code 33. However, for PVT code 33, the PVT tuning capacitor bank is incremented so that 2 capacitors are activated. Thus, the selection algorithm for PVT codes beyond 32 continues up to a maximum value of the PVT code.

Although described in the context of PVT tuning, the tuning scheme is applicable to other tuning capacitor banks. For example, in another embodiment, the quantization technique is applied to a coarse tuning capacitor bank.

Two or more RTWO rings can be coupled together to reduce phase noise. For example, if two RTWO rings are coupled, the phase noise of the resulting oscillator can be about 3 dB smaller than the phase noise of each RTWO individually. Further reduction in phase noise can be achieved by coupling three or more RTWO rings. For example, coupling four RTWO rings can reduce noise by about 6 dB.

9A-9J show an RTWO tuning capacitor sequence for fine integer tuning according to an embodiment. The RTWO tuning sequence shows four coupled RTWO rings annotated to show the number of active fine integer tuning capacitors in a particular segment of a particular RTWO ring as the value of the fine integer tuning code is incremented starting with a lowest value of a fine integer tuning code. For clarity of description, the lowest value of the fine integer tuning code is selected as zero and corresponds to the smallest value of the fine integer tuning capacitance. However, a tuning code can be implemented in a variety of ways.

In the illustrated embodiment, the RTWO rings are coupled using phase-locking conductors that electrically connect the RTWO rings together. Although an example of phase-locking is shown, RTWO rings can be coupled in a variety of ways.

The RTWO tuning sequence is illustrated in the context of four coupled RTWO rings with 32 segments each. Furthermore, the fine integer tuning capacitor bank of each RTWO segment in this example is 31 bits, resulting in 3968 tuning capacitors. Although a specific example is provided with 4 rings, 32 segments, 31 bits, and 3968 tuning capacitors, the teachings herein are applicable to a variety of RTWOs, including, but not limited to, with more or fewer coupled RTWO rings, more or fewer segments, more or fewer bits, and/or more or fewer tuning capacitors.

Although it is described in the context of fine-tuning, the distributed quantized tuning scheme of 9A-9J be used for other types of RTWO tuning capacitor banks, including for example coarse and/or PVT tuning.

9A shows a first fine-tuning configuration 301 with fine-tuning code 0, where all fine-tuning capacitors are turned off.

9B shows a second fine-tuning configuration 302 with fine-tuning code 1. As shown in 9B As shown, incrementing the fine-tuning code activates a tuning capacitor of a segment of an RTWO ring (the lower left ring in this example).

By activating a tuning capacitor of one segment of an RTWO ring at a time, a relatively fine step size is achieved.

For example, if each tuning capacitor of each RTWO segment has a value of 1.5 fF, then enabling the tuning capacitors in this way provides the RTWO with an LSB tuning capacitance C _LSB of 1.5 fF/4 = 0.375 fF. In certain processes, such as fine-line CMOS processes, a capacitance of 0.375 fF provides finer capacitance resolution than the smallest tunable LSB capacitor that can be made using the process. In addition, in an implementation where 1.5 fF corresponds to a frequency step size of 800 kHz, the RTWO operates with an LSB frequency step f _LSB of 200 kHz when tuned in this way. In contrast, if a tuning capacitor of each segment of each RTWO were turned on together, the LSB step size would be about 25.6 MHz if all segments of all rings were tuned simultaneously.

Accordingly, in the illustrated embodiment, a fine integer tuning is quantized across multiple RTWO rings.

9C shows a third fine-tuning configuration 303 with fine-tuning code 2. As shown in FIG. 9C, incrementing the fine-tuning code results in activation of a tuning capacitor of a segment for an RTWO ring (the lower right ring in this example). In the example shown, the second selected tuning capacitor is positioned at a location that is axisymmetric (or mirror image) with respect to the first selected tuning capacitor. capacitor. Activating the second selected tuning capacitor results in approximately twice the LSB capacitance change and approximately twice the frequency step.

9D shows a fourth fine-tuning configuration 304 with fine-tuning code 3. Incrementing the fine-tuning code results in activation of a tuning capacitor of a segment for an RTWO ring (in this example, the upper right ring).

9E shows a fifth fine-tuning configuration 305 with fine-tuning code 4. Incrementing the fine-tuning code results in activation of a tuning capacitor of a segment for an RTWO ring (in this example, the right-left ring).

As it is in 9A-9E As shown, incrementing the fine tuning code over a range of values from 0 to 4 results in a capacitor in one segment of each RTWO being activated. Thus, for successive fine frequency tuning codes, a respective one of the RTWO rings has at most one more activated capacitor than the other RTWO rings.

Activating the tunable capacitors in this manner keeps the free-running oscillation frequencies of each of the RTWO rings substantially equal to each other. Thus, the fine integer code can be incremented or decremented while maintaining the lock between the RTWO rings.

As it is in 9F-9I shown, the algorithm continues. 9F shows a sixth fine-tuning configuration 306 in which the fine-tuning code is 5. 9G shows a seventh fine-tuning configuration 307 in which the fine-tuning code is 6. 9H shows an eighth fine-tuning configuration 308 in which the fine-tuning code is 7. 9I shows a ninth fine-tuning configuration 309 in which the fine-tuning code is 8.

In 9J A tenth fine tuning configuration 310 is shown in which the fine code is 128 and each segment of each RTWO has one activated capacitor. The selection algorithm continues for fine codes beyond 128 up to a maximum value of the fine code. Thus, the selection of tuning capacitors is distributed across the four RTWO rings up to the total number of fine integer tuning capacitors, which in this particular example is 31 capacitors per segment × 32 segments × 4 rings = 3968 tuning capacitors. Although the example shown operates with 3968 tuning capacitors, other implementations are possible.

Although various examples of distributed quantized tuning have been described, distributed quantized tuning may be applied to RTWOs implemented in a variety of ways. For example, an RTWO may include one or more rings of various shapes and sizes, and the RTWO may include segments implemented in a variety of ways. Accordingly, the teachings herein are applicable to RTWOs implemented in a variety of ways.

Example of segmented decoding for a rotary traveling wave oscillator

In certain configurations herein, a segmented decoding scheme for RTWO frequency tuning codes is provided to reduce decoding complexity. The segmented decoding scheme may operate using a combination of global decoding and local decoding to process the frequency tuning codes. By using segmented decoding, a number of signal paths associated with frequency tuning codes may be reduced.

An RTWO can operate with a large number of tuning capacitors, including tuning capacitors for PVT tuning, coarse tuning, and fine tuning (which includes, for example, both fine integer and fine fractional tuning). The number of tuning capacitors can be further increased in implementations using multiple rings coupled together to reduce phase noise. The large number of tuning capacitors can result in a large number of signal paths or wires.

According to one example, a 4-ring RTWO has 32 segments per ring, with each segment containing a 2-bit PVT tuning capacitor bank, a 3-bit coarse tuning capacitor bank, and a Fine integer tuning capacitor bank with 5 bits. Additionally, each ring has an instantiation of a fine fractional tuning capacitor bank with 5 bits. In this example, the PVT tuning capacitor banks without segmented decoding operate with 256 wires (2 bits * 32 segments * 4 rings), the coarse tuning capacitor banks operate with 384 wires (3 bits * 32 segments * 4 rings), the fine integer tuning capacitor banks operate with 640 wires (5 bits * 32 segments * 4 rings), and the fine fractional tuning capacitor banks operate with 20 wires (5 bits * 4 rings). Thus, a total number of wires in this example can be 256 + 384 + 640 + 20 = 1300 wires.

However, routing a large amount of wires results in a routing bottleneck. In addition, the paths may result in an electrical environment that may couple digital noise components to the RTWO. For example, a large collection of wires on a semiconductor chip may act as a large antenna. In addition, the flexibility and/or scalability of the RTWO design may be limited. For example, such a routing bottleneck may limit a maximum number of RTWO rings that can be coupled together to improve phase noise.

In certain configurations herein, tuning capacitors are quantized across RTWO segments such that the tuning capacitors of each RTWO segment can be controlled separately from tuning capacitors of other segments. Additionally, a global decoder processes frequency tuning codes (e.g., a PVT tuning code, a coarse tuning code, and/or a fine integer tuning code) to generate input codes for local decoders of the RTWO. In certain implementations, thermometer decoding is performed locally for each segment using the local decoders. In multi-ring implementations, the frequency tuning codes may be routed to global decoders associated with each of the RTWO rings.

By using a segmented decoding scheme, a number of metal paths or wires can be reduced.

For example, in the specific example described above, 1300 wires were used for a 4-ring RTWO operating without segmented decoding. In contrast, in this particular example, segmented decoding can be used to provide 7-bit PVT tuning (e.g., 3 thermometer bits per segment * 32 segments = 96 LSB < 2 ⁷ ), 8-bit coarse tuning (e.g., 7 thermometer bits per segment * 32 segments = 224 LSB < 2 ⁸ ), and 12-bit fine integer tuning (e.g., 31 thermometer bits per segment * 32 segments * 4 rings = 3968 LSB < 2 ¹² ). Thus, PVT tuning operates with 28 wires (7 bits * 4 rings), coarse tuning with 32 wires (8 bits * 4 rings) and fine integer tuning with 48 wires (12 bits * 4 rings). Thus, a total number of wires in this example can be 28 + 32 + 48 + 20 = 128 wires, which is approximately an order of magnitude less than the implementation without segmented decoding.

10 shows an embodiment of an RTWO 400 with segmented decoding. In certain configurations herein, segmented decoding is provided to reduce a number of wires for routing to an RTWO, for example, a number of digital signal paths from an ADPLL core to an RTWO.

The RTWO 400 comprises a differential transmission line connected in a closed loop or ring. The differential transmission line comprises a first conductor 31, a second conductor 32 and a crossover 33. The RTWO 400 further comprises segments 100, which are connected as previously described with reference to 7 In the illustrated embodiment, thirty-two instantiations of the segment 100 are arranged around the ring, with eight segments per side of the ring. As shown in 10 As shown, the thirty-two segments are labeled with indices between 0 and 31.

The RTWO 400 further includes a global decoding system 401, a local decoding system 402, a digital routing bus 405, a serial interface 406, and a fine fractional tuning capacitor bank 410.

Although a specific RTWO implementation is shown, the teachings herein are applicable to RTWOs implemented in a variety of ways, including RTWOs with other ring implementations izations, other segment implementations, and/or other decoder implementations.

The global decoding system 401 includes a segment decoding system 403 and a voting decoding system 404. The global decoding system 401 may be implemented using digital logic circuitry, such as digital logic generated using digital synthesis. For example, the segment decoding system 403 and/or the voting decoding system 404 may be described using a hardware description language such as Verilog, which may be synthesized to generate digital logic circuits. However, other implementations are possible. Although shown as distributed across segments, one or more decoders may be configured to provide decoding for multiple segments. For example, one decoder may be used per RTWO page, as shown in 11 is shown.

The tuning decoding system 404 is operable to decode frequency tuning codes (e.g., PVT, coarse and/or fine integer tuning codes) to generate input codes for the local decoding system 402. The input codes are processed by the local decoding system 402 to activate appropriate tuning capacitors of the RTWO segments.

In the illustrated embodiment, the voting decoding system 404 includes a voting decoder (TD) for each segment 100. In addition, the local decoding system 402 includes a local decoder (LD) for each segment 100. In certain implementations, an LD is used to convert a binary input code from a corresponding TD into a thermometer-encoded output code that is used to select a number of active voting capacitors of a particular RTWO segment 100.

As it is in 10 As shown, the digital routing bus 405 surrounds a perimeter of the RTWO 400. The digital routing bus 405 may be used to route a variety of input signals to the global decoding system 401.

For example, the global decoding system 4101 of the RTWO 400 is annotated to illustrate the input signals 411-412 used for frequency tuning, including a PVT tuning code (pvt_code <6:0>), a coarse tuning code (coarse_code <7:0>), a fine integer tuning code (fineint_code <7:0>), and a fine fractional tuning code (finefrac_code <2:0>). Although this is shown in 10 Not shown, the RTWO 400 may receive one or more clock signals used to specify the timing of the voting codes.

In the illustrated embodiment, digital routing bus 405 provides the PVT tuning code, coarse tuning code, and fine integer tuning code to tuning decoding system 404, which processes the codes to generate input codes for controlling local decoding system 402. Local decoding system 402 processes the input codes to control PVT tuning banks, coarse tuning banks, and fine integer tuning banks of RTWO segments 100.

As it is in 10 As shown, an instantiation of fine fractional tuning bank 410 is included in the illustrated RTWO 400 and the fine fractional tuning code (finefrac_code <2:0>) is provided to fine fractional tuning bank 410 to control fine fractional tuning. Thus, in this example, the fine fractional tuning code bypasses the tuning decoding system 404. In certain implementations, an LD is included to decode the fine fractional tuning code to generate thermometer bits to control fine fractional tuning bank 410.

Although a specific implementation of frequency tuning codes and decoding is shown, the teachings herein are applicable to a variety of implementations.

The segment decoding system 403 includes a segment decoder (SD) for each segment 100. The segment decoding system 403 is used to decode data received via the serial interface 406 to the RTWO segments 100.

As it is in 10 As shown, the serial interface 406 receives input signals 413 that include a segment data signal (rtwo_seg_data <7:0>), a segment address signal (rtwo_seg_addr <4:0>), a write enable signal (rtwo_wr_en), a serial interface clock signal (rtwo_sclk), and a read data signal (rtwo_rd_data <7:0>). In certain implementations, serial port 406 is implemented as a local serial peripheral interface (SPI).

In the illustrated embodiment, the digital routing bus 405 routes the input signals 413 to each SD of the segment decoding system 403 for decoding.

It may be desirable for the segments of an RTWO, such as RTWO segments 100, to be configurable. To provide configurability, RTWO segments 100 may be read or written to via serial interface 406.

The illustrated RTWO 400 includes the segment decoding system 401, which reduces a number of paths associated with communication with the RTWO segments 100. In certain implementations, the segment decoding system 403 operates using a local tab. The local tab is used to provide bit addresses for each of the segments and is used to determine when the serial interface 406 is communicating with a particular one of the RTWO segments 100.

By including the segment decoding system 401, a number of data and address bus bits associated with routing from the serial interface 406 to the RTWO segments 100 can be reduced.

For example, in a specific implementation, a 4-ring RTWO with 32 segments per ring has a data bus that operates on 8 bits common to 4 rings and an address bus that operates on 5 bits common to 4 rings. According to such an example, the 4-ring RTWO operates on 13 bits and wires.

In contrast, a similar 4-ring RTWO implemented with a segment decoding system can have 2048 bits and wires (16 bits per segment * 32 segments * 4 rings). Thus, a reduction of more than 100 times can be achieved by including a segment decoding system in this particular example.

Additional details of the segment decoding system 403 may be described below with reference to 14-15 explained.

11 shows an embodiment of voting decoders for a multi-ring RTWO 600. The multi-ring RTWO 600 includes a southwest RTWO ring 601 (R0), a southeast RTWO ring 602 (R1), a northeast RTWO ring 603 (R2), and a northwest RTWO ring 604 (R3). Although a configuration using four rectangular RTWO rings is shown, the teachings herein are applicable to implementations using more or fewer rings and/or rings implemented with other shapes.

Although terms referring to cardinal directions (north, south, east, west, northeast, northwest, southwest, southwest) are used in describing the multi-ring RTWO, those skilled in the art will recognize that the terms are used here to understand relative orientations and do not refer to geographic directions. For example, the multi-ring RTWO 600 is typically implemented at least partially on an integrated circuit (IC) or semiconductor chip, and the orientation of the multi-ring RTWO 600 changes as the position or angle of the IC changes. Similarly, terms referring to up, down, left, and right are used to describe relative directions.

As in 11 As shown, PVT tuning decoders, coarse tuning decoders, and fine integer tuning decoders are provided around the sides of each of the RTWO rings 601 to 604.

With respect to the northwest RTWO ring 604, a north PVT decoder 614a, a north coarse decoder 624a, and a north fine integer decoder 634a are positioned on a first or upper side. Additionally, a south PVT decoder 614b, a south coarse decoder 624b, and a south fine integer decoder 634b are positioned on a second or lower side. Further, a west PVT decoder 614c, a west coarse decoder 624c, and a west fine integer decoder 634c are positioned on a third or left side. Additionally, an east PVT decoder 614d, an east coarse decoder 624d, and an east fine integer decoder 634d are positioned on a fourth or right side.

Moreover, the orientations of respective tuning decoders of the northeast RTWO ring 603 are axisymmetric with respect to the northwest RTWO ring 604. For example, with respect to the northeast RTWO ring 603, a north PVT decoder 613a, a north coarse decoder 623a, and a north fine integer decoder 633a are positioned on a top side. In addition, a south PVT decoder 613b, a south coarse decoder 623b, and a south fine integer decoder 633b are positioned on a bottom side. Further, a west PVT decoder 613c, a west coarse decoder 623c, and a west fine integer decoder 633c are positioned on a right side. In addition, an east PVT decoder 613d, an east coarse decoder 623d, and an east fine integer decoder 633d are positioned on a left side.

Furthermore, orientations of respective tuning decoders of the southwest RTWO ring 601 are axisymmetric with respect to the northwest RTWO ring 604. For example, with respect to the southwest RTWO ring 601, a north PVT decoder 611a, a north coarse decoder 621a, and a north fine integer decoder 631a are positioned on a bottom side. In addition, a south PVT decoder 611b, a south coarse decoder 621b, and a south fine integer decoder 631b are arranged on a top side. Furthermore, a west PVT decoder 611c, a west coarse decoder 621c, and a west fine integer decoder 631c are positioned on a left side. In addition, an east PVT decoder 611 d, an east coarse decoder 621 d and an east fine integer decoder 631 d are positioned on a right side.

In addition, the orientations of respective tuning decoders of the southeast RTWO ring 602 are axisymmetric with respect to both the southwest RTWO ring 601 and the northeast RTWO ring 603. For example, with respect to the southeast RTWO ring 602, a north PVT decoder 612a, a north coarse decoder 622a, and a north fine integer decoder 632a are positioned on a bottom side. In addition, a south PVT decoder 612b, a south coarse decoder 622b, and a south fine integer decoder 632b are arranged on a top side. Further, a west PVT decoder 612c, a west coarse decoder 622c, and a west fine integer decoder 632c are positioned on a right side. In addition, an east PVT decoder 612d, an east coarse decoder 622d, and an east fine integer decoder 632d are positioned on a left side.

Implementing voting decoders of one RTWO ring with axisymphology with respect to the voting decoders of another RTWO ring provides a symmetry that reduces mismatch between the rings.

In the illustrated embodiment, voting decoders are arranged on each side of the RTWO ring. In addition, the voting decoders control voting capacitors of adjacent RTWO segments, thereby reducing connections between the outputs of the voting decoders and the RTWO segments. For example, in an implementation with 32 segments per RTWO ring, the North voting decoders provide 8 corresponding segments of the RTWO ring. Accordingly, path lengths are reduced. Thus, the illustrated voting decoders can illustrate a collection of TD blocks as shown in 10 However, other implementations are also possible. For example, a separate TD block can be provided for each RTWO segment.

As it is in 11 As shown, the PVT tuning decoders of RTWO rings 601-604 are referred to with the text labels pvt_decoder_north, pvt_decoder_west, pvt_decoder_south, and pvt_decoder_east. Additionally, the coarse tuning decoders are referred to with the text labels coarse decoder north, coarse_decoder_west, coarse_decoder_south, and coarse_decoder_east. In certain implementations, the PVT tuning decoders for each of the RTWO rings and each of the segments are substantially identical, and the PVT tuning decoders operate using common PVT tuning codes. Additionally, in certain implementations, the coarse tuning decoders for each of the RTWO rings and each of the segments are substantially identical, and the coarse tuning decoders operate using common coarse tuning codes.

In one embodiment, the PVT and/or coarse tuning decoders operate with distributed quantized tuning as previously described with reference to 8A-8R was discussed.

As it is in 11 shown are the fine integer tuning decoders of RTWO rings 601-604 with text labels fineint_decoder_r0_north, fineint_decoder_r0_west, fineint_decoder_r0_south, fineint_decoder_r0_east, fineint_decoder_r1_north, fineint_decoder_r1_west, fineint_decoder_r1_south, fineint_decoder_r1_east, fineint_decoder_r2_north, fineint_decoder_r2_west, fineint_decoder_r2_south, fineint_decoder_r2_east, fineint_decoder_r3_north, fineint_decoder_r3_west, fineint_decoder_r3_south and fineint_decoder_r3_east.

In certain implementations, the fine integer tuning decoders are implemented using essentially identical hardware (for example, essentially identical Verilog), but operate on different values of rtwo_location <3:0> and thus have different output values. Implementing the decoders in this way improves scalability and flexibility.

In one embodiment, the fine integer tuning decoders operate with distributed quantized tuning of tuning codes across both segments and rings, as previously described with reference to 9A-9J discussed. By providing separate fine integer tuning decoders, fine tuning capabilities can be provided for each of the RTWO segments as well as for each RTWO ring. This in turn facilitates individual control of each tuning element of each segment of each RTWO ring. Accordingly, in certain implementations, fine integer tuning is performed across each of the RTWO segments and across each RTWO ring.

Although 11 represents an embodiment of voting decoders for a multi-ring RTWO, voting decoders can be implemented in a variety of ways.

12 shows an embodiment of an RTWO voting decoder 700. Multiple instantiations of the RTWO voting decoder 700 can be positioned along the RTWO pages. For example, the RTWO voting decoder 700 shows an implementation of the voting decoders of 11 positioned on one side of an RTWO ring.

In the illustrated embodiment, the RTWO tuning decoder 700 includes a PVT tuning decoder 701, a coarse tuning decoder 702, and a fine integer tuning decoder 703.

As it is in 12 As shown, the PVT tuning decoder 701 receives a PVT tuning code (pvt_code <6:0>) and a location code (rtwo_location <3:0>) and generates segment PVT tuning codes (pvt_tune0 <1:0>, ..., pvt_tune7 <1:0». The segment PVT tuning codes are used by local decoders (LDs) of corresponding segments to control the selection of PVT tuning capacitors.

The coarse tuning decoder 702 of 12 receives a coarse tuning code (coarse_code <7:0>) and the location code (rtwo_location <3:0>) and generates segment coarse tuning codes (coarse_tune0 <2:0>,..., coarse_tune7 <2:0>). The segment coarse tuning codes are used by LDs of the corresponding segments to control the selection of coarse tuning capacitors.

As it is in 12 As shown, the fine integer tuning decoder 703 receives a fine integer tuning code (fineint_code <11:0>), the location code (rtwo_location <3:0>), an LSB offset code (offset_lsb <1:0>), an offset location code (offset-location <2:0>), and a test mode code (test_mode <1:0>), and generates segment fine integer tuning codes (fineint_tune0 <4:0>,..., fineint_tune7 <4:0>). The segment fine tuning codes are used by LDs of the corresponding segments to control the selection of fine tuning capacitors.

Multiple instantiations of the RTWO voting decoder 700 can be placed along the sides of the RTWO rings 601-604 of 11 and the location code (rtwo_location <3:0>) can be used to control the response of the voting decoders to a particular voting code value. In one embodiment, the selected voting decoder location for different values of the location code (rtwo_location <3:0>) is given by Table 1 below. Table 1 rtwo_location<3:0> Selected voting decoder <3> <2> <1> <0> 0 0 0 0 West, R0 0 0 0 1 South, R0 0 0 1 0 East, R0 0 0 1 1 North, R0 0 1 0 0 West, R1 0 1 0 1 South, R1 0 1 1 0 East, R1 0 1 1 1 North, R1 1 0 0 0 West, R2 1 0 0 1 South, R2 1 0 1 0 East, R2 1 0 1 1 North, R2 1 1 0 0 West, R3 1 1 0 1 South, R3 1 1 1 0 East, R3 1 1 1 1 North, R3

In certain implementations, the address of a particular voting decoder is hard-wired when the voting decoder is instantiated at a specific location around an RTWO ring.

The voting decoders positioned around the RTWO rings decode the PVT voting code (pvt_code <6:0>), the coarse voting code (coarse_code <7:0>) and the fine integer voting code (fineint_code <11:0>). The voting codes indicate the total number of voting capacitors in the RTWO to be activated or selected.

In the illustrated embodiment, each of the tuning decoders generates segment tuning codes for a plurality of RTWO segments. For example, the PVT tuning decoder 701 outputs segment PVT tuning codes (pvt_tune0 <1:0>, ..., pvt_tune7 <1:0>) for eight RTWO segments. Additionally, the coarse tuning decoder 702 outputs segment coarse tuning codes (coarse_tune0 <2:0>, ..., coarse_tune7 <2:0>) for eight RTWO segments. Furthermore, the fine integer tuning decoder 703 outputs segment fine integer tuning codes (fineint_tune0 <4:0>, ..., fineint_tune7 <4:0>) for eight RTWO segments. Although the voting decoders shown output segment voting codes for eight segments, other implementations are possible.

In the illustrated embodiment, the outputs of the tuning decoders represent a binary representation of the tuning capacitors selected for each of the tuning capacitor banks. Corresponding local decoders (LDs) are used to process the output of the tuning decoders to control the selection of the tuning capacitors of the corresponding segments. In certain implementations, the LDs generate a thermometer code for each of the tuning capacitor banks based on the binary outputs of the tuning decoders.

According to one example, a PVT tuning capacitor bank of each segment has 3 PVT capacitors represented by 2 binary bits, and the LD processes the 2 binary bits to generate a thermometer code for controlling the selection of the 3 PVT capacitors. According to another example, a coarse tuning bank of each segment has 7 coarse tuning capacitors represented by 3 binary bits, and the LD processes the 3 binary bits to generate a thermometer code for controlling the selection of the 7 coarse tuning capacitors. In yet another example, a fine integer tuning bank has 31 capacitors represented by 5 binary bits, and the LD processes the 5 binary bits to generate a thermometer code for controlling the selection of the 31 capacitors.

In the illustrated embodiment, the fine integer tuning decoder 703 also receives the LSB offset code (offset_lsb <1:0>), the offset location code (offset-location <2:0>), and the test mode code (test_mode <1:0>).

In one embodiment, the test mode code controls whether the fine fractional tuning is quantized across segments and across multiple rings (as is done, for example, in 9A to 9J shown) or not, or is quantized across segments but not across multiple rings. Quantizing across segments and across multiple rings improves resolution.

The LSB offset code (offset_lsb <1:0>) and the offset-location code (offset-location <2:0>) may be used to add a number of offset LSBs to the fine integer tuning code (fineint_code <11:0>). Advantageously, the offset LSBs may be added by adjusting a value of the fine integer tuning code rather than selecting tuning capacitors of a particular tuning bank. By providing an offset, nonlinearity across an RTWO ring can be compensated for, where capacitance mismatches may occur particularly at segments near corners and/or crossovers. Thus, capacitance mismatch may be compensated for by adding a digital offset code to a particular segment taken from any of the segments of one of the rings of the RTWO (e.g., from one of 128 segments for a 4-ring RTWO with 32 segments per ring). The digital offset code is added to the segment identified by the offset-location code (offset-location <2:0>).

One embodiment of the added number of LSBs for different values of the LSB offset code (offset_lsb <1:0>) is given in Table 2 below. However, other implementations are possible. Table 2 offset_lsb<1> offset_lsb<0> Added number of LSBs 0 0 2 0 1 4 1 0 6 1 1 10

The LSB offset code (offset_lsb<1:0>) can also be used to evaluate the sensitivity of a multi-ring RTWO to the mismatch in one of the segments. Thus, the LSB offset code (offset_lsb<1:0>) serves as a powerful investigation tool to assess the quality of the physical design of an RTWO. For example, the 2, 4, 6 or 10 LSBs can be added to each of the 128 segments in the RTWO by programming a digital code without the need for additional fixed tuning capacitors in each of the RTWO segments.

An embodiment of the selected segment for different values of the offset location code (offset_location<2:0>) is given in Table 3 below. However, other implementations are possible. Table 3 offset_location<2:0> Selected segment <2> <1> <0> 0 0 0 Segments[0] 0 0 1 Segments[1] 0 1 0 Segments[2] 0 1 1 Segments[3] 1 0 0 Segments[4] 1 0 1 Segments[5] 1 1 0 Segments[6] 1 1 1 Segments[7]

The LSB offset code (offset_lsb<1:0>) and the offset location code (offset_location<2:0>) can be used to write a desired number of LSBs into one of the segments of the RTWO. In certain embodiments, the offset is determined using a segment decoding system (for example, the segmented digital addressing system of 14 ) rather than by means of a decoder. With respect to the embodiment of 10 For example, the SPI interface 406 can be used to write a desired number of LSBs to a specific segment.

In one embodiment, a random or pseudorandom number of offset LSBs are written periodically while the RTWO is operating. The process of writing a random number of offset LSBs can be performed at any speed while the RTWO oscillates at its fundamental frequency. By implementing the RTWO in this manner, the linearity of the RTWO is improved by randomizing the mismatches in fine integer tuning capacitors. For example, the LSB offset code (offset_lsb<1:0>) and the offset location code (offset_location<2:0>) can be used to provide dynamic adjustment of the capacitance values of the segments, thereby linearizing the fine tuning gain characteristics.

Although 12 shows an embodiment of an RTWO voting decoder, RTWO voting decoders can be implemented in many different ways.

Examples of algorithms for a voting decoding system are given below. The voting decoding algorithm can be used to control the voting decoders of the multi-ring RTWO 700 of 11 to implement if the voting decoders are configured using the 12 shown embodiment. In certain configurations, the hardware description language describing the algorithms can be synthesized to produce digital logic circuits. However, other implementations are possible.

Although specific voting decoding algorithms are described, the teachings herein are applicable to a variety of voting decoding algorithms.

A voting decoder can be implemented to map the binary voting codes (e.g. pvt_code<6:0>, coarse_code<7:0> and fineint_code<11:0>) to the segments of an RTWO.

According to one example, the PVT tuning and coarse tuning algorithms are implemented to have different maximum code values (e.g., 96 codes for PVT versus 224 codes for coarse tuning), but are otherwise essentially identical.

Although the following example focuses on quantized PVT tuning, a coarse tuning algorithm can be implemented in a similar way.

When a PVT code is incremented, the calculations described in the Hardware Description Language below (hereinafter "Hardware Description 1") determine which of the four sides (West, South, East, and North) of the RTWO ring is selected. Once a side is selected, the algorithm adjusts the segments within that side. Offset numbers 1, 2, 3, and 4 select one of the West, South, East, or North sides of the RTWO as the PVT code is incremented by 1. $$\begin{array}{ll}\text{pvt}\_\text{seg}\_\text{counter}\_\text{west}\hfill & =\text{mod}\left(\text{pvt}\_\text{code},32\right)-1\hfill \\ \text{pvt}\_\text{seg}\_\text{counter}\_\text{south}\hfill & =\text{mod}\left(\text{pvt}\_\text{code},32\right)-2\hfill \\ \text{pvt}\_\text{seg}\_\text{counter}\_\text{east}\hfill & =\text{mod}\left(\text{pvt}\_\text{code},32\right)-3\hfill \\ \text{pvt}\_\text{seg}\_\text{counter}\_\text{north}\hfill & =\text{mod}\left(\text{pvt}\_\text{code},32\right)-4\hfill \end{array}$$

The modulus of 32 indicates that a cycle of 32 segments in an RTWO ring elapses before these calculations are reset to zero. This corresponds, for example, to the time when all 32 segments in the RTWO ring have been activated by 1 LSB (see, for example, 8R) . Dem accordingly, if pvt_code = 32, all PVT tuning capacitors in each of the segments have a capacitance of 1 LSB, and then if pvt_code = 2 × 32, all PVT tuning capacitors in each of the segments have a capacitance of 2 LSB, and then if pvt_code = 3 × 32, all PVT tuning capacitors in each of the segments have a capacitance of 3 LSB.

$$\begin{array}{ll}\text{pvt}\_\text{seg}\_\text{block}\_\text{counter}\_\text{eat}\_\text{decoder}\hfill & =\text{floor}\left(\text{pvt}\_\text{seg}\_\text{counter}\_\text{east}/4\right)+1\hfill \\ \text{pvt}\_\text{seg}\_\text{block}\_\text{counter}\_\text{north}\_\text{decoder}\hfill & =\text{floor}\left(\text{pvt}\_\text{seg}\_\text{counter}\_\text{north}/4\right)+1\hfill \end{array}$$

The above calculations serve as input to the block counter calculations described by the hardware description language described below (hereinafter "Hardware Description 2"). As detailed in Hardware Description 2, the block counter increments by 1 every 4 codes of the pvt_seg_counter. This indicates that an equal number of LSB capacitors have been activated on each side of the RTWO rings, or that a full cycle around the west, south, east, and north sides of the RTWO (in that order in this example) has been completed. At the 5th count, the block counter indicates that it is time to return to the west side of the RTWO and add an LSB to another segment on that side. $$\begin{array}{ll}\text{pvt}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\hfill & =\text{floor}\left(\text{pvt}\_\text{seg}\_\text{counter}\_\text{west}/4\right)+1\hfill \\ \text{pvt}\_\text{seg}\_\text{block}\_\text{counter}\_\text{south}\_\text{decoder}\hfill & =\text{floor}\left(\text{pvt}\_\text{seg}\_\text{counter}\_\text{south}/4\right)+1\hfill \end{array}$$

$$\begin{array}{ll}\text{pvt}\_\text{seg}\_\text{block}\_\text{counter}\_\text{eat}\_\text{decoder}\hfill & =\text{floor}\left(\text{pvt}\_\text{seg}\_\text{counter}\_\text{east}/4\right)+1\hfill \\ \text{pvt}\_\text{seg}\_\text{block}\_\text{counter}\_\text{north}\_\text{decoder}\hfill & =\text{floor}\left(\text{pvt}\_\text{seg}\_\text{counter}\_\text{north}/4\right)+1\hfill \end{array}$$

The PVT code assigned to each of the 32 segments is calculated by the hardware description language below (hereinafter "Hardware Description 3"). In addition, for the first 32 PVT codes, the PVT code assigned to any of the 32 segments is 1, indicating that 1 LSB is added to the tuning capacitor banks in any of the segments. For the next 32 PVT codes (and so on), the PVT code assigned to any of the 32 segments is 2, indicating that 2 LSB are added to the tuning capacitor banks in each of the segments. The value of pvt_code_assign in this example is between 1 and 3. $$\begin{array}{cc}\text{pvt}\_\text{code}\_\text{assign}& =\text{floor}\left(\text{pvt}\_\text{code}/32\right)\end{array}+1$$

       if pvt_seg_block_counter_west_decoder == 0
                  pvt_tune0 = pvt_code_assign - 1
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign - 1
                  pvt_tune3 = pvt_code_assign - 1
                  pvt_tune4 = pvt_code_assign - 1
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign - 1
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 1
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign - 1
                  pvt_tune3 = pvt_code_assign - 1
                  pvt_tune4 = pvt_code_assign - 1
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign - 1
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 2
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign - 1
                  pvt_tune3 = pvt_code_assign - 1
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign - 1
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 3
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign - 1 
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign - 1
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 4
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign - 1
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 5
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 6
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 7
                  pvt_tune0 = pvt_code_assign 
                  pvt_tune1 = pvt_code_assign
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 8
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign
       endif

Based on the value of the block counter specified in Hardware Description 2, each tuning capacitor bank on each of the west, south, east, and north sides of the RTWO ring is set according to the hardware description language below (hereinafter "Hardware Description 4"). Although Hardware Description 4 only shows calculations for the west tuning decoder, the south, east, and north decoders may use similar calculations. For example, if pvt_seg_block_counter_west_decoder = 0 and pvt_code_assign = 1, the PVT code for the tuning capacitor banks on the west side of the RTWO ring is all zeros and the tuning capacitors are turned off. Furthermore, if pvt_seg_block_counter_west_decoder = 1, all but PVT of segment 0 on the west side of the RTWO are set to 1 or 1 LSB of tuning capacitance. Additionally, when pvt_seg_block_counter_west_decoder = 2, the PVT code for segment 0 and segment 4 of the tuning capacitor banks on the west side of the RTWO ring are set to 1. At the time pvt_seg_block_counter_west_decoder = 2, the input pvt_code is 5, indicating that the block counter returned to the west side of the RTWO after adding one LSB on each of the 4 RTWO sides.

 if pvt_seg_block_counter_west_decoder == 0
                  pvt_tune0 = pvt_code_assign - 1
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign - 1
                  pvt_tune3 = pvt_code_assign - 1
                  pvt_tune4 = pvt_code_assign - 1
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign - 1
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 1
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign - 1
                  pvt_tune3 = pvt_code_assign - 1
                  pvt_tune4 = pvt_code_assign - 1
pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign - 1
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 2
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign - 1
                  pvt_tune3 = pvt_code_assign - 1
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign - 1
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 3
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign - 1 
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign - 1
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 4
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign - 1
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 5
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign - 1
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 6
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign - 1
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 7
                  pvt_tune0 = pvt_code_assign 
                  pvt_tune1 = pvt_code_assign
                  pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign - 1
              elseif pvt_seg_block_counter_west_decoder == 8
                  pvt_tune0 = pvt_code_assign
                  pvt_tune1 = pvt_code_assign
pvt_tune2 = pvt_code_assign
                  pvt_tune3 = pvt_code_assign
                  pvt_tune4 = pvt_code_assign
                  pvt_tune5 = pvt_code_assign
                  pvt_tune6 = pvt_code_assign
                  pvt_tune7 = pvt_code_assign
       endif

Using the PVT voting algorithm described above, the block counter increments every 4 PVT codes at the decoder's input. At the end of these 4 PVT codes, 1 LSB is set at segments 0, 8, 16, and 24. At PVT code 32, the block counter is reset and each of the 32 segments has a voting capacity of 1 LSB (all segments from 0 to 31 are assigned code 1). At code 33, the block counters start incrementing and segment 0 has 2 LSB. The algorithm continues until PVT code 64 is reached, where all 32 segments have 2 LSB, and the algorithm repeats until the PVT code reaches 96.

In the following example, a quantized fine integer voting algorithm is provided. The quantized fine integer voting algorithm follows a similar approach to the quantized PVT voting algorithm described above. However, the quantized fine integer voting algorithm also provides quantization of the voting code across multiple RTWO rings (4 in this example) as well as across segments (32 per ring in this example). In contrast, the PVT voting algorithm described above was quantized across RTWO segments, but not across RTWO rings.

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r1}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-2\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r2}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-3\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r3}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-4\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r}0& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-\end{array}5$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r1}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-6\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r2}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-7\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r3}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-8\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{east\_r0}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-9\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{east\_r1}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-10\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{east\_r2}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-11\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{east\_r3}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-12\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{north\_r0}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-13\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{north\_r1}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-14\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{north\_r2}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-15\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{north\_r3}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-16\end{array}$$

The calculations described by the Hardware Description Language below (hereinafter "Hardware Description 5") determine the location of the segment to be selected on one of the west, south, east, or north sides of the four RTWO rings as fineint_code increases. $$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{<figure-callout id="0" label="r" filenames="DE112017005105B4\_0042.png,DE112017005105B4\_0045.png" state="{{state}}">r</figure-callout>}0& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-1\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r1}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-2\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r2}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-3\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r3}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-4\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{<figure-callout id="0" label="r" filenames="DE112017005105B4\_0042.png,DE112017005105B4\_0045.png" state="{{state}}">r</figure-callout>}0& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-\end{array}5$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r1}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-6\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r2}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-7\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r3}& =\text{mod}\left(\text{fineint}\_\text{code},32*4\right)-\mathrm{8th}\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{east\_r0}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-9\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{east\_r1}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-10\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{east\_r2}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-11\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{east\_r3}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-12\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{north\_r0}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-13\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{north\_r1}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-14\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{north\_r2}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-15\end{array}$$

$$\begin{array}{cc}\text{fineint}\_\text{seg}\_\text{counter}\_\text{north\_r3}& =\text{mod}\left(\text{fineint\_code}\mathrm{,32}*4\right)-16\end{array}$$

Offset numbers 1 through 16 in hardware description 5 above select one of the 16 segments of the 4-ring RTWO when the code is incremented by 1. The modulus 32 * 4 = 128 indicates that a cycle of 128 segments elapses before the calculations are reset to zero: this corresponds to the time at which all 128 segments in the 4-ring RTWO have been activated by 1 LSB. Accordingly, if fineint_code = 128, then all fine integer tuning capacitors in each of the 128 segments have a capacity of 1 LSB. If fineint_code = 2x128, then all fine integer tuning capacitors in each of the 128 segments have 2 LSB capacity, and so on. R0, R1, R2 and R3 indicate the ring numbers in the RTWO with 4 coupled rings, as shown in 11 are designated.

As the fineint_code increases, the sequence of the selected decoders is shown in Table 4 below. This sequence repeats every 16 codes of the fineint_code. Table 4 fineint_code Decoder 0 West, R0 1 West, R1 2 West, R2 3 West, R3 4 South, R0 5 South, R1 6 South, R2 7 South, R3 8th East, R0 9 East, R1 10 East, R2 11 East, R3 12 North, R0 13 North, R1 14 North, R2 15 North, R3

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r1}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r1}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r2}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r2}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r3}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r3}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r}0=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r0}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r1}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r1}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r2}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r2}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r3}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r3}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r}0=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{east}\_\text{r0}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r1}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{east}\_\text{r1}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r2}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{east}\_\text{r2}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r3}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{east}\_\text{r3}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r}0=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{north}\_\text{r0}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r1}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{north}\_\text{r1}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r2}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{north}\_\text{r2}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r3}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{north}\_\text{r3}/\left(4*4\right)\right)+1\end{array}$$

The above calculations in Hardware Description 5 serve as input to the block counter calculations described in the Hardware Description Language below (hereinafter "Hardware Description 6"). As detailed below, the block counter increments by 1 every 4 × 4 = 16 codes of the fineint_seg_counter. This indicates that all 16 sides of the 4-ring RTWO have an equal number of LSB capacity and that a full cycle around the west, south, east, and north sides of each of the 4 RTWO rings is completed. At the 17th count, the block counter indicates that it is time to return to the west side of ring number 0 of the RTWO and add an LSB at another segment on that side. $$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{<figure-callout id="0" label="r" filenames="DE112017005105B4\_0042.png,DE112017005105B4\_0045.png" state="{{state}}">r</figure-callout>}0=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r0}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r1}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r1}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r2}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r2}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r3}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{west}\_\text{r3}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{<figure-callout id="0" label="r" filenames="DE112017005105B4\_0042.png,DE112017005105B4\_0045.png" state="{{state}}">r</figure-callout>}0=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r0}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r1}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r1}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r2}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r2}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r3}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{south}\_\text{r3}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{<figure-callout id="0" label="r" filenames="DE112017005105B4\_0042.png,DE112017005105B4\_0045.png" state="{{state}}">r</figure-callout>}0=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{east}\_\text{r0}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r1}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{east}\_\text{r1}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r2}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{east}\_\text{r2}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r3}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{east}\_\text{r3}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{<figure-callout id="0" label="r" filenames="DE112017005105B4\_0042.png,DE112017005105B4\_0045.png" state="{{state}}">r</figure-callout>}0=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{north}\_\text{r0}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r1}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{north}\_\text{r1}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r2}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{north}\_\text{r2}/\left(4*4\right)\right)+1\end{array}$$

$$\begin{array}{l}\begin{array}{cc}& \text{fineint}\_\text{seg}\_\text{block}\_\text{counter}\_\text{west}\_\text{decoder}\_\text{r3}=\end{array}\\ \text{floor}\left(\text{fineint}\_\text{seg}\_\text{counter}\_\text{north}\_\text{r3}/\left(4*4\right)\right)+1\end{array}$$

The calculations described by the hardware description language below (hereinafter "Hardware Description 7") determine the fine integer code assigned to each of the 128 segments. In addition, for the first 128 fine integer codes, the code assigned to one of the 128 segments is 1, indicating that 1 LSB is added to the tuning capacitor banks in one of the segments. For the next 128 fine integer codes, the fine integer code assigned to one of the 128 segments is 2, indicating that 2 LSB are added to the tuning capacitor banks in one of the segments, and so on. The value of fineint_code_assign is between 1 and 8. $$\text{fineint\_code\_assign}=\text{floor}\left(\text{fineint}\_\text{code}/\left(32*4\right)\right)+1$$

              if fineint_seg_block_counter_west_decoder_r0 == 0
                  fineint_tune0r0 = fineint_code_assign - 1
                  fineint_tune1r0 = fineint_code_assign - 1
                  fineint_tune2r0 = fineint_code_assign - 1
                  fineint_tune3r0 = fineint_code_assign - 1
                  fineint_tune4r0 = fineint_code_assign - 1
                  fineint_tune5r0 = fineint_code_assign - 1
                  fineint_tune6r0 = fineint_code_assign - 1
                  fineint_tune7r0 = fineint_code_assign - 1
              elseif fineint_seg_block_counter_west_decoder_r0 == 1
                  fineint_tune0r0 = fineint_code_assign
                  fineint_tune1r0 = fineint_code_assign - 1
                  fineint_tune2r0 = fineint_code_assign - 1
                  fineint_tune3r0 = fineint_code_assign - 1
                  fineint_tune4r0 = fineint_code_assign - 1
                  fineint_tune5r0 = fineint_code_assign - 1
                  fineint_tune6r0 = fineint_code_assign - 1
                  fineint_tune7r0 = fineint_code_assign - 1
              elseif fineint_seg_block_counter_west_decoder_r0 == 2
                  fineint_tune0r0 = fineint_code_assign
                  fineint_tune1r0 = fineint_code_assign - 1
                  fineint_tune2r0 = fineint_code_assign - 1
                  fineint_tune3r0 = fineint_code_assign - 1 





                  fineint_tune4r0 = fineint_code_assign
                  fineint_tune5r0 = fineint_code_assign - 1
                  fineint_tune6r0 = fineint_code_assign - 1
                  fineint_tune7r0 = fineint_code_assign - 1

Based on the value of the block counter specified in Hardware Description 6, the individual tuning capacitor banks on the west, south, east and north sides of the RTWO ring are adjusted according to the calculations specified in the hardware description language below (hereinafter “Hardware Description 8”). Although Hardware Description 8 describes the calculations for the west tuning decoder only for ring number 0 and for certain values of fineint_seg_block_counter_west_decoder_r0, the rest of the decoders and other values of fineint_seg_block_counter_west_decoder_r0 may use similar calculations. For example, if fineint_seg_block_counter_west_decoder_r0 = 0 and fineint_code_assign = 1, the fine integer code for the tuning capacitor banks on the west side of RTWO ring 0 is all zeros and the tuning capacitors are off. In addition, if fineint_seg_block_counter_west_decoder_r0 = 1, all but the fine integer code of segment 0 on the west side of RTWO ring 0 are set to 1 (1 LSB of tuning capacity). Furthermore, when fineint_seg_block_counter_west_decoder_r0 = 2, the fine integer code for segment 0 and segment 4 of the tuning capacitor banks on the west side of RTWO ring 0 is set to 1. At the time fineint_seg_block_counter_west_decoder_r0 = 2, the input fineint_code is 17, which means that the block counter has returned to the west side of RTWO ring 0 after adding one LSB on each of the 16 RTWO sides.

 if fineint_seg_block_counter_west_decoder_r0 == 0
                  fineint_tune0r0 = fineint_code_assign - 1
                  fineint_tune1r0 = fineint_code_assign - 1
                  fineint_tune2r0 = fineint_code_assign - 1
                  fineint_tune3r0 = fineint_code_assign - 1
                  fineint_tune4r0 = fineint_code_assign - 1
                  fineint_tune5r0 = fineint_code_assign - 1
                  fineint_tune6r0 = fineint_code_assign - 1
                  fineint_tune7r0 = fineint_code_assign - 1
              elseif fineint_seg_block_counter_west_decoder_r0 == 1
                  fineint_tune0r0 = fineint_code_assign
                  fineint_tune1r0 = fineint_code_assign - 1
                  fineint_tune2r0 = fineint_code_assign - 1
                  fineint_tune3r0 = fineint_code_assign - 1
                  fineint_tune4r0 = fineint_code_assign - 1
                  fineint_tune5r0 = fineint_code_assign - 1
                  fineint_tune6r0 = fineint_code_assign - 1
                  fineint_tune7r0 = fineint_code_assign - 1
              elseif fineint_seg_block_counter_west_decoder_r0 == 2
                  fineint_tune0r0 = fineint_code_assign
                  fineint_tune1r0 = fineint_code_assign - 1
                  fineint_tune2r0 = fineint_code_assign - 1
                  fineint_tune3r0 = fineint_code_assign - 1 





                  fineint_tune4r0 = fineint_code_assign
                  fineint_tune5r0 = fineint_code_assign - 1
                  fineint_tune6r0 = fineint_code_assign - 1
                  fineint_tune7r0 = fineint_code_assign - 1

Using the voting algorithm described above, the block counter at the input of the decoder increments every 16 fine integer codes. At the end of these 16 fine integer codes, 1 LSB is set for each of the rings R0 (SW), R1 (SO), R2 (NO), and R3 (NW) at segments 0, 8, 16, and 24. At fine integer code 128, the block counter is reset and each of the 128 segments has voting capacity of 1 LSB (all segments from 0 to 31 are assigned code 1). At code 129, the block counter restarts incrementing and segment 0 has 2 LSB. The algorithm continues until fine integer code 256 is reached, when all 128 segments have 2 LSB, and the algorithm repeats until fine integer code 3968 is reached.

Although specific examples of algorithms for a voting decoding system have been given above, voting decoding algorithms can be implemented in a variety of ways.

Example of dynamic element matching to linearize the fine-tuning gain of an RTWO

In certain configurations herein, a dynamic element balancing scheme is provided to linearize the fine-tuning gain characteristics of an RTWO. For example, dynamic element balancing may be used to break a periodicity of a fixed sequence of segment selection used in the segmented decoding scheme for the RTWO. By reducing or eliminating the periodicity in the segment sequence selection, unwanted spurious frequency components may be mitigated. In contrast, a fixed sequence of selecting RTWO segments may degrade spectral integrity by generating spurious frequency components.

For example, a wide frequency ramp can span a full range of fine-tuning codes. When a fixed sequence of segment selection is used, a spurious component appears at a frequency offset from the fundamental frequency. The frequency of the spurious component is based on the period of the fixed sequence of segment selection.

The following Table 5 shows an example of a fixed sequence selection for an implementation of the multi-ring RTWO 600 of 11 . In Table 5, W0, W1, W2 and W3 indicate the west tuning decoders of RTWO rings R0, R1, R2 and R3, respectively. Similarly, S0, S1, S2 and S3 indicate the south tuning decoders of RTWO rings R0, R1, R2 and R3, respectively. Similarly, E0, E1, E2 and E3 indicate the east tuning decoders of RTWO rings R0, R1, R2 and R3, respectively. In addition, N0, N1, N2 and N3 indicate the north tuning decoders of RTWO rings R0, R1, R2 and R3, respectively.

As shown in the example presented in Table 5, the decoders activate or deactivate in a specific order as fineint_code increases. The periodicity in segment selection may lead to a degradation of the spectral purity of the RTWO output clock phases.

In certain implementations herein, an RTWO decoding system is implemented with a dynamic element matching scheme to linearize the fixed sequence. Additionally, the dynamic element matching scheme may increase the period of the fixed sequence and/or remove the periodicity entirely.

13A-1 and 13A-2 show an embodiment of a dynamic element matching for the segment selection of an RTWO. The dynamic element matching scheme of 13A-1 and 13A-2 illustrates an embodiment of the dynamic element adjustment for the multi-ring RTWO 600 from 11 Thus, the illustrated embodiment of dynamic element matching is used in conjunction with sixteen tuning decoders, each designated as decoder 0 through decoder 15.

However, dynamic element matching schemes can be used for a wide variety of RTWOs, including but not limited to RTWOs that have more or fewer rings, other implements ments of rings, more or fewer segments, other implementations of segments, more or fewer voting decoders, and/or other implementations of voting decoders.

As it is in 13A-1 and 13A-2 , a sequence of a 16 decoder cycle (in this example) is shown, with the sequence of selected decoders labeled first through sixteenth decoder selections 1001-1016. The decoder cycle indicates the selection of decoders in response to a ramp of the fine integer code received from the RTWO. As discussed above, in certain applications a wide frequency ramp may span the entire range of fine tuning codes.

A pointer 1000 is used to indicate the most recently selected voting decoder. Additionally, a next cycle pointer 1020 indicates a voting decoder that will be used at the beginning of a next decoder cycle (16-decoder cycle in this example). As shown by the first decoder selection 1001, the next cycle pointer 1020 is positioned at a different decoder location than the pointer 1000 in the first decoder selection 1001. Implementing dynamic element matching in this manner reduces the periodicity in decoder selection by preventing two consecutive 16-decoder cycles from starting at the same decoder location.

In the illustrated embodiment, pointer 1000 begins with decoder 0 upon first decoder selection 1001. In certain implementations, if pointer 1000 has never been set, for example upon power-up or reset of a chip, then pointer 1000 may be set to a particular starting value (for example, decoder 0) or to a random or pseudorandom decoder position.

As it is in 13A-1 and 13A-2 As shown, the selected decoders change when moving from one decoder selection to the next decoder selection. For example, in the illustrated embodiment, the selected decoders begin at the next decoder selection after an end of the decoders of the current decoder selection. Thus, in this embodiment, all previously selected decoders are turned off when moving to the next decoder selection.

For example, when transitioning from the first decoder selection 1001 to the second decoder selection 1002, decoder 0 is turned off and decoders 1-2 are turned on. In addition, when transitioning from the second decoder selection 1002 to the third decoder selection 1003, decoders 1-2 are turned off and decoders 3-5 are turned on. When transitioning from the third decoder selection 1003 to the fourth decoder selection 1004, decoders 3-5 are turned off and decoders 6-9 are turned on. When transitioning from the fourth decoder selection 1004 to the fifth decoder selection 1005, decoders 6-9 are turned off and decoders 10-14 are turned on.

In the illustrated embodiment, the selected decoders are designated with a numerical sequence that begins with a start index 0 and ends with an end index 15. If the end index is exceeded during decoder selection, the selected decoders cycle to include decoders beginning with the start index. For example, when moving from the fifth decoder selection 1005 to the sixth decoder selection 1006, decoders 10-14 are turned off and decoders 15 and 0-4 are turned on.

As shown in the sixth through sixteenth decoder selections 1006-1016, the algorithm repeats until the sixteenth decoder selection 1016 in which all sixteen decoders are selected.

The number of decoders selected can be chosen based on the fine integer code. In this embodiment, in case of distributed quantization over four rings, e.g., mod(fineint_code, 16)+1 can be calculated. Also, fineint_code 0 does not select any decoders in this example. Accordingly, the result is a value between 1 and 16.

Depending on the current position of the pointer 1000, the result will select a certain number of decoders from the current pointer position. According to an example where the pointer 1000 is at the decoder 5, fineint_code = 200 and mod(200, 16)+1 = 9, the 9 selected decoders are assigned to decoders 6 to 14. Thereafter, the position of the pointer 1000 is arranged at the decoder 14.

The dynamic element matching can work in combination with the quantized matching. According to an example, the embodiment of the dynamic element matching is 13A-1 and 13A-2 used in combination with the embodiment of quantized tuning described above with reference to 9A - 9J Implementing an RTWO in this way results in a given RTWO ring being separated from other RTWO rings by at most 1 LSB, thereby improving performance. Thus, the benefits of both dynamic element matching and quantized tuning can be realized. However, other implementations are possible.

13B-1 and 13B-2 show another embodiment of the dynamic element matching for the segment selection of an RTWO. The dynamic element matching scheme of 13B-1 and 13B-2 shows an embodiment of the dynamic element adjustment for the multi-ring RTWO 600 from 11 . Thus, the illustrated embodiment of dynamic element matching is used in conjunction with sixteen tuning decoders, designated Decoder 0 through Decoder 15.

However, dynamic element matching schemes can be used for a wide variety of RTWOs, including RTWOs that have more or fewer rings, other implementations of rings, more or fewer segments, other implementations of segments, more or fewer voting decoders, and/or other implementations of voting decoders.

In 13B-1 and 13B-2 16 is a sequence of a 16-decoder cycle (in this example), with the sequence of selected decoders designated as first through sixteenth decoder selections 1101 through 1116, respectively. The decoder cycle indicates the selection of decoders in response to an increase in the fine integer code received from the RTWO.

The implementation of dynamic element matching of 13B-1 and 13B-2 is the embodiment of the dynamic element adjustment of 13A-1 and 13A-2 , similar with the exception that the dynamic element matching of 13B-1 and 13B-2 is implemented such that only one decoder is turned off when transitioning from one decoder selection to the next decoder selection.

For example, when transitioning from the first decoder selection 1101 to the second decoder selection 1102, decoder 0 is turned off and decoders 1-2 are turned on. When transitioning from the second decoder selection 1102 to the third decoder selection 1103, decoder 1 is turned off, decoder 2 remains on, and decoders 3-4 are turned on. When transitioning from the third decoder selection 1103 to the fourth decoder selection 1104, decoder 2 is turned off, decoders 3-4 remain on, and decoders 5-6 are turned on. When transitioning from the fourth decoder selection 1104 to the fifth decoder selection 1105, decoder 3 is turned off, decoders 4-6 remain on, and decoders 7-8 are turned on.

As shown in the sixth through sixteenth decoder selections 1106-1116, the algorithm repeats until the sixteenth decoder selection 1116 in which all sixteen decoders are selected.

Additional details of dynamic element matching of 13B-1 and 13B-2 may be similar to those described previously.

The dynamic element matching scheme of 13A-1 and 13A-2 and the dynamic element matching scheme of 13B-1 and 13B-2 are rotating dynamic element matching schemes. In the example with 16 decoder selections, there are 256 starting possibilities (16*16) for a rotation cycle. Although rotating dynamic element matching schemes reduce periodicity by increasing a length of the fixed sequence period, a degree of periodicity may still remain.

In certain embodiments, a segment decoder system is implemented to operate with random or pseudorandom dynamic element matching.

For example, in certain embodiments, a pseudorandom binary sequence (PRBS) is used to change the selection sequence of the decoders. The PRBS may be generated in any suitable manner, for example using a digital logic circuit.

According to one example, the PRBS changes the selection pointer every certain number of codes, for example every 16 fine integer codes, every 128 fine integer codes, etc. Thus, an even longer rotation sequence can be achieved to break the periodicity of the decoder selection.

According to another example, dynamic element matching is used to randomize the sequence in which segments are selected by a particular voting decoder. Instead of activating a voting capacitor associated with a particular voting decoder in a given sequence, the order in which the voting capacitors controlled by a particular voting decoder are activated is dynamically selected. Accordingly, dynamic element matching can be used to break the periodicity in the selection of voting decoders (a voting decoding sequence) and/or to break the periodicity in voting capacitors selected by the voting decoders (a segment selection sequence).

13C-1 and 13C-2 show another embodiment of the dynamic element matching for the segment selection of an RTWO. The dynamic element matching of 13C-1 and 13C-2 illustrates a sequence of a 16 decoder cycle (in this example), where the sequence of selected decoders is designated as first through sixteenth decoder selections 1201-1216. The decoder cycle indicates the selection of decoders in response to an increase in the fine integer code received from the RTWO.

The implementation of dynamic element matching of 13C-1 and 13C-2 is similar to that of 13B-1 and 13B-2 , except that a PRBS is used to choose the selection of the next cycle pointer 1020 (position 5 was randomly selected in this example). Accordingly, the next cycle pointer 1020 was selected via a pseudorandom process to begin at decoder 5 for the next decoder cycle.

Thus, an RTWO may be implemented to operate in various ways with dynamic element matching. According to one example, a voting decoding system such as the voting decoding system 404 of 10 a digital logic circuit implemented to provide dynamic element balancing.

Although specific examples of dynamic element matching algorithms were given above, dynamic element matching algorithms can be implemented in a variety of ways. According to a first example, a random set of decoders is selected for a given fine-tuning code. For example, if three tuning decoders are activated in response to a particular fine-tuning code, the selected tuning decoders can be randomly or pseudorandomly selected. According to another example, PRBS is used to select between two or more fixed selection sequences. Thus, dynamic element matching can be implemented in a variety of ways.

Example of a segmented digital addressing scheme for RTWO segments

In certain configurations herein, a segmented digital addressing scheme is provided to individually control parameters of RTWO segments. In certain implementations, a serial interface communicates with the segments via segment decoders operating with shared or common wires to reduce the routing bottleneck. The controllable parameters may include, but are not limited to, presets (e.g., a bias current level) of the amplifiers used in the regeneration circuits of the RTWO, presets of a sampling latch of the RTWO (e.g., for a time-to-digital converter function), and/or providing a segment-specific capacitance adjustment to provide a linearity correction. Thus, the settings of a particular RTWO segment may be selected to make adjustments or corrections for linearity or other operating characteristics, thereby improving performance.

Referring again to 10 the RTWO 400 includes the segment decoding system 403, which includes a segment decoder (SD) for each segment 100. The segment decoding system 403 serves to decode data received via the serial interface 406 to the RTWO segments 100.

For example, serial port 406 receives 10 Input signals 413 including a segment data signal (rtwo_seg_data<7:0>), a segment address signal (rtwo_seg_addr<4:0>), a write enable signal (rtwo_wr_en), a serial interface clock signal (rtwo_sclk), and a read data signal (rtwo_rd_data<7:0>). In certain implementations, the serial interface 406 is implemented as a local serial peripheral interface (SPI).

In the illustrated embodiment, the digital routing bus 405 routes the input signals 413 to each SD of the segment decoding system 403 for decoding.

It may be desirable for the segments of an RTWO, such as RTWO segments 100, to be configurable. To provide configurability, RTWO segments 100 may be read or written to via serial interface 406.

The illustrated RTWO 400 includes the segment decoding system 401, which reduces a number of paths associated with communication with the RTWO segments 100. In certain implementations, the segment decoding system 403 operates using a local tab. The local tab is used to provide bit addresses for each of the segments and is used to determine when the serial interface 406 is communicating with a particular one of the RTWO segments 100.

By including the segment decoding system 401, a number of data and address bus bits associated with routing from the serial interface 406 to the RTWO segments 100 can be reduced.

For example, in a specific implementation, a 4-ring RTWO with 32 segments per ring has a data bus that operates on 8 bits common to 4 rings and an address bus that operates on 8 bits common to 4 rings. According to such an example, the 4-ring RTWO operates on 16 bits and wires.

In contrast, a similar 4-ring RTWO implemented with a segment decoding system may have 2048 bits and wires (16 bits per segment * 32 segments * 4 rings). Routing 2048 wires from a serial interface to each segment of the RTWO is a difficult task and may limit the flexibility and/or scalability of the RTWO design. In addition, a large collection of wires on a semiconductor chip may act as a large antenna.

14 shows an embodiment of an RTWO 1500 with segmented digital addressing. The RTWO 1500 has a ring with a first conductor 31, a conductor 32 and a crossover 33. The RTWO 1500 further has several segments distributed around the ring. The RTWO 1500 further has a segment decoding system with segment decoders 1501, 1502, 1503 and 1508. To clarify the figures, only a portion of the ring, the segments and the segmented decoding system are shown in 14 shown. 14 shows, for example, a circuit on the left side of the RTWO ring.

Although a specific RTWO implementation is shown, the teachings herein are applicable to RTWOs implemented in a variety of ways, including, but not limited to, RTWOs with other ring implementations (including, for example, more rings and/or rings of a different shape), other segment implementations, and/or other decoder implementations.

As it is in 14 As shown, segments on the left side of the RTWO ring are labeled as segment 0, segment 1, segment 2, ..., and segment 7. Thus, on the left side of the ring, there are 8 segments in this example. Additionally, the segment decoding system includes a corresponding segment decoder for each segment. For example, segment decoder 1501 is coupled to segment 0, segment decoder 1502 is coupled to segment 1, segment decoder 1503 is coupled to segment 2, and segment decoder 1508 is coupled to segment 7. In this example, there are 8 segment decoders on the left side of the ring.

In the illustrated embodiment, the segment decoding system receives data and address signals 1510. As shown in 14 As shown, the data and address signals 1510 include an 8-bit segment data signal rtwo_seg_data<7:0> and a 5-bit segment address signal rtwo_seg_addr<4:0>. Although an example with 8 data bits and 5 address bits is shown, other implementations are possible.

In certain implementations, the segmented decoding system 401 is implemented to provide addressing of segments associated with multiple rings. According to one example, the segment address signal is implemented as an eight-bit signal rtwo_seg_addr<7:0>, where a first portion of the bits are used to identify a segment location and a second portion of the bits are used to identify a particular ring.

It may be desirable for the segments of an RTWO to be configurable. To provide configurability, the RTWO segments may be described using the data and address signals 1510. In certain implementations, a segment decoding system for reading from segments is further implemented, for example using the method described in 10 shown read data signal rtwo_rd_data<7:0>.

As it is in 14 , each segment decoder communicates with a corresponding segment. For example, as shown in box 1511, segment decoder 1501 provides a segment write signal seg_data_wr<15:0> to segment 0. Additionally, as shown in box 1512, segment decoder 1502 provides a segment write signal seg_data_wr<15:0> to segment 1. As shown in box 1513, segment decoder 1503 also provides a segment write signal seg_data_wr<15:0> to segment 2. Additionally, as shown in box 1518, segment decoder 1508 provides a segment write signal seg_data_wr<15:0> to segment 7.

Thus, each segment includes one or more configurable circuits that are programmed or configured using configuration bits provided via a segment write signal. In one embodiment, the one or more configurable circuits include a regeneration circuit, a latch, a tuning capacitor, and/or a tap buffer.

In the illustrated embodiment, the segment write signal seg_data_wr<15:0> has a larger bit width than the segment data signal rtwo_seg_data<7:0>. Thus, in this example, a segment can be written in two cycles. By implementing segment writes over multiple cycles, a number of global segment data bits and corresponding wires can be reduced.

The illustrated segment decoders 1501, 1502, 1503, and 1508 each receive a segment address set signal seg_addr_set<4:0> having different values for different segment decoders (e.g., 00000, 00001, 00010, 00011, etc.). The segment address set signal seg_addr_set<4:0> is used to program a segment decoder with a code that indicates the position of the segment decoder. In certain implementations, the segment address set signal seg_addr_set<4:0> is hardwired and has a value selected based on a position in the ring.

The segment decoder compares the segment address set signal seg_addr_set<4:0> with the segment address signal rtwo_seg_addr<4:0> to determine when the segment is accessed.

In one embodiment, a segment decoder writes data to a corresponding segment when the segment address signal rtwo_seg_addr<4:0> matches the segment address set signal seg_addr_set<4:0>. If there is an address match, the segment decoder uses the segment write signal seg_data_wr<15:0> to write to the segment, where the written data corresponds to the bits of the segment data signal rtwo_seg_data<7:0>.

The written data may include, but is not limited to, a setting of an amplifier of the segment, a setting of a latch of the segment, and/or a capacitance setting of the segment (e.g., to add capacitance to apply a linearity correction to a particular segment). Thus, the settings of a particular RTWO segment may be selected to make adjustments or corrections for linearity or other operating characteristics, thereby improving performance. The written data may be stored in a segment in any manner. According to one example, a segment includes state elements, such as memory elements and/or latches (including, but not limited to, registers) that store data for configuring the segment.

Although an example of data and address signals 1510 is shown, other implementations are possible. According to another example, one or more of the 10 shown input signals 413 are supplied to each of the segment decoders.

Although an embodiment of segmented digital addressing in 14 As shown, the teachings herein are applicable to segmented digital addressing implemented in a variety of ways.

15 shows various embodiments of programmable segment circuits.

In 15 , an embodiment of a regeneration circuit 1600 with programmable bias current is shown. The regeneration circuit 1600 includes a first n-type field effect transistor (NFET) 1601 and a first p-type field effect transistor (PFET) 1603 operating as a first inverter, and a second NFET 1602 and a second PFET 1604 operating as a second inverter. The first and second inverters are connected in series, with an input of the first inverter connected to an output of the second inverter and vice versa. An instantiation of the regeneration circuit 1600 may be included in a segment, with a first terminal A connected to a first conductor of the RTWO ring and a second terminal B connected to a second conductor of the RTWO ring.

The regeneration circuit 1600 in this example includes a configurable bias current source implemented using a bank of parallel NFET transistors M[3:0]. Additionally, four program bits D[3:0] from a segment configuration register 1609 are used to control the selection of a number of active transistors and a corresponding amount of bias current of the inverters in this embodiment.

With further reference to 15 16, an embodiment of a regeneration circuit 1620 having programmable degeneration resistors 161, 162 is shown. Each of the programmable degeneration resistors 161, 162 may include multiple parallel resistance elements selected via control bits, thereby controlling an amount of degeneration resistance. Additional details of the regeneration circuit 1620 may be similar to those of the regeneration circuit 1600.

As it is in 15 , an embodiment of a regeneration circuit 1630 having programmable noise filter capacitors 1621, 1622, and 1623 is shown. Each of the noise filter capacitors 1621-1623 may include multiple parallel capacitor elements selected via control bits, thereby controlling an amount of capacitance. Additional details of the regeneration circuit 1640 may be similar to those of the regeneration circuit 1620.

Although 15 shows three examples of programmable segment circuits, a wide variety of segment circuits can be programmable. Examples of segment programmability include, but are not limited to, amplifier settings (e.g., bias current), TDC latch settings (e.g., sample point), and/or tuning capacitance settings (e.g., fine code offset LSBs).

Example of RTWO-based PLL system

16 shows an embodiment of an RTWO-based PLL system 1700. The PLL system 1700 comprises an RTWO 1710. As shown in 16 As shown, the RTWO 1710 includes metal stubs 1711, a distributed quantized tuning system 1712, a segmented decoding system 1713, a dynamic element matching system 174, and a segmented digital addressing system 1715.

The metal stubs 1711 are included in the RTWO segments and allow access to additional design resources for tuning capacitors and other circuitry while the length of the RTWO ring can be relatively short. Thus, the metal stubs 1711 do not prevent the RTWO 1710 from operating at a relatively high oscillation frequency, such as 10 GHz or more, while providing connection options for tuning capacitors that tune the oscillation frequency of the RTWO over a wide tuning range and/or provide a fine frequency step size.

The distributed quantized tuning system 1712 is used to control the tuning capacitors in the RTWO segments using separately controllable code values, thereby improving the frequency step size or resolution of the RTWO. In certain implementations, the RTWO 1710 has multiple rings and the distributed quantized tuning system 1712 adjusts the tuning capacitors separately across multiple RTWO rings. By implementing the RTWO with distributed quantized frequency tuning, a relatively fine frequency resolution is achieved, for example an LSB tuning resolution of 50 kHz/LSB or less.

The segmented decoding system 1713 is provided for RTWO frequency tuning codes to reduce decoding complexity. The segmented decoding system 1713 may include global and local decoders for processing frequency tuning codes to reduce routing bottleneck.

The dynamic element balancing system 1714 linearizes the fine tuning gain characteristics of the RTWO 1710. For example, the dynamic element balancing system 1714 can be used to reduce or eliminate the periodicity of a fixed sequence of segment selection used in the segmented decoding system 1713. By reducing or eliminating the periodicity in the selection of the segment sequence, unwanted spurious frequency components can be reduced, thereby improving the performance of the PLL system 1700.

The segmented digital addressing system 1715 may be used to individually control parameters of the RTWO segments and includes segment decoders that operate with shared or common wires to reduce the routing bottleneck. The controllable parameters may include, but are not limited to, presets (e.g., a bias current level) of the amplifiers used in the regeneration circuits of the RTWO, presets of a sampling latch of the RTWO (e.g., for a time-to-digital converter function), and/or providing a segment-specific capacitance adjustment to provide linearity correction for the RTWO 1710.

The PLL system 1700 represents one example of an electronic system that may include an RTWO implemented in accordance with the teachings herein. However, the RTWOs described herein may be used in a wide variety of electronic systems, including, but not limited to, a variety of data converters and/or frequency synthesizers.

Applications

Devices using RTWOs having one or more of the features described above may be implemented in various electronic devices. Examples of the electronic devices may include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, radar systems, etc. Examples of the electronic devices may also include circuits of optical networks or other communication networks. The consumer electronic products may include, but are not limited to, an automobile, a camcorder, a camera, a digital camera, a portable memory chip, a washing machine, a dryer, a washer-dryer, a copier, a fax machine, a scanner, a multifunctional peripheral device, etc. Further, the electronic device may include unfinished products, including those for industrial, medical, and automotive applications.

The foregoing description and claims may refer to elements or features that are "connected" or "coupled" to one another. Unless expressly stated otherwise herein, "connected" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Unless expressly stated otherwise, "coupled" means that one element/feature is directly or indirectly connected to another element/feature, and not necessarily mechanically. Thus, while the various schematics shown in the figures illustrate example arrangements of elements and components, in an actual embodiment, additional intervening elements, devices, features, or components may be present (provided that the functionality of the illustrated circuits is not compromised).

Although this invention has been described with respect to particular embodiments, other embodiments that will be apparent to those skilled in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Moreover, the various embodiments described above may be combined to provide further embodiments. Moreover, certain embodiments associated with an embodiment vention may be incorporated into other embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

Claims (34)

A rotary traveling wave oscillator (RTWO) (15, 30, 60, 70, 80, 400, 600, 1500) comprising: a first RTWO ring (601, 602, 603, 604); a plurality of segments (100) positioned around the first RTWO ring and comprising a plurality of tuning capacitors (92) selectable to control an oscillation frequency of the RTWO; and decoding circuitry configured to control selection of the plurality of tuning capacitors based on one or more frequency tuning codes, the selection of the plurality of tuning capacitors being quantized across the plurality of segments; wherein the decoding circuitry comprises a plurality of local decoders (402), each configured to control a number of selected capacitors for a corresponding segment of the plurality of segments, and a plurality of tuning decoders (404) configured to control the plurality of local decoders (402) based on the one or more frequency tuning codes. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 1 wherein the one or more frequency tuning codes comprise a fine frequency tuning code, the decoding circuitry being implemented such that a selection of one or more tuning decoders (404) is dynamically selected in response to a given value of the fine frequency tuning code. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 2 wherein the decoding circuitry is implemented such that a sequence of selecting each of the plurality of tuning decoders (404) for a first ramp of the fine frequency tuning code relative to a second ramp of the fine frequency tuning code is different. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 3 , where the selection sequence rotates through several different selection sequences. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 3 , where the sequence of selection is chosen randomly or pseudorandomly. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 1 wherein the decoding circuitry is implemented such that a selection of one or more tuning capacitors (92) is dynamically selected in response to a given value of the one or more frequency tuning codes. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 1 wherein the first RTWO ring (601, 602, 603, 604) has multiple sides, the decoding circuitry further configured to balance a number of selected tuning capacitors (92) for each side of the RTWO ring. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 7 wherein the decoding circuitry is implemented such that the number of selected tuning capacitors (92) per side of the RTWO ring differs by at most one tuning capacitor for each value of the one or more frequency tuning codes. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 1 further comprising a second RTWO ring (602) coupled to the first RTWO ring (601), wherein the decoding circuitry separately controls a number of selected capacitors of the first RTWO ring (601) and the second RTWO ring (602). RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 9 wherein the decoding circuitry is further configured to balance a number of selected tuning capacitors (92) for the first and second RTWO rings (602). RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 10 wherein the decoding circuitry is implemented such that a number of selected tuning capacitors (92) per RTWO ring differ by at most one tuning capacitor for each value of the one or more frequency tuning codes. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 1 wherein the plurality of tuning capacitors (92) comprise a plurality of coarse tuning capacitors (112), a plurality of fine tuning capacitors (113), and/or a plurality of process, voltage, and temperature (PVT) tuning capacitors. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 1 wherein the one or more frequency tuning codes comprise a fine frequency tuning code, the decoding circuitry further configured to receive an offset code configured to provide capacity adjustment for a particular segment of the plurality of segments by adjusting a value of the fine frequency tuning code. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 13 wherein the offset code is configured to provide dynamic capacity adjustment for the plurality of segments while the RTWO is operating to linearize the RTWO. A phase locked loop (PLL) (10, 1700) with fine frequency tuning resolution, the PLL comprising: a PLL core configured to generate one or more frequency tuning codes; and a rotary traveling wave oscillator (RTWO) (15, 30, 60, 70, 80, 400, 600, 1500) comprising: a first RTWO ring (601, 602, 603, 604); a plurality of segments positioned around the first RTWO ring and comprising a plurality of tuning capacitors (92) selectable to control an oscillation frequency of the RTWO; and decoding circuitry configured to control the selection of the plurality of tuning capacitors based on the one or more frequency tuning codes, wherein the selection of the plurality of tuning capacitors is quantized across the plurality of segments; wherein the decoding circuitry comprises a plurality of local decoders (402), each configured to control a number of selected capacitors for a corresponding segment of the plurality of segments, and a plurality of tuning decoders (404) configured to control the plurality of local decoders based on the one or more frequency tuning codes. PLL (10, 1700) after Claim 15 wherein the one or more frequency tuning codes comprise a fine frequency tuning code, the decoding circuitry being implemented such that a selection of one or more tuning decoders (404) is dynamically selected in response to a given value of the fine frequency tuning code. PLL (10, 1700) after Claim 16 wherein the decoding circuitry is implemented such that a sequence of selecting each of the plurality of tuning decoders (404) for a first ramp of the fine frequency tuning code relative to a second ramp of the fine frequency tuning code is different. PLL (10, 1700) after Claim 17 further comprising a second RTWO ring (15, 30, 60, 70, 80, 400, 600, 1500) coupled to the first RTWO ring, wherein the decoding circuitry separately controls a number of selected capacitors of the first RTWO ring and the second RTWO ring. PLL (10, 1700) after Claim 15 wherein the one or more frequency tuning codes comprise a fine frequency tuning code, the decoding circuitry further configured to receive an offset code configured to provide capacity adjustment for a particular segment of the plurality of segments by adjusting a value of the fine frequency tuning code. PLL (10, 1700) after Claim 19 , wherein the PLL core is configured to control the value of the offset code to dynamically change a capacity of the plurality of segments to linearize the RTWO. PLL (10, 1700) after Claim 15 , wherein the frequency step size of the RTWO (15, 30, 60, 70, 80, 400, 600, 1500) corresponds to a frequency change resulting from the selection of a tuning capacitor (92) of a segment. A rotary traveling wave oscillator (RTWO) (15, 30, 60, 70, 80, 400, 600, 1500) comprising: a first RTWO ring (601, 602, 603, 604); a plurality of segments positioned around the first RTWO ring and comprising a plurality of tuning capacitors (92) selectable to control an oscillation frequency of the RTWO; and decoding circuitry comprising a plurality of local decoders (402), each configured to control a number of selected tuning capacitors in a respective segment of the plurality of segments, wherein a plurality of input codes for the plurality of local decoders (402) are separately controllable; the decoding circuitry further comprising a plurality of tuning decoders (404) configured to control the plurality of input codes based on one or more frequency tuning codes. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 22 wherein the one or more frequency tuning codes comprise a fine frequency tuning code, the decoding circuitry being implemented such that a selection of one or more tuning decoders (404) is dynamically selected in response to a given value of the fine frequency tuning code. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 22 further comprising a second RTWO ring (602) coupled to the first RTWO ring (601), wherein the decoding circuitry separately controls a number of selected capacitors of the first RTWO ring and the second RTWO ring. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 22 wherein the one or more frequency tuning codes comprise a fine frequency tuning code, the decoding circuitry further configured to receive an offset code configured to provide capacity adjustment for a particular segment of the plurality of segments by adjusting a value of the fine frequency tuning code. A rotary traveling wave oscillator (RTWO) (15, 30, 60, 70, 80, 400, 600, 1500) comprising: at least one RTWO ring (601, 602, 603, 604); a plurality of segments (100) positioned around the at least one RTWO ring, each of the plurality of segments comprising one or more configurable circuits; and a segment decoding system (403) electrically connected to the plurality of segments and configured to control writing of configuration data to the one or more configurable circuits based on a segment address signal; wherein the segment decoding system (403) is configured to select a segment (100) of the plurality of segments based on a value of the segment address signal and read one or more bits from the selected segment. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 26 , wherein each of the multiple segments is individually addressable via the segment address signal. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 26 wherein the segment decoding system (403) comprises a plurality of segment decoders, each of which is connected to a corresponding segment of the plurality of segments. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 26 further comprising a serial interface configured to provide a segment data signal and the segment address signal to the segment decoding system (403). RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 29 wherein the segment decoding system (403) is configured to select a segment of the plurality of segments based on a value of the segment address signal and write a plurality of bits of the segment data signal to the selected segment. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 30 wherein the segment decoding system (403) is configured to write the plurality of bits of the segment data signal to the selected segment in a plurality of clock cycles over one or more wires of lesser number than the plurality of bits. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 29 , where the serial interface has a local serial peripheral interface (SPI). RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 26 wherein the one or more configurable circuits comprise a regeneration circuit, a latch, a tuning capacitor (92) and/or a tap buffer. RTWO (15, 30, 60, 70, 80, 400, 600, 1500) to Claim 26 , wherein the configuration data is configured to control a bias current, a resistance value, a capacitance value, and/or a transistor width of the one or more configurable circuits.

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