DE112017004644T5 - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- DE112017004644T5 DE112017004644T5 DE112017004644.0T DE112017004644T DE112017004644T5 DE 112017004644 T5 DE112017004644 T5 DE 112017004644T5 DE 112017004644 T DE112017004644 T DE 112017004644T DE 112017004644 T5 DE112017004644 T5 DE 112017004644T5
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor element
- unit
- molding
- sintered body
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000000034 method Methods 0.000 title description 5
- 238000000465 moulding Methods 0.000 claims abstract description 37
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052709 silver Inorganic materials 0.000 claims abstract description 16
- 239000004332 silver Substances 0.000 claims abstract description 14
- 230000000149 penetrating effect Effects 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 150000001875 compounds Chemical group 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000000956 alloy Substances 0.000 description 8
- 229910045601 alloy Inorganic materials 0.000 description 8
- 238000007747 plating Methods 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 4
- 238000006731 degradation reaction Methods 0.000 description 4
- 239000000843 powder Substances 0.000 description 4
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- BUHVIAUBTBOHAG-FOYDDCNASA-N (2r,3r,4s,5r)-2-[6-[[2-(3,5-dimethoxyphenyl)-2-(2-methylphenyl)ethyl]amino]purin-9-yl]-5-(hydroxymethyl)oxolane-3,4-diol Chemical compound COC1=CC(OC)=CC(C(CNC=2C=3N=CN(C=3N=CN=2)[C@H]2[C@@H]([C@H](O)[C@@H](CO)O2)O)C=2C(=CC=CC=2)C)=C1 BUHVIAUBTBOHAG-FOYDDCNASA-N 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8384—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
- Powder Metallurgy (AREA)
Abstract
Eine Halbleitervorrichtung weist auf: ein Halbleiterelement (1), das eine Fläche (1a) und eine andere Fläche (1b), die der einen Fläche (1a) gegenüberliegt, aufweist und eine Elektrode (2) auf der anderen Fläche (1b) aufweist; eine Anbringungseinheit (6), die eine elektrische Leitfähigkeit aufweist und so angeordnet ist, dass sie der Elektrode (2) gegenüberliegt; und eine Verbindungseinheit (3), die zwischen dem Halbleiterelement (1) und der Anbringungseinheit (6) angeordnet ist, um das Halbleiterelement (1) und die Anbringungseinheit (6) mechanisch und elektrisch zu verbinden. Die Verbindungseinheit (3) weist ein Formteil (4), das mit einer Vielzahl von Löchern (4b) geformt ist, die in einer Stapelrichtung des Halbleiterelements (1) und der Anbringungseinheit (6) durchdringen, und einen Silbersinterkörper (5), der in jedem der Vielzahl von Löchern (4b) angeordnet ist, auf. Das Halbleiterelement (1) und die Anbringungseinheit (6) sind durch den Silbersinterkörper (5) mechanisch verbunden. A semiconductor device comprises: a semiconductor element (1) having one surface (1a) and another surface (1b) facing the one surface (1a) and having an electrode (2) on the other surface (1b); an attachment unit (6) having an electrical conductivity and arranged to face the electrode (2); and a connection unit (3) disposed between the semiconductor element (1) and the attachment unit (6) for mechanically and electrically connecting the semiconductor element (1) and the attachment unit (6). The connection unit (3) has a molding (4) formed with a plurality of holes (4b) penetrating in a stacking direction of the semiconductor element (1) and the attachment unit (6), and a silver sintered body (5) formed in each of the plurality of holes (4b) is arranged on. The semiconductor element (1) and the attachment unit (6) are mechanically connected by the silver sintered body (5).
Description
QUERVERWEISE AUF VERWANDTE ANMELDUNGENCROSS-REFERENCES TO RELATED APPLICATIONS
Diese Anmeldung basiert auf der am 15. September 2016 eingereichten
TECHNISCHES GEBIETTECHNICAL AREA
Die vorliegende Erfindung betrifft eine Halbleitervorrichtung, bei der ein Halbleiterelement auf einer Anbringungseinheit durch eine Verbindungseinheit angebracht ist, und ein Verfahren zum Herstellen derselben.The present invention relates to a semiconductor device in which a semiconductor element is mounted on an attachment unit by a connection unit, and a method of manufacturing the same.
STAND DER TECHNIKSTATE OF THE ART
Im Stand der Technik wurde die folgende Halbleitervorrichtung als ein derartiger Typ einer Halbleitervorrichtung vorgeschlagen (siehe beispielsweise
Eine derartige Halbleitervorrichtung wird beispielsweise wie folgt hergestellt. Ein Pastenmaterial, das Ag-Partikel aufweist, wird auf der Anbringungseinheit platziert und das Halbleiterelement wird auf dem Pastenmaterial so angebracht, dass die Elektrode zur Anbringungseinheit gerichtet ist. Das Pastenmaterial wird dann gesintert, um einen Ag-Sinterkörper zu formen. Auf diese Weise wird die oben beschriebene Halbleitervorrichtung hergestellt.Such a semiconductor device is produced, for example, as follows. A paste material comprising Ag particles is placed on the mounting unit, and the semiconductor element is mounted on the paste material so that the electrode faces the mounting unit. The paste material is then sintered to form an Ag sintered body. In this way, the above-described semiconductor device is manufactured.
LITERATUR IM STAND DER TECHNIKLITERATURE IN THE PRIOR ART
PATENTLITERATURPatent Literature
Patentliteratur 1:
ZUSAMMENFASSUNG DER ERFINDUNGSUMMARY OF THE INVENTION
Während dem Sintern werden jedoch Hohlräume im Ag-Sinterkörper geformt. Falls die Hohlräume so verbunden sind, dass sie sich in einer ebenen Richtung der Anbringungseinheit ausdehnen, kann die Verbindungsstärke des Ag-Sinterkörpers verringert sein, was zu einem Brechen des Ag-Sinterkörpers führt. Das heißt, die Halbleitervorrichtung kann gebrochen bzw. defekt sein.However, voids are formed in the Ag sintered body during sintering. If the cavities are connected so as to expand in a planar direction of the attachment unit, the bonding strength of the Ag sintered body may be lowered, resulting in breakage of the Ag sintered body. That is, the semiconductor device may be broken.
Es ist Aufgabe der vorliegenden Erfindung, eine Halbleitervorrichtung, die imstande ist, das Brechen zu unterdrücken, und ein Verfahren zum Herstellen derselben bereitzustellen.It is an object of the present invention to provide a semiconductor device capable of suppressing breakage and a method of manufacturing the same.
Gemäß einem Aspekt der vorliegenden Erfindung weist eine Halbleitervorrichtung auf: ein Halbleiterelement, das eine Fläche und eine andere Fläche, die der einen Fläche gegenüberliegt, aufweist und mit einer Elektrode auf der anderen Fläche geformt ist; eine Anbringungseinheit, die eine elektrische Leitfähigkeit aufweist und so angeordnet ist, dass sie zu Elektrode gerichtet ist; und eine Verbindungseinheit, die zwischen dem Halbleiterelement und der Anbringungseinheit angeordnet ist und das Halbleiterelement und die Anbringungseinheit mechanisch und elektrisch verbindet. Die Verbindungseinheit weist ein Formteil, das mit einer Vielzahl von Löchern geformt ist, die in einer Stapelrichtung des Halbleiterelements und der Anbringungseinheit durch die Verbindungeinheit dringen, und einen Ag-Sinterkörper, der in jedem der Vielzahl von Löchern angeordnet ist, auf. Das Halbleiterelement und die Anbringungseinheit sind durch den Ag-Sinterkörper mechanisch verbunden.According to one aspect of the present invention, a semiconductor device comprises: a semiconductor element having one surface and another surface opposite to the one surface and formed with an electrode on the other surface; an attachment unit that has an electrical conductivity and is arranged so that it is directed to the electrode; and a connection unit disposed between the semiconductor element and the attachment unit and mechanically and electrically connecting the semiconductor element and the attachment unit. The connection unit includes a molding molded with a plurality of holes penetrating through the connection unit in a stacking direction of the semiconductor element and the attachment unit, and an Ag sintered body disposed in each of the plurality of holes. The semiconductor element and the mounting unit are mechanically connected by the Ag sintered body.
In einer derartigen Konfiguration beschränkt das Formteil die Hohlräume in den benachbarten Löchern, dass sie miteinander verbunden sind, sogar falls Hohlräume im Ag-Sinterkörper in den Löchern angeordnet sind. Dadurch ist es weniger wahrscheinlich, dass sich die Hohlräume entlang der ebenen Richtung der Anbringungseinheit ausdehnen. Dementsprechend ist es möglich, die Degradation bzw. die Abnahme der Verbindungsstärke der Verbindungseinheit und das Brechen der Halbleitervorrichtung zu unterdrücken.In such a configuration, the molding restricts the cavities in the adjacent holes to be bonded to each other even if voids are arranged in the Ag sintered body in the holes. As a result, the cavities are less likely to expand along the planar direction of the attachment unit. Accordingly, it is possible to suppress the degradation of the connection strength of the connection unit and the breakage of the semiconductor device.
Gemäß einem anderen Aspekt der vorliegenden Erfindung weist ein Verfahren zum Herstellen der oben beschriebenen Halbleitervorrichtung auf: Vorbereiten einer Verbindungseinheitsschicht durch Füllen eines Pastenmaterials, das Silberpulver aufweist, in die vorbereitete Vielzahl von Löchern des Formteils; Anbringen des Halbleiterelements auf der Anbringungseinheit durch die Verbindungseinheitsschicht, so dass die Elektrode des Halbleiterelements zur Anbringungseinheit gerichtet ist; und mechanisches Verbinden des Halbleiterelements und der Anbringungseinheit durch Formen des Sinterkörpers aus dem Pastenmaterial durch Erwärmen.According to another aspect of the present invention, a method of manufacturing the above-described semiconductor device comprises: preparing a compound unit layer by filling a paste material comprising silver powder into the prepared plurality of holes of the molding; Attaching the semiconductor element on the attachment unit through the connection unit layer such that the electrode of the semiconductor element faces the attachment unit; and mechanically bonding the semiconductor element and the mounting unit by forming the sintered body from the paste material by heating.
Bei einem derartigen Verfahren, sogar falls Hohlräume im Ag-Sinterkörper während des Formens des Ag-Sinterkörpers geformt werden, begrenzt das Formteil die Hohlräume in den benachbarten Löchern, dass sie miteinander verbunden sind. Es ist folglich möglich, die Halbleitervorrichtung herzustellen, in der ein Ausdehnen der Hohlräume in der ebenen Richtung der Anbringungseinheit unterdrückt wird. Das heißt, es ist möglich, die Halbleitervorrichtung herzustellen, die imstande ist, das Brechen aufgrund der Degradation der Verbindungsstärke der Verbindungseinheit zu unterdrücken.In such a method, even if voids are formed in the Ag sintered body during the molding of the Ag sintered body, the molding confines the cavities in the adjacent holes to be joined together. It is therefore possible to manufacture the semiconductor device in which expansion of the cavities in the planar direction of the mounting unit is suppressed. That is, it is possible to manufacture the semiconductor device capable of suppressing the breakage due to the degradation of the connection strength of the connection unit.
Figurenlistelist of figures
-
1 zeigt eine Querschnittsansicht einer Halbleitervorrichtung gemäß einer ersten Ausführungsform;1 shows a cross-sectional view of a semiconductor device according to a first embodiment; -
2 zeigt eine Ebenenansicht einer Verbindungseinheit, die in1 gezeigt ist;2 shows a plan view of a connection unit that in1 is shown; -
3A zeigt eine Querschnittsansicht, die einen Herstellungsvorgang der in1 gezeigten Halbleitervorrichtung zeigt;3A shows a cross-sectional view showing a manufacturing process of in1 shown semiconductor device; -
3B zeigt eine Querschnittsansicht, die einen Herstellungsvorgang der Halbleitervorrichtung nachfolgend zu3A zeigt;3B FIG. 12 is a cross-sectional view showing a manufacturing process of the semiconductor device below. FIG3A shows; -
3C zeigt eine Querschnittsansicht, die einen Herstellungsvorgang der Halbleitervorrichtung nachfolgend zu3B zeigt;3C FIG. 12 is a cross-sectional view showing a manufacturing process of the semiconductor device below. FIG3B shows; -
3D zeigt eine Querschnittsansicht, die einen Herstellungsvorgang der Halbleitervorrichtung nachfolgend zu3C zeigt;3D FIG. 12 is a cross-sectional view showing a manufacturing process of the semiconductor device below. FIG3C shows; -
4 zeigt eine Querschnittsansicht einer Umgebung der Verbindungseinheit in einem Fall, in dem die Verbindungseinheit nur aus einem Ag-Sinterkörper besteht;4 shows a cross-sectional view of an environment of the connection unit in a case where the connection unit consists only of an Ag sintered body; -
5 zeigt eine vergrößerte Ansicht einer Umgebung der Verbindungseinheit in3D ; und5 shows an enlarged view of an environment of the connection unit in3D ; and -
6 zeigt eine Ebenenansicht, die ein Formteil gemäß einer zweiten Ausführungsform zeigt.6 shows a plan view showing a molding according to a second embodiment.
BESCHREIBUNG DER AUSFÜHRUNGSFORMENDESCRIPTION OF THE EMBODIMENTS
Nachfolgend werden Ausführungsformen der vorliegenden Erfindung mit Bezug auf die Figuren beschrieben. In der folgenden Ausführungsformen wird denselben oder äquivalenten Teilen dasselbe Bezugszeichen zugewiesen.Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, the same or equivalent parts are given the same reference number.
(Erste Ausführungsform)First Embodiment
Eine erste Ausführungsform wird mit Bezug auf die Figuren beschrieben. Eine Halbleitervorrichtung einer vorliegenden Ausführungsform ist, wie in
Ein Halbleiterelement, das eine Fläche
Die Verbindungseinheit
Die Metallplatte
Der Ag-Sinterkörper
Die Anbringungseinheit
Die Distanz zwischen der Elektrode
Die Halbleitervorrichtung weist die Konfiguration, die vorhergebend beschrieben wurde, auf. Als nächstes wird ein Verfahren zum Herstellen der oben beschriebenen Halbleitervorrichtung beschrieben.The semiconductor device has the configuration described above. Next, a method of manufacturing the above-described semiconductor device will be described.
Als erstes wird die Metallplatte
Das Pastenmaterial
In einem Schritt, der zu den in den
Nachfolgend wird die Struktur, die in dem Vorgang bis zum Schritt von
Nachfolgend wird ein interner Zustand des Ag-Sinterkörpers
Da das Ag-Pulver kornförmig wächst, während es diffundiert wird, tendiert das Ag-Pulver, wie in
In der vorliegenden Ausführungsform weist die Verbindungseinheit
In der vorliegenden Ausführungsform weist die Verbindungseinheit
Die Verbindungseinheit
Das Formteil
(Zweite Ausführungsform)Second Embodiment
Eine zweite Ausführungsform wird beschrieben. In der vorliegenden Ausführungsform wird die Konfiguration des Formteils
In der vorliegenden Ausführungsform ist das Formteil
In ähnlicher Weise zur Metallplatte
Sogar falls das Formteil
(Andere Ausführungsformen)Other Embodiments
Während die vorliegende Erfindung mit Bezug auf Ausführungsformen davon beschrieben wurde, ist es zu verstehen, dass der Offenbarungsgehalt nicht auf die Ausführungsformen und Konstruktionen begrenzt ist. Die vorliegende Erfindung ist dafür vorgesehene, verschiedene Modifikationen und äquivalent Anordnungen abzudecken. Zusätzlich sind die verschiedenen Kombinationen und Konfigurationen, andere Kombinationen und Konfigurationen, die mehr, weniger oder nur eine einziges Element aufweisen, auch im Geist und Umfang der vorliegenden Erfindung enthalten.While the present invention has been described with respect to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and constructions. The present invention is intended to cover various modifications and equivalent arrangements. In addition, the various combinations and configurations, other combinations and configurations having more, less or only a single element are also included within the spirit and scope of the present invention.
In der ersten Ausführungsform kann beispielsweise ein Plattierfilm auf der Metallplatte
ZITATE ENTHALTEN IN DER BESCHREIBUNG QUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- JP 2016180612 [0001]JP 2016180612 [0001]
- JP 2010171271 A [0003, 0005]JP 2010171271 A [0003, 0005]
Claims (6)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016-180612 | 2016-09-15 | ||
JP2016180612A JP6737099B2 (en) | 2016-09-15 | 2016-09-15 | Method of manufacturing semiconductor device |
PCT/JP2017/032336 WO2018051896A1 (en) | 2016-09-15 | 2017-09-07 | Semiconductor device, and method for manufacturing same |
Publications (2)
Publication Number | Publication Date |
---|---|
DE112017004644T5 true DE112017004644T5 (en) | 2019-06-13 |
DE112017004644B4 DE112017004644B4 (en) | 2023-03-09 |
Family
ID=61618743
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE112017004644.0T Active DE112017004644B4 (en) | 2016-09-15 | 2017-09-07 | Semiconductor device and method of manufacturing the same |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP6737099B2 (en) |
CN (1) | CN109716493B (en) |
DE (1) | DE112017004644B4 (en) |
WO (1) | WO2018051896A1 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171271A (en) | 2009-01-23 | 2010-08-05 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
JP2016180612A (en) | 2015-03-23 | 2016-10-13 | セイコーエプソン株式会社 | Vibration device, electronic apparatus, and mobile body |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5032957U (en) * | 1973-07-20 | 1975-04-10 | ||
JPS5074278U (en) * | 1973-11-09 | 1975-06-28 | ||
JP2006202586A (en) * | 2005-01-20 | 2006-08-03 | Nissan Motor Co Ltd | Bonding method and bonding structure |
JP2008112955A (en) * | 2006-10-06 | 2008-05-15 | Toyota Industries Corp | Semiconductor device, metal bonding material, soldering method, and manufacturing method of electronic apparatus |
JP5493323B2 (en) * | 2008-09-30 | 2014-05-14 | 凸版印刷株式会社 | Manufacturing method of lead frame type substrate |
JP2010118575A (en) * | 2008-11-14 | 2010-05-27 | Nec Electronics Corp | Semiconductor device and method of manufacturing the same |
DE102009000192A1 (en) * | 2009-01-14 | 2010-07-15 | Robert Bosch Gmbh | Sintered material, sintered compound and method for producing a sintered compound |
JP5178759B2 (en) * | 2010-03-12 | 2013-04-10 | 三菱電機株式会社 | Semiconductor device |
JP2011238779A (en) * | 2010-05-11 | 2011-11-24 | Mitsubishi Electric Corp | Conductive joint structure, semiconductor device using same, and method of manufacturing semiconductor device |
CN202749376U (en) * | 2012-08-16 | 2013-02-20 | 西安黄河光伏科技股份有限公司 | Back-passivation solar cell |
JP2014180690A (en) * | 2013-03-19 | 2014-09-29 | Nippon Steel Sumikin Materials Co Ltd | Sheet-like high-temperature solder joint material, and die bonding method using the same |
JP6486369B2 (en) | 2013-09-05 | 2019-03-20 | ヘンケル アイピー アンド ホールディング ゲゼルシャフト ミット ベシュレンクテル ハフツング | Sintered metal film composition |
US9099567B2 (en) * | 2013-11-25 | 2015-08-04 | Freescale Semiconductor, Inc. | Packaged semiconductor devices and methods of their fabrication |
-
2016
- 2016-09-15 JP JP2016180612A patent/JP6737099B2/en active Active
-
2017
- 2017-09-07 DE DE112017004644.0T patent/DE112017004644B4/en active Active
- 2017-09-07 CN CN201780056158.2A patent/CN109716493B/en active Active
- 2017-09-07 WO PCT/JP2017/032336 patent/WO2018051896A1/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010171271A (en) | 2009-01-23 | 2010-08-05 | Renesas Technology Corp | Semiconductor device and method of manufacturing the same |
JP2016180612A (en) | 2015-03-23 | 2016-10-13 | セイコーエプソン株式会社 | Vibration device, electronic apparatus, and mobile body |
Also Published As
Publication number | Publication date |
---|---|
DE112017004644B4 (en) | 2023-03-09 |
WO2018051896A1 (en) | 2018-03-22 |
JP2018046186A (en) | 2018-03-22 |
JP6737099B2 (en) | 2020-08-05 |
CN109716493B (en) | 2023-04-04 |
CN109716493A (en) | 2019-05-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3204231C2 (en) | Laminate with a metal-fiber composite material and its use | |
DE2142146C3 (en) | Method for the simultaneous production of several semiconductor components | |
DE102014104399B4 (en) | Semiconductor chip package comprising a leadframe | |
DE112014005600T5 (en) | Metal part, metal part surface processing method, semiconductor device, semiconductor device manufacturing method and composite molded article | |
DE102009061178B3 (en) | Power semiconductor device | |
DE3913221A1 (en) | SEMICONDUCTOR ARRANGEMENT | |
DE102009032973A1 (en) | Power semiconductor device | |
DE102019212672A1 (en) | COIL COMPONENT | |
DE102018206482B4 (en) | Semiconductor component with a composite clip made of composite material | |
DE112016006376B4 (en) | Semiconductor device | |
DE2840308A1 (en) | CONTACT ELEMENT FOR A CONNECTING DEVICE | |
DE112016007464T5 (en) | Semiconductor device | |
DE112017007890B4 (en) | Semiconductor device, high-frequency power amplifier and method of manufacturing a semiconductor device | |
DE102017212186B4 (en) | Power semiconductor device sealed with cast resin | |
DE2454605C2 (en) | Semiconductor component | |
DE3406420A1 (en) | SEMICONDUCTOR POWER DEVICE WITH MULTIPLE PARALLEL SWITCHED, SAME ELEMENTS | |
DE102018130147A1 (en) | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE | |
DE2252833A1 (en) | COMPOSITE SEMI-CONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | |
DE112017004644B4 (en) | Semiconductor device and method of manufacturing the same | |
DE68923056T2 (en) | Semiconductor device with short-circuited anode and method for its production. | |
DE212018000086U1 (en) | Semiconductor device | |
DE112021005639T5 (en) | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE | |
EP1794787B1 (en) | Lead frame for an electronic component and method for the production thereof | |
DE112020006695T5 (en) | Semiconductor device and manufacturing method of a semiconductor device | |
DE102020120481A1 (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R012 | Request for examination validly filed | ||
R016 | Response to examination communication | ||
R018 | Grant decision by examination section/examining division | ||
R020 | Patent grant now final |