DE112017001027T5 - Page troubleshooting - Google Patents

Abstract

An indication of page size may be encoded into an unused and reserved field in an effective or virtual address for use by a software page fault handler when a page fault associated with the effective or virtual address is treated to be applied to an application allow an operating system or other software-based translation functionality to communicate page size preferences for the allocation of main memory pages and / or speed up the search for page table entries in a hardware page table.

Description

BACKGROUND

The invention relates generally to computer and computer software, and more particularly to main memory address translation.

Main memory management, that is, the operations that take place in managing the data stored in a computer, is often a key factor in the overall performance of the system for a computer. Among other things, main memory management monitors the retrieval and storage of data on a computer and also manages certain security tasks for a computer by imposing restrictions on what users and computer programs may access.

Modern computers are typically based on a main memory management technique called virtual memory management, to increase performance and allow greater flexibility in computers and the underlying architectural designs on which they are based.

In a virtual memory system, the underlying hardware that implements the main memory system of a computer is virtually invisible to the computer's software. A relatively large virtual memory area, e.g. with a width of 64 bits or more is specified for such a computer, wherein computer programs executing on the computer access the main memory system by means of virtual addresses pointing to memory locations in the main memory virtual area. However, the physical main storage units in the computer are accessed via "real" addresses which are mapped directly to specific main storage locations in the main physical storage units. Hardware and / or software in the computer are provided to perform an "address translation" to map the real main memory addresses of the physical memory into virtual addresses in the main memory virtual area. Thus, whenever a computer program on a computer attempts to access main storage by means of a virtual address, the computer automatically translates the virtual address to a corresponding physical address so that access can be made to the appropriate storage location in the corresponding physical unit which virtual address is assigned.

A feature of virtual addressing is that a computer need not contain memory for the entire virtual memory area in the main physical memory units in the main memory of the computer. Rather, lower storage levels such as disk drives and other mass storage units may be used as overhead storage, with main storage addresses grouped together into "pages" that are offloaded and reinserted as needed between the main storage and the auxiliary storage.

In addition, some computer architectures also incorporate the concept of segmentation, which divides virtual memory into different segments (each segment being allocated blocks by pages) to simplify main memory protection, simplify the handling of large and growing data structures, and otherwise, to allow greater flexibility to perform main memory management when multiple processes can run on a computer at a given time. When segmentation is used, an additional level of dereferencing is used, necessitating additional implementation. In systems that include segmentation and page paging, computer programs typically access the main memory system through "effective" addresses mapped to virtual addresses, thus first translating from an effective to a virtual address and then a virtual address a real address is required.

Because of the frequency of access requests in a computer, address translation can have a significant impact on the overall performance of the system. Thus, it is desirable to minimize the processing overhead associated with the critical timing path within which the address translation is performed.

Address translation in a main memory virtual system typically involves access to various address translation data structures. Such a structure, referred to as a page table, contains several entries which map virtual addresses to real addresses one page at a time. As well For example, in order to perform the segmentation, a segment table is often provided which contains entries which map effective addresses segment by segment to virtual addresses.

Due to the large number of main memory accesses that are constantly taking place in a computer, the number of entries necessary to map the entire main memory address space used by a computer can be significant, requiring that the entries be in main memory and not stored in dedicated memory, making access to these entries prohibitively slow. To speed address translation in such a scheme, high-speed memories called the translation lookaside buffers (TLBs) and the segment lookaside buffers (SLBs) are commonly used to cache most recently used entries for quick access by the computer , If a required entry is not stored in a TLB or SLB, this results in a performance penalty when loading the entry from main memory; Usually, however, the hit rate in TLBs and SLBs is extremely high and the penalty associated with loading entries from main memory is more than offset by the performance gains when entries can be accessed directly from the TLB and SLB.

In still other architectures, an additional level of caching may be used to further speed performance by providing an ERAT table for the conversion from effective to real addresses containing entries that allow direct mappings between effective and real addresses. Thus, an ERAT table contains practically information from the SLB as well as the TLB to make the implementation of two stages of implementation superfluous. In some architectures, separate data and instruction ERAT tables are provided in close proximity to the instruction and data processing logic in a processor to minimize the effects of address translation on the critical power paths in the processor.

Originally, paging was based on fixed page sizes, e.g. 4K or 4096 addressable memory locations per page. However, when using the segmentation, different page sizes in different segments can be supported. Smaller page sizes are often optimal for efficient use of a main memory system, especially when many processes are running simultaneously in a computer. However, as the memory requirements of computers and the programs running on them continue to increase, so does the number of main memory pages needed by a particular process or program, and consequently, larger page sizes can be more efficient for many situations.

In many architectures, large pages, i. Pages that are larger than 4K pages can be assigned at the time of booting. To avoid this need for pre-allocation, some operating systems implement "transparent" huge pages, trying to collate sequential pages and translate into a large page. In general, however, an operating system is unaware of the ability to map large pages, and by default assigns 4K pages.

SUMMARY

In accordance with one embodiment of the present invention, a page fault in a data processing system of a type supporting multiple main memory page sizes may be handled by detecting a page fault generated by a processor's hardware translation logic associated with a virtual address requested by program code For example, in response to the virtual address being addressed by the processor, an indication of the page size encoded in an unused and reserved virtual address field is determined and, using the established page size indication, a software address translation operation for the virtual address is performed.

According to another embodiment of the present invention, a program may be created by encoding an indication of the page size into an unused and reserved field of a virtual address referenced by a main memory access instruction and constructing the program with the main memory access instruction such that: after a page fault caused by the main memory access instruction has been detected by hardware translation logic of a data processing system on which the program is executed, the pointer to the page size is used in performing the software address translation operation.

These and other advantages and features which characterize the invention are set forth in the claims appended hereto and form a further part hereof. However, in order that the invention and the advantages and objectives attained by its use may be better understood, reference should be made to the drawings and the accompanying description, in which exemplary embodiments of the invention are shown.

list of figures

• die 1A und 1B Blockschaubilder einer beispielhaften Hardware- (1A) und Software-Umgebung (1B) gemäß den verschiedenen hierin beschriebenen Techniken sind;
• 2 ein Blockschaubild ist, das beispielhafte Hardware- und Software-Entitäten zeigt, die verwendet werden können, um eine Adressumsetzung in der Umgebung der 1A bis 1B durchzuführen;
• 3 ein Blockschaubild eines beispielhaften Formats einer effektiven Adresse ist, das in der Umgebung der 1A bis 1B verwendet werden kann;
• 4 ein Ablaufplan ist, der eine beispielhafte Abfolge von Operationen zur Behandlung eines Seitenfehlers in der Umgebung der 1A bis 1B zeigt;
• 5 ein Ablaufplan ist, der eine beispielhafte Abfolge von Operationen zur Durchführung der Suche nach dem in 4 referenzierten PTE-Block zeigt;
• 6 ein Ablaufplan ist, der eine beispielhafte Abfolge von Operationen zur Erstellung eines Programms in der Umgebung der 1A bis 1B zeigt.

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

• the 1A and 1B Block Diagrams of an Exemplary Hardware ( 1A) and software environment ( 1B) according to the various techniques described herein;
• 2 FIG. 12 is a block diagram showing exemplary hardware and software entities that may be used to implement address translation in the environment of 1A to 1B perform;
• 3 is a block diagram of an exemplary format of an effective address that is in the environment of 1A to 1B can be used;
• 4 FIG. 5 is a flowchart depicting an example sequence of operations for handling a page fault in the environment of 1A to 1B shows;
• 5 is a flowchart illustrating an exemplary sequence of operations for performing the search for the in 4 referenced PTE block shows;
• 6 is a flowchart illustrating an exemplary sequence of operations for creating a program in the environment of 1A to 1B shows.

DETAILED DESCRIPTION

Referring now to the drawings, in which like reference numerals designate like parts throughout the several views, FIGS 1A to 1B the most important hardware and software components in a computing environment or device 100 consistent with the invention and capable of performing main memory address translation in various cloud and / or non-cloud computing environments. As in 1A shown, the device can 100 a data processing system 102 containing multiple nodes, where the physical hardware on a variety of physical processor nodes 104 is distributed in a variety of hosts or computer systems 106 are arranged, with the hosts 106 in one or more pools 108 are arranged. Every processor node 104 contains one or more processors 110 , one or more main storage units 112 and in some embodiments additional hardware such as input / output / I / O) hardware 114 (eg, one or more input / output (I / O) adapters) and / or network hardware 116 , Suitable network functionality (not shown) may also be used to facilitate data transfer between the various processor nodes 104 and hosts 106 and other external systems.

The device 100 can be implemented using any of a variety of architectures suitable for realizing a virtualized environment, as well as various architectures suitable for non-virtualized environments, including both multi-user and single-user environments, and embedded environments. Consequently, the device can 100 also represent various desktop computers, supercomputers, servers, laptop computers, tablet computers, mobile devices and other programmable electronic devices and so on.

Every processor 110 can be implemented as a single thread or multithread processor and / or as a single or multi-core processor, while each main memory 112 may be construed as a main memory, which may include one or more levels of storage devices, eg, a DRAM-based main memory, and one or more levels of data, instruction, and / or combination cache memories, with certain caches serving either single processors or multiple processors as is well known in the art. Moreover, the main memory of the device 100 as a main memory, the main memory which physically resides elsewhere in the device 100 For example, it may contain any cache memory in a processor as well as any storage capacity used as a virtual memory, such as on a mass storage device or on another computer connected to the device 100 connected is stored.

The device 100 is operated by one or more kernels, hypervisors, operating systems, etc., and executes various computer software applications, components, programs, objects, modules, data structures, etc. or otherwise relies upon various computer software applications, components, programs, objects, modules, Data structures, etc., as described in more detail below. In addition, various applications, components, programs, objects, modules, etc., may also be executed on one or more processors in another computer that communicates with the device over a network, eg, in a distributed or client-server computing environment 100 wherein the processing required to perform the functions of a computer program can be assigned to multiple computers via a network.

For example, shows 1B different software components 118 to 132 who are in a host 106 in the device 100 can be located. A hypervisor or virtual machine monitor (VMM) 118 can have one or more virtual machines (VMs) 120 host and every virtual machine 120 a portion of the physical hardware resources of the host 106 (For example, processor, memory, and / or I / O resources related to one or more processor nodes 104 belonging to one or more virtual processors (VPs) 122 , a virtual memory (VMem) 124, and virtual input / output (VIO) resources 126. Every virtual machine 120 can turn an operating system 128 and optionally middleware 130 and one or more jobs and / or applications 132 host. It should be understood that every virtual machine 120 , which may also be referred to as a logical partition, virtual server or virtual machine, may be operated in a manner that emulates a separate physical computer and thus can host virtually all software components that can be hosted by a computer.

Additional hardware and / or software components may also be present in the device 100 For example, mass storage hardware, external input / output devices such as printers or monitors, as well as management hardware and / or software, such as a hardware management console (HMC), through which the hardware and / or software configuration of the device are managed by an administrator can. Furthermore, in the embodiments shown, the possibility of connecting to one or more external networks 134 as well as the possibility to connect to one or more storage systems 136 over one or more storage fabrics 138 , Virtualized environments can be implemented in a number of ways and include myriad hardware and / or software variants, and thus the invention is not limited to the particular implementation disclosed herein.

It should be understood that the present invention may be a system, a method, and / or a computer program product. The computer program product may include computer readable storage media (or media) having computer readable program instructions stored thereon for causing one or more processors to perform aspects of the present invention.

The computer-readable storage medium may be a physical entity that can retain and store instructions for use by a system for executing instructions. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of the computer readable storage medium include the following: a portable computer diskette, a hard disk, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM) Flash memory), a static random access memory (SRAM), a portable compact disk read only memory (CD-ROM), a DVD (digital versatile disc), a memory stick, a floppy disk, a mechanically coded unit such as for example, punched cards or raised structures in a groove on which instructions are stored, and any suitable combination thereof. A computer-readable storage medium is not to be construed as a transitory signal per se herein, such as radio waves or other free-propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (eg, through a fiber optic cable) guided light pulses) or electrical signals transmitted by a wire.

Computer readable program instructions described herein may be transferred from a computer readable storage medium to respective computing / processing units or over a network such as the Internet, a local area network, a wide area network, and / or a wireless network to an external computer or computer external storage unit downloaded become. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each data processing unit receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the corresponding data processing unit.

Computer readable program instructions for performing operations of the present invention may include assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, stateful data, or either source code or object code which are written in any combination of one or more programming languages, including object-oriented programming languages such as Java, Smalltalk, C ++, etc. as well as conventional procedural programming languages such as the programming language "C" or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g. Internet using an Internet service provider). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), or programmable logic arrays (PLA), may execute the computer readable program instructions by providing state information of the programmer use computer readable program instructions to personalize the electronic circuits to perform aspects of the present invention.

Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be appreciated that each block of the flowcharts and / or block diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams, may be executed by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, a special purpose computer, or other programmable data processing device to generate a machine such that the instructions executed via the processor of the computer or other programmable data processing device comprise means for implementing the functions described in U.S. Pat generate the blocks or blocks of the flowcharts and / or block diagrams or graphs defined functions / steps. These computer readable program instructions may also be stored on a computer readable storage medium that may control a computer, programmable computing device, and / or other devices to function in a particular manner such that the computer readable storage medium on which instructions are stored has a manufacturing product, including instructions which implement aspects of the function / step specified in the block (s) of the schedule and / or the block diagrams.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing device or other device to cause a number of process steps to be performed on the computer or other programmable device or other device to be run on a computer to execute the executed process so that the instructions executed on the computer, other programmable device, or other device implement the functions / steps specified in the block or blocks of the flowcharts and / or the block diagrams.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions that may contain one or more executable instructions Execution of the specific logical function (s). In some alternative embodiments, the functions indicated in the block may take place in a different order than shown in the figures. For example, two blocks shown in succession may in fact be performed substantially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. It should also be noted that each block of block diagrams and / or schedules, as well as combinations of blocks in the block diagrams and / or schedules, may be implemented by special hardware based systems that perform the designated functions or steps , or perform combinations of specialized hardware and computer instructions.

Further, computer readable program instructions, one or more of which may be collectively referred to herein as "program code," may be provided herein based on the application in which such instructions are executed in a particular embodiment of the invention. It should be understood, however, that any particular program nomenclature that arises is used for convenience only, and thus the invention should not be construed as a sole use in any particular application specified by and / or by this nomenclature Nomenclature is tacitly assumed to be limited. Given the typically endless number of ways in which computer programs can be organized into routines, procedures, methods, modules, objects, and the like, as well as the various ways in which program functionality can be divided among different software layers resulting in a typical Computers (eg, operating systems, libraries, application programming interfaces (APIs), applications, applets, etc.), it should be understood that the invention is not limited to the particular organization and distribution described herein.

The expert recognizes that in the 1A and 1B exemplary environment shown is not intended to limit the present invention. In fact, those skilled in the art will recognize that other alternative hardware and / or software environments may be used without departing from the scope of the invention.

Embedded note on page size for page fault recovery

Address translation is supported by most modern data processing systems and is generally based on both hardware and software to handle translation between virtual and real memory. 2 For example, address translation functionality in an exemplary data processing system 200 , In this data processing system, multiple page sizes as well as the segmentation are supported, so that a two-stage conversion is performed, ie, first from an effective address to a virtual address and then from a virtual address to a real address. It should be understood, however, that the invention is not limited to a two-stage implementation and can be practiced in various environments in which addresses are translated between virtual and real address spaces. For this reason, the following description refers to the addresses which are referenced by program instructions and translated in terms of "virtual addresses" into addresses in a real address space.

Such as in 2 may be a main memory access request, such as an attempt to read from a virtual memory address or to write to a virtual memory address, or a request for the allocation of main memory first of hardware conversion logic in a processor 202 , eg, an Effective-to-Real Address Translation (ERAT) unit 208, which in some embodiments may be implemented by means of separate data-specific and instruction-specific units (DATs and iERATs). If on the ERAT 208 If there is a hit, the address translation in the processor can 202 be performed; however, if a miss occurs, the main memory access request is typically directed to a memory controller or memory management unit (MMU). 204 forwarded to the same or a different chip than the processor 202 can be located. The MMU 204 can process the request using hardware translation logic that includes one or more address translation buffers (TLBs) and / or segment translation buffers (SLBs). 210 contains. In response to a hit on the TLB and / or SLB 210 can the main memory access request in the MMU 210 are processed; however, if a miss occurs, the software becomes 206 For example, an operating system (OS), hypervisor, virtual machine monitor, kernel, or other low-level software in a data processing system, generally reported a page fault to access various software data structures that are collectively known as hardware page tables , HPTs) 212 to access and thus correct the page fault.

It should be understood that each ERAT 208 , SLB / TLB 210 and HPT 212 may contain at least address translation data that make an association between two different addresses, eg between a virtual or effective address and a real address. In some embodiments, this address translation data may be implemented as a page table entry (PTE) and so designated. It should be understood, however, that PTEs may include additional information, such as protection data that limits access to certain processes or types of processes or to certain types of access (eg, read-only access), status data such as valid / Invalid indicator or a dirty indicator, tracking data such as a counter or LRU indicator, page size data, etc. While the PTEs of each ERAT 208 , SLB / TLB 210 and HPT 212 In some embodiments, the PTEs may also be similarly configured at different levels of the main memory hierarchy and contain different, additional or less data than at other levels, such that references to a PTE or virtual / effective address between different ones Layers of a main memory hierarchy are passed on, a change of data, an addition to additional data and / or a discard of data belonging to a PTE or a virtual / effective address in connection with the formatting of the PTE or virtual / effective address Format suitable for the particular data structure realized at this level of the hierarchy.

It should be understood that in various embodiments of the invention, a wide variety of address translation implementations may be used, and thus the invention is not limited to the implementation of 2 is limited. For example, in non-uniform memory access (NUMA) environments, multi-core environments and other environments, address translation logic and / or functionality may be redistributed throughout an entire data processing system and various combinations of data structures, buffers, tables, etc. may be used. to hold address translation data or PTEs for use by the address translation functionality of a data processing system in accordance with the invention. The HPT 212 For example, in some embodiments, in an attempt to minimize the latency associated with address translation operations that do not hit the hardware translation logic, multiple tables, multi-level tables, nested tables, virtualized tables may be implemented. It should also be understood that in some embodiments, the latency associated with performing address translation operations may be due to the need to potentially access multiple data structures and the potential need to retrieve these data structures from the slower main memory or even mass or persistent memory to be able to be different.

It should also be understood that various page sizes may be supported in various embodiments of the invention. In general, pages that exceed a standard size (e.g., 4K or 4096 bytes in some embodiments) may be referred to as large or giant pages. For example, large pages may be useful in some types of workloads, such as when a program contains a relatively large amount of contiguous data and / or instructions and / or when large and large blocks of data are accessed frequently and / or repeatedly. In contrast, smaller page sizes on other workloads, e.g. Workloads where main memory accesses are more distributed and random may perform better.

In some conventional approaches, pages that exceed a standard size must be allocated at the time of boot, while in other conventional approaches pre-allocation can be avoided through the use of "transparent" giant pages, with an operating system or similar software attempting sequential pages to put together and implement in a large or huge page. In general, however, conditions that are particularly suited to the use of large or giant pages are not known to the operating system, so the ability of operating systems and other software-based address translation logic to intelligently map different sizes of pages accounts for different types of workloads or scenarios to wear, is usually limited.

However, embodiments consistent with the invention may be used to optimize the allocation of main memory and the handling of page faults in a data processing system by providing page size information to an operating system, hypervisor / VM manager, or other software executed page fault handling logic in a data processing system become. The pointers to the page size may be, for example, virtual addresses requested by program code instructions in a program executed in such a data processing system, and more particularly in reserved and / or unused virtual address fields be embedded. The page size indications may then be read by software executed page fault handling logic to control the page size associated with a main memory access request and / or to optimize the search for address translation data from one or more hardware page tables due to a main memory request.

For example, in embodiments consistent with the invention, a page fault generated by a processor's hardware translation logic may be recognized by a software page fault handler, a page size indication encoded into an unused and reserved virtual address field may be detected, and then a software address translation operation may be performed the virtual address is made using the noted page size indication. As will become more apparent below, in some embodiments, an indication of the page size from an executing program may be seamlessly transferred to a software page fault handler to expedite main memory allocations and / or address translations by increasing the latency, the associated with the access to data structures such as hardware page tables and the like is partially reduced.

In this regard, hardware translation logic may be construed to include various types of hardware implemented address translation functionality, e.g. in a processor, processor core, memory controller, main memory management unit, cache controller, etc., and may include various data structures such as ERATs, SLBs, TLBs, or the like. Similarly, a software page fault handler may be considered to include various types of software implemented address translation functionality, e.g. may be implemented in an operating system, kernel, hypervisor, virtual machine monitor, or other low-level software to access various types of translation data structures, including various types of page tables.

A software page fault handler may, in some embodiments, be configured to implement various types of software address translation operation. One type of software address translation operation that may be performed is a search for a page table entry or other address translation data for use in performing an address translation from a virtual address to a physical address. Another type of software address translation operation that can be performed is the allocation of a new main memory page, e.g., based on the determination that a requested virtual address has not yet been mapped to a real address and no main memory page has yet been allocated for that virtual address. Additional software address translation operations may include various management operations, such as changing main memory pages or de-allocating main memory pages, dumping main memory pages to and from main memory, and so on.

If we now 3 turn to is at 220 an exemplary format of an effective or virtual address that is suitable for use in connection with the transmission of pointers to the page size. Specifically, the format represents 220 is any of several typical address formats that may be used in conjunction with some embodiments of the invention that include an offset field 222 which represents an offset into a main memory page corresponding to the effective or virtual address, as well as an index and tag field 224 and 226 contains, which together represent a unique identifier for a virtual page. The index field 224 for example, it can be used to address a data structure that contains PTEs, where the tag field 226 is used to distinguish the indexed page from other pages mapped to the same index. In some embodiments, the tag field 226 be omitted because the index field 224 sufficient to address the page in a data structure.

The format 220 can optionally also have one or more flags 228 which provide information such as status information, access control information, or other information, as understood by those skilled in the art having the current disclosure.

The format 220 can also be a reserved field 230 include one or more bits that are not used and reserved. Unused and reserved in the context of the invention refers to a field in a virtual or effective address that is expressly reserved by the system for future use and that is not used for address translation purposes or otherwise for addressing a memory location in main memory. It is therefore in the reserved field 230 where an indication of page size may be encoded in embodiments consistent with the invention.

As an exemplary implementation, in the case of a 64-bit radix conversion, as implemented, for example, in the Power8 architecture, 10 bits (eg, the bits 2 to 11 , Big Endian, or the bits 61 to 52 , Little Endian) reserved by the architecture and not used for the purpose of address translation or otherwise for the purpose of referencing main memory. In an exemplary embodiment, one or more bits of this field may be used to provide page size indications, as shown in Table I below. Table I: Encoding hints on page size Nesting mask bits of the translation page size: 0x3100000000000000 # Mask bits to know the page size of an address Verschachtle off-mask bit of implementation: 0x0000000000000000 # 4K page assignment Verschachtle 4K mask bit of implementation: 0x0800000000000000 # 64 K page assignment Verschachtle 64K mask bit of implementation: 0x1000000000000000 # 2MB page assignment. In the case of hash, this means that we are MPSS 4K / 64K. Verschachtle 16MB mask bit of implementation: 0x1100000000000000 # 16MB page assignment Verschachtle off-mask bit of implementation: 0x2000000000000000 # 16GB page assignment Verschachtle off-mask bit of implementation: 0x2100000000000000 # Reserved for future encodings Verschachtle off-mask bit of implementation: 0x300000000000000 # Reserved for future encodings Verschachtle off-mask bit of implementation: 0x310000000000000 # Reserved for future encodings

In the above coding, an effective address may become a convention for compilers, linkers, and applications to make a request for translation to an operating system or other software-based address translation functionality. Further, in some embodiments, this encoding may be incorporated into a header file and changed for new compilations of an operating system, compiler, bind loader, and / or application.

It should be understood that non-zero values in the reserved field 230 in some embodiments, may result in acknowledgment of an invalid address condition by a memory controller or other hardware translation logic. Conventionally, such a condition generally results in an operating system terminating an application or device driver. However, in some embodiments, this condition may be detected and used to provide an indication of page size for the purpose of address translation. In some embodiments, the hardware translation logic may also include a configurable mode that may be enabled or disabled to prevent the condition from being reported (ie, such that the hardware translation logic simply ignores the non-zero bits). Consequently, the mode of hardware translation logic may be set accordingly using page size hints.

If we now 4 Turning to this figure shows a sequence of operations 250 for a software page fault handler that implements software executed page fault handling logic that includes support for page size indications in a manner consistent with the invention. This sequence of operations may be started, for example, due to the acknowledgment of a page fault by hardware conversion logic, and performed in an operating system, hypervisor, virtual machine monitor, kernel, or other low-level software. Moreover, the sequence leads 250 automatically allocating new main memory pages due to page faults associated with effective addresses that have not yet been allocated, although it should be understood that in other embodiments, the main memory allocation may be made separate from the page fault handling.

The sequence 250 is passed with a virtual address, eg an effective address, and starts in the block 252 by searching for a matching page table entry in one or more data structures that implement the hardware page table for the environment. For the moment, return the operations associated with finding a matching page table entry (discussed below in connection with 5 the controller next switches to the block 254 where it is determined if a matching page table entry was found. If so, the controller switches to the block 256 to use the found page table entry to respond to the page fault in a manner that will be apparent to those skilled in the art having the current disclosure. However, if none is found, the block passes 254 the controller to the block 258 to access one or more of the reserved bits of the effective address to determine if an indication of page size has been encoded into the effective address, eg, by applying a mask and determining if any of the unmasked bits are non-zero values to have. If the unmasked bits are all zero, the block passes 260 the controller to the block 262 to map a new main memory page that has a default main memory page size to the effective address, since no indication of page size is encoded in the effective address. The assignment of a new main memory page can include both reserving a main memory page for the process by creating a new page table entry for the main memory page, and offloading and restoring that page into main memory or other operations or combinations of operations, that are obvious to those skilled in the art having the current disclosure. In particular, in the case of hardware page tables that contain multiple page size specific data structures that correspond to different page sizes, creating a new page table entry may involve creating the new page table entry in a data structure that is specific to the default page size.

If the block 260 On the other hand, if it detects that a non-zero value is stored in the non-masked bits of the effective address, an indication of the page size in the effective address is encoded and control goes to the block 264 to determine if the requested memory page size of the page size indication is allowed. For example, the requested memory page size may be denied if the requested amount of memory is unavailable. If it is not allowed, the controller will switch to the block 262 to assign the default page size; however, if allowed, the controller will switch to the block instead 266 to map a new main memory page with the requested page size specified by the page size hint. For example, in the case where different data structures hold page table entries that belong to different page sizes, a new page table entry may be created for the new main memory page in the data structure specific to the page size specified by the page size hint. After execution of any of the blocks 256 . 262 or 266 the page fault is treated as and the sequence 250 is closed.

Thus, in the sequence 250 a page size indication encoded in an effective address is used to create a new page table entry and allocate a new main memory page based on the page size specified by the page size indication. However, in some embodiments, an indication of the page size may be used to speed up and / or simplify the handling of a page fault for a main memory page that has already been allocated. 5 For example, FIG. 10 shows an exemplary sequence of operations for performing a search for the PTE block 252 from 4 , It should be understood that a similar sequence of operations may also be used in implementations where the main memory allocation is made separately from the page fault handling.

First, in the block 280 accessing one or more of the reserved bits of the effective address input to the page fault handler to determine if an indication of page size has been encoded into the effective address, eg, by applying a mask and determining if any of the non-masked bits have nonzero values. If the unmasked bits are all zero, the block passes 282 the controller to the block 284 to iterate through the various hardware page table data structures to try to find a matching page table entry for the effective address, assuming a default page size. In some embodiments, missing an indication of the page size may also result in finding a matching page table entry that corresponds to main memory pages that have page sizes that differ from the default page size. It should also understand that in the block 284 search can also be computationally intensive, since it may be necessary to access several different data structures in order to try to find a suitable page table entry, and these may even have to be retrieved from the mass storage, as the person skilled in the art would understand. who has the current revelation. The block 286 thus determines if a matching page table entry was found, and if so, the matching page table entry in the block 288 returned. If not, the controller switches to the block 290 to return a "not found" notice.

If the block 282 On the other hand, if it detects that a non-zero value is stored in the non-masked bits of the effective address, an indication of the page size in the effective address is encoded and control goes to the block 292 to search one or more data structures belonging to the page size specified by the page size hint. Assuming that the expected page size is known, the one in block 292 Therefore, the search performed using the pointer to the page size may be more efficient than a full search, and in some embodiments may reduce the latency associated with a page table error.

Next is the block 294 determines if a matching page table entry was found, and if so, control goes to the block 288 to return the matching page table entry. Otherwise, the block 294 the controller to the block 284 hand over to try a complete search. In other embodiments, a complete search may not be required and the block 294 instead, you can return a "not found" hint by sending the control directly to the block 290 passes. Thus, at the block 252 an indication of the page size encoded in an effective address may be used to speed up the retrieval of a page table entry based on the page size indicated by the page size indication. For example, in some embodiments, the acceleration may occur as a result of bypassing access by at least one data structure that would normally be accessed when the hardware page table is traversed after a main memory access instruction that lacks a coded pointer to the page size.

It should be understood that pointers to page size may be encoded into an effective or virtual address in a number of ways consistent with the invention. For example, in some embodiments, pointers to page size may be associated with creating a program, e.g. while compiling, optimizing, wrapping, installing or deploying a program, they are encoded into virtual addresses. In such embodiments, pointers to the page size may be encoded in the unused field and the reserved field by one or more of the main memory access instructions in a program referenced virtual address, and the program may be constructed with the main memory access instructions in that, after page faults caused by the main memory access instructions were detected by hardware translation logic of a data processing system on which the program is executed, the pointers to the page size may be used in performing software address translation operations.

6 shows, for example, a sequence of operations 300 for creating a program including three different scenarios that may be supported in some embodiments of the invention. In the example of 6 are hints on the page size shown as hints, due to compiler control statements (blocks 302 to 304 ), due to optimization (blocks 306 to 310 ) and due to the creation of an executable file (blocks 312 to 314 ) are encoded in main memory address instructions. Other operations performed during the creation of a program, eg, parsing source code, creating intermediate codes, executing various code optimizations, packaging code that generates executable code, associating code with other executable code, and / or libraries, providing or installing code, etc., will be in 6 however, to simplify the description below, it should be understood that such operations are generally understood in the art and one skilled in the art having the current disclosure would be able to incorporate the functionality described herein into any of these operations. 6 shows in the block 316 however, the issuance of one or more executables as a result of the build which, it should be understood, may include one or more main memory access instructions, where an indication of the page size in an unused and reserved field of the effective or virtual address of the Main memory access instruction is coded. It should also be understood that in some embodiments, all three in 6 shown scenarios can not be supported. It should also be understood that in other embodiments, other scenarios may be used to encode page size information into the main memory access instructions of a program, so that the invention will not be limited to the particular ones described in US Pat 6 Scenarios is limited.

The blocks 302 to 304 For example, FIG. 1 shows a scenario in which an application developer inserts a compiler control statement into the source code of an application being developed through a compiler (block 302 ) may be detected to cause the compiler to change one or more main memory access instructions in a program to encode page size indications into those main memory access instructions (block 304 ). For example, a compiler control statement may enable or disable the encoding of page size hints for all or portions of the source code. A compiler control statement may also specify a desired page size for particular main memory allocation instructions, for a particular piece of code, or for certain types of instructions (eg instructions fetching data as compared to instructions fetching other program instructions, etc.). Statements may belong to individual instructions, code sections, specific methods, classes or modules, or to a whole program. In general, the instructions allow an application developer to control the program building process to cause the application being developed to use the page sizes desired by the application developer. It should also be understood, however, that a developer may otherwise control the use of page size references in other embodiments in other embodiments.

The blocks 306 to 310 On the other hand, a scenario in which a compiler determines during optimization, for example, that certain page sizes would be optimal for particular main memory access instructions or requests. For example, the block 306 evaluate, as part of the optimization, patterns of memory requirements in an attempt to locate suitable candidates for encoding page size hints. In response to locating such candidates, the block 308 the controller to the block 310 redirect to change the main memory access instructions associated with such candidates to encode page size indications for appropriate page sizes. For example, suitable candidates may be present if it is determined that the storage volume accessed by a critical portion of the code in the program is greater than the default page size, so that it becomes advantageous to store all the storage in a single, larger pages and not in multiple pages that might otherwise be paged in and out of other memory traffic.

The blocks 312 to 314 show yet another scenario in which a compiler or binder loader can determine if an executable file created during the build process fits into a particular page size. In response to detecting such a scenario, the block 312 for example, the control to the block 314 to configure the program to load the pre-set page size, for example by encoding page size instructions into the instructions, which main memory is allocated to a program (or to specific modules, libraries, sections, classes, files, etc.). of the program). Thus, for example, if it can be determined that the compiled application fits into a single 2MB page, in some embodiments, it may be desirable to configure the application to request a 2MB page when it is loaded, so that the whole Application is loaded into a single page of main memory. In this way, page loading and unloading to load different modules or code sections for the application is avoided, thereby improving the overall performance of the application in appropriate scenarios.

Thus, embodiments consistent with the invention may allow unused and reserved bits of virtual or effective addresses to be redirected to page size indications of software page fault handling functionality in an operating system, hypervisor, virtual machine monitor, kernel, or other low-level software in a data processing system to be used in conjunction with the handling of a page fault. In addition, in some embodiments, the actual encoding may be performed prior to the execution of the program, and in some embodiments, may occur during compilation, bind loading, deployment, or installation of the program.

In some embodiments, the build process may further include incorporating one or more instructions into the program to configure the program hardware implementation logic of a data processing system to operate in a mode that is capable of generating invalid address notifications based on values nonzero in the unused and reserved fields of virtual or effective addresses disabled. In other embodiments, the hardware translation logic may not generate invalid address notifications, and in some embodiments, the selection of a suitable mode may be separate from the execution of a program activated by an indication of the page size, e.g. through an operating system.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, the practical application or technical improvement over the technologies on the market, or to assist others in understanding the embodiments disclosed herein.

Claims (20)

A method of handling a page fault in a data processing system of a type supporting a plurality of main memory page sizes, the method comprising: Detecting a page fault generated by hardware implementation logic of a processor, the page fault associated with a virtual address requested by program code executed by the processor; determining, by virtue of the virtual address, an indication of the page size encoded in an unused and reserved virtual address field; and Perform a software address translation operation on the virtual address using the noted page size indication. Method according to Claim 1 , where the reference to the page size is encoded before executing the program code in the unused and reserved field. Method according to Claim 2 in which the indication of the page size is encoded into the unused and reserved field during compilation, binding loading, the provision or installation of the program code. Method according to Claim 1 wherein the hardware translation logic is configurable to operate in a first and a second mode, the hardware translation logic in the first mode having an invalid address notification due to one or more values in the unused and reserved virtual address field wherein the generation of invalid address notifications is disabled by the hardware translation logic in the second mode due to the one or more values in the unused and reserved virtual address field, and wherein the method further comprises configuring the hardware translation logic in the second mode. Method according to Claim 4 wherein the hardware translation logic is configured to generate in the first mode an invalid address notification due to a nonzero value in the unused and reserved virtual address field. Method according to Claim 1 and further comprising selectively associating a page size that corresponds to the determined indication of page size based on the available main memory. Method according to Claim 1 wherein determining the indication of the page size is performed before searching one or more data structures of a hardware page table, and performing the software address translation operation for the virtual address using the established indication of the page size using the detected indication the page size includes to access the one or more data structures. Method according to Claim 7 wherein the at least one page size specific data structure configured to store address translation information for pages having a particular page size is associated with the one or more data structures, and performing the software address translation operation for the virtual address using the noted reference to Page size includes using the noted page size indication for accessing the page size specific data structure configured to store page size address translation information pertaining to the page size indication. Method according to Claim 8 wherein performing the software address translation operation for the virtual address using the established page size indication includes bypassing access by at least one other data structure that is accessed when the hardware Page table is traversed after a main memory access instruction which lacks a coded pointer to the page size. Method according to Claim 9 further comprising passing through a plurality of hardware page table data structures due to a second page fault associated with a second virtual address requested by program code executed by the processor and lacking a coded pointer to the page size to locate a page table entry corresponding to the second virtual address. Method according to Claim 1 wherein determining the indication of the page size is prior to the assignment of a main memory page for the virtual address, the method further comprising associating the main memory page for the virtual address with a page size indicated by the indication of the page size. Method according to Claim 11 wherein the assignment of the main memory page for the virtual address to a page size indicated by the page size indication is permitted based on the determination that the page size indicated by the page size indication is allowed. Method according to Claim 11 that is due to a second page fault associated with a second virtual address requested by program code that is executed by the processor and that lacks a coded pointer to the page size, further assigning a main page virtual address page with a default page size having. Method according to Claim 1 further comprising determining, based on the virtual address, that an indication of the page size is encoded into the unused and reserved virtual address field by a nonzero value in at least a subset of a plurality of bits in the unused and reserved Field is detected. A method of creating a program, the method comprising: Encoding an indication of the page size into an unused and reserved field of a virtual address referenced by a main memory access instruction; and Creating the program with the main memory access instruction such that after a page fault caused by the main memory access instruction has been detected by hardware translation logic of a data processing system on which the program is executed, the indication of the page size in the execution of software Address translation operation is used. Method according to Claim 15 wherein the encoding of the page size indication into the unused and reserved field of the virtual address referenced by the main memory access instruction is performed during compilation or binding of the program. Method according to Claim 15 wherein the encoding of the page size indication into the unused and reserved field of the virtual address referenced by the main memory access instruction is performed on the determination that an executable file for the program fits into a page size corresponding to the page size indication belongs. Method according to Claim 15 wherein the encoding of the page size indication into the unused and reserved field of the virtual address referenced by the main memory access instruction is performed on the basis of evaluating a pattern of data main memory requests during optimization of the program. An apparatus supporting multiple main memory page sizes, the apparatus comprising: at least one processor containing hardware translation logic; and program code configured to handle a page fault upon execution by the at least one processor by: detecting a page fault generated by the hardware translation logic, the page fault associated with a virtual address requested by a program which is executed by the processor; uses the virtual address to determine an indication of the page size encoded into an unused and reserved virtual address field; and performs a software address translation operation on the virtual address using the established page size indication. A program product comprising: a nonvolatile computer readable medium; and Program code stored on the non-transitory computer-readable medium and configured to handle, after execution by at least one processor, a page fault in a data processing system of a type that supports multiple main memory page sizes by: detecting a page fault generated by processor hardware conversion logic, the page fault associated with a virtual address requested by program code executed by the processor; by means of the virtual address, an indication of the page size coded in an unused and reserved field of the virtual address; and a software address translation operation is performed for the virtual address using the established page size indication.

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