DE112013002995T5 - Real-time measurement of virtualization I / O processing delays - Google Patents

Abstract

A computer system includes a memory that is divided into a plurality of logical partitions (LPARs), each LPAR executing one of a plurality of instances of an operating system (O / S). The system also includes a processor configured to execute a hypervisor program to manage operation of the plurality of LPARs. The processor determines a reference I / O service time of an I / O operation on a server, measures an actual I / O service time of the operation, and determines a virtualization delay time on the server based on the reference E / A service time and the actual I / O service time.

Description

TECHNICAL AREA

The present invention relates to measuring the delay in processing I / O operations caused by server virtualization, and more particularly to measuring a period of time taken by a hypervisor for multiple instances of an operating system manage.

BACKGROUND

In computers that work with virtual machines, a hypervisor program splits physical resources, including a central processing unit (CPU), memory, storage, and I / O units, of a real computer into separate virtual machines. For example, the hypervisor may allocate a predetermined time frame in which each virtual machine can access the CPU, and predetermined portions of memory or storage space that can be accessed by the respective virtual machines.

When an interrupt occurs that targets a particular virtual machine, the hypervisor receives the interrupt and determines which virtual machine the interrupt is addressed to. When another virtual machine uses system resources, such as the CPU, a delay in processing the interrupt is caused by the destination virtual machine until the hypervisor controls the CPU to start executing the destination virtual machine. The destination virtual machine may then perform one or more functions based on receipt of the interrupt.

Other delays that result from the hypervisor managing multiple virtual machines include emulation overhead in which instructions and operations for accessing I / O devices are intercepted by the hypervisor, and scheduling delays due to transmission and reception of packets, involving multiple hypervisor threads and virtual machines.

Therefore, there is a need in the art to solve the above problem.

SUMMARY

Exemplary embodiments include a method for determining a reference I / O service time of an I / O operation on a server. The server may include a processor executing a hypervisor configured to manage a plurality of logical partitions (LPARs), and each LPAR may execute one of a plurality of instances of an operating system (O / S) , The method may further include, by the processor, measuring an actual I / O service time of the I / O operation by the processor and determining a delay time of the virtualization on the server by the processor based on the reference I / O service time and the actual I / O service time.

Viewed from a first aspect, the present invention provides a method for managing multiple instances of an operating system, comprising: determining a reference I / O service time of an I / O operation on a server; Measuring an actual I / O service time of the I / O operation with a processor of the server executing a hypervisor configured to manage a plurality of logical partitions (LPARs), each LPAR containing one of a Runs a plurality of instances of an operating system (O / S); and determining, by the processor, a delay time of virtualization on the server based on the reference I / O service time and the actual I / O service time.

Viewed from a further aspect, the present invention provides a computer system for managing a plurality of instances of an operating system, comprising: a memory partitioned into a plurality of logical partitions (LPARs), each LPAR being configured to have one from a plurality of instances of an operating system (O / S) executes; a processor configured to detect a reference I / O service time of an I / O operation on a server, measure an actual I / O service time of the I / O operation, and a delay time The virtualization on the server is determined based on the reference I / O service time and the actual I / O service time.

Viewed from a further aspect, the present invention provides a computer program product for managing multiple instances of an operating system, the computer program product having a computer readable storage medium readable by a processing circuit and instructions for execution by the processing circuitry for performing a method of performing stores the steps of the invention.

Viewed from another aspect, the present invention provides a computer program stored on a computer-readable medium and capable of being loaded into the internal memory of a digital computer having portions of software code associated therewith Steps of the invention to perform when the program is run on a computer.

Additional exemplary embodiments include a computer program product that includes a non-transitory storage medium that may be read by a processing circuitry of a computer and that stores instructions for execution by the processing circuitry to perform a method. The method may include determining a reference I / O service time of an I / O operation on a server. The server may include a processor executing a hypervisor configured to manage a plurality of logical partitions (LPARs), and each LPAR may execute one of a plurality of instances of an operating system (O / S) , The method may further include, by the processor, measuring an actual I / O service time of the I / O operation by the processor and determining a delay time of the virtualization on the server by the processor based on the reference I / O service time and the actual I / O service time.

Other exemplary embodiments include a computer system that includes a memory that is divided into a plurality of logical partitions (LPARs), each LPAR that executes one of a plurality of instances of an operating system (O / S), and a processor. The processor is configured to execute a hypervisor program to manage operation of the plurality of LPARs. The processor may determine a reference I / O service time of an I / O operation on a server and measure an actual I / O service time of the I / O operation. The processor may further determine a virtualization delay time on the server based on the reference I / O service time and the actual I / O service time.

Additional features and advantages are realized by the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered part of the claimed invention. For a better understanding of the invention with the advantages and features, reference is made to the description and to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will now be described, by way of example only, with reference to preferred embodiments as illustrated in the following figures:

1 illustrates a virtual machine system according to a preferred embodiment of the present invention;

2 illustrates a subchannel gauge block according to a preferred embodiment of the present invention;

3 Figure 12 illustrates a block diagram of a method according to a preferred embodiment of the present invention;

4 illustrates a computer system according to a preferred embodiment of the present invention; and

5 illustrates a computer readable medium according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION

In exemplary embodiments, a delay caused by a hypervisor managing multiple virtual machines or logical partitions (LPARs) is calculated in real-time by calculating an elapsed time from generation of an I / O interrupt by a subchannel and a time at which the target operating system (O / S) is allocated by the hypervisor and a signal is generated that the I / O interrupt has been received and processed.

1 illustrates a block diagram of a virtual machine system 100 according to an embodiment of the present disclosure. The system 100 includes one or more real CPUs 111 and a real host memory 112 , Depending on the design requirements of the system 100 can one or more real CPUs 111 each correspond to a separate processor, or each CPU 111 may correspond to a plurality of processors, processing units or processing cores. The system 100 also includes an I / O subsystem 120 and one or more virtual machines 130 . 140 and 150 , The virtual machines 130 . 140 and 150 can also be called logical partitions (LPARs) 130 . 140 and 150 be designated. The system 100 is with one or more external storage devices 160 connected.

Every virtual machine 130 can be an instance or an image of an operating system (O / S) 131 . 141 and 151 (also as guest O / S 131 . 141 and 151 referred to) include. Each virtual machine can also have one or more applications 132 . 142 . 152 , Intermediate applications 133 . 143 . 153 and virtual private storage 134 . 144 and 154 include. For descriptive purposes, the virtual machine 130 as an example, although it is understood that the description of the virtual machine 130 for each of the virtual machines 130 . 140 and 150 applies.

At the guest O / S 131 it can be an instance or an image of an O / S that resides in the real host memory 112 is stored. Similarly, it may be in the application 132 and the intermediate application 133 to act instances or images of applications and intermediate applications that reside in the real host memory 112 are stored. In the virtual private storage 134 These may be memory addresses within the real host memory 112 act as the virtual machine 130 are designated accordingly. In operation, every virtual machine works 130 . 140 and 150 disconnected from any other virtual machine 130 . 140 and 150 where it runs separate instances of operating systems, applications and intermediate applications, and data in a separate memory or portions of the real host memory 112 saves as the respective virtual machines 130 . 140 and 150 are designated accordingly.

The I / O subsystem 120 includes a hypervisor 121 or an LPAR dispatcher routine 121 for controlling the operation of the virtual machines 130 . 140 and 150 , The hypervisor 121 can be a virtual private storage 122 that is the hypervisor 121 assigned. At the hypervisor 121 it can be a program that resides in the real host memory 112 is stored and by the one or more CPUs 111 is executed, and the virtual private memory 122 can be a segment of the real host memory 112 be the hypervisor 121 assigned.

The hypervisor 121 manages the virtual machines 130 . 140 and 150 by controlling which virtual machine 130 . 140 and 150 at the time to the one or more real CPUs 111 and by determining which transmitted and received signals, instructions or other data of which virtual machine 130 . 140 and 150 correspond. If, for example, a signal from a subchannel 113 for the virtual machine 130 is received while the virtual machine 150 the one or more CPUs 111 uses, stores the hypervisor 121 the signal until the virtual machine 130 runs and sets the virtual machine 130 the signal ready.

The I / O subsystem 120 further includes one or more subchannels 113 , The subchannels 113 For example, data transfer ports supporting circuits and memory for exchanging data between the system 100 and external devices such as the external storage device 160 correspond. Although a subchannel 113 and an external storage unit 160 in 1 It should be understood that embodiments of the present disclosure include any number of subchannels 113 include with any number of external storage devices 160 are connected. In particular, specific subchannels 113 specific external storage devices 160 correspond to an operating system on specific subchannels 113 must access to appropriate external storage devices 160 access.

In embodiments of the present disclosure, the hypervisor keeps track of 121 in real time a time that is required to run the virtual machines 130 . 140 and 150 manage. Managing the virtual machines 130 . 140 and 150 may include storing signals, commands, interrupts, or other data destined for a particular virtual machine until that particular virtual machine is executed. The management of the virtual machines may also include determining whether the operation of a virtual machine should be terminated to grant access to another virtual machine. If, for example, the three virtual machines 130 . 140 and 150 all the CPUs 111 can use the hypervisor 121 the virtual machines 130 . 140 and 150 so control that every virtual machine 130 . 140 and 150 during one third of the time accessing the CPUs. The hypervisor 121 however, can determine whether to allocate time among the virtual machines based on a received or processed command, signal, or data type, type of operation performed by a virtual machine, or any other consideration 130 . 140 and 150 An exception should be made to allow one virtual machine to use one part of the other's time.

In operation, an application 132 or an intermediate application 133 on one or more CPUs 111 work, access to a device such as the external storage device 160 Request. The access may include retrieving data in a load or sending data in a store. Although the external storage unit 160 as an example of a unit being provided by the system 100 can be accessed, it is understood that through the system 100 any unit such as a media unit, display unit, storage unit, network unit or any other unit can be accessed. The guest O / S 131 generates an access request signal based on the request from the application 132 or the intermediate application 133 , At a Embodiment, the access request signal is a subchannel start (Start SubChannel, SSCH) signal.

The guest O / S 131 transmits the SSCH signal to the I / O subsystem 120 , The I / O subsystem 120 may determine which subchannel of a plurality of subchannels of the unit 160 which is the desired target of the SSCH request. The I / O subsystem 120 transmits the SSCH with the address of the desired unit 160 to the subchannel 113 which controls one or more switches or other units such that a data transfer between the subchannel 113 and the external storage device 160 is possible. In a loading operation, data may be from a specified address of the external storage unit 160 the subchannel 113 to be provided. In a save operation, data from the subchannel 113 the external storage unit 160 to be provided.

After to the external storage unit 160 has been accessed and possibly data in the real host memory 112 have been stored generates the subchannel 113 an I / O interrupt and puts the I / O interrupt to the hypervisor 121 which indicates that an operation has been completed. The hypervisor 121 can be a guest O / S or an instance of the virtual machines 130 . 140 and 150 determine for which the I / O interrupt is intended. For example, the hypervisor 121 determine that the I / O interrupt is the guest O / S 131 should be provided.

The hypervisor 121 can store the I / O interrupt in a cache or buffer. The cache or buffer may include a plurality of I / O interrupts, the various guest operating systems 131 . 141 and 151 correspond, and the hypervisor 121 can allocate the I / O interrupts asynchronously and unsorted. The hypervisor 121 can determine whether a process of a currently running guest O / S should be halted to provide an I / O interrupt for another guest O / S, or whether the currently running guest O / S should be allowed Finish execution.

If the destination guest O / S, or in the present example the guest O / S 131 , the hypervisor can run 121 the I / O interrupt for the guest O / S 131 provide. The guest O / S 131 can then perform an operation completion routine to check the status of the subchannel 113 to determine and if the unit has been accessed. In embodiments of the present disclosure, the transaction completion routine may be a test subchannel (TSCH) command. If it is found to be successful on the unit 160 has been accessed, for example by a load or store operation, the guest O / S 131 the application 132 or the intermediate application 133 notify that data has been made available or stored.

In embodiments of the present disclosure, the hypervisor keeps track of 121 a time between receipt of the I / O interrupt from the subchannel 113 and a time when the guest O / S 131 the TSCH signal generates the status of the subchannel 113 retrieve. Accordingly, the I / O subsystem 120 able to delay when executing instructions from the virtual machines 130 . 140 and 150 due to the execution of the hypervisor 121 and running the multiple virtual machines 130 . 140 and 150 instead of just one operating system. The tracked delay corresponds to the time that the hypervisor 121 needed to manage an I / O interrupt to one of the guest operating systems 131 . 141 or 151 is directed.

In some embodiments, the real CPUs 111 or the I / O subsystem 120 After a delay has been calculated due to virtualization, perform a capacity planning to process the hypervisor 121 , the guest operating systems 131 . 141 and 151 or external storage devices 160 manage. In addition, the real CPUs or the I / O subsystem 120 provide a performance bottleneck analysis by performing operations that are operating systems 131 . 141 or 151 , the applications 132 . 142 or 152 or the intermediate applications 133 . 143 or 153 identify the ones that contribute most to a detected delay.

2 illustrates the storage of a measured elapsed time according to an embodiment of the disclosure. The subchannel 213 can the subchannel 113 from 1 and may be one of a plurality of subchannels, each connected to one or more external units such that it transmits data between the system 100 and the external units. The subchannels 213 can make a measuring block 214 include the fields for storing transaction data of the subchannel 213 includes. Example metric values may include a subchannel start count, connection and interrupt duration, an initial command response (ICR) duration, any other desired metric (shown as "metric X"), and an interrupt delay time. In embodiments of the present disclosure, the interrupt delay time corresponds to a period between a time when an I / O interrupt by the subchannel 213 is generated to indicate that an external device has been accessed and a time at which an external device has been accessed Signal such as a subchannel test (CHCH) signal is received from an O / S in response to the I / O interrupt. The interrupt delay time may thus provide a measure of a time delay caused by the hypervisor 121 is generated, which is a plurality of instances of an O / S 131 . 141 and 151 performs.

3 illustrates a method according to an embodiment of the present disclosure. In block 301 An application or an intermediate application can request access to a device. The application or the intermediate application may be part of a virtual machine running on an instance of an O / S associated with the virtual machine. The virtual machine may be one of a plurality of virtual machines running concurrently on a computer system. The plurality of virtual machines may share one or more CPUs, and a hypervisor may manage the access of the plurality of virtual machines to the one or more CPUs and the real memory. The request to access the device may be a load, save, or any other desired operation.

In block 302 For example, the O / S associated with the application or interim application may generate a request to access the device. The request may be a Subchannel Start (SSCH) request and may be provided by the O / S to an I / O subsystem that includes the hypervisor. The SSCH request specifies a subchannel associated with the destination unit.

In block 303 The I / O subsystem determines the unit location and selects the route to the specific unit associated with the destination sub-channel. The request is then passed from the appropriate interface to reach the destination unit. This route may include a path through switches and a network to reach the destination unit. In block 304 the unit has been accessed and a connection has been made to the unit.

In block 305 the requested operation is performed. For example, if the requested operation is a read, the I / O subsystem uses pointers and controls in the subchannel to retrieve the target data from the target device and stores the data in the host memory. If the requested operation is a write operation, the I / O subsystem uses pointers and controls in the subchannel to provide the target data from the host memory for the target location of the device.

In block 306 The I / O subsystem generates an I / O interrupt after the process for the device is completed. For example, the I / O interrupt may be provided to the hypervisor. In one embodiment, a start time stamp is in block 307 recorded when the I / O interrupt is generated by the I / O subsystem. In another embodiment, a clock or counter may be started.

In block 308 The hypervisor manages the I / O interrupt as well as any additional I / O interrupts, commands or instructions from the multiple instances of the O / S that are running on the computer system. The hypervisor can determine which O / S corresponds to the generated I / O interrupt and can determine whether to execute another instance of the one based on a predetermined interval in which each instance of the O / S executes over a given time period O / S should be terminated to allow the I / O interrupt to be transmitted, or to wait for the I / O interrupt to be delivered until the appropriate instance of the O / S is executed.

In block 309 The hypervisor can provide the I / O interrupt of the corresponding instance of the O / S. In block 310 For example, the instance of the O / S may generate a signal (such as a Subchannel Test (TSCH) signal) to determine the status of the subchannel and whether the unit has been accessed. In embodiments of the present disclosure, an end timestamp may be in block 311 may be recorded at a time when the TSCH signal is received by the I / O subsystem, hypervisor or subchannel, and a difference between the end time and the start time may be in block 312 to calculate the logical partition (LPAR) allocation time, which may also be referred to as interrupt delay time or hypervisor delay time. In another embodiment, a time may be stopped and the elapsed time on the timer may provide the LPAR allocation time.

Accordingly, a system running multiple virtual machines, each having an instance of O / S, is capable of tracking time based on a time that a hypervisor requires to manage I / O interrupts; which can be added to the execution of instructions by running the virtual machines. The system and method provide real-time data regarding any delays generated by the hypervisor.

3 merely provides an example of a method according to embodiments of the present disclosure. There are many changes to this chart or the one described therein Steps (or operations) possible without departing from the spirit of the invention. For example, the steps may be performed in a different order, or steps added, deleted, or modified. All of these changes are considered part of the claimed invention.

4 illustrates a block diagram of a virtual machine system 400 , The methods described herein may be implemented in hardware, software (eg, firmware), or a combination thereof. In an exemplary embodiment, the methods described herein are implemented in hardware as part of the microprocessor of a special purpose or general purpose digital computer such as a personal computer, workstation, minicomputer, or mainframe computer. The system 400 can therefore be a universal computer or mainframe 401 which is capable of executing multiple instances of an O / S simultaneously.

In an exemplary embodiment, the computer includes 401 in terms of hardware architecture, as in 4 represented one or more processors 405 , a store 410 that with a storage controller 415 one or more input and / or output (I / O) units 440 . 445 (or peripherals) used for data transfer via a local input / output controller 435 are connected. At the input / output control unit 435 For example, it may be one or more buses or other prior art wireless or wireless links, without limitation. The input / output control unit 435 may include additional elements such as controllers, buffers (caches), drivers, repeaters, and receivers, which are omitted for simplicity in order to facilitate data transfers. Furthermore, the local interface may include address, control, and / or data connections to facilitate appropriate data transfers between the above-mentioned components. The input / output control unit 435 may include a plurality of subchannels configured to be responsive to the output units 440 and 445 access. The subchannels may include fiber optic communication links.

At the processor 405 it is a hardware unit for executing software, especially those in a memory 420 such as a cache or memory 410 is stored. The processor 405 can be any custom-made or commercially available processor, a central processing unit (CPU), an auxiliary processor of multiple processors connected to the computer 401 be a microprocessor based on a semiconductor (in the form of a micro-chip or a chip set), a macro-processor or in general any unit for executing instructions.

The memory 410 may include any volatile memory element (e.g., random access memory, RAM such as DRAM, SRAM, SDRAM, etc.) and nonvolatile memory elements (e.g., a ROM, erasable programmable read only memory) read only memory, EPROM), an electrically erasable programmable read only memory (EEPROM), a programmable read only memory (PROM), a tape, a CD-ROM (compact disc read only memory, Compact disk read-only memory), a disk, a floppy disk, a cartridge, a cartridge or the like, etc.) or a combination thereof. In addition, the memory can 410 electronic, magnetic, optical and / or other types of storage media. It should be noted that the memory 410 may have a distributed architecture with different components remote from each other, but by the processor 405 can be accessed.

The instructions in the memory 410 may include one or more separate programs, each of which has an ordered listing of executable instructions for implementing logical functions. In the example of 4 the instructions in the memory 410 a suitable operating system (OS) 411 , The operating system 411 essentially controls the execution of other computer programs and provides scheduling, input-output control, file and data management, memory management and data transfer control, and related services.

The memory 410 can use multiple logical partitions (LPARs) 412 each running an instance of an operating system. The LPARs 412 can be managed by a hypervisor, which can be a program that resides in memory 410 stored and by the processor 405 is performed.

In an exemplary embodiment, a conventional keyboard 450 and a mouse 455 with the input / output control unit 435 get connected. To other output units such as the I / O units 440 . 445 may include input devices such as, but not limited to, a printer, a scanner, a microphone, and the like. Finally, the I / O units 440 . 445 Furthermore, units that transfer data between inputs and outputs, such as a network interface card (NIC) or a modulator / demodulator (for accessing other files, devices, systems or a network), a radio frequency (RF) or another transceiver, a telephone interface, a bridge, a router and the like, without being limited thereto. The system 400 Further, a display control unit 425 Include that with an ad 430 connected is. In an exemplary embodiment, the system 400 furthermore a network interface 460 to connect to a network 465 include. At the network 465 It can be a network based on IP for data transfer between the computer 401 and any external server, client, and the like over a broadband connection. The network 465 transmits and receives data between the computer 401 and external systems. In an exemplary embodiment, the network may be 465 to be a managed IP network managed by a service provider. The network 465 can be implemented wirelessly, eg. B. using wireless protocols and technologies such. WiFi, WiMax etc. in the network 465 it may also be a packet-switched network such as a local area network, a wide area network, a high-speed network, an Internet network, or another similar type of network environment. The network 465 a fixed wireless network, a local area network (LAN), a wide area network (WAN), a personal area network (PAN), a virtual private network (VPN), an intranet or other suitable network system, and includes devices for receiving and transmitting signals.

If it is the computer 401 The instructions in the memory may be a PC, workstation, intelligent unit or the like 410 further include a basic input output system (BIOS) (which is omitted for simplicity). The BIOS is a set of essential software routines that initialize and test hardware at boot time, the OS 411 start and support the transfer of data between the hardware units. The BIOS is stored in ROM so that the BIOS can be run when the computer 401 is activated.

If the computer 401 is in operation, is the processor 405 configured to be in memory 410 Saved statements execute data in and out of memory 410 transfers and generally processes the computer 401 according to the instructions.

In an exemplary embodiment, the hypervisor delay real-time calculation methods described herein can be implemented with any of the following technologies well known in the art, or a combination thereof: with one or more discrete logic circuits implementing logic gates to implement have logical functions on data signals, an application specific integrated circuit (ASIC) having suitable circuit logic gates, one or more programmable gate arrays (PGA), a field programmable gate array (FPGA), etc.

As described above, embodiments may be embodied in the form of computer-implemented processes and devices for implementing these processes. An embodiment may be a computer program product 500 , as in 5 shown on a computer readable / usable medium 502 include, wherein computer program code logic 504 that contains instructions embodied in physical media such as an article of manufacture. Exemplary articles of manufacture for the computer readable / usable medium 502 may include floppy disks, CD-ROMs, hard disks, universal serial bus (USB) flash drives, or any other computer-readable storage medium, the computer, when the computer program code logic 504 is loaded into and executed by a computer, becomes an apparatus for practicing the invention. Embodiments include computer program code logic 504 regardless of whether it is stored in a storage medium, loaded into and / or carried by a computer or transmitted via a transmission medium such as electrical wiring or cabling, optical fibers or electromagnetic radiation, for example, the computer computer program code logic 504 is loaded into and executed by a computer, becomes an apparatus for practicing the invention. When implemented on a general-purpose microprocessor, segments of computer program code logic configure 504 the microprocessor to create specific logic circuits.

Embodiments of the present disclosure may be implemented by any suitable architecture. For example, the architecture of IBM ^® z / Architecture ^® is used to implement the embodiments of the disclosure. A description of the z / Architecture general operations and specifications is provided in "IBM z / Architecture Principles of Operation", p. Publication No. SA22-7832-08, 9th edition, August 2010. IBM and z / Architecture are registered trademarks of International Business Machines Corporation, Armonk, NY, USA.

In addition, embodiments of the present disclosure may be implemented by any suitable system for utilizing subchannels and measuring I / O characteristics. For example, the measurement of I / O characteristics in an embodiment according to the disclosure of the application with the serial no. 10/435 906 to Scott M. Carlson et al. which relates to EXTENDED INPUT / OUTPUT MEASUREMENT FACILITIES, the application of which was granted as US Pat. No. 7,000,036.

As one of ordinary skill in the art appreciates, aspects of the present disclosure may be embodied as a system, method, or computer program product. Accordingly, aspects of the present disclosure may assume a purely hardware embodiment, a pure software embodiment (including firmware, resident software, microcode, etc.), or an embodiment that combines software and hardware aspects, all of which are generalized herein as " Circuit "," module "or" system "can be called. Further, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable media embodied with computer readable program code.

Any combination of one or more computer-readable media may be used. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the above. More concrete examples (non-exhaustive list) of the computer-readable storage medium would include: electrical connection to one or more lines, a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory ( EPROM or flash memory), an optical fiber, a portable Compact Disk Read Only Memory (CD-ROM), an optical storage unit, a magnetic storage unit, or any suitable combination of the above. For the purposes of this document, a computer-readable storage medium may be any physical medium that may contain or store a program for use by, or in connection with, a system, apparatus, or device for executing instructions.

Program code embodied on a computer readable medium may be transmitted using any suitable medium, such as, but not limited to, wireless, cable, fiber optic cable, radio frequency (RF), etc., or any suitable combination of the above.

Computer program code for performing operations for aspects of the present disclosure may be written in any combination of one or more programming languages, for example, in an object-oriented programming language such as ^Java® , Smalltalk, C ++ or the like and in conventional procedural programming languages such as the "C" programming language Or similar programming languages. The program code may be executed entirely on the user's computer, partly on the user's computer, as a standalone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server , In the latter scenario, the remote computer may be connected to the user's computer through any type of network, such as a Local Area Network (LAN) or Wide Area Network (WAN), or the connection may be to an external computer (e.g. Example over the Internet using an Internet service provider) are produced. Java and all Java-based marks and logos are trademarks or registered trademarks of Oracle and / or its affiliates.

Aspects of the present disclosure are described above with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It is understood that each block of the flowcharts and / or block diagrams and combinations of blocks in the flowcharts and / or block diagrams may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special purpose computer, or other programmable data processing device to generate a machine so that the instructions executed by the processor of the computer or other programmable data processing device provide a means for implementing the functions. Generate operations specified in the block or blocks of the flowcharts and / or block diagrams.

These computer program instructions may also be stored in a computer-readable medium that may control a computer, other programmable computing device, or other entity to function in a particular manner such that the instructions stored in the computer-readable medium produce an article of manufacture containing instructions that implement the function / task specified in the block or blocks of the flowcharts and / or block diagrams.

The computer program instructions may also be loaded onto a computer, other programmable computing device, or other device to cause a series of steps of an operation to be performed on the computer, other programmable device, or other device to produce a computer-implemented process. the instructions executed on the computer or other programmable device provide processes to implement the functions / operations specified in the block or blocks of the flowcharts and / or block diagrams.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of code having one or more executable instructions for implementing the specified logical function (s). It should also be noted that in some alternative implementations, the functions noted in the block may occur in a different order than noted in the figures. For example, depending on the functionality involved, two consecutive blocks may even be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order. It is further to be noted that each block of the block diagrams and / or the flowcharts and combinations of blocks in the block diagrams and / or flowcharts may be executed by specialized systems based on hardware performing the specified functions or operations, or by combinations of specialized Hardware and computer instructions can be implemented.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms "a," "an," and "the," "the," are also intended to encompass the plural forms, unless the context clearly dictates otherwise. It should also be understood that the terms "having" and / or "having" when used in this specification refer to the presence of specified features, integers, steps, acts, elements, and / or components, but not the presence or preclude the inclusion of one or more other features, integers, steps, acts, elemental components, and / or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act of performing the function in combination with other claimed elements as expressly claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the invention.

While the preferred embodiment of the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements that fall within the scope of the following claims.

Claims (15)

A method for managing multiple instances of an operating system, comprising: Determining a reference I / O service time of an I / O operation on a server; Measuring an actual I / O service time of the I / O operation with a processor of the server executing a hypervisor configured to manage a plurality of logical partitions (LPARs), each LPAR containing one of a Runs a plurality of instances of an operating system (O / S); and Determining a delay time of virtualization on the server by the processor based on the reference I / O service time and the actual I / O service time. The method of claim 1, wherein measuring the actual I / O service time of the I / O operation comprises monitoring the actual I / O service time. Includes times of real-time I / O operations for each device in communication with the majority of LPARs. The method of any one of the preceding claims, further comprising: Performing at least one of capacity planning and performance bottleneck analysis by the processor based on determining the delay time of the virtualization on the server. The method of any one of the preceding claims, wherein measuring the actual I / O service time of the I / O operation comprises: Receiving, by the processor, an I / O signal from a subchannel indicating that a requested I / O operation has been performed on a device; Determining, by the hypervisor, that a first instance of the O / S of the plurality of instances of the O / S corresponds to the I / O signal; Providing the I / O signal for the first instance of the O / S; Receiving an acknowledgment signal from the first instance of the O / S to verify that the requested I / O operation has been performed; and Determining an elapsed time by the processor between receiving the I / O signal and receiving the acknowledgment signal. The method of claim 4, further comprising: Determining, by the hypervisor, that a second instance of the O / S is executing on the processor when the I / O signal is received; and Determine by the hypervisor whether the second instance of the O / S should be interrupted to provide the I / O signal for the first instance of the O / S, or whether the second instance of the O / S should be allowed to continue executing becomes. The method of claim 4 or 5, further comprising: Receiving, by the processor, a request to access the device from either an application or an intermediate application executing on the first instance of the O / S. The method of any of claims 4 to 6, further comprising: Generating a subchannel start (SSCH) signal by the first instance of the O / S to request connection of a subchannel of the computer to the unit; and Generating control signals through the subchannel to establish a data transfer path between the subchannel and the unit based on receiving the request to access the unit. The method of claim 5, wherein the I / O signal is an I / O interrupt, and the hypervisor is configured to maintain a plurality of I / O interrupts corresponding to the plurality of instances of the O / I. S corresponds. Computer system for managing multiple instances of an operating system, comprising: a memory divided into a plurality of logical partitions (LPARs), each LPAR configured to execute one of a plurality of instances of an operating system (O / S); a processor configured to detect a reference I / O service time of an I / O operation on a server, measure an actual I / O service time of the I / O operation, and a delay time The virtualization on the server is determined based on the reference I / O service time and the actual I / O service time. The computer system of claim 9, wherein measuring the actual I / O service time of the I / O operation includes monitoring, in real time, the actual I / O service times of real-time I / O operations for each device associated with the device A plurality of LPARs are in communication. The computer system of claim 9 or 10, wherein measuring the actual I / O service time of the I / O operation comprises: Receiving, by the processor, an I / O signal from a subchannel indicating that a requested I / O operation has been performed on a device; Determining, by the hypervisor, that a first instance of the O / S of the plurality of instances of the O / S corresponds to the I / O signal; Providing the I / O signal for the first instance of the O / S; Receiving an acknowledgment signal from the first instance of the O / S to verify that the requested I / O operation has been performed; and Determining an elapsed time by the processor between receiving the I / O signal and receiving the acknowledgment signal. The computer system of claim 11, wherein the processor is configured to determine a second instance of the O / S executed on the processor when the I / O signal is received, and determines whether the second instance of the O / S S should be interrupted to provide the I / O completion completion signal for the first instance of the O / S, or allowed to allow the second instance of the O / S to continue execution. The computer system of any one of claims 9 to 12, wherein the processor is configured to store the delay time in a segment of the memory associated with the subchannel. A computer program product for managing multiple instances of an operating system, the computer program product comprising: a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuitry for performing a method according to any one of claims 1 to 8. A computer program stored on a computer readable medium and loadable into the internal memory of a digital computer having portions of software code for performing the method of any of claims 1 to 8 when the program is run on a computer.

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