DE112012001611T5 - Optimizing the performance of storage adapters - Google Patents

Abstract

A method and a control unit for implementing the performance optimization of memory adapters with concatenated hardware operations that minimize the interactions between hardware and firmware, and a circuit design structure on which the circuit of the relevant control unit resides. The control unit has a plurality of hardware modules; and one or more processors. An event queue is connected to at least one processor and notifies the processor of a variety of predefined events. A control block is used to control an operation in one of the plurality of hardware modules, which also includes the writing of an event queue entry by the hardware module. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the writing of event queue entries to the processor by the hardware module.

Description

Field of the invention

The present invention relates generally to the field of data processing, and more particularly to a method and controller for implementing performance optimization of memory adapters with chained hardware operations that minimize hardware-firmware interactions, and a circuit design structure that houses the circuitry of that particular control unit.

Description of the Related Art

Storage adapters are used to connect a host computer system to peripheral storage I / O devices such as hard disk drives, solid state drives, tape drives, compact disk drives, and the like. Currently, various fast connection systems such as Peripheral Component Interconnect Express (PCIe), Serial Attach SCSI (SAS), Fiber Channel, and InfiniBand are used to connect the host computer system with the storage adapter and the storage adapter with the I / O storage units.

For many years, Hard Disk Drive (HDD) or rotating disk drives have been the predominant storage I / O unit for the permanent storage of computer data requiring online access. Recently, Solid State Drives (SSDs) are gaining in popularity due to their superior performance. In particular, SSDs are usually capable of performing more I / Os per second (IOPS) than HDDs, even though their maximum transmission speed is not always higher than that of HDDs.

US20040162926A1 describes a hard disk drive adapter for a computer system. An intermediate adapter uses a Serial Advanced Technology Attachment (ATA) for data exchange between the central processor and the hard disk drives. The intermediate adapter essentially implements an automatic disk drive mirroring via an immediate RAID 1 or other transfer of disk data via serial ATA.

US20100199039 discloses a method by which a storage adapter controls a redundant array of independent disks (RAID). The method includes examining performance curves of a memory adapter with a write buffer, determining whether an amount of data entering the memory buffer's write buffer has exceeded a threshold, and implementing a policy based on the discovery operation ,

From an operational standpoint, an ideal storage adapter for the system would not be a bottleneck in performance. In reality, however, storage adapters often present a performance bottleneck for the computer system. One effect of the increasing popularity of SSDs is that the storage adapter is becoming an increasingly bottleneck in the computer system.

There is a need for an efficient method and an efficient control unit for implementing performance optimization of memory adapters. There is a need for such a method and controller that are used in conjunction with either HDDs or SSDs, and which significantly reduce the time required for an I / O operation while preserving the required functions of the memory adapter for various arrangements of the present invention Memory adapters and I / O devices of the memory, such as the use of caching of writes, two-controller configurations, and write and read operations on a redundant array of low cost drives (RAID), can be effectively and efficiently maintained.

The terms "controller" and "controller circuit" as used in the following description and claims are to be understood in a broad sense to include an input and output adapter (IOA) and an IO-RAID adapter to which various arrangements of a host computer system and peripheral storage I / O units, among others, hard disk drives, semiconductor drives, tape drives, compact disk drives and the like are connected.

Brief description of the invention

The present invention is intended to provide a method and control unit for realizing the performance optimization of memory adapters with chained hardware operations that minimize the hardware-firmware interactions, and a circuit design structure that houses the circuitry of that control unit. The present invention seeks to provide such a method, control unit and circuit design structure without adverse effects, overcoming many of the disadvantages of the prior art arrangements.

Briefly, it is intended to provide a method and controller for implementing performance optimization of memory adapters with chained hardware operations that minimize hardware-firmware interactions, and a circuit design structure that houses the circuitry of that particular controller. The control unit has a plurality of hardware modules and a processor. An event queue that notifies the processor of a variety of predefined events is connected to the processor. A control block is used to control an operation in one of the plurality of hardware modules, including the writing of an event queue entry by the hardware module. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the writing of event queue entries to the processor by the hardware module.

In accordance with features of the invention, each predefined chain has consecutive control blocks stored in a contiguous memory area. Each control block may be linked to any other control block or to several other control blocks that define a chain of operations. Each predefined chain defines controls that are applied to appropriate hardware modules. Each predefined chain is modifiable to selectively define controls that are applied to the respective hardware modules.

According to features of the invention, each control block has a common header including a control block identifier, a chain position and an identifier of the next control block. The control block's chain position identifies a control block as first in the chain, last in the chain, middle in the linked chain, or as stand-alone. The shared header has a predefined hardware event queue entry that is selectively written when the block is terminated. The predefined hardware event queue entry is written when a standalone control block terminates and when the last control block in the chain terminates. The predefined hardware event queue entry is written when a control block fails with an error.

In accordance with features of the invention, the predefined chain of the plurality of control blocks is executed without any firmware interaction between the initial device and the completion of the series of operations. The predefined chain minimizes the interaction between the hardware modules and the processor and provides a significant reduction in the code path for establishing and terminating each host operation.

Brief description of the drawings

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

1 12 is a schematic block diagram illustrating an exemplary system for implementing performance optimization of memory adapters with chained hardware operations, thereby minimizing hardware-software interactions in accordance with the preferred embodiment;

2A illustrative chained hardware operations thereby minimizing hardware-software interactions according to the preferred embodiment;

2 B Illustrates hardware and firmware interactions of a conventional prior art memory adapter;

3A illustrates an example structure of a control store (CS) having a plurality of consecutive control blocks according to the preferred embodiment;

3B an enhanced hardware and firmware (HW) interface with a plurality of exemplary hardware work queues (HW work queues) and a HW event queue stored in the control store (CS) according to the preferred embodiment;

4A illustrates an exemplary common header of a control block according to the preferred embodiment;

4B illustrate a variety of exemplary control blocks according to the preferred embodiment;

the 5A and 5B describe a flow of hardware logic operations and a flowchart illustrating the exemplary operations illustrate that are performed by a predefined chain of a plurality of the control blocks selectively arranged to realize an exemplary normal RAID 5 parity update according to the preferred embodiment;

the 6A and 6B depicting a flow of hardware logic operations and a flowchart illustrating exemplary operations performed by a predefined chain of a plurality of the control blocks selectively arranged to implement an exemplary normal RAID 6 parity update according to the preferred embodiment;

the 7A and 7B illustrate a flow of hardware logic operations and a flow chart illustrating exemplary operations performed by a pair of predefined chains of a plurality of the control blocks selectively arranged to perform an exemplary RAID 5/6 stripe write (Stripe) stored data block) with cache buffer according to the preferred embodiment; and

8th is a flowchart of a design process used in the design, fabrication and / or testing of semiconductors.

Detailed Description of the Preferred Embodiments

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which illustrate exemplary embodiments by means of which the invention may be practiced. It is understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention.

The terminology used herein is intended solely to describe particular embodiments and is not intended to limit the invention. The singular forms "a / a" and "the" used here also include plurals, unless expressly stated otherwise in the context. It is further understood that the terms "having / having" as used in the present specification refer to the presence of specified features, integers, steps, operations, elements and / or components, but the presence or addition of a or one or more other features, integers, steps, operations, elements, components and / or groups thereof.

In accordance with features of the invention, a method and controller are provided that realize improved performance and performance optimization of memory adapters with chained hardware operations that minimize hardware-firmware interactions, and a circuit design structure that houses the circuitry of that particular controller.

With reference to the drawings, in 1 an input / output adapter and / or an input / output control unit according to the preferred embodiment, shown generally by the reference numeral 100 is designated. The control unit 100 has a semiconductor chip 102 on that with at least one processor complex 104 associated with one or more processors or one or more central processor units (CPUs). 106 having. The control unit 100 has a control store (CS) 108 such as dynamic random access memory (DRAM) near the CPU 106 which provides control block, work queue, and event queue storage. The control unit 100 has a non-volatile backup storage (NV backup storage) 110 and a data store (DS) 112 which provide data and work buffers for setting up and processing control blocks that are executed by, for example, hardware. The control unit 100 has a nonvolatile random access memory (NVRAM) 114 and a flash memory 116 on.

According to features of the invention, the control unit realizes 100 Techniques that uniquely concatenate hardware operations to minimize hardware-firmware interactions with the goal of maximizing performance. The hardware chaining (HW chaining) is completely uneven; asynchronous, requires no synchronization or fixed time window for operations; has a completely free form with any HW modules concatenated with arbitrary HW modules and a processing policy in firmware (FW) allocating HW speeds.

The ECU semiconductor chip 102 has a variety of hardware modules 120 on, for example, a Hardware Direct Memory Access (HDMA) Module (HDMA). 120 , an SIS module 120 , an assignment and assignment cancellation module 120 , an XOR or SOP module (SOP = sum of products, sum of products) 120 , a SAS module (SAS = Serial Attach SCSI) 120 , a module for setting / updating / deleting / mirroring the memory requirement ("S / U / C / M FP" module) (S / U / C / M FP = Set / Update / Clear / Mirror Footprint) 120 and a compression and decompression module (COMP / DECOMP module) 120 ,

In accordance with features of the invention, most of the conventional firmware functionality relocates to HW operations performed by the hardware modules 120 be performed. The hardware modules 120 are completely non-uniform and can be fully expanded by linking any modules with any other activated modules.

As shown, the controller semiconductor chip 102 a corresponding PCIe interface (PCIe = Peripheral Component Interconnect Express) 128 with a fast PCIe system connection between the ECU semiconductor chip 102 and the processor complex 104 and a SAS control unit 130 with a fast SAS system connection between the ECU semiconductor chip 102 and each of the plurality of storage units 132 such as hard disk drives (HDDs) or rotating drives 132 and solid state drives (SSDs) 132 on. A host system 134 is via a fast PCIe system connection to the control unit 100 connected.

For example, DS stores 112 , 8 GB DRAM, volatile or non-volatile pages containing data such as a 4 kB page of data or 8 x 528 bytes of usable data or 64 CAS accesses (66 bytes), a 32-byte cache line (cache line, CL), where there is a CL for each non-volatile page of the write cache in a contiguous area of the DS and a 32-byte parity update footprint (PUFP) memory space on a contiguous area of the DS after the CL area.

The control store (Control Store, CS) 108 stores other structures and control blocks as in the 3A and 3B and in the 4A and 4B illustrated and described with reference to these figures. The control store (CS) 108 has a control block buffer area (CB) (CB) with, for example, 8 MB size and 8 MB alignment, a HW event queue with, for example, 4 MB size and 4 MB alignment, which provides 1 million entries of 4 bytes each , a SIS SEND queue of, for example, 64KB size and 64KB alignment, providing 4000 entries of 16 bytes each, a "list of free indices, volatile" and a "list of free indices, non-volatile" with, for example, 4MB each Size and 4 MB alignment, which provide 1 million entries of 4 bytes each, Work Queue (HQ) work queue (WQ) with, for example, 512 kB size and 512 kB alignment providing 32 WQ of 16 kB each. Other structures in the CS 108 For example, page table index lists of, for example, 4 B and 1 to N have entries of 4 B each, which may be anywhere in the 256 MB space and are often within the CS buffer area of 8 MB, CS destination buffers of 128B alignment, where each is 1KB and can be anywhere in the 256MB space, and an HW-CB of 64B alignment that is within the CS buffer area of 8MB, such as for example in 3A illustrated.

With reference to 2A There are exemplary chained and generally with the reference numeral 200 illustrates hardware operations that minimize interactions between hardware and software, in accordance with the preferred embodiment. The chained hardware operations 200 have a chain 202 a multitude of consecutive operations by the hardware (HW) 204 with an initial interaction with code or firmware (FW) 206 at the initial setup and further interaction with the FW 208 upon completion of the sequence or chain 202 of operations by the HW 204 on.

According to features of the invention, the types of concatenated operations include the operations "allocate buffer", "unblock buffer", "read SAS read XOR", "write SAS" and "set memory requirement for parity update (PUFP)", "delete PUFP", "Mirrored Writing of a PUFP to a Remote Adapter", "Mirrored Writing of Cache Buffer Data to a Remote Adapter," and the like. The following is an example of concatenated operations in a RAID 5 write: a) allocating buffers, b) reading XOR of data, c) setting the PUFP, d) writing data, e) updating parity storage needs, f) reading XOR parity, g) write the parity, h) delete the PUFP and i) cancel buffer allocation.

2 B FIG. 4 illustrates interactions between the hardware and firmware of a prior art memory adapter, which in each of the multiple IOA operations involves interaction between a code or firmware (FW) and hardware. As in 2A shown, reduce the chained hardware operations 200 The invention significantly reduces the length of the firmware path required in an EIA operation. The chained hardware operations 200 of the invention are arranged to minimize interactions between hardware and firmware to maximize performance.

With reference to 3A there is a generally by the reference numeral 300 designated control storage structure (CS structure) according to the preferred embodiment shown. The CS structure has predefined fields, including an offset 302 , a size 304 and a definition 306 belong. The CS structure 300 has a plurality of sequential control blocks (HW-CB) Nos. 1 to 17, 308 , which are selectively arranged in a predefined chain, for example, to minimize the interaction between hardware and firmware, so that the hardware modules 120 only a minimum of event queue entries to the processor complex 104 write.

According to features of the invention, each predefined chain has successive ones control blocks 308 on that in a contiguous memory CS 108 are stored as in 3A illustrated. Each predefined chain defines controls based on corresponding hardware modules 120 be applied. Every control block 308 can with any other control block 308 be linked, which defines a chain of operations. For example, each buffer in the CS structure is 2 kb in size. The FW passes these buffers to the HW by writing CS indices to the global hardware work queue. The HW returns a response to the FW by writing to the HW event queue, as in 3B illustrated and described with reference thereto.

With reference to 3B there is a generally by the reference numeral 350 designated interface between hardware (HW) and firmware (FW) according to the preferred embodiment shown. The HW / FW interface 350 has a HW block 352 with the variety of HW modules 120 in the controller chip 102 and a firmware block 354 on that with the cpu 106 in the processor complex 104 provided. The HW / FW interface 350 has a global hardware work queue 356 such as a small embedded array in the controller chip 102 on. The global HW work queue 356 is with each of a variety of hardware work queues 358 connected.

Each of the variety of hardware work queues 358 is to appropriate hardware modules 1 to N 120 in the chip 102 applied. A HW event queue 360 is with the firmware (FW) 354 connected and puts the processor complex 104 Final results ready. A work queue manager 362 in the control unit chip 102 is with each of the variety of hardware work queues 358 and each of the plurality of hardware modules 1 to N 120 and the HW event queue 360 connected. The global HW work queue 356 has a queuing input associated with the FW 354 in the processor complex 104 is connected, and a queue input that is connected to the work queue manager 362 in the control unit chip 102 connected is. The work queue manager 362 and the global HW work queue 356 set the HW event queue 360 an entrance ready. The HW work queues 358 and the HW event queue 360 are in the control store (CS) 108 saved.

The hardware modules 120 are designed to receive data from the host system 134 via DMA to the control unit 100 recall. The HDMA module 120 gets data from the host system 134 by DMA on the CS 108 or the DS 112 and then notifies the FW of the HW event queue 360 , The hardware modules 120 are designed to perform some functions in parallel, for example, 8 or 12 SAS modules 120 , 4 host DMA modules 120 and the same. The hardware modules 120 are designed to perform multiple operations on different steps of the same function, for example calling an HDMA module 120 Data from the host system 134 at the same time as another HDMA module 120 via DMA other data on the host system 134 retrieves.

According to features of the invention, each control block 308 a common header including a control block identifier, a chain position and an identifier of the next control block. The control block's chain position identifies a control block as first in the chain, last in the chain, middle in the linked chain, or as stand-alone. The shared header has a predefined hardware event queue entry that is selectively written when the block is terminated. The predefined hardware event queue entry is written when a standalone control block terminates and when the last control block in the chain terminates. The predefined hardware event queue entry is written if the control block fails with an error.

With reference also to 4A there is a generally by the reference numeral 400 designated common head of the control block 308 shown in the preferred embodiment. Each control block header 400 has a byte 0, 402 , for example, a reserved identifier or drive identifier.

Each control block header 400 has a byte 1, 404 , for example, "selectively write HW event queue entry". The predefined hardware event queue entry 404 is selectively written when the block is terminated. The predefined hardware event queue entry 404 is written when a self-contained control block is terminated or when a last control block in the chain is terminated. The predefined hardware event queue entry 404 is written if the control block fails with an error.

Each control block header 400 has a byte 2, 406 including a "Update HW event queue entry" and an identifier (ID) 406 of the next control block module. In the 3B HW event queue shown 360 is a first-in-first-out ring buffer (FIFO) in the CS 108 , The HW event queue 360 is aligned with a 4 MB address boundary and is 4 MB in size. This size allows the queue to record the history of the last 1 million events. For each event, the HW writes 4-byte entries 406 in the HW event queue. The FW reads the entries periodically and removes them from the HW event queue.

Each control block header 400 has a byte 3, 408 including a control block module identifier and a chain position 408 on, and he has a head address (ADR) 410 on. The chain position 408 of the control block identifies a chain position of the control block as first in the chain, last in the chain, middle in the linked chain, or as stand-alone.

Running chained or standalone CBs begins when an entry is made from the global HW work queue 356 and through the work queue manager 362 sent to one of the HW work queues connected to one of the hardware modules 120 are connected. The hardware modules 120 in 3B can use a chain of control blocks, HW-CB Nos. 1 to 17, 308 , perform as in 3A shown and in the 4A and 4B further illustrated. The HW-CB 308 Links to the next operation in the predefined chain if the current module 120 finished the execution of its operation in the predefined chain. The mechanism to the execution of the next HW-CB 308 Finally, starting in a corresponding predefined chain is done by the appropriate hardware module 120 triggered. The hardware module 120 adds on completion of running its HW-CB 308 in the chain 64 to his current CB address in the CS 108 then added the new CB address in the CS 108 forms directly to the next 64-byte offset 302 in the in 3A shown chain refers. This new CB address is provided by the hardware module 120 along with the field labeled "ID of the next linked CB" to the work queue manager 362 to hand over. The work queue manager 362 then adds a new entry to the global HW-WQ 356 added. If this entry is from the global HW-WQ 356 then the next CB in the predefined chain is executed and sent to a HW work queue 358 Posted.

With reference to 4B There is shown a variety of exemplary control blocks according to the preferred embodiment. The control blocks 308 indicate:
Set / update / delete / mirror memory requirements - F
Set / delete / mirror CL - M
Send SAS-Op - p
Release assigned pages - D
Execute SOP module - X
Assign Pages - A
Send HDMA Op - H and
Comp / decompression - C

Set / refresh / delete / mirror memory block - F " 308 are among the CS actions taken by the HW module or the "Set / Update / Delete / Mirror Memory" module 120 for example, when setting the reading of 32 bytes from the CS 108 , reading 4 bytes each, reading 32 bytes, writing 32 bytes to the DS 112 and writing 32 bytes to the NVRAM 114 and optionally, mirroring to a remotely located controller; when updating the reading of 32 bytes from the CS 108 or DS 112 , writing 32 bytes to the DS 112 and writing 32 bytes to the NVRAM 114 and optionally, mirroring to a remotely located controller; as well as deleting the writing of 32 bytes on the DS 112 and writing 32 bytes to the NVRAM 114 and optionally mirroring to a remote control unit.

At the control block "CL set / delete / mirror - M" 308 are among the CS actions taken by the HW module or by the "CL set / delete / mirror" module 120 for example, when setting the reading of 32 bytes from the CS 108 , reading 4 bytes each, reading 32 bytes, writing 32 bytes to the DS 112 and at 4K each, reading the 4-byte index and possibly reading 4K from the DS 112 and optionally, mirroring to a remotely located controller; and when clearing at 4K each, reading the 4-byte index and writing 32 bytes to the DS 112 and optionally mirroring to a remote control unit.

At the control block "SAS-Op - S" 308 and the "Send HDMA Op - H" are among the CS actions taken by the hardware module or the corresponding SAS module 120 and the HDMA module 120 For example, at 4K each, the 4-byte index is read by the SAS module 120 and the HDMA module 120 , and the HDMA module 120 reads or writes 4K from / to the DS 112 , and the SAS module may read and write 4K to / from the DS 112 , The HDMA module 120 moves data between the DS 112 and the host system 134 , and the SAS module 120 moves data between the DS 112 and the storage units 132 ,

For the control blocks "Release Assigned Pages - D" and "Assign Pages - A" 308 belong to the CS Actions that pick up from the HW or the "Mapping / Mapping" module 120 for example, 4K each reading 4 bytes and writing 4 bytes.

With the control module "Execute SOP module - X" 308 belong to the CS actions, those from the HW or XOR module 120 be carried out for For example, with 4K of the source (for each source) reading 4 bytes and reading 4K of the DS 112 ; and at 4K each of the target (at each target) reading 4 bytes and writing 4K from DS 112 , The sum-of-products module (SOP module) 120 takes as input 0 to N source page lists and 0 to M destination page lists as well as an N × M array of multipliers. For example, N = 18 and M = 2. For each 4K, the first source page is read by the DRAM and the first set of M multipliers is applied to each byte. The resulting data is stored on summation buffers of the chip in M. Each subsequent source page is multiplied by its associated M multipliers, and the product is XORed to the corresponding summation buffers. After each source has been processed, the summing buffers are written out to the appropriate M destination buffers. Afterwards the next 4 K will be started. This allows the calculation of an XOR with N inputs so that the RAID 5 parity can be calculated, or in the case of RAID 6 P and Q redundancy data on Reed Solomon basis, the simultaneous multiply XOR of M equations ( at N inputs).

At the control block "Comp / Decompression - C" 308 belong to the CS actions that come from the HW or the "Komp / Decomp" module 120 for example, each 4K (compressed data may be <4K) reading 4 bytes and reading 4K (or less in decompression) of DS 112 and writing 4K (or less in decompression) from DS 112 , and optionally, other operations may be performed.

A corresponding exemplary chain of control blocks 308 according to the preferred embodiment is in the 5A . 6A and 7A illustrated and described with reference to each of these figures.

With reference to the 5A and 5B There are a generally by the reference numeral 500 designated sequence of operations of hardware logic and in 5B a flow chart illustrating exemplary operations that are generally indicated by a reference numeral 520 designated predefined chain of a plurality of the control blocks, which are selectively arranged to realize an exemplary normal RAID 5 parity update according to the preferred embodiment. In 5A belong to the chain 520 of the control block 308 the control blocks A1, S2, F3, S4, F5, S6, S7, F8, D9, M10 and D11, as in 4B defined together with the appropriate steps 1 to 11, which in the 5A and 5B are shown.

5A has a local CS 502 a first or local control unit 100A up, over a HW module 505 with a remote DS 504 and a remote NVRAM 506 a second or remote control unit 100B connected is. The local CS 502 is via the HW module 505 with a local NVRAM 508 and with a local DS 510 the first control unit 100A connected. A plurality of buffers of a first control unit 100A to the buffer A 512 , Buffer B 514 and buffer C 516 , belong, is with a plate P. 518 and a plate X 520 connected.

In step 1, the A list and B list for buffer A become 512 and buffer B 514 at control block A1 of the chain 520 in CS local 502 in 5A and like a block 540 in 5B assigned or filled. Next, in step 2, data from the disk X becomes 520 read and with the buffer C 516 linked via XOR, and the result is at control block S2 of the chain 520 at 2 XOR in 5A and like a block 542 in 5B indicated in buffer B 514 stored. In step 3, control block F3 becomes the chain 520 the setting of the through the HW module 505 , Line 3, read memory requirement from the HW module 505 on the DS 510 and NVRAM 508 at the local control unit 100A and setting the memory requirement at the remote control unit 100B from the HW module 505 on the DS 504 and NVRAM 506 in 5A and like a block 544 in 5B specified performed.

In step 4, the writing of data from the buffer C 516 on the plate X 520 at control block S4 of the chain 520 , Line 4, from the buffer C 516 on the plate X 520 in 5A and like a block 546 in 5B specified performed. Next, in step 5, at control block F5, the chain 520 updating the through the HW module 505 , Line 5, Read memory requirement from the HW module 505 on the DS 510 and NVRAM 508 at the local control unit 100A and updating the memory requirement at the remote control unit 100B from the HW module 505 on the DS 504 and NVRAM 506 in 5A and like a block 547 in 5B specified performed. Next, in step 6, data from the disk P 518 read and with the buffer B 514 linked via XOR, and the result is at control block S6 of the chain 520 at 6 XOR in 5A and like a block 548 in 5B indicated in buffer A 512 stored. Next, in step 7, the writing of data from the buffer A becomes 512 on the plate P 518 at control block S7 of the chain 520 in line 7 from the buffer A 512 on the plate P 518 in 5A and like a block 550 in 5B specified performed.

In step 8, the HW module 505 deleting the memory required, by at control block F8 of the chain 520 in line 8 zeros from the HW module 505 on the DS 510 and NVRAM 508 at the local control unit 100A and clearing the memory requirement at the remote control unit 100B at line 8 from the HW module 505 on the DS 504 and NVRAM 506 in 5A and like a block 552 in 5B specified performed. In step 9, the assignment of the A list and B list for buffer A becomes 512 and buffer B 514 at control block D9 of the chain 520 in CS local 502 in 5A and like a block 554 in 5B specified or the lists are emptied. In step 10, the HW module 505 for the cache buffer, sending "Mirrored Clear" is performed by writing zeros to the CL in the local DS 510 delete and the CL in the remote DS 504 at control block M10 of the chain 520 , displayed in line 10, from the HW module 505 on the local DS 510 and the remotely located DS 504 in 5A and as with block 556 in 5B specified to delete. In step 11, the allocation of page lists for buffer C 516 at control block D11 of the chain 520 in CS local 502 in 5A and like a block 558 in 5B specified or the lists are emptied.

With reference to the 6A and 6B There are a generally by the reference numeral 600 designated sequence of operations of hardware logic and in 6B a flow chart illustrating exemplary operations that are generally indicated by a reference numeral 630 designated predefined chain of a plurality of the control blocks, which are selectively arranged to realize an exemplary normal RAID 6 parity update according to the preferred embodiment. In 6A belong to the chain 630 of the control block 308 the control blocks A1, S2, F3, S4, S5, S6, S7, F8, S9, S10, F11, D12, M13 and D14, as in FIG 4B together with the corresponding steps 1 to 14 defined in the 6A and 6B are shown.

6A has a local CS 602 a first or local control unit 100A on top of a hardware module 605 with a remote DS 604 and a remote NVRAM 606 a second or remote control unit 100B connected is. The local CS 602 is about the hardware module 605 with a local NVRAM 608 and with a local DS 610 the first control unit 100A connected. A plurality of buffers of a first control unit 100A to the buffer A 612 , Buffer B 614 and buffer C 616 , belong, is with a plate P. 618 , a plate X 620 and a plate Q 620 connected.

In step 1, the A list and B list for buffer A become 612 and buffer B 614 at control block A1 of the chain 630 in CS local 602 in 6A and like a block 640 in 6B assigned or filled. Next, in step 2, data from the disk X becomes 620 read and with the buffer C 616 linked via XOR, and the result is at control block S2 of the chain 630 at 2 XOR in 6A and like a block 642 in 6B indicated in buffer B 614 stored. In step 3, control block F3 becomes the chain 630 the setting of the through the HW module 605 , Line 3, read memory requirement from the HW module 605 on the DS 610 and NVRAM 608 at the local control unit 100A and setting the memory requirement at the remote control unit 100B from the HW module 605 on the DS 604 and NVRAM 606 in 6A and like a block 644 in 6B specified performed.

In step 4, the writing of data from the buffer C 616 on the plate X 630 at control block S4 of the chain 630 , Line 4, from the buffer C 616 on the plate X 630 in 6A and like a block 646 in 6B specified performed. Next, in step 5, data from the disk P 618 read and with the buffer B 614 over XOR with multiplied data from buffer B 614 linked, and the result is at control block S5 of the chain 630 at 5 XOR in 6A and a multiply-read XOR link B with A as in a block 648 in 6B indicated in buffer A 612 stored. In step 6, control block F6 becomes the chain 630 updating the through the HW module 605 , Line 6, Read memory requirement from the HW module 605 on the DS 610 and NVRAM 608 at the local control unit 100A and updating the memory requirement at the remote control unit 100B , Line 6, from the HW module 605 on the DS 604 and NVRAM 606 in 6A and like a block 650 in 6B specified performed.

Next, in step 7, the writing of data from the buffer A becomes 612 on the plate P 618 at control block S7 of the chain 630 in line 7 from the buffer A 612 on the plate P 618 in 6A and like a block 652 in 6B specified performed. In step 8, control block F8 becomes the chain 630 updating the through the HW module 605 , Line 8, Read memory requirement from the HW module 605 on the DS 610 and NVRAM 608 at the local control unit 100A and updating the memory requirement at the remote control unit 100B , Line 8, from the HW module 605 on the remote DS 604 and remotely located NVRAM 606 in 6A and like a block 654 in 6B specified performed. Next, in step 9, data from the disk Q 622 read and XOR with multiplied data from buffer B 614 linked, and that The result is at control block S9 of the chain 630 at 9 XOR in 6A and by multiplying-reading-XORing B to A as in a block 656 in 6B indicated in buffer A 612 stored. Next, in step 10, the writing of data from the buffer A becomes 612 on the plate Q 622 at control block S10 of the chain 630 in line 10 from the buffer A 612 on the plate Q 622 in 6A and like a block 658 in 5B specified performed.

In step 11, the HW module 505 the memory requirement is cleared by the control block F11 of the chain 630 in line 11 zeros from the HW module 605 on the DS 610 and NVRAM 608 at the local control unit 100A and clearing the memory requirement at the remote control unit 100B in line 11 from the HW module 605 on the remote DS 604 and remotely located NVRAM 606 in 6A and like a block 660 in 6B specified performed. In step 11, the allocations of the A list and B list for buffer A become 612 and buffer B 614 at control block D12 of the chain 630 in CS local 602 in 6A and like a block 662 in 6B specified or the lists are emptied. In step 13, the HW module 505 for the cache buffer, sending "Mirrored Clear" is performed by writing zeros to the CL in the local DS 610 delete and the CL in the remote DS 604 at control block M13 of the chain 630 in line 13 from the HW module 605 on the local DS 610 and the remotely located DS 604 in 6A and as with block 664 in 6B specified to delete. In step 14, the allocation of page lists for buffer C 616 at control block D14 of the chain 630 in CS local 610 in 6A and like a block 666 in 6B specified or the lists are emptied.

With reference to the 7A and 7B There are a generally by the reference numeral 700 designated sequence of operations of hardware logic and in 7B a flow chart illustrating exemplary operations that are generally indicated by a reference numeral 720 designated predefined chain pair of a plurality of the control blocks, which are selectively arranged to realize an exemplary RAID 5/6 stripe cache memory write according to the preferred embodiment. In 7A belong to the chain pair 720 of the control block 308 the control blocks A1, X2, F3, S4 and the control blocks F6, D7, M8 and D9, by an interaction of the firmware (FW) 5 with the control blocks 308 are separated, as in 4B together with the corresponding steps 1 to 9 defined in the 7A and 7B are shown.

7A has a local CS 702 a first or local control unit 100A on top of a hardware module 705 with a remote DS 704 and a remote NVRAM 706 a second or remote control unit 100B connected is. The local CS 702 is via the HW module 705 with a local NVRAM 708 and with a local DS 710 the first control unit 100A connected. Cache memory data 712 The first control unit comes with a variety of drives 714 and a sum-of-products module (SOP module) connected via the parity buffer 718 with a pair of drives 714 connected is. RAID-6 has two parity buffers 718 and two drives 714 while RAID-5 has a parity buffer 718 and a drive 714 can be used.

In step 1, if necessary, page lists at control block A1 of the chain pair 720 in CS local 702 in 7A and like a block 730 in 7B assigned or filled. Next, in step 2, "execute SOP module" and parity or P and Q redundancy data is performed on control block X2 of the chain pair 720 at 2 SOP 716 in 7A and like a block 732 in 7B specified generated.

In step 3, at control block F3 of the chain pair 720 the setting of the through the HW module 705 , Line 3, read memory requirement from the HW module 705 on the DS 710 and NVRAM 708 at the local control unit 100A and setting the memory requirement at the remote control unit 100B , Line 3, from the HW module 705 on the remote DS 704 and NVRAM 706 in 7A and like a block 734 in 7B specified performed.

In step 4, performing the overlapped writing of data on multiple drives 714 , as with several parallel control blocks S4 of the chain pair 720 , Line 4, from cache staging data 712 on multiple drives 714 in 7A and as with block 736 in 7B provided. Optionally, the firmware accepts the detection of completions of the multiple SAS operations, as with a block FW 5 between the pair of chains 720 indicated and like a block 738 in 7B specified. The firmware operation on FW 5 might be on a different hardware module 120 be implemented.

In step 6, the HW module 705 the deletion of the memory required carried out by at control block F6 of the chain 720 in line 6 zeros from the HW module 705 on the DS 710 and NVRAM 708 at the local control unit 100A and clearing the memory requirement at the remote control unit 100B in line 6 from the HW module 705 on the remote DS 704 and remotely located NVRAM 706 in 7A and like a block 740 in 7B specified performed. In step 7, if necessary, the assignment of page lists at control block D7 of the chain 720 in CS local 702 in 7A and like a block 742 in 7B specified or the lists are emptied. In step 8, updating the cache to clear the CL is performed by the hardware module 705 Zeros on the local DS 710 and clear the CL on the remote DS 704 at control block M8 of the chain pair 720 in line 8 from the hardware module 705 on the local DS 710 and the remotely located DS 704 in 7A and as with block 744 in 7B specified writes. In step 9, the allocation of cache page lists at control block D9 of the chain pair 720 in CS local 710 in 7A and like a block 746 in 7B specified or the lists are emptied.

8th shows a block diagram of an exemplary design process 800 , The design process 800 may vary depending on the type of IC to be designed. For example, a design flow may be 800 to build an application specific IC (ASIC) from a design flow 800 for the design of a standard component. The design structure 802 is preferably an input to a design process 804 and may come from an IP provider, a cores development company, or another development company, or may come from the designer or from other sources. The design structure 802 assigns the circuits 100 . 200 . 300 . 308 . 350 . 400 . 500 . 600 . 700 in the form of schemas or HDL, a hardware description language, for example, Verilog, VHDL, C, and the like. The design structure 802 may be included in one or more machine-readable media. For example, the design structure may be a text file or a graphical representation of the circuits 100 . 200 . 300 . 308 . 350 . 400 . 500 . 600 . 700 be. Preferably, the design process 804 the circuit 100 synthetic in a netlist 806 represents or sets the circuit 100 into a netlist 806 um, which is the netlist 806 for example, is a list of lines, transistors, logic gates, control circuits, I / Os, models, etc., which describes the connections to other elements and circuits in the integrated circuit design and is recorded on at least one machine-readable medium. This can be an iterative process involving the netlist 806 synthetically regenerated once or several times depending on the design specifications and parameters for the circuit.

The design process 804 can have the use of a variety of inputs; for example, input values from library elements 808 which may contain a lot of frequently used elements, circuits and units including models, layouts and symbolic representations for a particular manufacturing technology such as different technology nodes, 32nm, 45nm, 90nm and the like, design specifications 810 , Description data 812 , Verification data 814 , Design rules 816 and audit data files 818 which may include test samples and other test information. To the design process 804 may further include, for example, standard circuit design processes such as timing analysis and verification, design rule checking, placement and routing operations, and the like. Those skilled in the art of integrated circuit design will appreciate the scope of possible electronic aids and design automation applications that are involved in the design process 804 may be used without departing from the scope and spirit of the invention. The design structure of the invention is not limited to any particular design process.

The design process 804 preferably one in the 1 . 2A . 3A . 3B . 4A . 4B . 5A . 5B . 6A . 6B . 7A and 7B 4 shows an embodiment of the invention together with any other designs or data of integrated circuits (if applicable) in a second design structure 820 around. The design structure 820 resides on a storage medium in a data format used for the exchange of integrated circuit layout data, for example information stored in GDSII (GDS2), GL1, OASIS or any other suitable format suitable for storing such design structures , The design structure 820 may include information such as inspection data files, design content files, manufacturing data, layout parameters, conduits, metal levels, vias, shapes, routing data, and any other data needed by a semiconductor manufacturer to obtain one of 1 . 2A . 3A . 3B . 4A . 4B . 5A . 5B . 6A . 6B . 7A and 7B shown embodiments of the invention produce. The design structure 820 can then go to a stage 822 go over in which the design structure 820 issued on tape, released for manufacturing, released for a mask making business, sent to another design company, sent back to the customer, and the like.

Although the present invention has been described with reference to the details of the embodiments of the invention shown in the drawings, these details are not intended to limit the scope of the invention claimed in the appended claims.

Claims (25)

Data storage system, comprising: a control unit comprising a variety of hardware modules; a processor; an event queue associated with the processor that notifies the processor of a variety of predefined events; a control block for controlling an operation in one of the plurality of hardware modules, including the writing of an event queue entry by the hardware module; and a plurality of the control blocks selectively arranged in a predefined chain to minimize the writing of event queue entries to the processor by the hardware module. The data storage system of claim 1, wherein the predefined chain comprises successive control blocks stored in a contiguous storage area. The data storage system of claim 1 or claim 2, wherein each control block is selectively connected to any other control block. A data storage system as claimed in any one of the preceding claims, wherein the control block is selectively connected to a plurality of other control blocks for parallel sending of controls applied to corresponding hardware modules. The data storage system of any of the preceding claims, wherein the predefined chain defines controls that are applied to corresponding hardware modules. The data storage system of any one of the preceding claims, wherein the control block comprises a common control block header having a control block identifier, a control block's chain position, and an identifier of the next control block. The data storage system of claim 6, wherein the control block identifier identifies one of the plurality of hardware modules and the identifier of the next control block identifies one of the plurality of hardware modules. The data storage system of claim 6 or claim 7, wherein the control block's chain position identifies a control block as first in the chain, last in the chain, middle in the linked chain, or as standalone. The data storage system of any one of claims 6 to 8, wherein the common control block header has a predefined hardware event queue entry which is selectively written when the control block is terminated. The data storage system of any one of claims 6 to 9, wherein the common control block header has a predefined hardware event queue entry, wherein the predefined hardware event queue entry is written when a stand-alone control block terminates or when a last control block in the chain is terminated. The data storage system of any one of claims 6 to 10, wherein a predefined hardware event queue entry is written if a control block fails with an error. The data storage system of any one of the preceding claims, wherein the predefined chain of the plurality of control blocks is executed by corresponding hardware modules without any processor interaction. A method for implementing the optimization of the performance of memory adapters in a data storage system, comprising: Providing a control unit comprising a plurality of hardware modules; and a processor; Providing an event queue associated with the processor that notifies the processor of a plurality of predefined events; Providing a control block for controlling an operation in one of the plurality of hardware modules, including the writing of an event queue entry by the hardware module; and Providing a plurality of the control blocks selectively arranged in a predefined chain to minimize the writing of event queue entries to the processor by the hardware module. The method of claim 13, wherein providing a control block comprises providing a common control block header having a control block identifier, a control block's chain position, and an identifier of the next control block. The method of claim 13 or claim 14, wherein providing an event queue also includes writing an event queue entry in response to the termination of a self-contained control block and in response to the completion of a last control block in the chain. The method of claim 13, wherein providing an event queue comprises writing an event queue entry in response to a control block failing with an error. The method of any of claims 13 to 16, wherein providing a plurality of the control blocks selectively arranged in a predefined chain comprises storing consecutive control blocks in dynamic random access memory (DRAM). The method of claim 13, wherein providing a plurality of the control blocks comprises corresponding hardware modules executing the plurality of control blocks in the predefined chain without any processor interaction. A controller for realizing optimization of performance of storage adapters in a data storage system, comprising: a processor; a variety of hardware modules; an event queue associated with the processor that notifies the processor of a variety of predefined events; a control block for controlling an operation in one of the plurality of hardware modules, including the writing of an event queue entry by the hardware module; and a plurality of the control blocks selectively arranged in a predefined chain; wherein the predefined chain is executed by corresponding hardware modules without any processor interaction. The control unit of claim 19, wherein the control block comprises a common control block header having a control block identifier, a control block's chain position, and an identifier of the next control block. A control unit according to claim 19 or claim 20, wherein the predefined chain comprises successive control blocks stored in a contiguous storage area. A design structure embodied in a machine-readable medium used in a design process, the design structure comprising: a controller circuit materially embodied on the machine-readable medium used in the design process, the controller circuit serving to optimize the performance of storage adapters in a storage system and comprising the controller circuitry: a variety of hardware modules; a processor; an event queue associated with the processor that notifies the processor of a variety of predefined events; a control block for controlling an operation in one of the plurality of hardware modules, including the writing of an event queue entry by the hardware module; and a plurality of the control blocks selectively arranged in a predefined chain to minimize the writing of event queue entries to the processor by the hardware module, wherein the design structure, when read and used in the manufacture of a semiconductor chip, generates a chip comprising the chip Control unit circuit has. The design structure of claim 22, wherein the design structure comprises a netlist describing the controller circuitry. A design structure according to claim 22 or claim 23, wherein the design structure is on a storage medium as a data format used for exchanging integrated circuit layout data. A design structure according to any one of claims 22 to 24, wherein the design structure comprises at least one of test data files, description data, verification data, or design specifications.

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