DE112010004322T5 - Vorhersagen und Vermeiden von Operand-Speichervorgang-Vergleich-Gefahren in Mikroprozessoren mit abweichender Reihenfolge - Google Patents

Vorhersagen und Vermeiden von Operand-Speichervorgang-Vergleich-Gefahren in Mikroprozessoren mit abweichender Reihenfolge Download PDF

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Publication number
DE112010004322T5
DE112010004322T5 DE112010004322T DE112010004322T DE112010004322T5 DE 112010004322 T5 DE112010004322 T5 DE 112010004322T5 DE 112010004322 T DE112010004322 T DE 112010004322T DE 112010004322 T DE112010004322 T DE 112010004322T DE 112010004322 T5 DE112010004322 T5 DE 112010004322T5
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Germany
Prior art keywords
instruction
load
store
hazard
entry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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DE112010004322T
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German (de)
English (en)
Inventor
Brian William Thompto
Christian Jacobi
Gregory William Alexander
Khary Jason Alexander
Brian William Curran
James Russell Mitchell
Jonathan Ting Hsieh
Brian Robert Prasky
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International Business Machines Corp
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International Business Machines Corp
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Publication date
Priority claimed from US12/644,923 external-priority patent/US8468325B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE112010004322T5 publication Critical patent/DE112010004322T5/de
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE112010004322T 2009-12-22 2010-12-13 Vorhersagen und Vermeiden von Operand-Speichervorgang-Vergleich-Gefahren in Mikroprozessoren mit abweichender Reihenfolge Ceased DE112010004322T5 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US12/644,923 US8468325B2 (en) 2009-12-22 2009-12-22 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
US12/644,923 2009-12-22
US12/822,960 2010-06-24
US12/822,960 US8521992B2 (en) 2009-12-22 2010-06-24 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors
PCT/EP2010/069496 WO2011076602A1 (en) 2009-12-22 2010-12-13 Predicting and avoiding operand-store-compare hazards in out-of-order microprocessors

Publications (1)

Publication Number Publication Date
DE112010004322T5 true DE112010004322T5 (de) 2012-08-23

Family

ID=43416544

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112010004322T Ceased DE112010004322T5 (de) 2009-12-22 2010-12-13 Vorhersagen und Vermeiden von Operand-Speichervorgang-Vergleich-Gefahren in Mikroprozessoren mit abweichender Reihenfolge

Country Status (6)

Country Link
US (2) US8521992B2 (https=)
JP (2) JP5850532B2 (https=)
CN (1) CN102652304B (https=)
DE (1) DE112010004322T5 (https=)
GB (1) GB2486155B (https=)
WO (1) WO2011076602A1 (https=)

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US10606590B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Effective address based load store unit in out of order processors
US10606591B2 (en) 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10394558B2 (en) 2017-10-06 2019-08-27 International Business Machines Corporation Executing load-store operations without address translation hardware per load-store unit port
US10572256B2 (en) 2017-10-06 2020-02-25 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
US10929140B2 (en) 2017-11-30 2021-02-23 International Business Machines Corporation Scalable dependency matrix with a single summary bit in an out-of-order processor
US10942747B2 (en) 2017-11-30 2021-03-09 International Business Machines Corporation Head and tail pointer manipulation in a first-in-first-out issue queue
US10572264B2 (en) 2017-11-30 2020-02-25 International Business Machines Corporation Completing coalesced global completion table entries in an out-of-order processor
US10884753B2 (en) 2017-11-30 2021-01-05 International Business Machines Corporation Issue queue with dynamic shifting between ports
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US10802829B2 (en) 2017-11-30 2020-10-13 International Business Machines Corporation Scalable dependency matrix with wake-up columns for long latency instructions in an out-of-order processor
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JP7151439B2 (ja) * 2018-12-06 2022-10-12 富士通株式会社 演算処理装置および演算処理装置の制御方法
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Also Published As

Publication number Publication date
US8521992B2 (en) 2013-08-27
GB201206367D0 (en) 2012-05-23
US20110153986A1 (en) 2011-06-23
JP5850532B2 (ja) 2016-02-03
JP2013515306A (ja) 2013-05-02
US20130318330A1 (en) 2013-11-28
WO2011076602A1 (en) 2011-06-30
US9430235B2 (en) 2016-08-30
CN102652304B (zh) 2015-04-15
JP6143306B2 (ja) 2017-06-07
JP2015228237A (ja) 2015-12-17
CN102652304A (zh) 2012-08-29
GB2486155B (en) 2017-04-19
GB2486155A (en) 2012-06-06

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