DE1096088B - Computing device with dynamic register - Google Patents

Description

GERMAN

The invention relates to a computing device in which the summands in a dynamic Registers can be stored in decimal format.

A computing device has already been proposed in which the summands are divided into two dynamic Registers can be stored decimally and a second next to the first read and write head of the result register The write head is arranged in the running direction at a distance from a digit, which the previous entries in a digit position is deleted if another additional value entry is made in this digit position the first head is impossible. In these devices, a memory element is each based on the scanning of the element itself actuated. For this purpose, highly sensitive scanning means are necessary, since they determine the memory status of the scanned memory element with regard to the point in time of the switchover in advance need to recognize.

The invention is now based on the object of eliminating this disadvantage and creating a device by which the switching over of a memory element no longer depends on the scanning of the same, but on the Sampling of the storage element in front of this depends, so that between the two processes one practically evaluable time span arises.

To solve the problem, it is proposed according to the invention that the computing device at which the summands can be stored decimally in a dynamic register and in addition to a first write and Read head a second write head is provided, characterized in that one in the memory register digit value to be entered an entry in all digit positions scanned one after the other regardless of the respective memory status concerned triggers and that by scanning the first digit position in which no digit value is entered, with effect the entry is interrupted by the next digit.

Further details of the invention emerge from the description of an exemplary embodiment of the subject matter of the invention, which is shown in FIGS. 1 and 2 of the Drawing is shown schematically. It shows

1 shows a part of a dynamic register and the time signal generator of a decimal calculator,

Fig. 2 is a block diagram of the decimal calculator.

The object of the invention is suitable for use in a wide variety of computing devices, such as B. in pulse counting devices, computing devices of various types, four-species computing devices inter alia, but is described below only as applied to a computing device. That General calculation methods can be found in the description of German patent specification 1,070,412.

Computing device
with dynamic register

Applicant:

Ing.C.Olivetti & C ₁ SpA,
Ivrea (Italy)

Representative: Dipl.-Ing. H.-H. Wey, patent attorney,
Munich 22, Widenmayerstr. 49

Claimed priority:
Italy from February 3, 1954

Dr.-Ing. Luciano Cignetti and Dr. Siegfried Reisch,

Ivrea (Italy),
have been named as inventors

The memory 1 shown in Fig. 1 is designed as a magnetic memory and developed in a straight line. The memory consists of η places Dl, D2 ... Dn, each of which is subdivided into the sub- locations IR1, IR2 ... IRn of an input register IR and the sub-locations AR1 AR2 ... ARn of a result register AR . The input register IR is used to record the addend or subtrahend. The result register is used to record the amount to which the addend is added or from which the subtrahend is subtracted.

Although the magnetic track constitutes an uninterrupted recording medium, those shown in FIG. 1 are shown here Storage cells considered finite. The hatched rectangles show the amount27 in the input register and the amount 34 in the result register. The hatched rectangles each represent one with a positive one Memory cell occupied by a magnetic point.

The memory 1 is cyclically moved past a switching head 2 in the direction of the higher positions, the has two magnetic heads 3 and 4 spaced apart from one another by a sub-location.

Three magnetic tracks 5, 6 and 7, which are used to transmit the time signals, are rigidly connected to the memory 1. The magnetic heads which are not shown and are arranged opposite these magnetic tracks are in a row with the magnetic head 3. The emitted time signals m and the control signals d or the control signals r adjusted by a sub-digit are the usual point signals.

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As can be seen from Fig. 2, the magnetic head 3 has gate 22, while the writing coil 11 is still able to use a reading coil 8 and a writing coil 11 thanks to the delay To write memory cell,
cells, the output 9 is energized when scanning by the excitation of the sum gate 22 on the one hand negative magnetic points, ie from unoccupied memory 5, the flip-flop 21 is switched to the state I and cells, the output 10 is energized. The writing coil 11, on the other hand, writes positive via the alternative gate 20, the flip-flop 25, when it is switched to state II at input 15, or negative, so that the buzz when it is excited at input 16. gate 27 no longer lets the write pulses through. the

The reference numerals 19, 22, 23, 24, 27, 28, 29, 32 and 33 rest when scanning occupied memory cells from

each designate a sum goal; the reference numerals 20 io output 9 emitted pulses remain ineffective,

and 26 each designate an alternative gate. It is because the sum gate 22 is now closed.

are known components. The transition of the magnetic head 3 from the lower

The reference numerals 17, 21, 25 and 31 provide a respective spot IRL on sub-location ARL emitted places flip-flop represents the two below with I or marked II signal r switches the flip-flop 17 to the state II to can take drawn states of equilibrium. In 15 and switches the flip-flop 25, FIG. Since this shows the one on which the flip-flop is excited again by the excitation of the sum gate 27, this input is now switched over, or positive points are written for each of the sum gate 28.
Flip-flop output shows the state through which the output concerned is excited when scanning occupied memory cells. With regard to the ao output 9 transmitted pulses remain ineffective, flip-flops 17, which are excited by the position signals d and r because the sum gate 22 is closed. If the reading is to be noted that this flip-flop in each coil 8 indicates on the first unoccupied memory cell of ARI instant whether the magnetic head meets opposite, so it excites via the output 10 the summing gate of a / i? . a ^^ - substation is located. 19, while the writing coil 11 thanks to the delay

The three switches 18, 30 and 34 are rigid among themselves 35 device 35 is still able to connect a positive point in order to write this unoccupied memory cell at the same time from the addition shown. The total position [A) in the subtraction position (S) adjusted gate 19 now switches over the alternative gate 20 to be able to flip. Flop 25 to state II, so that the sum goal 27

At the output of the reading coil 8 there is a known one which no longer lets write pulses through. aside from that

Arranged delay device 35, which aims to switch the summator 19 to the flip-flop 21 on the 30

the pulses returned by the reading coil 8 via the sum state I, so that the further from the output 10

gates 19 or 22 and the alternative gate 20 to the flip-sent pulses remain ineffective, since the

Flop 25 are sent, with a delay to over- Summentor 19 is now closed.

average, which is not greater than the time span between the transition of the magnetic head 3 from the lower

the scanning of two successive storage positions A Rl on the lower position IR 2 outgassed positions

elements. signal d switches the flip-flops 17 and 25 back to the

Another delay device is back between state I, and the device is thus ready to

Summentors 23 or 24 and the alternative gate 20 to process the new memory control,

watch so that when the position signals d If the flip-flop 25

or r the alternative gate 20 does not change to state II in comparison to the alternative 40 due to a lack of occupied memory cells

gate 26, the flip-flop 25 is energized with a delay. is switched, the flip-flop 21 remains in

As in the German patent specification 1 070 412 state I, and the next position signal r switches

described, the flip-flop 25 is on the addition of its units via the gates 23 and 20

resolved addend additively from the input register to state II. During the whole of the next

Transfer result register. 45 Subsection .4 2? »The writing coil 11 thus remains unexcited.

According to the invention, the magnetic head 3 begins in each case. At the end of the lower position ARn, the position signal i switches

in a lower position of the input register IR as long as the flip-flop 25 via the alternative gate 26 to the

Write negative points until a negative point returns to the state I and thus enables the excitement of the

first occupied memory cell has been written; Writing coil 11.

similarly, the magnetic head 3 begins in each case in a 5 ° alike, if in the course of a sub- location ARn

Substitute positive for result register AR as long as flip-flop 25 is not due to lack of unoccupied memory cells

To write points until a positive point is switched to the first to state II, that remains

unused memory cell has been written. The down flip-flop 21 in state II, on which it is in the next

Sampling of a memory cell that has one polarity, lower sub- digit IRn had been switched. this

that of the polarity of the point 55 written at the same time is the case with a tens transmission. At the end of

is opposite, the writing thus represents the sub- digit ARn switches the digit signal d via the

of these points from the next memory cell at gates 24 and 20 to the flip-flop 25 to the state II,

a. so that during the whole sub- digit IR (w + 1) the

The write coil 11 sent out at the beginning of a storage cycle remains unexcited. The next position signal d switches the flip-flops 17, 25 and 31; 60 position signal r switches over to the state I via the alternative gate 26. As long as the magnetic head 3 scans flip-flop 25 back to state I and enables negative points in the lower position IR1 , the excitation of the writing coil 11 is again excited.
Read coil 8 via the output 10 to the summator 19, in the present case of a tens transmission that switches through the state I of the flip-flops 17 or 21, however, which is excluded at the beginning of the sub- digit IR (w + l). At the same time, the point signals m 65 excite the position signal d sent via the summing gate 24, which via the summing gates 27 and 29 converts the input 13 of the flip-flop 31 to state II. The input 16 write coil 11, as a result of which negative points are written into the off-write coil 14 for each point-scanned memory cell. When signal m excites and writes the reading coil 8 to the first occupied memory cell from the fully occupied sub- location ARn in each case a negative IR1 in all memory cells, it excites the summation point down via output 9.

When the magnetic head 3 passes from the lower point IR (n + a) to the lower point AR [n - \ - i) the suramentor is closed by the new state II of the flip-flop 17, and the writing coil 14 is no longer excited. If the substation AR (m + 1) has an unoccupied memory cell, the pulse sent by the output 10 switches the flip-flop 25 to state II via the gates 19 and 20. As a result, the sum gate 27 is closed and the flip-flop 21 is also switched back to state I. The flip-flop 21 has thus been able to store the pulse that was received from the substation IRn and triggered the tens transmission. At the beginning of the next sub-digit 72? (n + 2) switches the position signal 6, the flip-flop 25 via the gate 25 and the flip-flop 31 via the sum gate 32 back to the state I, and the device is thus ready to process the new memory location.

On the other hand, should the substation / Ii? (w + 1) do not have an unoccupied memory cell, the flip-flop 25 ao remains in state I for the entire lower position and is only switched to state II by the next position signal d. The same digit signal ^{1 also} switches the flip-flop 17 back to the state I, and the write coil 14 writes down negative points again. In summary, it can be said that as long as the flip-flop 21 assumes the state II, negative points are written in the scanned subordinate positions of the result register AR , while the assigned subordinate positions of the input register remain unchanged.

To carry out a subtraction, the device also works according to that in the German patent specification 1 070 412 described method according to which the subtrahend resolved into its units is subtractive is transferred from the input register to the result register.

According to the invention, the magnetic head 3 begins to write negative points in each sub-position of the input register IR until a negative point is written in an occupied memory cell; The magnetic head 3 moves in exactly the same way in the subordinate positions of the result register AR.

To carry out the subtraction, the switches 18, 30 and 34 are set to the subtraction position S beforehand.

As long as the magnetic head 3 scans a sub-location IRn of the input register IR , the device operates in the manner described for the addition. When the magnetic head 3 passes over to the lower point ARn , negative points are now also written into the lower point ARn via the sum gate 27 and the input 13. The summator 19 then switches the flip-flop 25 to state II when reading the first occupied memory cell.

If a completely unoccupied lower digit of the result register AR triggers a tens transmission, positive points are now written into the lower digit ARn via the sum gate 33 and the input 15 of the write coil 14.

If all higher subordinate positions of the result register AR are also completely unoccupied, ie if the minuend is smaller than the subtrahend, then these subordinate positions are fully assigned positive points. The flip-flop 21, which remained in state II during the memory cycle, can only store the pulse received from the sub-unit IRn during the next memory cycle as a result of the scanning of the first occupied memory cell of the result register AR . There is thus the known transfer of the fleeing one from the upper memory location to the lowest memory location, whereby on the one hand the device receives an indication that the balance is negative and on the other hand the direct negative balance can be ejected by reading the negative points instead of the positive points.

Claims (2)

Patent claims: 1. Computing device in which the summands can be stored decimally in a dynamic register and a second write head is provided in addition to a first read and write head, characterized in that a digit value to be entered in the memory register is an entry in all digits scanned one after the other regardless of the respective relevant memory state triggers and that by scanning the first digit in which no digit value is entered, the entry is interrupted with effect from the next digit. 2. Apparatus according to claim 1, characterized in that the setting by delay means the switchover is delayed by a period of time that is not longer than the period of time between the scanning of two successive memory elements. 1 sheet of drawings © 009 680/276 12.60