DE1076746B - Electronic switching network for telecommunications, especially telephone switching systems - Google Patents

Description

The present invention relates to assemblies for establishing connections on electronic Paths preferably in systems in which any input can be switched to any Outputs should take place and in which the control and holding circuits according to a time division multiplex method work.

If the task of electronically operating switching systems, namely those used in automatic telephone exchanges, is to achieve a connection between η incoming lines and m further lines, a number of η m electronic gates are provided, as is known, in the form a matrix of η rows and m columns are arranged. The electronic gate circuits used here contain two connections, each of which leads to one of the circuits to be connected to one another, and generally a special connection for the control. Such an electronic gate circuit is generally symmetrical with regard to its transmission properties, and in the following description the two connections which lead to the lines to be connected to one another are designated with connection 1 and connection 2. Each of the η incoming lines is connected to the connection 1 of each of the η switching elements of a row, while each of the m further lines is connected to the connection 2 of each switching element of a column. Means are now provided to control the electronic gate circuits individually and to maintain the through-connection between the incoming and outgoing lines -

to obtain. The electronic gate circuits used generally have either Due to their properties or as a result of the operation of the circuits connected to them two certain conditions in which there is either a very high or a have very low impedance. In certain cases these two states are stable, and As a result, the electronic gate circuit exhibits storage properties: it is sufficient to provide a specific Signal to bring them into the corresponding of these two defined states by it then remains there until it is returned to its original state by another incoming signal is brought back. This applies e.g. B. on gas diodes, in which, in addition to the through-connection Connections no special control electrodes need to be provided.

When the electronic gate circuit is implemented in one of the usual forms and for example Elektr onis this sustaining network for telecommunications, in particular telephone exchange systems

Applicant:

International standard

Electric Corporation,

New York, N.Y. (V. St. A.)

Representative: Dipl.-Ing. H. Ciaessen, patent attorney, Stuttgart-Zuffenhausen, Hellmuth-Hirth-Str. 42

Claimed priority: France, December 27, 1957

Jacques Henri Dejean, Malakoff, Seine (France), has been named as the inventor

works with vacuum tubes, transistors or diodes are generally suitable means of generation the corresponding control potentials provided in such a way that the electronic gate circuit is blocked in the absence of a control signal, d. H. between the two lying at their connections Lines with their high impedance value is effective. If one wishes to achieve a connection, so · this electronic gate circuit must be continuously switched on during the entire switching time Control signal are applied.

It has also already been proposed that every electronic gate circuit of this type be a bistable Assign switching element and control the gate circuit via this; in this case it is sufficient to use the bistable The switching element can only be influenced by a brief signal.

It has also already been proposed to equip a switching matrix of this type with a memory, in which the corresponding markings are recorded, for example the marking the row and the column through which the high permeability, i.e. H. so on connection, electronic gate circuit to be controlled is specified. In this case you are forced to have so many

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Reading circles to be provided / as simultaneous connections now those gates that are opposite should or can be produced. the connection you want, or the connection you want

Task of the invention described below assigned buffer elements at the same time

it is now a simple circuit to be controlled.

Establishing and maintaining through-switching 5 The invention will now be explained on the basis of an example between, for example, η inputs and m:
To create exits. Fig. 1 shows the control circuit for the gate

For this purpose, as with the known connections, a schematic representation;

Orders corresponding to the arbitrary through-connection of η Fig. 2 shows the structure of a through-connection

Inputs to m outputs are used · - · where m are two elements.

For example, smaller than η and p through-connections In the following, those points should be possible at the same time, where p is smaller than in a through-connection option from the input side - an arrangement of η Crossing circuits are provided, each of which is designated an entry point. Each such crossing electrode, an output electrode and a control point is contained in an electronic gate circuit in an electrode. These gate circuits are arranged in connection with an individual memory element in such a way that each input forms the entire arrangement in which the information used to control the gate circuit can be connected to each of its outputs during a relative period. Furthermore, switching means are provided in order to save a short time, for example gate switching by applying a corresponding 20 for the duration of a fraction of a second. A potential in the absence of a special control such element can either be closed by an electrical signal. Depending on whether a control niche gate circuit of classic form occurs in connection with a signal at the control electrode or not, it is formed with a memory that is only effective for a short time, i.e. each electronic gate circuit is formed between or by a gate circuit that has either one in its input and its output 25 itself has the properties to control the very low or very high impedance. In contrast to these known arrangements, which are to be stored at Ver; In the latter case, this use of non-bistable switching means would behave like a monostable trigger circuit, require continuous control signals or vice versa must be, are taken when, namely "closed" or "permeable", the electronic switching network according to the invention, corresponding to a low or a high Impe, neither bistable switching means nor danzwert between their two connections. You need continuous control signals. This is DA can for example consist of a diode or of a by achieved that the message channels are formed via a 35 transistor, turned on in the latter way multiple, however, the position of a symmetric transistor particular advantages to manufacturers case and maintaining \ ^r onnectivity provides .

Serving auxiliary information in a time multiple. Means are assigned to such a gate circuit,

are given, and that at the switching points they are used in the absence of a control signal

Switching means are provided which hold the 40 in the form of a bias in the state that one

Brief impulses incoming auxiliary information interruption of the connection between the two

evaluate for a continuous connection. Connections. The simultaneously assigned

There are according to a further training switching storage circuit acts as a monostable trigger circuit and

means are provided for temporary storage, which can be structured in the usual way. In this

For example, from monostable flip-flop elements. In this case, this accumulator consists of a capacitor,

and each connection point indi- whose discharge current flows through a resistor and

are viduell assigned; They are used to control the elec-

electrode of the gate circuit opens a control voltage to tronic gate circuit. This simplest solution

transmit, for a time that is the same or solution is explained in more detail with reference to FIG. 2,

is only a little longer than a period of duration t, 5 ° The switching network in the real sense,

wherein the application of such control voltage by which the through-connection of incoming Leitun- η

Control signal is triggered, which is permitted in relation to t gen on m further lines

is short-lived. There are also switching means in the usual way and has

provided to this the preliminary storage ffm crossing points, which are in the form of a matrix too

serving intermediate storage are arranged according to the herzu- 55 η rows and m columns. Everyone

connecting connections to transmit control signals, crossing point comprises two switching electrodes or

their duration in each case independent of t and in the connections 1 and 2 and a control electrode. Every other

ratio to t is small, and the line coming from the line leads to the η in one line.

repeat quenz l / i the whole time, orderly connections 1 of the crossing points,

during which the connection should exist. 60 while each of the continuing lines to the

During each of the successive periods m connections 2 of the respective column belonging to

from the duration t the electronic gate scarf leads to intersection points.

lines or the storage means assigned to them, with In Fig. 2 is to simplify the representation

the help of which a through-connection is effected, one after the other. the four incoming lines and three

each other a control signal. Here, within a 65 continuing lines, which are shown in Fig. 1

such period of each electronic gate circuit is set, only one line is shown. With Lh is

assigned a specific time slot. The line that passes through a transformer is also designated inside

half of each such period of each input or TLh is at the £ -th intersection of line h , and

a certain time slot is assigned to each output. with Jk the further line that goes through the

Corresponding to the connections to be made, the 70 formator TJk at the-th crossing point of the column k

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lies. Only a single crossing point is formed, at which each magnetic circuit represents two, which in the case under consideration is formed by the symmetric transistor Ghk adopting different magnetization states Conclusions 1 and 2 alternately correspond to the role of the collector of the number 0. Such magnetic Kippoder the emitter take over and accordingly on 5 circles are already known, so that here the multiple conductors h and k are connected, the writing can be dispensed with. However, on the one hand, line Lh and, on the other hand, must correspond to further ^ when using a storage system, in the case of the leading line Jk. The base of the Infor transistor Ghk stored by the reading at the same time represents the control electrode and the mation is deleted, of course the control will normally be formed via the resistors RAhk and io circuit for the reading in such a way that RBhk is brought to a positive potential, which from - at the same time the restoration of the just enough to block the transistor Ghk. The partially read information is guaranteed. The capacitor-like arrangements lying parallel to the resistor RAhk are also already known and, as will be shown later, Chk at a potential is not the subject of the present invention. The size and polarity of which are suitable for the marking of the lines, in order to compensate for the bias voltage and with which the establishment of a connection based on the transistor Ghk is desired on a sufficiently negative basis, are shown schematically by CE , to bring tive potential to unlock it. In order to effect the connection to a further target between the multiple conductors h and k , the conductive connection must of course be established, so the partial memory of the memory M corresponding to the identification of the incoming line is charged in the capacitor Chk in a manner to be shown later . The charge on the capacitor must be marked. If the signal voltage is on a range around that occurs at the base of the transistor Ghk of the lines Ll to L 3, the potential is given during a given. Timings to make d 11 to d 13 of the evaluation matrix MD 1 brace sufficiently negative. In the sequence 25 are bound, may the reading correspond to the identification recorded in the capacitor is then reloaded in periodic sequence in the partial memory, as long as they are started in this way. If the reading of a partial memory is set, the connection should be maintained. triggered in the memory M , then the in Fig. 1 a control circuit is shown, which allows lines 5 * 11 and 5 "12 occurring outputs to selectively establish connections and 30 signals to the trigger circuits BS 1 and BS 2 and to maintain, The tilting circuits BSI and 55 * 2 lines, as shown in FIG - GC denotes a pulse generator, of the three tilt len conditions; in the latter case, a circles Cl ₁ must be fed C 2 and CZ the tilt functions 35 are connected is controlled by the pulse generator GC particular manner of a counting circuit; give provide post-reset circuit. , which is marked in Fig. 1 with GR one next to the other in binary representation over their outputs For example, for the further generator GR , leading connections as well as an identification must of course be designed so that the delay caused by it is to be used as a control 40 below the period duration of the pulse gene signal, which will be shown later. rator GC generated pulse frequency is. The time of Fig. 1 is with regard to a simplified space, during which the coming from the memory M representation is an embodiment with only four of the signals in the trigger circuits BSi and BS2 lines and. Three further entries are recorded, of course, must be laid out for reasons. Each of which consists of two conductors is shorter in duration than the period of time that separates the two, outputs St ₁ S2 and S3 that form the counting chain, control pulses from the pulse generator GC . The deaden trigger circles lead to an evaluation matrix from the trigger circles BSI and BS2 coming MjDI with four outputs. The outputs d 11, dl2 signals control a second evaluation matrix MDI, and c? 13 correspond to the three secondary encryption whose four outputs d21bis-d24 the four arrive bonds, while the output of DL4 correspond to a comparison 50 the lines. A controls more strongly via the outputs cf 11. In the here underlying mono- to ti 13 of the first evaluation matrix MJD 1 and the fold case ill on the outputs (, xfl2 and outputs ^ 21 to CF24 the second evaluation matrix d 13 of the first evaluation matrix MD 1 each MD2, a third evaluation matrix of normal signal voltage occur when the identifier 1 O, version controlled with toroidal cores; the third 0 1 or 1 1 occur on the input side, while on 55 evaluation matrix comprises four rows and three columns the output d 14, for example, a signal voltage and consists of twelve toroidal cores ill to IL3 occurs i21 as soon as the indicator is given 0 0. to ΐ23, ί31 to ί33 and ί41 to ΐ43. Each of the outputs dll, d 12 and d 13 are connected via lines ring cores, for example, i22, is on the one hand an output Ll to L 3 and connected to the reading circuit of a memory M of the first evaluation matrix MD1, e.g. rende lines are provided. Assigned to each matrix MDI, e.g. iZ22. The winding partial memory comprises as many memory elements as the winding attached to each toroidal core to identify the incoming lines and the currents supplied by the evaluation matrices, taking into account the codes used, are selected so that when all rings are required. The two cores on which this is based are located in a certain magnetization play with four incoming lines and with a backlog two binary digits wise on the output d 12, and the simultaneous one to be measured. The memory M can receive a signal coming from the second evaluation matrix of magnetic circuits in a matrix arrangement 70 MD 2 , for example on the

Output d22, only the toroidal core i22 assigned to these two outputs switches to the other magnetization state. On the other hand, a circuit is fed via the amplifier ^ which consists of a series connection of one winding each of all toroidal cores. The direction of the winding of this last-mentioned winding and the magnitude and direction of the current supplied by the amplifier ^ are chosen so that when a signal occurs at the output α! 14 all toroidal cores, which were previously brought into the magnetization state corresponding to the recording of the number 1, now tilt back into the state corresponding to the recording of a 0 and therefore generate a signal voltage in the respectively assigned reading winding. is

For the sake of simplicity, only the reading winding assigned to the toroidal core i22 is shown in FIG. 1 Jkf 22 shown, but in reality it goes without saying each toroidal core is provided with a reading winding in the same way.

Each toroidal core ill to i43 of the third evaluation matrix is now assigned to an electronic gate circuit as shown in FIG.

The mode of operation of the arrangement shown in FIG. 1 is as follows: First of all, it is assumed that at the beginning all toroidal cores ill to i43 were in the magnetic state corresponding to the recording of a 0, ie that all electronic gate circuits of the through-connection network are blocked. This can easily be achieved by applying a signal to the output ^ 14 from an external source, not shown, before the arrangement is put into operation. If one now wishes to establish a conductive connection between a certain incoming line and a certain outgoing line, then via the trigger circuit C 1 the identification of the incoming line in question is recorded in the partial memory assigned to the outgoing line. If one wishes, for example by switching on the further line 2, which is the output d 12 of the second evaluation matrix MD2 corresponds, one causes via the Tilt Circuit Cl recording the identifier of the third incoming trunk, that is, "1 1" in which the z. B. second further line corresponding partial memory of the memory M. The output signals of the pulse generator GC cause, as already explained above, that signal voltages appear successively at the outputs d 11, dl2, d 13 and d 14 of the first evaluation matrix MD 1. As soon as a signal appears at an output that corresponds to a further line to which a connection is to be made, for example at output d 12, it causes the corresponding partial memory to be read in the first evaluation matrix MD 1 and, subsequently, the immediate recording of the Identifier of the 'required line in the two breakover circles BS 1 and BS 2, in the case considered here, "1 1". The transmission of this identifier to the second evaluation matrix MD 2 has the effect that a signal appears on output d 23 which corresponds to the desired line; the magnetic breakover circuit or toroidal core i32 consequently goes into its magnetization state corresponding to the number 1. The breakover circuits BSI and BS2 return to their rest position and can now be used to identify another incoming line marked in a partial memory corresponding to a continuing line. In this way, during a scanning process that encompasses all further lines, all of those toroidal cores ill to i43 for which through-connection is required are brought into the corresponding magnetization state. When the scanning process is completed, a signal occurs at the output ti 14 which causes all toroidal cores, which have been brought into the magnetic state corresponding to the number 1, to their original state, which causes a signal voltage to appear on the winding of each toroidal core, the one to be established or to be maintained through connection corresponds.

In Fig. 2, Thk denotes that toroidal core which corresponds to the incoming line h and the outgoing line k. This toroidal core carries, on the one hand, the windings dl k and d2h, which correspond to the outputs of the evaluation matrices MD 1 and MD 2, and a read winding Le, which is connected to the output L of the amplifier A. The direction of winding of these windings is indicated by a point, the direction of current in the windings by an arrow. The toroidal core Thk also carries a further winding C, which is connected in series to the two terminals of the capacitor Chk via a diode Dhk. If the toroidal core is in its rest position and no signals have previously been received, then the capacitor Chk is only charged to a very low potential, since the current in the resistors RAjk and RBjk is very low; the transistor Ghk is blocked. If the ring core Thk contrast placed 1 corresponding magnetic state in which the digit, because occur at the windings Dik and D2H two to accumulated control signals., The diode Dh flowing on the winding C due to the high resistance of no current. In the case of the reading taking place at the end of the sampling period, on the other hand, a current is sent through the reading winding Le , which causes the toroidal core to be reset to its zero state. As a result, a voltage is generated in the winding C , on the basis of which a charging current flows to the capacitor Chk and charges it up to such a voltage that the unlocking threshold of the base of the transistor RBhk is reached and exceeded. The mode of operation just described, which is triggered by the current flowing through the reading winding, is the same for all intersection points whose toroidal cores were brought into the magnetic state corresponding to number 1 during the previous sampling period. The capacitor Chk discharges during the following sampling period via the resistor RAhk \ the time constant of this discharge circuit is dimensioned such that the voltage at the terminals of the capacitor remains high enough during the entire following sampling period to keep the associated transistor unlocked. These processes are repeated during each sampling period, and the connection is automatically maintained in this way as long as the identification of the line is recorded in the partial memory corresponding to the outgoing connection.

If one uses commercially available symmetrical transistors, one has to use a capacitor Chk with a duration of the sampling period of 1 millisecond, the capacitance of which is of the order of 7 x 1.0 ~ ⁸ farads and the charging voltage of which is about 10 V, while the resistors RAhk and RBhk are about on the order of

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20,000 ohms. The power to be supplied by the amplifier A is approximately in the order of 0.1 W per further line.

In the examples shown with reference to FIGS. 1 and 2, a symmetrical transistor was assumed. This represents a particularly favorable solution to the present problem. Of course, you can use an electronic gate circuit of another known type instead, for example Semiconductor diodes.

It goes without saying that the idea of the invention is applied not limited to the example described above, but also leaves others Applications too.

Claims (7)

PATENT CLAIMS: 1. Electronic through-switching network for telecommunications, in particular telephone exchanges, characterized in that the communication channels through a multiple through ao tet, the auxiliary information used to establish and maintain the connections, however, are given in a time multiple, and that switching means (Chk in Fig. 2) are provided, which evaluate the incoming auxiliary information in the form of brief pulses for continuous switching. 2. switching network according to claim 1, characterized in that as switching means monostable tilting elements are used. 3. switching network according to claim 2, characterized in that as switching means symmetrical transistors are used, which in the quiescent state by a corresponding one lying at the base Potential are blocked. 4. switching network according to claim 2, characterized in that the switching points Switching means are assigned, which arrive in the form of short-term pulses Evaluate auxiliary information with the help of a delay process for continuous switching. 5. Switching network according to claim 4, characterized in that as delay switching means a capacitor is provided in each case, which is based on the short-term auxiliary information charged to a voltage value that compensates for the blocking potential and via a resistor is discharged, and that the initial value of the capacitor voltage, the capacitor and the resistance are dimensioned so that the capacitor voltage up the switching element keeps unlocked for the arrival of the next auxiliary information. 6. switching network according to claim 1, characterized in that for evaluating the Auxiliary information is assigned a monostable or bistable tilting element to each switching point is, on the one hand, an element of the time division system which supplies the auxiliary information represents and on the other hand acts on the switching means to be controlled. 7. switching network according to claim 6, characterized in that the evaluation of the auxiliary information the switching points assigned toggle elements in turn in the time multiple through the interaction of scanning elements (counting chains) and memory arrangements to store the required information according to one of those known per se Coincidence method can be controlled. 1 sheet of drawings © 909 758/117 2.