DE10361934B3 - Quantum electronics nanocomponent has charge zone provided by nanocluster below window opening in insulation provided as etched ion track - Google Patents

Abstract

Nanocomponent has a concentric clustered charge zone (CA) provided in an insulation layer (IL) between a window opening (W) and at least two electrodes above and below the charge zone, a tunnel barrier (TB) provided between the charge zone and each of the electrodes. The window opening is provided as an etched ion track (P), the charge zone provided by at least one metallic or semiconductor nanocluster (NC) and the tunnel barriers provided by regions of the insulation layer above and below the nanocluster(s). An independent claim for a manufacture of a quantum electronics nanocomponent is also included.

Description

The The invention relates to a quantum electronic nanodevice with a concentric in an insulating layer below a window opening arranged clustered charge zone and at least two electrodes above and below the clustered charge zone, wherein between the clustered charge zone and the two electrodes each arranged a tunnel barrier is, and methods for its production.

One The focus of nanotechnology is nanoelectronics, in which various Concepts for the use of the electronic properties of nanostructures for the diverse Applications of a future Information technology to be investigated. Today's CMOS electronics can be considered one of the most important factors of today's technology be considered. Currently the switching speeds are doubling every three years the microprocessors. From a certain point in time, however, it is foreseeable that also alternative technologies to the CMOS process in nanoelectronics To be introduced. As pure CMOS devices with increasing Miniaturization is at its physical limits it is necessary to timely supplementary or to provide function-expanding technology concepts. The Nanotechnology is already of considerable importance in the field of CMOS electronics today Importance. Today there are transistors with gate lengths of 40 nm and a component size of 90 nm shortly before the product launch. In the course of further miniaturization of CMOS technology are also in the next A multitude of research-intensive nanotechnological problems to overcome. Become in molecular electronics as a subarea of nanoelectronics Streams within of a molecule or between individual molecules connected. Here are the reversibility of such switching operations, the Switching speed, scaling, contacting and the Particular attention should be paid to the manufacturing process. First applications however, are not based on the use of individual molecules for logical or for Memory functions, but it will be layers of the functional molecules formed as an ensemble already implements each one by itself have used switching function. The long term goal is molecular electronics an ultimate miniaturization with device sizes the scale of less nm with very high performance.

Esaki- or tunnel diodes and single-electron transistors ("single electron transistor "SET) are quantum electronic nanodevices that function in their function on the extremely fast based on quantum mechanical tunneling effect. This promises over conventional Components a significant increase in speed. adversely So far, there are hardly any transistor concepts. Likewise that depends Behavior of the tunnel elements very much of the geometry of the component from. The quantum mechanical tunnel effect becomes quantization the charge transfer from an electrode to a nanocluster through a tunnel barrier exploited. The smaller the cluster, the larger the band gap. While at very big Clusters in the μm range the energy gain of the cluster by taking an electron so small is that it competes with thermal fluctuations and therefore is not visible (except by cooling to very low temperatures), exceeds the energy gain at enough small clusters (below some 10 nm to 20 nm) the thermal Energy by far, so this effect even at room temperature clearly occurs and therefore used technologically in principle can be. However, the technological realization of such Structure with conventional Techniques very expensive. Because today's common Lithography in the range below 100 nm fails, these become Structures have not yet been used industrially. It is known however, a SET structure using an atomic force microscope by Oxidation of selected individual To create atoms manually. Such techniques are today mature and very modern, but even with automation the manipulation for time and cost reasons never for a mass production of such Components suitable.

From the German patent DE 197 57 327 C1 , from which the present invention proceeds as the closest prior art, a generic quantum electronic nanodevice is known, which consists of a sequence of lower electrode, n-doped charge zone and upper electrode based on a p-doped silicon substrate. Between the semiconducting n-doped, clustered charge zone and the two metallic electrodes, two Schottky contacts are formed as thin tunneling barriers due to the occurring band bending in the semiconductor. Thus, only tunnel structures with two contacts can be realized, which are not controllable (tunnel diode-like structures). For the production of the known nanodevice element, an insulating layer SiO _{2 is first} formed on the p-doped silicon substrate by oxidation. By large-scale, high-dose implantation of Co-ions of predetermined energy, a conductive cobalt silicide layer CoSi _{2 is constructed} as a lower electrode in the p-doped substrate at a small distance below the insulating layer. Then, by means of a lithography, mask or sputtering method, a small window opening (below 100 nm) is etched into the insulating layer and the entire substrate, including the etched one Window steamed with a thick Au layer as upper electrode. In a subsequent implantation with annealing of As ions in the substrate between the insulating layer and the upper electrode, the area under the window becomes an n-doped region and forms the charge zone, which as a whole forms a cluster. Here, the annealing serves only to bring the doping on lattice sites, so that the material here is well n-type and thus provides a contrast to the p environment. At the intended low n-type doping, Schottky contacts now form between the two metallic electrodes and the semiconducting charge zone, ie depletion zones of electrons which serve as tunneling barriers are formed by migration of the boundary electrons from the semiconductor into the metal. Upon application of a voltage between the two electrodes, when the breakdown voltage to an electrode is exceeded, an electron current which depends on the size of the charge zone is introduced into the charge zone. If its capacity is filled and the breakdown voltage to other electrode reached, the electrons flow away therefrom. The current can thus flow through the nanodevice in both directions. With a correspondingly small window opening or charge zone (about 10 nm thick, about 15 × 15 nm in size), only a single electron will tunnel through each. With the given structuring methods, it is not possible to produce such a small charge zone based on the previous structuring of the window opening. Furthermore, two low energy high dose implants are needed to form the lower electrode and the charge zone. In addition, the layer thickness of the insulator layer must be strictly adhered to, since there are no insulator tunnel barriers.

From the German patent application DE 101 42 913 A1 For example, an electronic nanodevice in the form of a controllable transistor arrangement is known, which is based on an ion track etched throughout in a polymer film composite as an insulation layer. Upper and lower electrodes on the top and bottom of the insulating layer are conductively connected to an isolated semiconductor layer in the ion track. The further electrode required for the transistor control is formed by a metal foil in the middle of the polymer film composite. Although dimensions of the order of 30 nm can be realized in the described component by the use of etched ion traces, only transistor structures which are based on the field effect with a multiple-electron conduction (MESFET, MOSFET) are described.

González-Varona et al., Appl. Phys., Lett., Vol. 82 (13), pp. 4,194,954, issued to González-Varona, et al., "Control of tunnel oxide thickness in nanocrystal array .2151-2152, March 31, 2003) describe Si nanoclusters embedded in silicon dioxide (SiO ₂ ) for the fabrication of memory arrays, which, in contrast to today's floating gate technologies, open up the possibility of Si nanocluster arrays faster write speeds at lower injection voltages, very low degradation due to the absence of hot carrier injection, longer retention times, lower lateral leakage currents, and the inherent ability to downscale to single electron devices. The paper investigates the electronic efficiency of nanoclusters in thin SiO ₂ layers t produced by implantation of 15 keV Si ⁺ ions with a fluence of 2 × 10 ¹⁶ cm ^-2 and subsequent annealing and passivation steps. The devices made in the publication are macroscopic planar structures that can be understood as a parallel connection of billions of interacting SETs. It is shown that typical tunneling effects occur in the current-voltage characteristic. An optimal charge uptake of the generated Si nanoclusters with typically 3 nm diameter is achieved at layer thicknesses of 30 nm and an optimal storage time at layer thicknesses of 40 nm.

Starting from the generic quantum electronic nanostructure with a contacted in an insulating layer window opening and an underlying charge zone and the method for its preparation according to the DE 197 57 327 C1 The object of the invention is to specify an alternative quantum-electronic nanodevice in which a single-electron line is reliably ensured and which is easy to produce. In addition, a larger component diversity is to be achieved. Furthermore, alternative methods for the production of such a quantum electronic nano-device are to be specified, which is simple and economical, and with high accuracy and flexible feasible. As a solution to the problem with regard to the quantum electronic nanostructure element, it is provided according to the invention that the window opening is formed as an ion track which is not continuously etched in the insulation layer and the clustered charge zone of at least one metallic nanocluster and the tunnel barriers of layer regions of the insulation layer above and below the at least one metallic nanoclusters are formed. Advantageous developments can be found in the dependent claims. The solutions to the problem with respect to the alternative manufacturing process can be found in the three alternative method claims. Again, advantageous developments are shown in the respective subclaims. In the following the invention and its advantageous developments are explained in detail. Details of the preferred production methods can be found in the special description part.

With The invention provides a new concept for ion trace-based production of quantum electronic nanodevices, in particular tunnel diodes and SETs, presented. The new concept eliminates the known concepts some of the shortcomings so far occurring. The invention uses etched for the first time Ion traces for the targeted response of a single conductive nanocluster. Thus, the disadvantage of the above-mentioned González-Varona et al. cited Publication avoided, in which a multiplicity of interacting SETs simultaneously was measured. With the invention, novel tunnel structure geometries created, especially new tunnel diodes and SETs. The with the invention claimed tunnel diodes can much smaller (up to a minimum of about 10 nm to 20 nm in diameter) than the ones currently produced. The with the invention claimed single electron transistors can be fast, in large quantities for the first time and compatible with conventional silicon electronics become. The production of these nano-devices will be explained below various production methods described.

The devices proposed by the invention are relatively easy to manufacture and can be integrated into classical Si electronics. With the method of bombarding the insulator layer with heavy ions, the invention makes it possible to produce very small windows and thus precisely definable nanopatterns that can be minimized in size, so that the most important prerequisite for a single-electron component is created by increasing the capacitance of the nanocluster and so that the height of the electron current can be precisely controlled down to a single electron in wide ranges. Instead of a semiconducting charge zone below a relatively large window, the invention uses at least one metallic cluster which is located below an ion track etched in the form of a bottom hole. The ion track is thus used as a guide for positioning the charge zone. Since the window size determines the size of the charge zone, the use of an etched ion trace can create a very small charge zone of the diameter of the single ion trace. In this case, the charge zone lies in the middle of the insulation layer in dependence on the applied energy of the implanted metal ions, so that above and below it insulation barriers are formed in the insulation layer. Thus, it is not necessary to set the thickness of the insulation layer with high precision, but the width of the isolation barriers can be determined by the height of the charge zone as a function of the kinetic energy spectrum of the projectiles during implantation, while preserving the quantum mechanical effect, which depends on the cluster size (see Introduction). to be determined. In addition, the lower electrode is not implanted, but is easily on the bottom of the insulating layer, which also acts as a supporting substrate. By contrast, in the case of the invention, only one low-energy high-dose implantation for producing the charge zone is required for a nanodevice with two electrodes (nanodiode), but an additional high-energy low-dose implantation for forming the ion traces. Furthermore, in the prior art, the silicon substrate must be highly doped to obtain a metallically conductive layer (CoSi ₂ ) in Si. In the invention, if necessary, an arbitrary substrate can be used, which remains unchanged. Furthermore, the presented here new concept can be varied. For example, instead of a single ion track, a large number of etched ion traces can be contacted simultaneously. In this case, all clustered charge zones in the form of at least one nanocluster have the same geometry. Thus, the total switchable currents are greatly increased at the same tunnel physics and thus consistent characteristics.

forms of training The invention will be described below with reference to the schematic figures explained in more detail. there demonstrate

1A ... 1E different production states in the production of a tunnel diode (process concept I),

2A ... 2D various production states in the production of a single electron transistor (process concept I),

3A ... 3F different production states in an alternative production of a tunnel diode (process concept II),

4A . 4B different production states in an alternative production of a single electron transistor (process concept II),

5A ... 5E different production states in an alternative production of a tunnel diode (process concept III),

6A . 6B various production states in an alternative production of a single electron transistor (process concept III),

7 a schematic diagram for charging a nanocluster chain,

8th a schematic diagram for Nanoclusteransteuerung and

9 a schematic diagram for nanocluster sizing.

Process Concept I

• i. Schwere Ionen (z.B. Ar, Kr, Xe, U, Au...) mittlerer Energie und geringer Fluenz (ein bis maximal etwa 10⁶ bis 10⁹ Ionen pro cm² zur Minimierung des Überlappens von Ionenspuren) werden vertikal in eine geeignete ätzbare Isolatorschicht IL, beispielsweise eine SiO₂-Schicht, eingeschossen. Die Ionenenergie wird dabei so gewählt, dass die Ionenreichweite R in der Isolatorschicht IL etwas geringer als deren Dicke d ist, beispielsweise R ≈ 3/4 d), vergleiche 1A.
• ii. Danach wird die Spur der Ionen auf möglichst kleine Durchmesser (in der Größenordnung von ungefähr 10 nm bis 50 nm) angeätzt. Hierbei entsteht eine nichtdurchgängig geätzte Ionenspur P in Form einer Pore, die etwa bis in die Tiefe R der Isolationsschicht IL reicht. Weil die Abbremskraft der eingeschossenen Schwerionen gegen Ende der Ionenreichweite R stets stark ansteigt, entsteht eine geätzte Ionenspur P, die leicht konisch zum Bahnende hin aufgeht, vergleiche 1B.
• iii. Anschließend werden vertikal niederenergetische metallische (z.B. Au, Ag, Ni) oder halbleitende Schwerionen (z.B. Si) bei hohen Fluenzen (typischerweise ungefähr 10¹⁵ bis 10¹⁶ Ionen pro cm²) in die Isolationsschicht IL eingeschossen. Deren Reichweite r wird so gewählt, dass sie etwa (d-R)/2 beträgt. Damit entsteht unter der Oberfläche der Isolationsschicht IL eine vergrabene leitende Schicht BL. Diese bleibt jedoch für die Tunneldiode TD ohne Funktion. Unterhalb der geätzten Ionenspur P liegt diese Schicht BL deutlich tiefer und bildet hier die funktionsrelevante Ladungszone CA, vergleiche 1C. Damit bildet die grundlochartig geätzte Ionenspur P eine Fensteröffnung W zur Deposition der Ladungszone CA. Auf Grund der Reichweitenstreuung ist die implantierte Schicht BL unterhalb der geätzten Ionenspur P etwas breiter als die geätzte Ionenspur P selbst. Je nach System bleiben die implantierten Metall- oder Halbleiterionen in der Isolationsschicht IL atomar erhalten oder formen nanoskopisch kleine Ausscheidungen. Ober- und unterhalb der Ladungszone CA bildet sich in der Isolationsschicht IL jeweils eine Tunnelbarriere TB aus.
• iv. Der nächste Verfahrensschritt ist ein Ausheiz-Schritt (Tempern). Durch Erhöhung der thermischen Beweglichkeit der mit der Isolationsschicht IL nicht mischbaren Metall- oder Halbleiterionen formieren sich jene zu wohldefinierten, leitfähigen Nanoclustern NC. Dabei entsteht in der vergrabenen Leiterschicht BL eine Kette von Nanoclustern und in der Ladungszone CA zumindest ein Nanocluster NC, vergleiche 1D.
• v. Zur Fertigstellung der Tunneldiode TD werden anschließend nun eine obere Elektrode UE und eine untere Elektrode IE auf die Isolationsschicht IL im Bereich der Tunnelbarrieren TB angebracht. Wurde die Isolationsschicht IL zuvor auf ein Substrat S aufgebracht, so liegt die untere Elektrode IE auf dem Substrat S unterhalb des Nanoclusters NC. Zur Erzeugung der unteren Elektrode IE wird die untere Seite der Isolationsschicht IL beispielsweise mit einem Metall (z.B. Au, Al) bedampft. Auf der oberen Seite der Isolationsschicht IL wird die obere Elektrode UE beispielsweise durch chemische Deposition (electrodeless deposition ELD) aufgebracht, vergleiche 1E. Damit ist die nanostrukturierte Tunneldiode TD zur Einzelelektronenleitung fertiggestellt. Die vergrabene Schicht BL aus metallischen Nanoclustern NC neben der geätzten Ionenspur P bleibt funktionslos und liegt auf demselben Potenzial wie die obere Elektrode UE.

A method for producing a tunnel diode TD according to the invention can be carried out with the following method steps (method concept I) (parameter assignment by way of example)

• i. Heavy ions (eg Ar, Kr, Xe, U, Au ...) of medium energy and low fluence (one to a maximum of about 10 ⁶ to 10 ⁹ ions per cm ² to minimize overlap of ion traces) are vertically transformed into a suitable etchable insulator layer IL, for example a SiO ₂ layer, injected. The ion energy is chosen so that the ion range R in the insulator layer IL is slightly less than its thickness d, for example R ≈ 3/4 d), cf. 1A ,
• ii. Thereafter, the trace of ions is etched to the smallest possible diameters (on the order of about 10 nm to 50 nm). This results in a non-continuously etched ion trace P in the form of a pore, which extends approximately to the depth R of the insulating layer IL. Because the deceleration force of the injected heavy ions always rises sharply toward the end of the ion range R, an etched ion trace P arises, which rises slightly conically towards the tail, cf. 1B ,
• iii. Subsequently, vertically low-energy metallic (eg Au, Ag, Ni) or semiconducting heavy ions (eg Si) are injected into the insulating layer IL at high fluences (typically about 10 ¹⁵ to 10 ¹⁶ ions per cm ² ). Their range r is chosen to be approximately (dR) / 2. This results in a buried conductive layer BL under the surface of the insulating layer IL. However, this remains without function for the tunnel diode TD. Below the etched ion trace P, this layer BL is significantly deeper and forms the functionally relevant charge zone CA, cf. 1C , Thus, the bottom hole etched ion trace P forms a window opening W for the deposition of the charge zone CA. Due to the range scattering, the implanted layer BL below the etched ion trace P is slightly wider than the etched ion trace P itself. Depending on the system, the implanted metal or semiconductor ions in the isolation layer IL remain atomic or form nanoscopically small precipitates. Above and below the charge zone CA, a tunnel barrier TB is formed in the insulation layer IL.
• iv. The next process step is a annealing step (tempering). By increasing the thermal mobility of the metal or semiconductor ions which are immiscible with the insulating layer IL, these form into well-defined, conductive nanoclusters NC. In this case, a chain of nanoclusters is formed in the buried conductor layer BL and at least one nanocluster NC in the charge zone CA, cf. 1D ,
• v. To complete the tunnel diode TD, an upper electrode UE and a lower electrode IE are then subsequently applied to the insulating layer IL in the region of the tunnel barriers TB. If the insulating layer IL was previously applied to a substrate S, the lower electrode IE lies on the substrate S below the nanocluster NC. To produce the lower electrode IE, the lower side of the insulating layer IL is vapor-deposited, for example, with a metal (eg Au, Al). On the upper side of the insulating layer IL, the upper electrode UE is applied, for example, by chemical deposition (electrodeless deposition ELD), cf. 1E , Thus, the nanostructured tunnel diode TD is completed for single electron conduction. The buried layer BL of metallic nanoclusters NC next to the etched ion trace P remains inoperative and is at the same potential as the top electrode UE.

The completed tunnel diode TD according to 1E now shows the following structure. In an insulating layer IL below a window opening W, it concentrically has a clustered charge zone CA. Above and below this charge zone CA, there are two electrodes UE, IE on the insulation layer IL, a tunnel barrier TB being arranged in each case between the clustered charge zone CA and the two electrodes UE, IE. The window opening W in the insulation layer IL is formed as a non-continuous etched ion trace P. The clustered charge zone CA is formed by at least one metallic nanocluster NC. By contrast, the two tunnel barriers TB are formed by layer regions of the insulation layer IL above and below the at least one metallic nanocluster NC.

• ii-a. Zunächst muss eine weitere Ionenspur IT für die Kontaktierung der erforderlichen weiteren Elektrode GE eingebracht werden. Diese Spur muss länger als die andere Ionenspur P sein. Zur Vereinfachung des Verfahrens kann die weitere Ionenspur IT durchgehend geätzt werden, vergleiche 2A.
• ii-b. Der nachfolgende Niederenergie-Implantationsschritt wird wie in Verfahrensschritt iii beschrieben durchgeführt, jedoch darf zur Vermeidung von Kurzschlüssen mit der weiteren Elektrode GE nur ein Teil der Fläche der Isolationsschicht IL bestrahlt werden.
• iii-a. Nun erfolgt eine weitere Hochdosis-Implantation von metallischen oder halbleitenden Schwerionen zur Erzeugung einer vergrabenen, konzentrischen Leiterschicht GL zur Steuerung der Einzelelektronenleitung, vergleiche 2B. Die Energie der zweiten Implantation wird so dabei gewählt, dass diese Schwerionen nach einer Ionenreichweite r_g zur Ruhe kommen, die sich deutlich von der Tiefe R+r des die Ladungszone CA bildenden Nanoclusters NC unterscheidet. Dann kommen die implantierten Schwerionen in der steuernden Leiterschicht GL unter- und außerhalb der Ladungszone CA zur Ruhe, sodass Kurzschüsse zwischen dem Nanocluster NC und der noch zu erstellenden weiteren Elektrode GE ausgeschlossen sind.
• iv-b. Der nächste Verfahrensschritt ist wie der Verfahrensschritt iv bei der Tunneldiode TD ein Ausheizschritt. Durch Erhöhung der thermischen Beweglichkeit der mit der Isolationsschicht IL nicht mischbaren Schwerionen scheiden sich jene zu wohldefinierten Nanoclustern NC aus, vergleiche 2C.
• v-a. Nach dem Anbringen der beiden Elektroden UE, IE wird zusätzlich die weitere Elektrode GE zur Kontaktierung der steuernden Leiterschicht GL hergestellt. Dafür wird die durchgehende weitere Ionenspur IT beispielweise galvanisch oder mit ELD mit einem Metall aufgefüllt, sodass sie die vergrabene Leiterschicht GL kontaktiert, vergleiche 2D. Damit ist der Einzelelektron-Transistor SET fertiggestellt. Die obere vergrabene Schicht BL aus metallischen oder halbleitenden Nanoclustern NC neben der geätzten Ionenspur P bleibt wie bei der Tunneldiode TD funktionslos.

The production of a single-electron transistor SET according to the invention requires a few additional process steps:

• ii-a. First, a further ion track IT must be introduced for contacting the required further electrode GE. This trace must be longer than the other ion trace P. To simplify the process, the further ion track IT can be continuously etched, cf. 2A ,
• ii-b. The following low-energy implantation step is carried out as described in method step iii, however, to avoid short circuits with the other electro de GE only a portion of the surface of the insulating layer IL are irradiated.
• iii-a. Now, a further high-dose implantation of metallic or semiconducting heavy ions to produce a buried, concentric conductor layer GL for controlling the single electron conduction, cf. 2 B , The energy of the second implantation is chosen so that these heavy ions come to rest after an ion range r _g , which differs significantly from the depth R + r of the nanocluster NC forming the charge zone CA. Then the implanted heavy ions come to rest in the controlling conductor layer GL below and outside the charge zone CA, so that short shots between the nanocluster NC and the further electrode GE to be created are excluded.
• iv-b. The next method step, like method step iv, in the tunnel diode TD is a baking step. By increasing the thermal mobility of the heavy ions which are immiscible with the insulating layer IL, those to well-defined nanoclusters NC precipitate, cf. 2C ,
• va. After attaching the two electrodes UE, IE, the further electrode GE for contacting the controlling conductor layer GL is additionally produced. For this purpose, the continuous further ion track IT is, for example, filled with a metal galvanically or with ELD so that it makes contact with the buried conductor layer GL, cf. 2D , Thus, the single-electron transistor SET is completed. The upper buried layer BL of metallic or semiconducting nanoclusters NC next to the etched ion trace P remains functionless as in the tunnel diode TD.

The completed single-electron transistor SET according to 2D now shows the following structure. In an insulating layer IL below a window opening W, it concentrically has a clustered charge zone CA. Above and below this charge zone CA, there are two electrodes UE, IE on the insulation layer IL, a tunnel barrier TB being arranged in each case between the clustered charge zone CA and the two electrodes UE, IE. The window opening W in the insulation layer IL is formed as a non-continuous etched ion trace P. The clustered charge zone CA is formed by at least one metallic or semiconducting nanocluster NC. In contrast, the two tunnel barriers TB are formed by layer regions of the insulation layer IL above and below the at least one metallic or semiconducting nanocluster NC. Concentrically below the charge zone CA is in the plane of the lower tunnel barrier TB in the insulation layer IL a buried controlling conductor layer GL. This is driven by a further electrode GE, which lies outside of the other electrodes UE, IE and the buried layer BL of metallic or semiconducting nanoclusters NC.

process concept II

• i. Hochenergetische (ungefähr 100 MeV bis 1 GeV; genaue Energie beliebig) schwere Ionen (z.B. Ar, Kr, Xe, U, Au...) geringer Fluenz (bis maximal etwa ~10^6..8 Ionen pro cm², um das Überlappen von Ionenspuren zu minimieren) werden in eine Isolationsschicht IL (z.B. eine SiO₂-Schicht) geschossen. Dabei ist die Energie der schweren Ionen so bemessen, dass sie die Isolatorschicht IL vollständig durchdringen. Die Isolationsschicht IL ist aus Gründen besserer Handhabbarkeit zweckmäßigerweise nicht freitragend, sondern z.B. durch trockene Oxidation auf ein Substrat S, beispielsweise aus Si, aufgetragen worden sein, vergleiche 3A.
• ii. Im zweiten Verfahrensschritt wird die Ionenspur IT der Schwerionen derart angeätzt, dass der Spurdurchmesser im Bereich der Grenzschicht zwischen der Isolationsschicht IL und dem Substrat S so gering wie möglich ist. Technisch lassen sich derzeit Durchmesser in der Größenordnung von ungefähr 10 nm bis 20 nm problemlos realisieren; Durchmesser von nur einigen nm erscheinen machbar zu sein. Weil sich SiO₂ als Isolationsschicht IL im Vergleich mit z.B. SiON nur relativ schlecht anätzen lässt, entstehen hierbei konische Spuren mit etwa 20° bis 30° Öffnungswinkel, sodass z.B. bei einer Isolationsschicht IL mit 100 nm Dicke der oberflächliche Spurendurchmesser in der Größenordnung von mindestens 70 bis 130 nm liegt, vergleiche 3B.
• iii. Im Unterschied zum Verfahrenskonzept I wird nun eine weitere Isolationsschicht IL₂, insbesondere auch aus SiO₂, aufgewachsen. Ihre Dicke D liegt vorteilhaft aufgrund der in der oben zitierten Veröffentlichung von González-Varona et al. in der Größenordnung von 30 nm bis 40 nm. Das Aufwachsen kann z.B. thermisch geschehen und erfolgt im Falle eines vorhandenen Substrats S auch auf dessen Unterseite, sodass hier eine zusätzliche Isolationsschicht IL₃ aufwächst, vergleiche 3C.
• iv. Danach werden niederenergetische halbleitende oder metallische Schwerionen (z.B. Si, Au, Ag, Ni) bei hohen Fluenzen (typischerweise einige 10¹⁶ cm^-2) vertikal eingeschossen. Dabei wird die Ionenreichweite r so gewählt, dass sie etwa D/2 beträgt. Im Bereich der geätzten Ionenspur IT liegen die implantierten Ionen dann etwa in der Mitte der weiteren Isolationsschicht IL₂, vergleiche 3D.
• v. Der nächste Verfahrensschritt ist ein wieder ein Ausheiz-Schritt. Durch Erhöhung der thermischen Beweglichkeit der mit den Isolationsschichten IL, IL₂ nicht mischbaren Implantate scheiden sich jene zu wohldefinierten Nanoclustern NC aus, vergleiche 3E.
• vi. Der letzte Verfahrensschritt umfasst im Falle der Herstellung einer Tunneldiode TD wieder das Aufbringen der Elektroden UE, IE, wobei die untere Elektrode IE direkt auf das ggfs. vorhandene Substrat S aufgebracht wird. Dazu muss vorher die zusätzliche Isolationsschicht IL₃ entsprechend abgeätzt werden. Vergleiche 3F.

In the process concept II described below, a further insulation layer is constructed and a continuous ion trace P is used. This has the advantage that the exact depth of the etched ion trace does not need to be known exactly as in Process Concept I. However, a further method step for applying the further insulation layer for realizing the final structure is required. The method concept II is advantageous for a practical realization of the desired structures because it is tolerant of possible errors occurring during production.

• i. High energy (about 100 MeV to 1 GeV, exact energy arbitrary) heavy ions (eg, Ar, Kr, Xe, U, Au ...) low fluence (up to a maximum of about ~10 ^6..8 ions per cm ² to avoid overlapping to minimize ion traces) are shot in an insulating layer IL (eg a SiO ₂ layer). The energy of the heavy ions is so dimensioned that they completely penetrate the insulator layer IL. For reasons of better handling, the insulating layer IL is expediently not self-supporting, but has been applied to a substrate S, for example of Si, by dry oxidation, for example 3A ,
• ii. In the second method step, the ion track IT of the heavy ions is etched in such a way that the track diameter in the region of the boundary layer between the insulation layer IL and the substrate S is as small as possible. Technically, diameters of the order of magnitude of approximately 10 nm to 20 nm can currently be realized without difficulty; Diameters of only a few nm appear to be feasible. Because SiO ₂ as insulating layer IL can be estimated relatively poorly in comparison with, for example, SiON, this results in conical tracks with an opening angle of approximately 20 ° to 30 °, so that, for example, with an insulating layer IL of 100 nm thickness, the superficial track diameter is on the order of at least 70 to 130 nm, see 3B ,
• iii. In contrast to method concept I, a further insulation layer IL ₂ , in particular also of SiO ₂ , is now grown. Its thickness D is advantageous due to the above-cited publication by González-Varona et al. on the order of 30 nm to 40 nm. The growth can be done, for example, thermally and takes place in the case of an existing substrate S on its underside, so that here an additional insulating layer IL ₃ grows, see 3C ,
• iv. After that, low energy will semiconduct de or metallic heavy ions (eg Si, Au, Ag, Ni) at high fluences (typically some 10 ¹⁶ cm ^-2 ) shot vertically. The ion range r is chosen to be approximately D / 2. In the region of the etched ion track IT, the implanted ions are then approximately in the middle of the further insulation layer IL ₂ , cf. 3D ,
• v. The next step is again a bake step. By increasing the thermal mobility of the implants immiscible with the insulating layers IL, IL ₂ , those to well-defined nanoclusters NC are eliminated, cf. 3E ,
• vi. In the case of the production of a tunnel diode TD, the last method step again involves the application of the electrodes UE, IE, the lower electrode IE being applied directly to the optionally present substrate S. For this purpose, the additional insulation layer IL _{3 must} be etched off beforehand. comparisons 3F ,

• i-a. Die Verfahrensschritte i bis v erfolgen wie zuvor beschrieben, allerdings wird vor dem Ätzschritt ii der Ionenspur IT die Stelle der zu platzierenden weiteren Elektrode GE durch eine ggfs. angeschrägte Maske M abgedeckt, sodass diese Stelle ungeätzt bleibt. Damit wird die Position der anschließend erzeugten Nanocluster NC gegenüber ihrer ursprünglichen Position zur Oberfläche der Isolationsschicht IL hin verschoben, sodass sie teilweise im Bereich der Maske M liegen (vergleiche 4A).
• vi-a., vi-b. Nach dem Ablösen der Maske M ist die Schicht aus Nanocluster NC kontaktierbar, Die Erzeugung einer weiteren implantierten Leiterschicht GE entfällt. Die Steuerspannung wird bei diesem Konzept über die vergrabene Schicht aus Nanoclustern NC zum aktiven Einzelelektronen-Nanocluster NC in der Ladungszone CA übertragen, Die Schicht aus Nanoclustern NC wirkt dabei als sehr hochohmiger Widerstand. (vergleiche 4B). Alternativ kann die Schicht aus Nanoclustern NC in Analogie zum Verfahrenskonzept I auch durch Einbringen zusätzlicher Ionenspuren IT kontaktiert werden..

Compared to the fabrication of an Esaki or tunnel diode TD, the fabrication of a single electron transistor SET requires some modifications:

• ia. The method steps i to v are as described above, however, before the etching step ii of the ion track IT, the location of the further electrode GE to be placed is covered by a possibly bevelled mask M so that this point remains unetched. Thus, the position of the subsequently generated nanoclusters NC is shifted with respect to their original position to the surface of the insulating layer IL, so that they are partially in the region of the mask M (see 4A ).
• vi-a., vi-b. After detachment of the mask M, the layer of nanocluster NC can be contacted, the generation of a further implanted conductor layer GE is eliminated. In this concept, the control voltage is transmitted via the buried layer of nanoclusters NC to the active single-electron nanocluster NC in the charge zone CA. The layer of nanoclusters NC acts as a very high-resistance resistor. (see 4B ). Alternatively, the layer of nanoclusters NC can be contacted in analogy to the method concept I by introducing additional ion traces IT.

process concept III

• i. Implantation niederenergetischer halbleitender oder metallischer Schwerionen (z.B. Si, Au, Ag, Ni) bei hohen Fluenzen (typischerweise einige 10¹⁶ cm^-2) in eine Isolationsschicht IL, insbesondere Oxidschicht, bevorzugt auf einem Substrat S aus Silizium derart, dass die Ionenreichweite r etwa 5 nm geringer als die Schichtdicke d der Isolationsschicht IL ist (d – 5 nm), vergleiche 5A.
• ii. Es folgt ein Ausheiz-Schritt zur Bildung von Nanoclustern NC, vergleiche 5B.
• iii. Danach folgt die Implantation hochenergetischer (ungefähr 100 MeV bis 1 GeV; genaue Energie beliebig) schwerer Ionen (z.B. Ar, Kr, Xe, U, Au...) geringer Fluenz, vergleiche 5C.
• iv. Im nachfolgenden Verfahrensschritt werden die Ionenspuren IT angeätzt. Der Ätzprozess erfolgt langsam, aber wohldefiniert in einem speziellen Ätzbad EB derart, dass während des Ätzprozesses die Strom-Spannungs-Charakteristik ständig überprüft wird, vergleiche 5D. Solange der angeätzte Bereich zu kurz ist, fließt kein Strom. Wenn sich die Spitze der geätzten Ionenspur IT den Nanoclustern NC nähert, beginnt ein Tunnelstrom zu fließen. Mit sinkendem Abstand der Spitze der geätzten Ionenspur IT zum Nanocluster NC in der Ladungszone CA steigt dieser Strom stark an, bis er beim Erreichen des Nanoclusters NC maximal wird. Um diesen Fall zu vermeiden, der einer Zerstörung des Nanobauelements gleichkäme, wird der Ätzvorgang unmittelbar davor abgebrochen. Der diesem Zustand entsprechende Wert des Tunnelstromes wird zuvor durch einige Test-Ätzversuche ermittelt werden.
• v. Im diesem Verfahrensschritt wird die Tunneldiode TD in der zuvor beschriebenen Weise kontaktiert, vergleiche 5E.

In the third method concept III, an interactive etching for implementation is proposed. This is the most technically demanding, but probably also optimal concept. The principle of method concept III is to control the etching process by direct comparison with the achieved electrical characteristic. The following process steps are required for this:

• i. Implantation of low-energy semiconducting or metallic heavy ions (eg Si, Au, Ag, Ni) at high fluences (typically some 10 ¹⁶ cm ^-2 ) in an insulating layer IL, in particular oxide layer, preferably on a substrate S made of silicon such that the ion range r about 5 nm less than the layer thickness d of the insulating layer IL is (d - 5 nm), see 5A ,
• ii. This is followed by a bake-out step for the formation of nanoclusters NC, cf. 5B ,
• iii. This is followed by the implantation of high-energy (approximately 100 MeV to 1 GeV, exact energy arbitrary) heavy ions (eg, Ar, Kr, Xe, U, Au ...) of low fluence, cf. 5C ,
• iv. In the subsequent method step, the ion traces IT are etched. The etching process is slow but well-defined in a special etching EB so that the current-voltage characteristic is constantly checked during the etching process, see 5D , As long as the etched area is too short, no current flows. As the tip of the etched ion track IT approaches the nanoclusters NC, a tunnel current begins to flow. With decreasing distance of the tip of the etched ion track IT to the nanocluster NC in the charge zone CA, this current increases strongly until it reaches its maximum upon reaching the nanocluster NC. In order to avoid this case, which would be equivalent to a destruction of the nanobuilding element, the etching process is aborted immediately before. The value of the tunnel current corresponding to this state will be determined beforehand by some test etching tests.
• v. In this method step, the tunnel diode TD is contacted in the manner described above, cf. 5E ,

In the production of a single-electron transistor SET according to method concept III, as in the preceding concepts, the goal here too is to drive the nanocluster NC selected by the ion track IT in the charge zone CA via the layer of the adjacent nanoclusters NC buried in the insulation layer IL. For this purpose, for example, as in the preceding concepts, either a further ion track IT for contacting the buried layer of nanoclusters NC with a further electrode GE can be introduced for control purposes 6A or the layer of nanoclusters NC can be guided to the surface by implantation through an oblique mask M, cf. 6B ,

There the generation of a single electron line for the present invention is of particular importance in the following is still based on the underlying physics at the nanoclusters are discussed.

In a typical tunnel structure of the type "Electrode-Insulation-Layer-Nanocluster-Insulation-Layer-Electrode" determines both the dimensions of the cluster and the oxide layer the cut-off frequency ω _{m of} this structure, given by ω _m ≈ Γ, where Γ = τ ^{-1 is} the resonance width of an electron in the corresponding quantum well is (τ = characteristic residence time of an electron in the quantum well), whereas for δ <Γ (δ = ε - ε _r ; ε = energy of an electron, which falls from the emitter into a quantum well = applied voltage, ε _r = resonance energy in the quantum well) is classical Oscillator behavior (ie τ is smaller than the time in which the coherent oscillations in a tunnel structure are lost), there is a maximum frequency for δ> Γ at ω _m ² = δ ² - Γ ² , which is called the "quantum regime" the tunnel structure is called. This means that a tunnel structure can be operated in the classical as well as in the quantum range depending on the given ratio δ / und and that there is no limitation of the oscillation frequency in the quantum regime.

First, the general case of tunneling current is determined by a nanocluster according to 7 closer look. From an electrode A at the potential V _A , a single-electron transition to a nanocluster NC (1) with the potential V _NC0 (1) takes place when the potential _difference V _{A -V NC0} (1) ≥ ΔV _e . Here ΔV _{e is} the increase of the potential energy of the nanocluster by an electron; the new potential of the nanocluster is: V _NC1 (1) = V _NC0 (1) + ΔV _e . Another condition for the single-electron transition is that A and NC are close enough (ie, less than about 5 nm to 10 nm) to allow a significant tunneling probability of the electron. Conversely, when the potential _difference V _NC1 (1) - V _NC0 (2) ≥ ΔV _e , the nanocluster delivers its charge to a second uncharged, closely spaced nanocluster NC (2). Here, V _NC0 (i) and V _NC1 (i) are the potentials of the ith nanocluster with or without an electron (i = 1,2). If initially both nanoclusters were uncharged (ie, V _NC0 (1) = V _NC0 (2) = 0), then one electron is applied to both nanoclusters by a potential V _A applied to the electrode A until their potentials converge to V _NC1 (1) = V _NC1 (2) = V _NC0 + ΔV _e ≤ V _a .

Analogously, by applying a potential to an entire chain of k sufficiently close adjacent nanoclusters, the entire chain is brought to the potential V _NC0 (i) + ΔV _e (i = 1,2, ... k) if V _A ≥ V _NC0 (i) + ΔV _e . At higher contact potentials V _A ≥ V _NC0 (i) + n ΔV _e , the entire chain is brought to the potential V _NC0 (i) + n ΔV _e (number of electrons per nanocluster n = 1,2,3, ...) , As V _A rises steadily, the chain potential will increase discretely in n steps of width ΔV _e . This means that a control layer in the form of a nanocluster chain, which is intended to drive a nanocluster other than the charge zone (cf. 8th ), in principle only a step-by-step activation will be possible. However, the step size ΔV _e can be predetermined by the nanocluster size. The larger the nanoclusters of a chain are (that is, for example, the longer the implantation time to produce these clusters), the finer control settings are possible. In the invention, therefore, a technically easily realizable single-electron transistor structure is produced by the interaction of two nanocluster populations of different sizes. Of course, the description given here for chains of nanoclusters applies, of course, also to nanocluster planes.

In a single-electron transistor, tunnel currents are to flow from the nanocluster NC in the direction of the electrodes A and B, but preferably not in the direction of the control layer G. That is, while the cluster spacings A-NC and B-NC should be low (<5 nm to 10 nm), the cluster spacing G-NC should be greater - but not too large, so that there is still a good capacitive coupling, that is, about 10 nm). This can be easily realized by the dimensioning of the ion traces in concepts that work with nanoclusters in etched ion traces. For example, with an ion track diameter of more than 30 nm and nanocluster diameters of the order of less than 5 nm, the cluster spacing G-NC is greater than 12.5 nm. Thus, no appreciable tunnel currents are more possible, but influence and thus control about the cluster distances G-NC. The above-proposed nanocluster diameter of less than 5 nm can be set relatively accurately by the choice of implantation dose or bakeout temperature and time. An example of the dimensioning of control layer, nanocluster and ion trace is the 9 refer to.

The numbers indicate the distances in [nm] (in the 9 not shown to scale).

BL

buried conductive layer

CA

charge zone

D d

thickness

EB

etching bath

GE

Further controlling electrode

GL

buried controlling conductor layer

IE

lower electrode

IL

insulation layer

IT

ion track

M

mask

NC

metallic or semiconducting nanocluster

P

non-uniformly etched ion trace

R, r, r ₉

Ion range

S

substratum

SET

Single-electron transistor

TB

tunnel barrier

TD

tunnel diode

UE

upper electrode

W

window opening

Claims (18)

A quantum electronic nanodevice with a clustered charge zone arranged concentrically in an insulation layer below a window opening and at least two electrodes above and below the charge zone, a tunnel barrier being arranged between the clustered charge zone and the two electrodes, characterized in that the window opening (W) is arranged as in the insulation layer (IL) not continuously etched ion trace (P) is formed and that the clustered charge zone (CA) of at least one metallic or semiconducting nanocluster (NC) and the tunneling barriers (TB) of layer regions of the insulating layer (IL) above and below of the at least one metallic or semiconducting nanocluster (NC) are formed. Quantum electronic nanodevice according to claim 1, characterized in that in the insulating layer (IL) concentric to the lower tunnel barrier (TB) between the at least one metallic or semiconducting nanocluster (NC) and the bottom electrode (IE) a conductor layer (GL) of metallic or semiconducting nanoclusters (NC) is arranged over another electrode (GE) is contacted, wherein the further electrode (GE) does not touch the other two electrodes (UE, IE). Quantum electronic nanodevice according to claim 2, characterized in that the further electrode (GE) in a further etched Ion track (IT) is formed. Quantum electronic nanodevice according to claim 2, characterized in that the further electrode (GE) on the Top of the insulating layer (IL) is formed, wherein the Conductor layer (GL) into the top of the insulation layer (IL) guided is. Quantum electronic nanodevice according to one of claims 2 to 4, characterized in that the non-continuously etched ion trace (P) from the surface the insulating layer (IL) ago cone-shaped expanded is. Quantum electronic nanodevice according to one of claims 1 to 5, characterized in that the insulating layer (IL) is formed as a SiO ₂ layer. Quantum electronic nanodevice according to one of claims 1 to 6, characterized in that the insulation layer (IL) is applied to a substrate (S). Quantum electronic nanodevice according to claim 2, characterized in that the further ion track (IT) through by etched the insulating layer (IL) is. Process for the preparation of a quantum electronic Nanowauelements (TD) with one in an insulating layer (IL) below a window opening (W) concentrically arranged clustered charge zone (CA) and at least two electrodes (UE, IE) above and below the clustered charge zone (CA), where between the clustered charge zone (CA) and the two Electrodes (UE, IE) each have a tunnel barrier (TB) arranged is, with the procedural steps i. vertical injection of Heavy ions of medium energy and low fluence in the insulation layer (IL) from the top, the ion energy being chosen that the ionic range R in the insulating layer (IL) is lower is as its thickness d, ii. etching at least one ion track (P) to the smallest possible diameter up to a maximum of 50 nm, iii. vertical insertion of metallic or semiconducting Heavy ions of low energy and high fluence in the insulation layer (IL) from the top to generate the charge zone (CA), wherein the ion energy is chosen is that the ion range r is in the range of (d-R) / 2, iv. Annealing the implanted metallic or semiconducting heavy ions for the formation of nanoclusters (NC) and v. Apply the two Electrodes (UE, IE). Process according to claim 7 for the production of a quantum electronic Nanobauelements (SET) with the additional process steps ii-a etching a another ion track (IT) in the neighborhood of the first ion track (P), but outside the in step iii to be inserted metallic heavy ions, the etch depth the other ion track (IT) is greater as the etch depth the first ion track (P), iii-a vertical shooting of further metallic or semiconducting heavy ions of high energy and high fluence in the insulating layer (IL) from the top thereof to produce a controlling conductor layer (GL), wherein the Ion energy so chosen is that the ionic range is above the range of (d-R) / 2, but still within the insulation layer (IL) lies and v-a Insert another electrode (GE) into the further ion track (IT). Method for producing a quantum electronic nanodevice element (TD) with one in one further insulation layer (IL ₂ ) which is provided below an insulating layer (IL), below a window opening (W) concentrically arranged clustered charge zone (CA) and at least two electrodes (UE, IE) above and below the clustered charge zone (CA), wherein between the clustered charge zone (CA) and the two electrodes (UE, IE) in each case a tunnel barrier (TB) is arranged, with the method steps i. vertically injecting high energy, low fluence heavy ions into the insulating layer (IL) from the top thereof, the ion energy being selected such that the ion coverage R is greater than the thickness d of the insulating layer (II), ii. Etching at least one ion track (IT) completely penetrating the insulation layer (IL) to a diameter as small as possible, to a maximum of 50 nm, iii. thermally growing a further insulating layer (IL ₂ ) with a thickness D in the range of 30 nm to 40 nm on the underside of the insulating layer (IL), iv. vertically injecting low energy and high fluence metallic or semiconductive heavy ions into the insulating layer (IL) in the region of the etched ion trace (IT) from the top thereof to form the charge zone (CA) in the further insulating layer (IL ₂ ), the ion energy thus it is chosen that the ion range r is in the range of D / 2, v. Annealing the implanted metallic or semiconducting heavy ions to form nanoclusters (NC) and vi. Apply the two electrodes (UE, IE). Process according to claim 8 for the production of a quantum electronic nano-device (SET) with the additional steps i-a. Apply a bevelled mask (M) on the top of the insulating layer (IL) in the area of a to be positioned further electrode (GE), via. Replacing the Mask (M) and vi-b. Apply the other, the upper electrode (UE) not touching Electrode (GE) on the top of the insulating layer (IL) in the area the accessible metallic or semiconducting heavy ions. Process for the preparation of a quantum electronic Nanowauelements (TD) with one in an insulating layer (IL) below a window opening (W) concentrically arranged clustered charge zone (CA) and at least two electrodes (UE, IE) above and below the clustered charge zone (CA), where between the clustered charge zone (CA) and the two Electrodes (UE, IE) each have a tunnel barrier (TB) arranged is, with the procedural steps i. vertical injection of metallic or semiconducting heavy ions of low energy and high fluence in the insulating layer (IL) of the thickness d of the Top side for generating the charge zone (CA), wherein the ion energy so chosen is that the ion range r is in the range of (d - 5 nm) lies, ii. Bake out the implanted metallic or semiconducting Heavy ions for the formation of nanoclusters (NC), iii. vertical inject of heavy ions of medium energy and low fluence in the insulation layer (IL) from the top, the ion energy being chosen that the ionic range R is greater than the thickness d of the insulating layer (IL), iv. At least etch an ion track (IT) in an etching bath (EB) under in-situ control of the current flow through the insulation layer (IL) and the clustered charge zone (CA), where the etching process is aborted immediately when an incoming current flow registers will, and v. Apply the two electrodes (UE, IE) the top and bottom of the insulation layer (IL). Process according to claim 11 for the production of a quantum electronic nano-device (SET) with the additional steps iv-a. etching another ion track (IT) in the etching bath (EB) under in-situ control of the current flow through the insulation layer (IL), wherein the etching process is stopped first becomes, if a clear current flow is registered and v-a. Apply another, the upper electrode (UE) not touching Electrode (GE) in the etched another Ion trace (IT). Process according to claim 11 for the production of a quantum electronic nano-device (SET) with the additional steps i-a. Apply a bevelled mask (M) on the top of the insulating layer (IL) in the area of a to be positioned further electrode (GE), v-a. Replacing the Mask (M) and v-b applying another, the upper electrode (UE) not touching Electrode (GE) in the area of the surface of the insulation layer (IL) lying metallic or semiconducting heavy ions. Method according to one of the preceding claims 1 to 13 with an application of the insulating layer (IL) on a substrate (S), with the lower electrode (IE) directly on the substrate (S) is applied. Method according to one of the preceding claims 1 to 14 with a low fluence in the range between 1 ion / cm ² to a maximum of 10 ⁶ to 10 ⁹ ions / cm ² and with Ar, Kr, Xe, U or Au as heavy ions to produce the ion traces ( P, IT). Method according to one of the preceding claims 1 to 15 with a high fluence in the range of 10 ¹⁵ to 10 ¹⁶ ions / cm ² and with Au, Ag or Ni as metallic or Si as semiconducting heavy ions for generating the charge zone (CA) and the conductor layer (GL).