DE10359234A1 - Multi-port memory test method using a sequence convolution scheme to reduce test time - Google Patents

Abstract

According to the invention, a method for testing a multi-port memory according to a test pattern is provided, test contact signals (clk A, clk B, clk C) having the same test clock frequency but with different delay times for controlling memory access via the different access ports (port A, port B , Port C) of the memory. Then, successive memory operations of a test element of the test pattern are performed in a folded sequence with respect to a memory cell via the various access ports (port A, port B, port C) in accordance with the test clock signals (clk A, clk B, clk C) such that the memory operations within the same test cycle of the test element can be completed.

Description

The The present invention relates to a method for testing a Multi-port or multi-port memory and in particular a method for testing a multi-port memory using a sequence convolution scheme to effectively reduce the test time.

System-on-Chip (SOC) products generally have hundreds of embedded memories whose size is 90% of entire chip area can take. Apart from the storage capacity, the requirements are also to the data bandwidth of a SOC chip. This led to Development of multi-port memories with multiple access ports that enable simultaneous access to memory cells. Multiport memory are used in microprocessor systems, network processors, graphics processing chips, Devices with high performance requirements, etc. widely used used and can also be found in data communication applications with different timing requirements. Therefore, regarding the ever higher Multi-port storage requirements technical problems regarding an effective and fast detection and diagnosis of defects or interference in multi-port memories during the development phase and efficient testing during the mass production phase has become an important topic in industry.

Different than with a one-port memory through a multi-port memory parallel access paths provided that a simultaneous Access to different (or even the same) memory cells enable. In this regard, a multi-port memory differs in terms of architecture essentially from a single-port memory. Therefore, an interport word line short or In terport bit line short in a multi-port memory is more difficult to detect than damage or disorder in a conventional Single-port memory. Therefore, in the past few years to increase efficiency when detecting damage or interference in a multi-port memory to improve numerous test algorithms for one Multiport memory have been proposed, such as the zero-one, the checkerboard, the CALPAT-, the Walking-1 / 0-, the Sliding-Diagonal-, the Butterfly and the March algorithm. Among these algorithms, the March algorithm as the best algorithm in terms of test efficiency exposed. According to various Error models of a multi-port memory the base march algorithm can be extended to include others Algorithms are obtained, such as the (MATS +) -, the Marching-1 / 0-, the (MATS ++) -, the March-X-, the (Match-C + / C -) -, the March-A-, the March-Y, the March-B algorithm, etc.

For example, if the March-C algorithm is considered, the test pattern is; {↕ (wa); ↑ (ra, wb); ↑ (rb, wa); ↓ (ra, wb); ↓ (rb, wa); ↕ (ra)}, where a = 0 or 1, b = a (ie the inverse of a) is, w represents a write operation, r represents a read operation, ↕ represents that a memory write or read operation can be performed in an ascending or descending sequence of memory addresses, ↑ represents that a memory write or read operation executing in the ascending sequence of memory addresses, ↓ represents that a memory write or read operation is being performed in the descending sequence of memory addresses, and () indicates a test element that contains one or more memory operations, eg "Read a" (ra), "Write b" (wb), "Read b" (rb) and "Write a" (wa). In addition, the memory operations of a previous test element with respect to one of the memory cells (or memory addresses) must be processed or completed before the memory operations of a subsequent test element with respect to the one memory cell (or memory address) can be carried out.

Therefore provided a multi-port memory is a pair Has access ports A and B when a test element ↑ (ra, wb) are executed should, conventional the successive storage operations (ra) and (wb) of the test element for every Memory cell (or memory address) executed via access port A, whereupon the same memory operations (ra) and (wb) of the test element for each memory cell (or memory address) via access sport B executed become. In this case, because for each storage operation (ra) and (wb) at least one test clock cycle To complete the operation, at least two test clock cycles are required required if the storage operations of the test element ↑ (ra, wb) in terms of one of the memory cells (or memory addresses) via one access ports A or B are running. Because an inspection process indeed executed like this is that the Access ports A and B are treated as individual ports the test algorithm executed twice, so that one Access ports A or B are inactive or unused if the Test process via the other of the access ports A or B is running.

According to one other conventional Test procedure the successive memory operations become a multi-port memory (ra) and (wb) of the test element for every Memory cell (or memory address) executed by between the access ports A and B are switched alternately. In particular, the storage operation (ra) during the first test cycle over the Access sport A executed while the Store operation (wb) during a subsequent, second test cycle over the Access sport B executed becomes. Although still two test clock cycles are required if the storage operations of the test element ↑ (ra, wb) in terms of one of the memory cells (or memory addresses) are executed, it is no longer necessary to run the test algorithm twice. One of Access ports A or B are still inactive or unused, if the test process is via the other of the access ports A or B is running.

Because Failure models for Multi-port memories tend to be very complicated for error detection and the testing process accordingly complex algorithms required. As a result, because of the capacities of multi-port memories bigger and the structures of multi-port memories are becoming increasingly complex, too the necessary test algorithms more complicated, so the Test time extremely increasing and testing efficiency for multi-port memory adversely decreases.

Therefore it is a main object of the present invention, a method for testing a multi-port memory using a sequence convolution scheme to provide the test time effectively reduce.

It Another object of the present invention is a computer program to provide to cause a tester to complete the steps of inventive method performs.

• a) Erzeugen eines Satzes von Prüftaktsignalen mit der gleichen Prüftaktfrequenz, wobei die Prüftaktsignale mindestens einen ersten Prüftakt zum Steuern des Speicherzugriffs über den ersten Port und einen zweiten Prüftakt zum Steuern des Speicherzugriffs über den zweiten Port aufweisen, wobei die Taktimpulse des zweiten Prüftaktes den entsprechenden Taktimpulsen des ersten Prüftaktes um eine Verzögerungszeit (delay period) nacheilen; und
• b) Ausführen der ersten und der zweiten Speicheroperation in einer gefalteten Sequenz bezüglich der Speicherzellen während des gleichen Prüftaktzyklus des Prüfelements, wobei die erste Speicheroperation über den ersten Port während einer ersten Zeitdauer (time period) ausgeführt wird, die an der vorderen Flanke eines der Taktimpulse des ersten Prüftaktes beginnt und an einer nacheilenden Flanke des einen der Taktimpulse des ersten Prüftaktes endet, und wobei die zweite Speicheroperation über den zweiten Port während einer zweiten Zeitdauer (time period) ausgeführt wird, die an der vorderen Flanke eines der Taktimpulse des zweiten Prüftaktes beginnt und an einer nacheilenden Flanke des einen der Taktimpulse des zweiten Prüftaktes endet.

According to one aspect of the present invention, a method for testing a multi-port memory according to a test pattern is provided. The memory has a set of access ports and a plurality of memory cells that can be accessed via the access ports. The access ports have at least a first and a second access port. The test pattern has at least one test element that is to be executed with respect to each of the memory cells and has at least a first and a second memory operation that are carried out successively. The process has the following steps:

• a) generating a set of test clock signals with the same test clock frequency, the test clock signals having at least a first test clock to control memory access via the first port and a second test clock to control memory access via the second port, the clock pulses of the second test clock having the corresponding clock pulses lag the first test clock by a delay period; and
• b) performing the first and second memory operations in a folded sequence with respect to the memory cells during the same test clock cycle of the test element, the first memory operation being carried out over the first port for a first time period that occurs on the leading edge of one of the clock pulses of the first test clock begins and ends on a trailing edge of one of the clock pulses of the first test clock, and the second storage operation is carried out via the second port during a second time period which begins on the leading edge of one of the clock pulses of the second test clock and ends on a trailing edge of one of the clock pulses of the second test clock.

The Delay Time is long enough to ensure is that the first storage operation is carried out contiguously and is not affected by the second storage operation, and is guaranteed is that the second period overlaps the first period such that the first and the second store operation within the same test clock cycle of the test element be completed.

According to one Another aspect of the present invention is a computer program provided, which has program instructions, a test device cause the steps of the aforementioned method to test a Multi-port memory according to one samples perform.

Other Features and advantages of the present invention will become apparent from the following detailed Description of the preferred embodiments with reference to FIG the attached Drawings clarified; show it:

1 a timing diagram to show a first preferred embodiment of a method according to the invention for testing a two-port memory according to a test pattern;

2 a timing diagram to show a second preferred embodiment of a method according to the invention for testing a three-port memory according to a test pattern;

3 a table for comparing test times of the method according to the invention with test times of a conventional one-port test method; and

4 an example to illustrate an application of the first preferred embodiment of the method according to the invention.

The inventive method for testing a multi-port memory is described below using a test specimen described that according to the above mentioned March-C algorithm is generated to compare with the above described conventional test methods to enable. However, it should be mentioned here be that test method according to the invention is not limited to an application on March algorithms, it's actually also applicable to other test algorithms, the test elements having multiple storage operations, such as the MSCAN algorithm, the butterfly algorithm, etc.

• a) Erzeugen eines ersten Satzes von Prüftaktsignalen mit der gleichen Prüftaktfrequenz, wobei die Prüftaktsignale einen ersten Prüftakt (clk A) zum Steuern des Speicher zugriffs über den Zugriffsport A und einen zweiten Prüftakt (clk B) zum Steuern des Speicherzugriffs über den Zugriffsport B aufweisen, wobei die Taktimpulse des zweiten Prüftaktes (clk B) entsprechenden Taktimpulsen des ersten Prüftaktes (clk A) um eine Verzögerungszeit (tcc) nacheilen; und
• b) Ausführen der Speicheroperationen (ra) und (wb) in der gefalteten Sequenz bezüglich einer der Speicherzellen (oder Speicheradressen) während des gleichen Prüftaktzyklus des Prüfelements, wobei die Speicheroperation (ra) über den Zugriffsport A während einer ersten Zeitdauer ausgeführt wird, die an der vorderen Flanke eines der Taktimpulse des ersten Prüftaktes (clk A) beginnt und an einer nacheilenden Flanke des einen der Taktimpulse des ersten Prüftaktes (clk A) endet, und wobei die zweite Speicheroperation (wb) über den zweiten Port B während einer zweiten Zeitdauer ausgeführt wird, die an der vorderen Flanke eines der Taktimpulse des zweiten Prüftaktes (clk B) beginnt und an einer nacheilende Flanke des einen der Taktimpulse des zweiten Prüftaktes (clk B) endet.

In the first preferred embodiment of the present invention, the test method is applied to a multi-port memory having a pair of access ports A and B and a plurality of memory cells which can be accessed via the access ports A and B in a conventional manner. According to the invention, successive memory operations of a test element, for example ↑ (ra, wb), of the test pattern are carried out in a folded sequence with respect to one of the memory cells (or memory addresses) via the access ports A and B during the same test clock cycle of the test element. As in 1 is illustrated, the first preferred embodiment of the method according to the invention has the steps:

• a) generating a first set of test clock signals with the same test clock frequency, the test clock signals having a first test clock (clk A) for controlling memory access via access port A and a second test clock (clk B) for controlling memory access via access port B, wherein the clock pulses of the second test clock (clk B) lag corresponding clock pulses of the first test clock (clk A) by a delay time (tcc); and
• b) performing the memory operations (ra) and (wb) in the folded sequence with respect to one of the memory cells (or memory addresses) during the same test clock cycle of the test element, the memory operation (ra) being carried out via the access port A during a first period of time that is on the leading edge of one of the clock pulses of the first test clock (clk A) begins and ends on a trailing edge of one of the clock pulses of the first test clock (clk A), and wherein the second memory operation (wb) is carried out via the second port B for a second period of time is, which begins on the leading edge of one of the clock pulses of the second test clock (clk B) and ends on a trailing edge of one of the clock pulses of the second test clock (clk B).

The Delay Time (tcc) should not be less than a minimum specified Duration of the two-port memory, to ensure, that the previous store operation (ra) performed contiguously and is not affected by the subsequent storage operation (wb), and should be set appropriately to ensure that the second Time period overlaps the first time period such that the two Store operations (ra) and (wb) within the same test clock cycle (tcyc) of the test element be completed.

wobei

anzeigt, daß die Speicheroperationen (rb), (wa) bezüglich der gleichen Speicherzelle (oder Speicheradresse) über den Zugriffsport A und B innerhalb des gleichen Prüftaktzyklus des Prüfelements ausgeführt werden. Das hierin verwendete Schema wird nachstehend als Sequenzfaltungsschema bezeichnet. Auf diese Weise kann die Prüfzeit für den Zweiport-Speicher effektiv reduziert werden.Because the successive storage operations (ra, wb) of the test element ↑ (ra, wb) are carried out via the access ports A and B under the control of two test clocks, for example clk A and clk B, the storage operations in the folded sequence can be the same Memory cell (or memory address k, k + 1, k + 2, ...) can be executed at different times within the same test clock cycle (tcyc) of the test element ↑ (ra, wb). According to the first preferred embodiment of the test method according to the invention, the original March-C algorithm {↕ (wa); ↑ (ra, wb); ↑ (rb, wa); ↓ (ra, wb); ↓ (rb, wa); ↕ (ra)} therefore modified in:

in which

indicates that the memory operations (rb), (wa) with respect to the same memory cell (or memory address) are carried out via access ports A and B within the same test clock cycle of the test element. The scheme used herein is referred to below as the sequence folding scheme. In this way, the test time for the two-port memory can be effectively reduced.

In the second preferred embodiment of the present invention, the test method is applied to a multi-port memory with three access ports A, B and C and a plurality of memory cells which can be accessed via the access ports A, B and C. Successive memory operations of a test element, for example ↑ (ra, wb, rb), of the test pattern are carried out in a folded sequence with respect to one of the memory cells (or memory addresses) via the access ports A, B and C during the same test clock cycle of the test element. As in 2 is made clear, the test clock signals generated in this embodiment, unlike in the first preferred embodiment of the method according to the invention, furthermore have a third test clock (clk C) for controlling the memory access via the access port C, the clock pulses of the third test clock (clk C) lag the corresponding clock pulses of the second test clock (clk B) by a second delay time (tcc). In addition, the third storage operation, ie (rb), is performed in the folded sequence with respect to the same memory cell as in the first and second storage operations and during the same test cycle of the test element, the third storage operation being performed via the access port C for a third period of time is, which begins on the leading edge of one of the clock pulses of the third test clock (clk C) and ends on a trailing edge of one of the clock pulses of the third test clock (clk C).

Similar to the delay time (tcc) between corresponding clock pulses of the first and the second test clock (clk A and clk B) the second delay time (tcc) is also sufficient long to ensure that the second store operation, i.e. (wb), executed together and is not adversely affected by the third storage operation, and to ensure that the third time period overlaps the second time period in such a way that the first, the second and third storage operations (ra, wb, rb) within the same test cycle of the test element be completed.

modifiziert, für dessen Abarbeitung nur ein Prüftaktzyklus erforderlich ist, so daß die Prüfzeit von 12N auf 8N reduziert wird. Außerdem wird, wenn ein Dreiport-Speicher unter Verwendung der zweiten bevorzugten Ausführungsform des erfindungsgemäßen Sequenzfaltungsschemas geprüft wird, weil aufeinanderfolgende Speicheroperationen eines Prüfelements geeignet verschiedenen Ports A, B und C zugeordnet sind, das ursprüngliche Prüfelement ↓(ra, wb, rb), für dessen Abarbeitung drei Prüftaktzyklen erforderlich sind, in ein neues Prüfelement

modifiziert, für dessen Abarbeitung ebenfalls nur ein Prüftaktzyklus erforderlich ist, so daß die Prüfzeit von 12N auf 6N reduziert wird.It can therefore be seen from the above description that the greater the number of access ports of the multi-port memory, the greater the degree of reduction of the test time when using the method according to the invention. According to 3 if, for example, the following extended March-C algorithm is considered: {↕ (wa); ↑ (ra, wb); ↑ (rb, wa); ↓ (ra, wb, rb); ↓ (rb, wa, ra); ↕ (ra)}, if a single-port memory or a multi-port memory is tested, a single test cycle being required for each memory operation, the total test time 12N, where N denotes the size of the memory field. On the other hand, if a two-port memory is tested using the first preferred embodiment of the sequence convolution scheme according to the invention because successive memory operations of a test element are suitably assigned to different ports A and B, the original test element ↑ (ra, wb) requires two test clock cycles to be processed are in a new test element

modified, for the processing of which only one test cycle is required, so that the test time is reduced from 12N to 8N. In addition, if a three-port memory is tested using the second preferred embodiment of the sequence convolution scheme according to the invention because successive memory operations of a test element are suitably assigned to different ports A, B and C, the original test element ↓ (ra, wb, rb), for which Processing three test clock cycles are required in a new test element

modified, for the processing of which only one test cycle is required, so that the test time is reduced from 12N to 6N.

The first preferred embodiment of the inventive method is applicable to a test algorithm, the Wu et al., "Simulation-Based Test Algorithm generation and port scheduling for multi-port memories," Proceedings of the 38 ^th Design Automation Conference, DAC 2001, 18 .-22. June 2001, Las Vegas, NV, USA is proposed. In this article, after establishing a port drive schedule for embedding a test pattern to detect an address decoder fault for each access port and a test pattern for a specific inter-port test in a test pattern to detect a stuck-at error, Transition error, a stuck-open error, a read error and a coupling error, a redundancy reduction was carried out in order to obtain a compact algorithm with a test length of 10N. By using the first preferred embodiment of the method according to the invention in the compact algorithm proposed by the aforementioned article, the in 4 Modified compact algorithm shown with a test length of 8N obtained.

Preferably is the inventive method through a tester executed into which a suitable computer program is loaded, the program instructions has the test device cause to carry out the steps of the method according to the invention. alternative is the inventive method through a tester executed which has a hardware circuit which causes the test device, the Steps of the method according to the invention perform.

According to the invention Generation of test signals with the same test clock frequency, however with different delay times to control memory access via different access ports Multiport memory and by performing successive memory operations a test element a test sample in a folded sequence with respect to a memory cell above the various access ports according to the test clock signals the memory operations within the same test cycle of the test element be completed, which reduces the test time to a minimum becomes.

Claims (5)

Method for checking a multi-port memory according to one Specimens the memory comprising a set of access ports and a plurality of memory cells has on the over the access ports can be accessed, the access ports at least a first and a second port (port A, port B) have the test sample at least one test element has that regarding each of the memory cells executed and at least a first and a second storage operation contains which are carried out sequentially, the method comprising the steps of: a) Create one Set of test clock signals with the same test clock frequency, the test clock signals at least a first test cycle (clk A) to control memory access via the first port (port A) and a second test cycle (clk B) to control memory access via the second port (port B), the clock pulses of the second test clock (clk B) the corresponding clock pulses of the first test clock (clk A) by a first delay time (tcc) lag; and b) Execution of the first and the second Store operation in a folded sequence with respect to a of memory cells during the same test cycle the test element, the first storage operation over the first port (port A) while a first period of time that is on the leading edge of one of the clock pulses of the first test clock (clk A) begins and on a trailing edge of one of the clock pulses the first test cycle (clk A) ends, and the second store operation over the second port (port B) during a second period of time that is on the leading edge of one of the clock pulses of the second test clock (clk B) begins and on a trailing edge of one of the clock pulses of the second test cycle (clk B) ends; the first delay time (tcc) being sufficient is long so that ensures is that the first storage operation is carried out contiguously and is not affected by the second storage operation, and is guaranteed is that the second period overlaps the first period such that the first and the second store operation within the same test clock cycle of the test element be completed. The method of claim 1, wherein the access ports further comprise a third port (port C) and the test element further comprises a third memory operation following the second memory operation; wherein in step a) the test clock signals further have a third test clock (clk C) for controlling a memory access via the third port (port C), clock pulses of the third test clock (clk C) corresponding clock pulses of the second test clock (clk B) by a second delay time (tcc) lag; and in step b) the third memory operation is further performed in the folded sequence with respect to one of the memory cells during the same test clock cycle of the test element, the third memory operation being carried out via the third port (port C) during a third period of time that is on the front Edge of one of the clock pulses of the third test clock (clk C) begins and on a trailing edge of one the clock pulse of the third test clock (clk C) ends; wherein the second delay time (tcc) is long enough to ensure that the second memory operation is performed contiguously and is not affected by the third memory operation, and to ensure that the third period overlaps the second period such that the first, second and the third storage operation is completed within the same test clock cycle of the test element. The method of claim 1, wherein the test pattern according to one March algorithm is generated. The method of claim 1, wherein each of the storage operations an operation to read a "1", an operation to write a "0", an operation to read a "0" or an operation for writing a "1". Computer program with program instructions that a test device cause the steps of the method according to any one of claims 1 to 4 to execute.