DE10348167A1 - Verfahren zum Verdrahten von Schaltelementen in einer integrierten Schaltung - Google Patents

Verfahren zum Verdrahten von Schaltelementen in einer integrierten Schaltung Download PDF

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Publication number
DE10348167A1
DE10348167A1 DE2003148167 DE10348167A DE10348167A1 DE 10348167 A1 DE10348167 A1 DE 10348167A1 DE 2003148167 DE2003148167 DE 2003148167 DE 10348167 A DE10348167 A DE 10348167A DE 10348167 A1 DE10348167 A1 DE 10348167A1
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DE
Germany
Prior art keywords
circuit
circuit elements
integrated
wiring
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE2003148167
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English (en)
Inventor
Michael Wagner
Manfred Selz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE2003148167 priority Critical patent/DE10348167A1/de
Publication of DE10348167A1 publication Critical patent/DE10348167A1/de
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

Die Erfindung betrifft ein Verfahren zum Verdrahten von Schaltelementen in einer integrierten Schaltung, insbesondere in einer integrierten Speicherschaltung mit folgenden Schritten: DOLLAR A - Bereitstellen einer Netzliste, die eine elektrische Verbindungsleitung zwischen einem Ausgang eines Schaltelementes und Eingängen von einem oder mehreren weiteren Schaltelementen in der zu integrierenden Schaltung beschreibt; DOLLAR A - Dimensionieren des Schaltelementes und des/der weiteren Schaltelemente so, dass die Ausgangstreiberstärke des Ausgangs des Schaltelementes zum Treiben der gesamten Last der mit dem jeweiligen Ausgang verbundenen Eingänge der weiteren Schaltelemente abgestimmt ist; DOLLAR A - Dimensionieren eines Querschnitts der Verbindungsleitung, abhängig von der Ausgangstreiberstärke.
DE2003148167 2003-10-16 2003-10-16 Verfahren zum Verdrahten von Schaltelementen in einer integrierten Schaltung Ceased DE10348167A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE2003148167 DE10348167A1 (de) 2003-10-16 2003-10-16 Verfahren zum Verdrahten von Schaltelementen in einer integrierten Schaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2003148167 DE10348167A1 (de) 2003-10-16 2003-10-16 Verfahren zum Verdrahten von Schaltelementen in einer integrierten Schaltung

Publications (1)

Publication Number Publication Date
DE10348167A1 true DE10348167A1 (de) 2005-03-10

Family

ID=34178046

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2003148167 Ceased DE10348167A1 (de) 2003-10-16 2003-10-16 Verfahren zum Verdrahten von Schaltelementen in einer integrierten Schaltung

Country Status (1)

Country Link
DE (1) DE10348167A1 (de)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4122833A1 (de) * 1991-07-10 1993-01-21 Siemens Ag Verfahren zum anordnen eines stromversorgungsnetzes fuer zellen auf einem baustein
US5502649A (en) * 1990-11-21 1996-03-26 Fujitsu Limited Method and apparatus for determining power supply wirings of a semiconductor device
US5537328A (en) * 1992-01-14 1996-07-16 Nec Corporation Method for laying out power supply wiring conductors in integrated circuits
US5649170A (en) * 1995-06-30 1997-07-15 International Business Machines Corporation Interconnect and driver optimization for high performance processors
US5737580A (en) * 1995-04-28 1998-04-07 International Business Machines Corporation Wiring design tool improvement for avoiding electromigration by determining optimal wire widths
US6405346B1 (en) * 1999-06-08 2002-06-11 Fujitsu Limited Method for optimizing power supply wiring in a semiconductor integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5502649A (en) * 1990-11-21 1996-03-26 Fujitsu Limited Method and apparatus for determining power supply wirings of a semiconductor device
DE4122833A1 (de) * 1991-07-10 1993-01-21 Siemens Ag Verfahren zum anordnen eines stromversorgungsnetzes fuer zellen auf einem baustein
US5537328A (en) * 1992-01-14 1996-07-16 Nec Corporation Method for laying out power supply wiring conductors in integrated circuits
US5737580A (en) * 1995-04-28 1998-04-07 International Business Machines Corporation Wiring design tool improvement for avoiding electromigration by determining optimal wire widths
US5649170A (en) * 1995-06-30 1997-07-15 International Business Machines Corporation Interconnect and driver optimization for high performance processors
US6405346B1 (en) * 1999-06-08 2002-06-11 Fujitsu Limited Method for optimizing power supply wiring in a semiconductor integrated circuit

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Legal Events

Date Code Title Description
OAV Applicant agreed to the publication of the unexamined application as to paragraph 31 lit. 2 z1
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection