DE10344818A1 - Vorrichtung zum Kalibrieren der relativen Phase zweier Empfangssignale eines Speicherbausteins - Google Patents

Vorrichtung zum Kalibrieren der relativen Phase zweier Empfangssignale eines Speicherbausteins Download PDF

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Publication number
DE10344818A1
DE10344818A1 DE10344818A DE10344818A DE10344818A1 DE 10344818 A1 DE10344818 A1 DE 10344818A1 DE 10344818 A DE10344818 A DE 10344818A DE 10344818 A DE10344818 A DE 10344818A DE 10344818 A1 DE10344818 A1 DE 10344818A1
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Germany
Prior art keywords
relative phase
memory module
signals
influencing
controller
Prior art date
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Application number
DE10344818A
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English (en)
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DE10344818B4 (de
Inventor
Andreas Jakobs
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Qimonda AG
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Infineon Technologies AG
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Publication date
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Priority to DE10344818A priority Critical patent/DE10344818B4/de
Priority to US10/949,793 priority patent/US7016259B2/en
Publication of DE10344818A1 publication Critical patent/DE10344818A1/de
Application granted granted Critical
Publication of DE10344818B4 publication Critical patent/DE10344818B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Hardware Redundancy (AREA)

Abstract

Kalibriervorrichtung zum Justieren der relativen Phase zwischen zwei an einem Speicherbaustein (120) empfangenen Signalen (CLK, DTS), die in einem Controller (110) zueinander synchronisiert erzeugt und über getrennte Leitungen (CL, SL) an den Speicherbaustein gesendet werden, enthaltend eine im Speicherbaustein angeordnete Messeinrichtung (40), die zum Messen der relativen Phase zwischen den beiden empfangenen Signalen ausgebildet ist, und eine Rückkopplungsschleife, die eine phasensteuernde Korrektureinrichtung (60) enthält. Die Messeinrichtung (40) ist ausgebildet zur Erzeugung einer Stellinformation (STL), welche die Abweichung der gemessenen relativen Phase von einem definierten Toleranzbereich anzeigt. Die Korrektureinrichtung (60) spricht auf die Stellinformation an, um die besagte Abweichung zu kompensieren. Erfindungsgemäß ist die Korrektureinrichtung (40) im Controller (110) angeordnet und ist ausgebildet zur Beeinflussung der relativen Phase zwischen den beiden an den Speicherbaustein zu sendenden Signalen. Die Rückkopplungsschleife enthält eine vom Speicherbaustein (120) zum Controller (110) führende Signalverbindung (RL).
DE10344818A 2003-09-27 2003-09-27 Vorrichtung zum Kalibrieren der relativen Phase zweier Empfangssignale eines Speicherbausteins Expired - Fee Related DE10344818B4 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10344818A DE10344818B4 (de) 2003-09-27 2003-09-27 Vorrichtung zum Kalibrieren der relativen Phase zweier Empfangssignale eines Speicherbausteins
US10/949,793 US7016259B2 (en) 2003-09-27 2004-09-24 Apparatus for calibrating the relative phase of two reception signals of a memory chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10344818A DE10344818B4 (de) 2003-09-27 2003-09-27 Vorrichtung zum Kalibrieren der relativen Phase zweier Empfangssignale eines Speicherbausteins

Publications (2)

Publication Number Publication Date
DE10344818A1 true DE10344818A1 (de) 2005-04-28
DE10344818B4 DE10344818B4 (de) 2008-08-14

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Family Applications (1)

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DE10344818A Expired - Fee Related DE10344818B4 (de) 2003-09-27 2003-09-27 Vorrichtung zum Kalibrieren der relativen Phase zweier Empfangssignale eines Speicherbausteins

Country Status (2)

Country Link
US (1) US7016259B2 (de)
DE (1) DE10344818B4 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same

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US6570944B2 (en) 2001-06-25 2003-05-27 Rambus Inc. Apparatus for data recovery in a synchronous chip-to-chip system
US8121237B2 (en) * 2006-03-16 2012-02-21 Rambus Inc. Signaling system with adaptive timing calibration
US7706996B2 (en) * 2006-04-21 2010-04-27 Altera Corporation Write-side calibration for data interface
KR100915387B1 (ko) * 2006-06-22 2009-09-03 삼성전자주식회사 병렬 인터페이스의 데이터 신호와 클럭 신호 간의 스큐를보상하는 방법 및 장치
WO2008130703A2 (en) 2007-04-19 2008-10-30 Rambus, Inc. Clock synchronization in a memory system
EP2223227B1 (de) * 2007-10-22 2013-02-27 Rambus Inc. Quellensynchrone signalisierung mit niedriger leistung
US8489912B2 (en) * 2009-09-09 2013-07-16 Ati Technologies Ulc Command protocol for adjustment of write timing delay
US9929972B2 (en) * 2011-12-16 2018-03-27 Qualcomm Incorporated System and method of sending data via a plurality of data lines on a bus
KR101880700B1 (ko) * 2014-07-02 2018-07-20 주식회사 아나패스 양방향 통신 방법 및 이를 이용한 양방향 통신 장치
US10579833B1 (en) * 2014-12-16 2020-03-03 Thales Esecurity, Inc. Tamper detection circuit assemblies and related manufacturing processes

Citations (5)

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US6003118A (en) * 1997-12-16 1999-12-14 Acer Laboratories Inc. Method and apparatus for synchronizing clock distribution of a data processing system
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6323705B1 (en) * 2000-04-25 2001-11-27 Winbond Electronics Corporation Double cycle lock approach in delay lock loop circuit
US20020105838A1 (en) * 2001-02-06 2002-08-08 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device performing data output in synchronization with external clock
US20030117864A1 (en) * 2001-10-22 2003-06-26 Hampel Craig E. Phase adjustment apparatus and method for a memory device signaling system

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US4305045A (en) * 1979-11-14 1981-12-08 Bell Telephone Laboratories, Incorporated Phase locked loop clock synchronizing circuit with programmable controller
GB8802471D0 (en) * 1988-02-04 1988-03-02 Secr Defence Correction of long term drift & short term fluctuating corruption of signal
US6310821B1 (en) 1998-07-10 2001-10-30 Kabushiki Kaisha Toshiba Clock-synchronous semiconductor memory device and access method thereof
US5513377A (en) * 1994-06-17 1996-04-30 International Business Machines Corporation Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus
DE19713660A1 (de) 1997-04-02 1998-10-08 Siemens Nixdorf Inf Syst Phasenjustierung schneller paralleler Signale
KR100493054B1 (ko) * 2003-03-04 2005-06-02 삼성전자주식회사 지연동기 루프를 구비하는 반도체 장치 및 지연동기 루프제어방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6003118A (en) * 1997-12-16 1999-12-14 Acer Laboratories Inc. Method and apparatus for synchronizing clock distribution of a data processing system
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6323705B1 (en) * 2000-04-25 2001-11-27 Winbond Electronics Corporation Double cycle lock approach in delay lock loop circuit
US20020105838A1 (en) * 2001-02-06 2002-08-08 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device performing data output in synchronization with external clock
US20030117864A1 (en) * 2001-10-22 2003-06-26 Hampel Craig E. Phase adjustment apparatus and method for a memory device signaling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same

Also Published As

Publication number Publication date
DE10344818B4 (de) 2008-08-14
US7016259B2 (en) 2006-03-21
US20050094462A1 (en) 2005-05-05

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OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee