DE10343362A1 - Leiterplatte mit verbessertem EMV-Verhalten und Verfahren zu deren Herstellung - Google Patents

Leiterplatte mit verbessertem EMV-Verhalten und Verfahren zu deren Herstellung Download PDF

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Publication number
DE10343362A1
DE10343362A1 DE2003143362 DE10343362A DE10343362A1 DE 10343362 A1 DE10343362 A1 DE 10343362A1 DE 2003143362 DE2003143362 DE 2003143362 DE 10343362 A DE10343362 A DE 10343362A DE 10343362 A1 DE10343362 A1 DE 10343362A1
Authority
DE
Germany
Prior art keywords
circuit board
circuits
ferrite thin
thin layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE2003143362
Other languages
English (en)
Other versions
DE10343362B4 (de
Inventor
Frank Graebner
Stefan Hildedrandt
Axel Hungsberg
Peter Beil
Mario Festag
Uwe Fischer
Christian Knedlich
Henry Rosmanus
Walter Suellau
Gerd Teichert
Johannes Weiss
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BRUNEL IMG GMBH, 99734 NORDHAUSEN, DE
Original Assignee
INST MASCHINEN ANTRIEBE und EL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by INST MASCHINEN ANTRIEBE und EL filed Critical INST MASCHINEN ANTRIEBE und EL
Priority to DE2003143362 priority Critical patent/DE10343362B4/de
Publication of DE10343362A1 publication Critical patent/DE10343362A1/de
Application granted granted Critical
Publication of DE10343362B4 publication Critical patent/DE10343362B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0233—Filters, inductors or a magnetic substance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/08—Magnetic details
    • H05K2201/083—Magnetic materials
    • H05K2201/086—Magnetic materials for inductive purposes, e.g. printed inductor with ferrite core
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Die Erfindung betrifft eine Leiterplatte, welche ein gegenüber Leiterplatten gewöhnlicher Struktur und Schichtenfolge verbessertes EMV-Verhalten aufweist. Aufgabe ist es, eine Leiterplatte zu schaffen, deren Einsatz zu einer signifikanten Verminderung, vorzugsweise einer nahezu vollständigen Vermeidung der Abgabe von Störstrahlen nach außen führt. Gleichzeitig soll die Leiterplatte für die mit ihr realisierten Schaltungen und Geräte einen Schutz vor eingestrahlter HF-Strahlung bieten. Gegenstand ist weiterhin ein Verfahren zur Herstellung einer entsprechenden Leiterplatte. DOLLAR A Die Aufgabe wird durch eine Leiterplatte gelöst, bei der wenigstens eine der die Schichtenfolge der Leiterplatte ausbildenden Schichten eine ferritische Dünnschicht ist. Entsprechend dem vorgeschlagenen Verfahren wird die ferritische Dünnschicht auf einer eine spätere Leitschicht der Leiterplatte ausbildenden Folie abgeschieden und die Folie zusammen mit der darauf abgeschiedenen Dünnschicht mit dem Trägermaterial der Leiterplatte verpresst.
DE2003143362 2003-09-15 2003-09-15 Verfahren zur Herstellung einer Leiterplatte mit verbessertem EMV-Verhalten Expired - Fee Related DE10343362B4 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE2003143362 DE10343362B4 (de) 2003-09-15 2003-09-15 Verfahren zur Herstellung einer Leiterplatte mit verbessertem EMV-Verhalten

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2003143362 DE10343362B4 (de) 2003-09-15 2003-09-15 Verfahren zur Herstellung einer Leiterplatte mit verbessertem EMV-Verhalten

Publications (2)

Publication Number Publication Date
DE10343362A1 true DE10343362A1 (de) 2005-04-28
DE10343362B4 DE10343362B4 (de) 2005-09-22

Family

ID=34398804

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2003143362 Expired - Fee Related DE10343362B4 (de) 2003-09-15 2003-09-15 Verfahren zur Herstellung einer Leiterplatte mit verbessertem EMV-Verhalten

Country Status (1)

Country Link
DE (1) DE10343362B4 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2192824A1 (de) 2008-11-27 2010-06-02 Siemens Aktiengesellschaft Leiterplatte mit einer Beschichtung aus einem elektromagnetische Strahlungen dämpfenden Material
EP2461657A1 (de) 2010-12-02 2012-06-06 Siemens Aktiengesellschaft Elektrische Baugruppe und Verfahren zur Herstellung einer elektrischen Baugruppe

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987009A (en) * 1987-10-09 1991-01-22 Tdk Corporation Producing method of thick film complex component
US5698131A (en) * 1995-05-15 1997-12-16 Matsushita Electric Industrial Co., Ltd. Paste for manufacturing ferrite and ferrite
EP0880150A2 (de) * 1997-05-22 1998-11-25 Nec Corporation Gedruckte Leiterplatte
US5966294A (en) * 1996-12-20 1999-10-12 Nec Corporation Printed circuit board for prevention of unintentional electromagnetic interference
US6097080A (en) * 1996-04-24 2000-08-01 Susumu Okamura Semiconductor device having magnetic shield layer circumscribing the device
US6136458A (en) * 1997-09-13 2000-10-24 Kabushiki Kaisha Toshiba Ferrite magnetic film structure having magnetic anisotropy
US6603080B2 (en) * 2001-09-27 2003-08-05 Andrew Corporation Circuit board having ferrite powder containing layer

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4987009A (en) * 1987-10-09 1991-01-22 Tdk Corporation Producing method of thick film complex component
US5698131A (en) * 1995-05-15 1997-12-16 Matsushita Electric Industrial Co., Ltd. Paste for manufacturing ferrite and ferrite
US6097080A (en) * 1996-04-24 2000-08-01 Susumu Okamura Semiconductor device having magnetic shield layer circumscribing the device
US5966294A (en) * 1996-12-20 1999-10-12 Nec Corporation Printed circuit board for prevention of unintentional electromagnetic interference
EP0880150A2 (de) * 1997-05-22 1998-11-25 Nec Corporation Gedruckte Leiterplatte
US6136458A (en) * 1997-09-13 2000-10-24 Kabushiki Kaisha Toshiba Ferrite magnetic film structure having magnetic anisotropy
US6603080B2 (en) * 2001-09-27 2003-08-05 Andrew Corporation Circuit board having ferrite powder containing layer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2192824A1 (de) 2008-11-27 2010-06-02 Siemens Aktiengesellschaft Leiterplatte mit einer Beschichtung aus einem elektromagnetische Strahlungen dämpfenden Material
EP2461657A1 (de) 2010-12-02 2012-06-06 Siemens Aktiengesellschaft Elektrische Baugruppe und Verfahren zur Herstellung einer elektrischen Baugruppe

Also Published As

Publication number Publication date
DE10343362B4 (de) 2005-09-22

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8181 Inventor (new situation)

Inventor name: BEIL, PETER, 30559 HANNOVER, DE

Inventor name: FESTAG, MARIO, 10555 BERLIN, DE

Inventor name: FISCHER, UWE, 10439 BERLIN, DE

Inventor name: GRäBNER, FRANK, DR.-ING., 99734 NORDHAUSEN, DE

Inventor name: HILDEBRANDT, STEFAN, 99734 NORDHAUSEN, DE

Inventor name: HUNGSBERG, AXEL, 99734 NORDHAUSEN, DE

Inventor name: KNEDLIK, CHRISTIAN, PROF. DR.-ING. HABIL.DR.RER.NA

Inventor name: ROMANUS, HENRY, 98693 ILMENAU, DE

Inventor name: SüLLAU, WALTER, 38100 BRAUNSCHWEIG, DE

Inventor name: TEICHERT, GERD, DR.RER.NAT., 98704 GRäFINAU-ANGSTE

Inventor name: WEISS, JOHANNES, DR.RER.NAT., 79194 HEUWEILER, DE

8381 Inventor (new situation)

Inventor name: BEIL, PETER, 30559 HANNOVER, DE

Inventor name: FESTAG, MARIO, 10555 BERLIN, DE

Inventor name: FISCHER, UWE, 10439 BERLIN, DE

Inventor name: GRäBNER, FRANK, DR.-ING., 99734 NORDHAUSEN, DE

Inventor name: HILDEBRAND, STEFAN, 99734 NORDHAUSEN, DE

Inventor name: HUNGSBERG, AXEL, 99734 NORDHAUSEN, DE

Inventor name: KNEDLIK, CHRISTIAN, PROF. DR.-ING. HABIL.DR.RER.NA

Inventor name: ROMANUS, HENRY, 98693 ILMENAU, DE

Inventor name: SüLLAU, WALTER, 38100 BRAUNSCHWEIG, DE

Inventor name: TEICHERT, GERD, DR.RER.NAT., 98704 GRäFINAU-ANGSTE

Inventor name: WEISS, JOHANNES, DR.RER.NAT., 79194 HEUWEILER, DE

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BRUNEL IMG GMBH, 99734 NORDHAUSEN, DE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20140401