DE10338665A1 - Production of insulating regions in semiconductor memories comprises forming a hard mask with openings in a region of a stronger electrical insulation and in a region of a weaker electrical insulation on a substrate, and further processing - Google Patents
Production of insulating regions in semiconductor memories comprises forming a hard mask with openings in a region of a stronger electrical insulation and in a region of a weaker electrical insulation on a substrate, and further processing Download PDFInfo
- Publication number
- DE10338665A1 DE10338665A1 DE10338665A DE10338665A DE10338665A1 DE 10338665 A1 DE10338665 A1 DE 10338665A1 DE 10338665 A DE10338665 A DE 10338665A DE 10338665 A DE10338665 A DE 10338665A DE 10338665 A1 DE10338665 A1 DE 10338665A1
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- Germany
- Prior art keywords
- hard mask
- trenches
- substrate
- region
- electrical insulation
- Prior art date
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Links
- 239000000758 substrate Substances 0.000 title claims abstract description 19
- 230000015654 memory Effects 0.000 title claims abstract description 17
- 238000010292 electrical insulation Methods 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000011049 filling Methods 0.000 claims abstract description 9
- 239000000945 filler Substances 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims description 33
- 238000000034 method Methods 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 10
- 150000004767 nitrides Chemical class 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- 244000208734 Pisonia aculeata Species 0.000 claims description 2
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical compound [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 239000003973 paint Substances 0.000 description 5
- 239000002966 varnish Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004922 lacquer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
Description
Mit zunehmender Integrationsdichte von Bauelementen auf IC-Chips nimmt auch die Anzahl unterschiedlicher Funktionen der Komponenten auf dem Chip zu (System-on-Chip). Derartige unterschiedliche Funktionen können z. B. die Speicherzellen eines Speicherzellenfeldes auf einem Halbleiterspeicherchip und die zugehörige Ansteuerperipherie mit Logikschaltungen sein. Die Logikschaltungen werden z. B. in CMOS-Technologie hergestellt. Die Bauelemente der Logikschaltung sind vorwiegend Niedervolt-Transistoren, zwischen denen elektrische Isolationen vorhanden sind, die nur niedrige Spannungen isolieren müssen.With Increasing integration density of devices on IC chips is also increasing the number of different functions of the components on the Chip to (system-on-chip). Such different functions can z. B. the memory cells of a memory cell array on a semiconductor memory chip and the associated Be control peripherals with logic circuits. The logic circuits will be z. B. manufactured in CMOS technology. The components of the logic circuit are mainly low-voltage transistors, between which electrical insulation are present, which must isolate only low voltages.
Für die elektrischen Isolationen sind üblicherweise Isolationsgräben vorgesehen, die zwar so schmal wie möglich sein sollen, um einen möglichst geringen Anteil der Chipoberfläche zu verbrauchen, die andererseits aber ausreichend breit sein müssen, um eine ausreichende elektrische Isolation zu gewährleisten. Diese Isolationsgräben sind als STI (Shallow Trench Isolation) ziemlich flach ausgebildet, um beispielsweise Latch-up-Probleme zu vermeiden, die zum Auftreten unerwünschter parasitärer Bipolartransistoren führen können. Ebenfalls vorhandene Hochvolt-Transistoren dagegen müssen besser elektrisch isoliert werden, da sie mit Spannungen von typisch 12 V und mehr betrieben werden. Die für die Hochvolt-Transistoren vorgesehenen Isolationsgräben sind daher breiter und/oder tiefer als die für die Niedervolt-Transistoren vorgesehenen Isolationsgräben. Eine STI-Isolation kann unter Umständen auch für Hochvolt-Transistoren verwendet werden, z. B. mit einer zusätzlichen Kanalstopp-Implantation.For the electrical Isolations are common isolation trenches provided, which should be as narrow as possible, to a as low as possible Share of the chip surface but on the other hand, they have to be sufficiently wide to to ensure sufficient electrical insulation. These isolation trenches are as STI (shallow trench isolation) formed rather flat to For example, to avoid latch-up issues that occur undesirable parasitic Lead bipolar transistors can. On the other hand, existing high-voltage transistors also need to be better electrically isolated, as they have voltages of typically 12 V and more are operated. The for the high-voltage transistors provided isolation trenches are therefore wider and / or deeper than those for the low-voltage transistors provided isolation trenches. An STI isolation may also be used for high-voltage transistors be, for. B. with an additional Channel stop implantation.
In einem Speicherzellenfeld sollen die Isolationsgräben zwischen den Speicherzellen aus Gründen der Flächenersparnis ebenfalls möglichst schmal ausgebildet sein. Da aber insbesondere Charge-Trapping-Zellen mit einer Oxid-Nitrid-Oxid-Speicherschichtfolge, insbesondere SONOS-Zellen oder NROM-Zellen sowie Flash- bzw. EEPROM-Zellen mit einem isolierten Gate (Floating Gate) als Speicherschicht, mit relativ hohen Spannungen betrieben werden, sollten auch hier die Gräben für eine gute Isolation tiefer ausgebildet werden als bei den Niedervolt-Transistoren.In a memory cell array to the isolation trenches between the memory cells for reasons the area savings also preferably be formed narrow. But because in particular charge-trapping cells with an oxide-nitride-oxide storage layer sequence, in particular SONOS cells or NROM cells as well as flash or EEPROM cells with an insulated gate (floating gate) as storage layer, with should be operated at relatively high voltages, here too trenches for one good insulation are formed deeper than the low-voltage transistors.
Die Verwendung unterschiedlich tiefer Isolationsgräben resultiert bei bisher bekannten Ausführungsformen in einem erheblich höheren Herstellungsaufwand. Ein nachträgliches Tieferätzen eines zunächst flach hergestellten STI-Grabens ist mit den Nachteilen einer begrenzten Skalierbarkeit und eines höheren Flächenbedarfs verbunden.The Use of different depth isolation trenches results in previously known embodiments in a considerably higher Production expense. An afterthought Tieferätzen one at first flat-made STI trench is a limited with the disadvantages Scalability and a higher space requirements connected.
In
der
Aufgabe der vorliegenden Erfindung ist es, ein Verfahren zur Herstellung von Isolationsbereichen in Halbleiterspeichern anzugeben, mit dem mit vergleichsweise geringem Aufwand Isolationsbereiche unterschiedlicher Tiefen hergestellt werden können.task The present invention is a process for the preparation of isolation regions in semiconductor memories, with the With comparatively little effort isolation areas of different Depths can be made.
Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruchs 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.These The object is achieved by the method having the features of claim 1 solved. Embodiments emerge from the dependent claims.
Bei dem Verfahren werden Isolationsgräben hergestellt, die jeweils bis zu unterschiedlich vorgesehenen Tiefen geätzt werden. Wesentlich ist dabei, dass die Position der Gräben durch dieselbe Maske definiert wird. Eine billigere weitere Maske geringeren Auflösungsvermögens dient zur Unterscheidung der flacher zu ätzenden Gräben von den tiefer zu ätzenden Gräben. Das Ätzen und Füllen der Gräben mit dielektrischem Material geschieht in parallelen Herstellungsschritten, so dass der Herstellungsaufwand sehr gering ist.at Isolation trenches are produced in the process, each one etched to different depths. It is essential doing that, the position of the trenches is defined by the same mask. A cheaper additional mask lower resolution serves for distinguishing the shallow trenches to be etched from the deeper ones to be etched Trenches. The etching and filling the trenches with Dielectric material happens in parallel manufacturing steps, so that the production cost is very low.
Auf der Oberseite des Substrats, das mit den Isolationsbereichen zu versehen ist, wird eine Hartmaske, vorzugsweise z. B. aus TEOS, hergestellt, die Öffnungen im Bereich der herzustellenden Isolationsbereiche aufweist. Es werden dann diejenigen Öffnungen dieser Hartmaske verschlossen, die für die flacheren Gräben vorgesehen sind. Dazu kann eine Maske geringeren Auflösungsvermögens eingesetzt werden. Das liegt daran, dass die für die tieferen Isolationsgräben bzw. für die flacheren Isolationsgräben vorgesehenen Bereiche in der Regel jeweils zusammenhängende größere Gebiete umfassen, die mit einer gröberen Struktur erfasst werden können als die schmalen Isolationsgräben.On the top of the substrate, that with the isolation areas too is provided, a hard mask, preferably z. From TEOS, made the openings having in the region of the isolation areas to be produced. It will then those openings this hard mask closed, which provided for the shallower trenches are. For this purpose, a mask of lower resolution can be used. The is because the for the deeper isolation trenches or for the shallower isolation trenches areas generally each contiguous larger areas include those with a coarser one Structure can be detected as the narrow isolation trenches.
Es können dann die tiefer herzustellenden Gräben bis zu einer gewissen Tiefe ausgeätzt werden. Danach werden alle Öffnungen der Hartmaske freigelegt. In einem weiteren Ätzschritt werden die flacher herzustellenden Isolationsgräben auf volle Tiefe ausgeätzt und gleichzeitig die zuvor bereits geätzten Gräben noch tiefer ausgeätzt. Auf diese Weise erhält man mit nur wenigen zusätzlichen Verfahrensschritte und unter Verwendung nur einer hochauflösenden Maske in praktisch demselben Arbeitsgang Gräben unterschiedlicher Tiefe sowie der vorgesehenen geringen Breite.It can then the deeper ditches to a certain depth etched become. After that, all the openings the hard mask exposed. In a further etching step, the flatter to be produced isolation trenches etched to full depth and at the same time etched the previously etched trenches even deeper. On get that way one with only a few additional ones Procedural steps and using only a high-resolution mask in practically the same operation, trenches of different depths as well as the intended small width.
Es
folgt eine genauere Beschreibung eines bevorzugten Beispiels des
Verfahrens anhand der
Die
Die
Die
Die
Die
Die
In
der
Mit
einer Maske hohen Auflösungsvermögens wird
die Lackschicht
Dieses
Füllmaterial
kann vorzugsweise eine weitere Antireflexschicht
Die
noch freien Öffnungen
der Hartmaskenschicht
Die
Die
Das
seitlich der Gräben
vorhandene Pad-Nitrid
Das
Pad-Nitrid
Das
beschriebene Verfahren kann grundsätzlich auch angewendet werden,
nachdem bereits für
Halbleiterbauelemente vorgesehene Strukturen in dem Substrat
Ein wesentlicher Vorteil dieses Verfahrens liegt darin, dass die Gräben unterschiedlicher Tiefe in demselben, nur durch das Entfernen der zweiten Maske unterbrochenen Ätzprozess hergestellt werden können. Eine bevorzugte Anwendung liegt im Bereich der Herstellung von Speicherzellenfeldern aus Embedded-Flash-Speicherzellen oder SONOS-Speicherzellen.One The main advantage of this method is that the trenches differ Depth in the same etching process interrupted only by the removal of the second mask can be produced. A preferred application is in the field of manufacturing memory cell arrays Embedded flash memory cells or SONOS memory cells.
- 11
- Substratsubstratum
- 22
- Pad-OxidPad oxide
- 33
- Pad-NitridPad nitride
- 44
- Hartmaskehard mask
- 55
- AntireflexschichtAnti-reflective coating
- 66
- Lackschichtpaint layer
- 77
- Öffnung der HartmaskeOpening the hard mask
- 88th
- Grabendig
- 99
- Dielektrikumdielectric
- 1010
- Füllmaterialfilling material
- 4040
- HartmaskenschichtHard mask layer
- 5151
- AntireflexschichtAnti-reflective coating
- 6161
- weitere LackschichtFurther paint layer
Claims (7)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10338665A DE10338665A1 (en) | 2003-08-22 | 2003-08-22 | Production of insulating regions in semiconductor memories comprises forming a hard mask with openings in a region of a stronger electrical insulation and in a region of a weaker electrical insulation on a substrate, and further processing |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10338665A DE10338665A1 (en) | 2003-08-22 | 2003-08-22 | Production of insulating regions in semiconductor memories comprises forming a hard mask with openings in a region of a stronger electrical insulation and in a region of a weaker electrical insulation on a substrate, and further processing |
Publications (1)
Publication Number | Publication Date |
---|---|
DE10338665A1 true DE10338665A1 (en) | 2005-03-31 |
Family
ID=34223120
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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DE10338665A Ceased DE10338665A1 (en) | 2003-08-22 | 2003-08-22 | Production of insulating regions in semiconductor memories comprises forming a hard mask with openings in a region of a stronger electrical insulation and in a region of a weaker electrical insulation on a substrate, and further processing |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE10338665A1 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6436611B1 (en) * | 1999-07-07 | 2002-08-20 | Samsung Electronics Co., Ltd. | Trench isolation method for semiconductor integrated circuit |
US20020187615A1 (en) * | 2001-06-07 | 2002-12-12 | United Microelectronics Corp. | Method for forming isolations in memory devices with common source lines |
-
2003
- 2003-08-22 DE DE10338665A patent/DE10338665A1/en not_active Ceased
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6436611B1 (en) * | 1999-07-07 | 2002-08-20 | Samsung Electronics Co., Ltd. | Trench isolation method for semiconductor integrated circuit |
US20020187615A1 (en) * | 2001-06-07 | 2002-12-12 | United Microelectronics Corp. | Method for forming isolations in memory devices with common source lines |
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Date | Code | Title | Description |
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OP8 | Request for examination as to paragraph 44 patent law | ||
8131 | Rejection |