DE10332311B3 - Pipeline processing method for implementation of jump commands in which to speed processing jump command addresses and control information are stored in a special jump memory - Google Patents

Abstract

Method for accelerated implementation of a jump command that is carried out by a microprocessor using pipeline processing, whereby: if a jump command is present in a write stage (5) a jump memory (6) is interrogated and control information produced via a decoding stage (2, 3). If an entry is found in the jump memory the control information is simultaneously transmitted to a pipeline loading stage. If the entry is not found in the jump memory then jump address and control information for this command are stored in memory after execution of the jump command.

Description

The present invention relates to a method for accelerated execution of a jump instruction, which is executed by pipeline processing a microprocessor.

The efficiency of modern microprocessors the average execution time of instructions is increased by accelerated a pipeline architecture with multiple stages. there each pipeline stage processes a specific task before the execution to the next Stage of the pipeline is passed. So at every level faster in the process be worked on the specific task, whereby the Pipeline overall with higher Speeds works and the total throughput and thus the Performance of the microprocessor is increased.

• – Laden des Befehls aus dem Befehlsspeicher oder aus einem externen Speicher,
• – Dekodieren des Befehls,
• – Bestimmung der Operanden des Befehls,
• – Laden der Operanden aus dem Speicher,
• – Ausführen der für den Befehl erforderlichen einen oder mehreren Operationen in einer oder mehreren Stufen und
• – Zurückschreiben der Ergebnisse der Operation oder der Adresse eines Sprungziels in Register oder Speicher.

An instruction to be processed is broken down into processing steps to be executed one after the other and executed in the separate pipeline stages. For example, a command can be processed in the following stages of a pipeline:

• - loading the command from the command memory or from an external memory,
• - decoding the command,
• - determination of the operands of the instruction,
• Loading the operands from the memory,
• - Perform the one or more operations required for the command in one or more stages and
• - Write back the results of the operation or the address of a jump destination in register or memory.

To execute the command, the Pipeline include other stages not listed here. So can for example the decoding of a command several decoding stages require to provide control information of those required to execute the command Receive steps and these to an execution unit of a microprocessor to be able to forward.

In the presence of control and data dependencies between successive executions The must command Pipeline to be stopped.

There are control dependencies, for example with conditional jumps before since the next one executed Command is only known when the condition of the jump is evaluated is. Processing the next one Command generally cannot be started overlapping.

One speaks of data dependencies if that Result of an instruction in a subsequent instruction as an operand needed becomes.

Processing all commands after a dependency is blocked until all commands have been processed before dependence is completed. As a result, the pipeline is stopped and the execution of the command is delayed by a few process cycles.

A standard method of wasting time keeps the execution of the command in the pipeline as low as possible represents the branch prediction. The dynamic branch prediction to speed up execution of jumps is about a so-called branch prediction buffer, a small memory, which is indicated, for example, by the low-order address part of the jump instruction becomes. A memory contains certain bits, the so-called prediction bits than 1-bit or 2-bit information, for example possible is to predict whether a jump is likely to occur or not. Achieving high accuracy of a jump prediction This method requires complex logic to calculate Jump probabilities.

Another method of virtual shortening the pipeline related to the branch prediction represents the Use of a jump target memory, a so-called branch target buffer. The branch target buffer is a small additional cache that keeps the predicted destination jump address for a jump instruction and usually addressed with the least significant bits of the address of the jump instruction becomes. The branch target buffer is already in use during the Load the command using the command address of the current command accessed. If it is a jump command, you know the destination jump address at the end of the command. So in Branch target buffer for a branch instruction found an entry of a branch target address, becomes the assigned program counter as a new program counter set if the jump should be taken. The one under the destination jump address command must be from the predicted address from the instruction memory and then in the intended decoding stages are decoded so that the control information for execution the execution level command fed to the pipeline can be.

In the US 5511175 A If there is a jump instruction to be executed, which is executed by pipeline processing of a microprocessor, the branch target buffer is queried for an entry of a known jump target address and a command located under this address. If the entry is present, the command is forwarded to a stage of the pipeline and the command following the command at the jump destination address is loaded into a loading stage of the pipeline. If there is no entry, the jump target address and the command located at this address are stored in the branch target buffer when the jump command is executed.

Another method of stopping to shorten a pipeline, is about the decoded instructions stored in a so-called trace cache realized. In this trace cache becomes independent whether the instruction is a jump instruction or not, the decoded instruction is saved. This method also draws is characterized by a high implementation effort.

The DE 69031229 T2 proposes, in order to accelerate the execution of conditional jump instructions, to temporarily store decoded instructions in which the instructions immediately following a conditional jump instruction are pre-decoded and temporarily stored, so that these instructions, if no jump occurs, can be fed directly to an execution stage.

Object of the present invention is to propose a procedure in which programs with jump instructions accelerated become.

• – beim Auffinden des Eintrags im Sprung-Speicher gleichzeitig die Steuerinformation an eine Ausführungsstufe der Pipeline weitergeleitet und der auf den Befehl unter der Sprungzieladresse folgende Befehl in eine Ladestufe der Pipeline geladen wird und
• – bei Nichtauffinden des Eintrags die Sprungzieladresse und der Steuerinformation des unter dieser Adresse befindlichen Befehls nach der Ausführung des Sprungbefehls in dem Sprung-Speicher abgespeichert wird.

The object is achieved by a method in which, when a jump command to be executed is available, a jump memory is queried for an entry of a known jump destination address and control information of the command located at this address generated via at least one decoding step,

• - When the entry in the jump memory is found, the control information is simultaneously forwarded to an execution stage of the pipeline and the command following the command under the jump destination address is loaded into a loading stage of the pipeline and
• - If the entry is not found, the jump destination address and the control information of the command located at this address are stored in the jump memory after the execution of the jump command.

The method according to the invention has the advantage on that jump commands, which in the course of a program execution previously executed were accelerated. In that a jump memory is provided which is a destination hop address and the decoded instruction, i.e. the control information of the command located at this address, stores, the decoding stage or several decoding stages can be skipped become. As a result, the Pipeline is virtually shortened by the level of decoding and thus also the loss of time when jumping, since clock cycles are saved are effectively shortened becomes.

Requires to implement the procedure it is simply the use of a memory area of an already available memory a microprocessor or the use of an additional one small cache, so this only minor additional ones Hardware is required.

Depending on availability of storage resources, the method also offers the possibility of just a preliminary stage of the decoded control information Command to store in the jump memory. Even saving the execution a single decoding stage already results in a significant increase in performance.

Will the tax information to be saved compressed, additional memory resources are saved. The tax information required have to only when reading out for further processing, for example be decompressed by a decompression stage.

Below are details of the inventive method explained in more detail using an example with reference to the drawing.

It shows:

1 Processing steps of a jump instruction to be executed using the example of a 5-stage pipeline.

The 1 shows a pipeline architecture with five stages 1 . 2 . 3 . 4 . 5 , wherein each individual stage is provided for the processing of a specific task for processing a command, and a jump memory 6 whose content is determined by the execution of jump commands.

In the first stage 1 , the loading level, a command from a command memory 7 or loaded from an external memory, not shown here, and from subsequent second and third stages 2 . 3 , the decoding stages, is decoded to obtain the control information of the steps required to execute the command. The tax information is at a fourth stage 4 , an execution stage that executes the command. The results obtained from executing the command become a fifth stage 5 , a write stage, which writes the results of the operation or the address of a jump target when executing a jump instruction into a register (not shown here) or a memory (not shown here).

For example, in the charging stage 1 If a conditional jump instruction is loaded, which is to be executed on the basis of a condition, the write stage initiates an access (A) to the jump memory 6 and looks for an entry of the corresponding address of the jump destination. It is in the jump memory 6 the entry of this address before, is from the jump memory 6 the control information of the command located at this address directly to the execution stage 4 forwarded (B). At the same time, the charging stage charges 1 the command from the command memory following the command at the jump destination address 7 (C).

Will in the jump memory 6 no correspond If the entry of the address of the jump destination and the decoded instruction located at this address is found, the instruction located at the address of the jump destination is extracted from the instruction memory 7 in the charging stage 1 loaded, subsequently in the decoding stages 2 . 3 decodes the control information of the instruction located at the address of the branch destination and the address of the branch destination in the branch memory 6 saved (D) and the command in the execution stage 4 executed. The results obtained are saved in corresponding registers, not shown here.

Thus the execution of Jump commands that have already been executed during program execution significantly accelerated because the reload of the jump command the execution information of the command located under the jump target is already in the jump memory are available and individual stages of the pipeline are thus skipped can. This makes the overall performance of the microprocessor essential elevated.

Claims (8)

Method for accelerated execution of a jump instruction, which is executed by means of pipeline processing of a microprocessor, in which: - when the jump instruction to be executed is present from a write stage ( 5 ) a jump memory ( 6 ) after an entry of a known jump destination address and one via at least one decoding stage ( 2 . 3 ) control information generated for the command located at this address is queried, - when the entry is found in the jump memory ( 6 ) at the same time the control information to an execution stage ( 4 ) forwarded to the pipeline and the command following the command under the jump destination address into a loading stage ( 1 ) the pipeline is loaded and - if the entry is not found, the jump destination address and the control information of the command located under this address after the execution of the jump command in the jump memory ( 6 ) is saved. Method according to Claim 1, characterized in that when a jump command which is not to be carried out is present, the loading of the command following the jump command into the loading stage ( 1 ) the pipeline takes place without delay. A method according to claim 1, characterized in that the displacement of the in the jump memory ( 6 ) stored entries are made in a defined sequence (round-robin). A method according to claim 1, characterized in that the in the jump memory ( 6 ) least used stored entries are displaced first (least recently used). A method according to claim 1, characterized in that the displacement of the in the jump memory ( 6 ) stored entries weighted according to frequency (branch history table). Method according to Claim 1, characterized in that the control information is stored in the jump memory ( 6 ) are stored compressed. Method according to claim 1 or 6, characterized in that the control information after reading out from the jump memory ( 6 ) can be decompressed. Method according to one of the preceding claims, characterized in that only one preliminary stage of the decoded control information of the instruction located under the jump address in the jump memory ( 6 ) is saved.