DE10324002A1 - Control of access to an external interface by an IMBUS and MIL-BUS simultaneously accessing the interface dual port ram, whereby a MIL-BUS control mechanism checks for an IMBUS busy signal prior to MIL-BUS transmission - Google Patents

Abstract

Method for resolution of busy problems occurring when an IMBUS and MIL-BUS simultaneously access a dual port ram (DPR) includes the following steps: determination of access priorities, control of the MIL-BUS access to the DPR by means of a special MIL-BUS control mechanism that has a one MHz reference clock signal and avoidance of access conflicts with the IMBUS by checking for an IMBUS busy signal before each data transfer.

Description

1 generic term

method to the solution the so-called "busy problem" simultaneous access of IMBUS and MIL bus to a dual-port ram ", using this method at the external interface (XI) used in the missile project DWS39 is, is applied. The external interface (XI) assembly points the following basic functions:

1.1 Basic Functions of the "External Interface (XI) "

The External Interface (XI) is intended to exchange information between a carrier plane and the missile's steering and control system DWS 39 in the pre-launch phase of the mission. The connection to the aircraft is made by means of a "Dual Redundant 1553B Remote Terminal" Connection to the steering and steering system will over the internal missile bus IMBUS-M produced.

1.1.1 IMBUS-M interface

• • 16 Bit-Daten-Transfer zum XI mit 16 Bit Adresse
• • 16 Bit-Daten-Transfer vom XI mit 16 Bit Adresse
• • 8 Bit-Interrupt-Vektor-Transfer
• • 8 Bit-Command-/Status-Transfer
• • 8-Bit-Synchronisations-Botschaften-Transfer

The exchange of information between the external interface (XI) and the guidance computer (GC) is carried out via an IMBUS-M SLAVE interface, whereby the following IMBUS-M messages are provided:

• • 16-bit data transfer to XI with 16-bit address
• • 16-bit data transfer from XI with 16-bit address
• • 8-bit interrupt vector transfer
• • 8 bit command / status transfer
• • 8-bit synchronization messages transfer

1.1.2 1553B-MIL-BUS interface

• • implementierte Botschaftsarten: – Daten-Transfer Bus-Controller (BCU) → Remote-Terminal (RTU) – Daten-Transfer Remote-Terminal (RTU) → Bus-Controller (BCU) – Daten-Transfer Remote-Terminal (RTU) → Remote-Terminal (RTU)
• • implementierte Mode-Codes: – Transmit Status-Wort (Mode-Code: 00010) – Transmit Last Command (Mode-Code: 10010) – Reset Remote Terminal (Mode-Code: 01000) Das Mode-Command „Reset-Remote-Terminal" ist zur Initialisierung des External-Interfaces durch das Flugzeug vorgesehen.
• • Dem „1553-Remote-Terminal" kann eine Adresse 0 ... 30 zugewiesen werden, wobei diese von extern, galvanisch getrennt über 5 Adress-Leitungen + 1 Parity-Leitung zugeführt werden.
• • Das External-Interface (XI) wird mittels „Transformer-Coupled-Stubs" an den MIL-BUS des Flugzeugs angeschlossen.

The exchange of information between the external interface (XI) and the aircraft is carried out via a "1553B remote terminal interface", which has the following features:

• • Implemented message types: - Data Transfer Bus Controller (BCU) → Remote Terminal (RTU) - Data Transfer Remote Terminal (RTU) → Bus Controller (BCU) - Data Transfer Remote Terminal (RTU) → Remote Terminal (RTU)
• • implemented mode codes: - transmit status word (mode code: 00010) - transmit load command (mode code: 10010) - reset remote terminal (mode code: 01000) The mode command "reset remote terminal "is provided for initialization of the external interface by the aircraft.
• • The "1553 Remote Terminal" can be assigned an address 0 ... 30, whereby these are supplied externally, galvanically isolated via 5 address lines + 1 parity line.
• • The external interface (XI) is connected to the MIL-BUS of the aircraft using "Transformer-Coupled-Stubs".

The said method is characterized by the following features, wherein this for the sake of clarity and readability with headings are provided:

2 Characteristic part

Signs and symbols:

• • signals, which are "active-low" are marked with "! signal name".
• • One any signal value is marked with "X".
• • One state change is marked with: "signal name → new state"
• • The Holding a state is indicated by: "signal name = old state"
• • The "logical Inverting "one Signal is marked with "! Signal name".
• • The "logical AND "is marked with" & ".
• • The "logical OR "is marked with" # ".

2.1 Definition of Access Priorities

There IMBUS access to the dual-port ram (DPR) in principle neither interruptible yet to slow down, this is at the same time Access of IMBUS-M and MIL-BUS granted the higher priority. This means that when Simultaneous access of IMBUS-M and MIL-BUS to the DPR of IMBUS access carried out unhindered whereas the MIL-BUS access must be stopped ("Hold" state) during IMBUS access.

to Realization of this access arbitration are the following circuitry activities necessary:

2.2 Processing of IMBUS accesses and generation of a busy signal

• • Generation a "special IMBUS-busy signal " because the Busy signal from the DPR itself at simultaneous access on both memory ports is generated, not used can, because this is only generated after the arrival of the IMBUS address and thus with an IMBUS access during a currently occurring MIL-BUS access this can not be interrupted fast enough (state "Hold") to to ensure, that this DPR at the beginning of IMBUS data transmission is unlocked.
• • The "IMBUS Busy Signal" is generally included any IMBUS access, regardless from the IMBUS address, generated.
• • The "IMBUS Busy signal" becomes the earliest possible Produces a toe point, i. immediately upon detection of a to the external interface (XI) addressed IMBUS traffic.
• • The "IMBUS Busy Signal" is used for the total duration IMBUS access generated and thus covers both temporally the transfer the 16-bit IMBUS data as well as the 16-bit IMBUS address.
• • The for the IMBUS access to the DPR needed On the other hand, the enable signal "IMBUS chip enable" only becomes active after Reception of the IMBUS address generated with the beginning of the IMBUS data transmission.
• • The Enable signal "IMBUS Chip Enable" is only for the duration the IMBUS data transmission is active and therefore outputs the DPR outside this time period for MIL-BUS accesses free.
• • The time windows of two (2) IMBUS clock periods, i. from the beginning of IMBUS access to the beginning of the actual IMBUS data transfer, will conclude a started shortly before and thus within this time window used MIL-BUS access.

2.2.1 Control mechanism for carrying out the IMBUS Hits

• • CNTR = valid ⇒ ISW-Clock = IMBUS-CLK & IMBUS-SYNC
• • CNTR = invalid ⇒ ISW-Clock = IMBUS-CLK

To control the IMBUS accesses to the DPR, a special IMBUS control unit (ISW) is provided, which is clocked with a clock signal that is generated differently depending on the received control word (CNTR):

• • CNTR = valid ⇒ ISW-Clock = IMBUS-CLK & IMBUS-SYNC
• • CNTR = invalid ⇒ ISW-Clock = IMBUS-CLK

2.3 Carrying out the MIL-BUS accesses and processing of the IMBUS busy signal

The Read / write accesses of the MIL-BUS to the DPR are designed to that she completed within the time window of 2 IMBUS clock periods can be.

The following Circuitry measures while accessing the MIL-BUS on the DPR are necessary, where In addition, a distinction is made between reading and writing.

2.3.1 General information on Control of MIL-BUS read / write accesses

• • As a general rule applies that the MIL-BUS side of the DPR at rest, i. there is no MIL-BUS traffic, is controlled so that IMBUS requests to the DPR at any time without hindrance.
• • The transfer of a MIL-BUS data block from / to the DPR is performed word by word, wherein before each single-word transmission the IMBUS busy signal is polled and then in dependence from the state of the IMBUS busy signal the data transfer is started or is stopped.
• • This also means that read / write accesses of the MIL-BUS on the DPR before and after each single-word transmission must be locked by the associated Enable signal "MIL-BUS-Chip-Enable → false" is switched, to the DPR for IMBUS requests to release.
• • To control the MIL-BUS accesses to the DPR, a special MIL-BUS control unit (SW) is provided which is clocked with a clock signal which is generated in phase with a supplied by the MIL-BUS controller "1 MHz reference clock signal" and whose frequency corresponds to an even multiple (factor: 4) of this reference clock ,

2.3.1.1 Processing asynchronous Input signals for the MIL-BUS control unit

• • „IMBUS-Busy-Signal" mit 16 MHz
• • „Write-Strobe-Signal" des MIL-BUS-Controllers mit 8 MHz

Asynchronous input signals to be processed by the MIL-BUS controller are sampled at a higher clock frequency, such as the controller's strobe clock, to reduce response times to these inputs, namely:

• • "IMBUS Busy Signal" with 16 MHz
• • Write-strobe signal of the MIL-BUS controller at 8 MHz

These higher frequency Synchronizing signals also become like the indexing clock of the MIL-BUS controller Steadfast to the "1 MHz reference clock signal "of MIL-BUS controller generated.

2.3.2 Implementation of the MIL-BUS read accesses

• • Around ensure that no Access collisions with a higher priority IMBUS access are possible, as well an already started MIL-BUS read access to the DPR within of the available a specific time window can be processed Signal "MIL-BUS-Read-Enable" generated, with its Help read transfers are arbitrarily released or stopped can and thus the desired word-by-word traffic is enabled.
• • The actual read signal "read strobe", which is the MIL bus controller and to generate synchronous with the "1 MHz reference clock signal", is through a logical link of the "MIL-BUS-Read-Enable" signal with the "1 MHz reference clock signal" that this Read-signal "Read-strobe" during the positive half-period of the 1 MHz reference clock is set to "active".
• • There the signal "MIL-BUS-Read-Enable" also with the "1 MHz reference clock "is synchronized, enable these measures the MIL-BUS control unit (SW) a data transfer from the DPR to the MIL-BUS within three (3) SW clock periods.
• • Thus, even considering a time delay of T (Syn) = 62.5 ns when synchronizing the IMBUS Busy signal at 16 MHz, the condition is met: T (MIL-BUS-Read) <T (time window) with: T (MIL-BUS-Read) = 3 × T (SW-cycle) + T (Syn) T (time-window) = 2 × T (IMBUS-cycle)

2.3.2.1 Processing of the IMBUS busy signal for MIL-BUS read accesses

• • IMBUS-Busy = false & 1MHz-Referenz-Clock = low (0) In diesem Fall wird der MIL-BUS-Lesetransfer freigegeben und zwar durch Erzeugung der Signale: – Freigabe Read-Strobe durch „MIL-BUS-Read-Enable → true" – Freigabe Zugriff DPR durch „MIL-BUS-Chip-Enable → true"
• • IMBUS-Busy = false & 1MHz-Referenz-Clock = high (1) In diesem Fall wird der MIL-BUS-Lesetransfer durchgeführt und zwar durch Halten der Signale: – „MIL-BUS-Read-Enable = true" – „MIL-BUS-Chip-Enable = true" Der Lesezugriff wird beendet, sobald „1 MHz-Referenz-Clock = low (0)" erkannt wird und zwar durch Erzeugung der Signale: – Sperren Freigabe Read-Strobe durch „MIL-BUS-Read-Enable → false" – Sperren Zugriff DPR mit „MIL-BUS-Chip-Enable → false"
• • IMBUS-Busy = true & (1MHz-Referenz-Clock = low # 1MHz-Referenz-Clock = high) In diesem Fall wird der MIL-BUS-Lesetransfer durch Erzeugung der Signale: – Sperren Freigabe Read-Strobe durch „MIL-BUS-Read-Enable → false" – Sperren Zugriff DPR mit „MIL-BUS-Chip-Enable → false" verhindert und ein Wartezyklus von einer Referenz-Clock-Periode eingefügt, nachdem erneut das „IMBUS-Busy-Signal" abgefragt wird.

To avoid access conflicts with the IMBUS, the "IMBUS-Busy-Signal" is polled by the MIL-BUS-Controller before every data transfer from the DPR to the MIL-BUS-Controller. to synchronize the signals to be generated by the control unit "MIL-BUS-Read-Enable" and "MIL-BUS-Chip-Enable" with the "1 MHZ reference clock".

• • IMBUS-Busy = false & 1MHz reference clock = low (0) In this case, the MIL-BUS read transfer is enabled by generating the signals: - Enable read strobe by "MIL-BUS-Read-Enable → true "- enable access DPR by" MIL-BUS-Chip-Enable → true "
• • IMBUS busy = false & 1MHz reference clock = high (1) In this case, the MIL-BUS read transfer is performed by holding the signals: - "MIL-BUS-Read-Enable = true" - "MIL -BUS-Chip-Enable = true "The read access is terminated as soon as" 1 MHz reference clock = low (0) "is detected by generating the signals: - Disable Enable read strobe by" MIL-BUS-Read -Enable → false "- Lock access DPR with" MIL-BUS-Chip-Enable → false "
• • IMBUS-Busy = true & (1MHz-Reference-Clock = low # 1MHz-Reference-Clock = high) In this case, the MIL-BUS read transfer is performed by generating the signals: - Disable Enable read strobe by "MIL-BUS -Read-Enable → false "- Lock access DPR with" MIL-BUS-Chip-Enable → false " prevented and inserted a wait cycle of a reference clock period after the "IMBUS-Busy-signal" is queried again.

2.3.3 Implementation of the MIL-BUS-write access

• • Around to ensure a write access of the MIL-BUS to the DPR that no Access collision with a higher priority IMBUS access possible is, as well as an already started MIL-BUS access within the disposal standing time window performed becomes the block transfer also released by word of mouth from the MIL-BUS to the DPR.
• • The Criterion for enabling a word transfer to the DPR is provided by the "IMBUS Busy signal", wherein the Release even a special signal "MIL-BUS-Write-Enable" is generated with whose help the write enabled "MIL-BUS-Write-Enable → true" or stopped can.
• • There in general, the MIL-BUS side of the DPR at rest, i.e., there is no MIL-BUS traffic taking place, is controlled so that IMBUS requests on the DPR at any time can be performed unhindered means this, that writes requests of the MIL-BUS on the DPR before and after each single-word transmission be disabled by switching the signals "MIL-BUS-Write-Enable → false" and "MIL-BUS-Chip-Enable → false".
• • There the MIL-BUS controller initiates a write transfer to the DPR signaled by the signal "Write-strobe → true" and this writing process can be stopped externally (state: "Hold") by the Signal "Write strobe = true " "Write-strobe" is logically linked to the signal "MIL-BUS-Write-Enable" in such a way that in the case of "MIL-BUS-Write-Enable = false "and" Write-strobe → true "holds the signal" Write-strobe = true "and thus the write transfer is interrupted.
• • There the MIL-BUS controller under the condition "IMBUS-Busy = false" write transfers with a data rate of 1 MHz and the associated signal "Write Strobe" a pulse duration of ζa 500 ns has enabled this fact the MIL-BUS control unit a data transfer from the MIL-BUS to complete the DPR within two (2) SW clock periods.
• • Thus, even taking into account a time delay of T (Syn) = 125 ns when synchronizing the signal "Write Strobe" with 8 MHz, the condition is fulfilled: T (MIL-BUS-Write) <T (time window) with: T (MIL-BUS-Write) = 2 × T (SW-cycle) + T (Syn) T (time-window) = 2 × T (IMBUS-cycle)

2.3.3.1 Processing of the IMBUS busy signal for MIL bus write accesses

• • Write-Strobe = false (IMBUS-Busy = X) In diesem Fall verbleibt das Steuerwerk im Wartezustand „Wait: Write-Strobe → true" und sperrt den Schreib-Zugriff auf das DPR durch Erzeugung der Signale: – Sperren Zugriff DPR mit „MIL-BUS-Chip-Enable = false" – Freigabe Halten Write-Strobe = true mit „MIL-BUS-Write-Enable = false"
• • Write-Strobe = true & IMBUS-Busy = false In diesem Fall wird ein Schreib-Zugriff auf das DPR durchgeführt mit: – Freigabe Zugriff DPR durch „MIL-BUS-Chip-Enable → true" – Freigabe Write-Strobe durch „MIL-BUS-Write-Enable → true"
• • Write-Strobe = true & IMBUS-Busy = true In diesem Fall wird ein Schreib-Zugriff auf das DPR verhindert durch Erzeugen der Signale: – Sperren Zugriff DPR mit „MIL-BUS-Chip-Enable → false" – Halten Write-Strobe = true mit „MIL-BUS-Write-Enable → false" Das Steuerwerk verharrt anschließend im Wartezustand „Wait: IMBUS-Busy → false" bis die Bedingung „No-Busy" erkannt wird und der Schreibvorgang durchgeführt werden kann.

To avoid access conflicts with the IMBUS, the "IMBUS-Busy-Signal" is polled by the MIL-BUS-Controller before every data transfer from the MIL-BUS-Controller to the DPR and the signal "Write-Strobe" synchronized with 8 MHz is sampled to detect the beginning of a write transfer. There are 3 cases:

• • Write strobe = false (IMBUS busy = X) In this case, the control unit remains in the wait state "Wait: Write strobe → true" and blocks the write access to the DPR by generating the signals: - Disable access DPR with " MIL-BUS-Chip-Enable = false "- Release Hold Write-Strobe = true with" MIL-BUS-Write-Enable = false "
• • Write-strobe = true & IMBUS-Busy = false In this case, write access to the DPR is performed with: - Enable DPR access by "MIL-BUS-Chip-Enable → true" - Enable write-strobe by "MIL -BUS Write Enable → true "
• • Write-strobe = true & IMBUS-Busy = true In this case, write access to the DPR is prevented by generating the signals: - Block access DPR with "MIL-BUS-Chip-Enable → false" - Hold Write-Strobe = true with "MIL-BUS-Write-Enable → false" The control unit then remains in the wait state "Wait: IMBUS-Busy → false" until the condition "No-Busy" is detected and the writing process can be carried out.

description

1 title

method to the solution the so-called "busy problem" Simultaneous access from IMBUS and MIL-BUS to a dual-port Ram ", this method is applied to the external interface (XI) in the steering missile project DWS39 is used.

2 genus and details to the genus

The The invention relates to a method for realizing a simultaneous Access of IMBUS-M and MIL-Bus to the Dual-Port-Ram of the external interface (XI) according to the preamble of the main claim, this interface assembly following usual Basic features include:

2.1 Basic Functions of the "External Interface (XI) "

The External Interface (XI) is intended to exchange information between a carrier plane and the missile's steering and control system DWS 39 in the pre-launch phase of the mission. The connection to the aircraft is made by means of a "Dual Redundant 1553B Remote Terminal" Connection to the steering and steering system will over the internal missile bus "IMBUS-M" manufactured.

2.1.1 IMBUS-M interface

• • 16 Bit-Daten-Transfer zum XI mit 16 Bit Adresse
• • 16 Bit-Daten-Transfer vom XI mit 16 Bit Adresse
• • 8 Bit-Interrupt-Vektor-Transfer
• • 8 Bit-Command-/Status-Transfer
• • 8-Bit-Synchronisations-Botschaften-Transfer

The exchange of information between the external interface (XI) and the guidance computer (GC) is carried out via an "IMBUS-M SLAVE interface", with the following IMBUS-M messages being provided:

• • 16-bit data transfer to XI with 16-bit address
• • 16-bit data transfer from XI with 16-bit address
• • 8-bit interrupt vector transfer
• • 8 bit command / status transfer
• • 8-bit synchronization messages transfer

2.1.2 1553B-MIL-BUS Interface

• • implementierte Botschaftsarten: – Daten-Transfer Bus-Controller (BCU) → Remote-Terminal (RTU) – Daten-Transfer Remote-Terminal (RTU) → Bus-Controller (BCU) – Daten-Transfer Remote-Terminal (RTU) → Remote-Terminal (RTU)
• • implementierte Mode-Codes: – Transmit Status-Wort (Mode-Code: 00010) – Transmit Last Command (Mode-Code: 10010) – Reset Remote Terminal (Mode-Code: 01000) Das Mode-Command „Reset-Remote-Terminal" ist zur Initialisierung des External-Interfaces durch das Flugzeug vorgesehen.
• • Dem „1553B-Remote-Terminal" kann eine Adresse 0 ... 30 zugewiesen werden, wobei diese von extern, galvanisch getrennt über 5 Adress-Leitungen + 1 Parity-Leitung zugeführt werden.
• • Das „1553B-Remote-Terminal" wird mittels Transformer-Coupled-Stubs an den MIL-BUS angeschlossen.

The exchange of information between the external interface (XI) and the aircraft is carried out via a "1553B remote terminal interface", which has the following features:

• • Implemented message types: - Data Transfer Bus Controller (BCU) → Remote Terminal (RTU) - Data Transfer Remote Terminal (RTU) → Bus Controller (BCU) - Data Transfer Remote Terminal (RTU) → Remote Terminal (RTU)
• • implemented mode codes: - transmit status word (mode code: 00010) - transmit load command (mode code: 10010) - reset remote terminal (mode code: 01000) The mode command "reset remote terminal "is provided for initialization of the external interface by the aircraft.
• • The "1553B remote terminal" can be assigned an address 0 ... 30, whereby these are supplied externally, galvanically isolated via 5 address lines + 1 parity line.
• • The "1553B Remote Terminal" is connected to the MIL-BUS via Transformer-Coupled Stubs.

3 state of the art

• • Beim MIL-BUS-Zugriff auf das DPR während eines IMBUS-Zugriffs wird das „Busy-Bit" im „1553-Status-Word" gesetzt, das dem 1553-Bus-Controller im Flugzeug signalisiert, daß der kommandierte Botschafts-Transfer nicht durchgeführt werden konnte. Damit wird dieser veranlasst, die MIL-BUS-Botschaft so lange zu wiederholen, bis erkannt wird, daß das „Busy-Bit" im „1553-Status-Word" nicht mehr gesetzt ist.

To realize the simultaneous access of IMBUS-M and MIL-BUS to the Dual-Port-Ram (DPR) of the external interface (XI), the following possibility is known:

• • During MIL-BUS access to the DPR during IMBUS access, the "Busy Bit" is set in the "1553 Status Word" which signals to the 1553 bus controller in the aircraft that the commanded message transfer is not could be performed. This causes it to repeat the MIL-BUS message until it is detected that the "busy-bit" in the "1553-status-word" is no longer set.

4 criticism of the state of technology

Of the Disadvantage of the known implementation method is that the data transfer from the aircraft to the steering and control system of the DWS missile 39 is slowed down by the message repeats. In addition are special extra Software measures on the plane to enable to carry out these message repetitions.

5 references

• 1. TN AE13-27 / 87 Technical Description of the Bus system IMBUS-M
• 2. S DWS16212 Critical Item Development Specification External Interface (XI) DWS39
• 3. TN-AK241-2 / 89 Critical Item Product Specification External Interface (XI) DWS39
• 4. S-DWS-16211 Critical Item Development Specification for Missile Computer DWS39
• 5. TN AK243-2 / 87 Critical Item Product Specification for Missile Computer DWS39
• 6. MIL-STD-1553B aircraft internal time division Command / Response multiplex databus
• 7. MIL-STD-1760 Aircraft / Store electrical interconnection system
• 8. Data Sheet MT32802 MCE MIL-STD-1553B remote terminal
• 9. INTEGRATED DEVICE TECHNOLOGY (IDT) Specialized Memories & Modules

6 task

Of the Invention is based on the object, an implementation method for the Simultaneous access from MIL-BUS and IMBUS-M to the dual-port Ram to develop the external interface (XI), which compared to the known Method for a more effective data transfer between aircraft and Steering and control system of the missile DWS 39 allowed.

7 solution

The Task is erfindungsmäßig by the method steps according to the "characterizing part of the main claim" solved, wherein the goal of the proposed solution steps is the disadvantages avoid the known implementation method.

8 Achievable benefits

• • Höhere „Daten-Rate" zwischen Flugzeug und Flugkörper DWS 39
• • Geringerer „Software-Aufwand" im Flugzeug

Compared with the known method, the presented method allows a much more effective realization of the information exchange between a carrier aircraft and the steering and control system of the missile DWS 39, whereby effectiveness in this case means:

• • Higher "data rate" between aircraft and missile DWS 39
• • Reduced "software effort" in the aircraft

9 Description of an embodiment

To the understanding the structure and operation of an access control on the IMBUS-SLAVE "external interface (XI) "below the architecture features of the used bus system IMBUS-M short described.

9.1 General information on the IMBUS-M

• • IMBUS-M BUSMASTER Der BUSMASTER wird normalerweise in den Lenkrechner integriert und hat die Aufgabe die Steuerung und Synchronisation der Bus-Transfers zu übernehmen.
• • IMBUS-M BUSSLAVE Mit BUSSLAVES werden die übrigen Funktionseinheiten (wie z.B.: Inertial-System, Rudermaschinen, Flugzeug-Interface usw.), die am IMBUS-M angeschlossen sind, bezeichnet.
• • IMBUS-M Verkabelung Die Verkabelung besteht aus 2 × 10 Signal-Leitungen sowie einer Masse-Leitung. Zudem sind Bus-Abschlüsse (Widerstände) an jedem Leitungs-Ende vorgesehen.

The Bus System IMBUS-M is a low-cost, high-speed data connection between the various functional units (such as: steering, inertial, steering, etc.) of a missile, the bus itself being composed of the following components:

• • IMBUS-M BUSMASTER The BUSMASTER is normally integrated into the steering computer and has the task of controlling and synchronizing the bus transfers.
• • IMBUS-M BUSSLAVE With BUSSLAVES the other functional units (such as: inertial system, steering machines, aircraft interface, etc.) connected to the IMBUS-M are designated.
• • IMBUS-M cabling The cabling consists of 2 × 10 signal cables and a ground cable. In addition, bus terminations (resistors) are provided at each line end.

9.1.1 Principle of IMBUS-M information exchange

A IMBUS-M message consists of a control cycle and a or several data transfer cycles (Data / addresses), the byte-wise in the time-multiplexing method over eight (8) transmit bidirectional bus lines (B0 ... B7) and from the BUSMASTER by means of the signals "IMBUS-CLK (B9) "and" IMBUS SYNC (B8) "are synchronized.

each Message starts with a control cycle (IMBUS-SYNC = high to Time of the rising edge of the IMBUS-CLK), whereby the corresponding "control byte" is generated by the MASTER and is decoded by all SLAVES to the addressed functional unit (Source / destination) and data transfer type (type and number of bytes) the following data transfer cycle to recognize.

transfers with a "type field of the control byte = 0 " Command / status transfers and are mainly used for error detection / treatment of the slave-side bus interface.

The Timing synchronization of MASTER / SLAVE real-time communication is accomplished by synchronization transfers. A synchronization transfer is a message MASTER to all SLAVES, with each data bit one different synchronization signal (eg Reset, Sync1, Sync2 etc.).

A System synchronization and an alarm / interrupt detection is by a bus transfer with "type and slave fields of the control byte = 0 "realized.

9.1.2 General information on IMBUS-M BUSMASTER

at the application of the bus system IMBUS-M in the "steering missile system DWS 39 "is the IMBUS-M-BUSMASTER in the "Guidance Computer (GC) "integrated. Due to the wide 24-bit address space of the "MOTOROLA MC 68000 processor "offers in the realization of the IMBUS-M-BUSMASTER interface, the IMBUS-M control byte into the address space of the processor. This means that the Access of the processor to the IMBUS-M SLAVES from programmatic View takes place in a memory-mapped form (memory-mapped).

9.2 Structure and function of the "external interface (XI) "

The construction and operation of the "External-Interface (XI)" with the capability of "simultaneous access of IMBUS-M and MIL-BUS to the dual-port Ram, is in the 1 to 14 and will be described in more detail below.

The individual pictures show:

1 : Block Diagram of the EXTERNAL INTERFACE (XI)

2 : Block diagram of the IMBUS-M SLAVE interface

3 : State Diagram IMBUS CONTROL

4 : State Diagram SSIU-BUS-CONTROL Storage "1553-Command-Word" with Processing IMBUS-Busy

5 : State diagram SSIU-BUS-CONTROL Process "Data-Transmit" with processing IMBUS-Busy

6 : State diagram SSIU-BUS-CONTROL Process "Data-Receive" with processing IMBUS-Busy

7 : Timing Diagram IMBUS-M Data-Write-Message

8th : Timing Diagram IMBUS-M Data-Read-Message

9 : Timing Diagram Transmit 32/1 Data Words with IMBUS Busy

10 : Timing Chart Transmit any / last Data Word with IMBUS Busy

11 : Timing Diagram Transmit first Data Word with IMBUS Busy

12 : Timing Diagram Receive 32/1 Data Words with IMBUS Busy

13 : Timing diagram Receive first / last data word with IMBUS busy

14 : Timing Diagram Receive any Data Word with IMBUS Busy

list 1: "Text-Design-File" of the control unit "SSIU-BUS-CONTROL"

list 2: "Text-Design-File" of the control unit "IMBUS-CONTROL"

Note to Lists 1 and 2:

at the additional attached Lists are the summary of the so-called "Boolean equations", which is the function exactly describe the control units "SSIU-BUS-CONTROL" and "IMBUS-CONTROL". The underlying description language is one, developed by the manufacturer DATA-IO and standardized Description language VHDL derived derivative, namely ABEL. Of the Advantage and also the purpose of the attached lists lies in the fact that everyone any expert, in case he over has a development software SCENARIO from DATA-IO, which Function of access control of IMBUS-M and MIL-BUS to the DUAL-PORT-RAM easy to understand using SCENARIO simulation.

Signs and symbols:

• • signals, which are "active-low" are marked with "! signal name".
• • One any signal value is marked with "X".
• • One state change is marked with: "signal name → new state"
• • The Holding a state is indicated by: "signal name = old state"
• • The "logical INVERTING " marked with "!".
• • The "logical AND "is marked with" & ".
• • The "logical OR "is marked with" # ".

9.2.1 Structure and function of the IMBUS-M BUSSLAVE interface

• • Steuerwerk „IMBUS-CONTROL"
• • Funktionsgruppe „IMBUS-ADDRESS-REGISTER"
• • Funktionsgruppe „IMBUS-BUFFER"
• • Funktionsgruppe „IMBUS-DEKODER"
• • IMBUS RS485-Receiver/Transmitter

As in 2 The IMBUS-M interface consists of the following function groups whose functions are described individually below:

• • Control unit "IMBUS-CONTROL"
• • "IMBUS ADDRESS REGISTER" function group
• • Function group "IMBUS BUFFER"
• • Function group "IMBUS DECODER"
• • IMBUS RS485 receiver / transmitter

9.2.1.1 Control Unit (State Machine) "IMBUS CONTROL"

9.2.1.1.1 Principle of IMBUS-M data transfers

each activity on the IMBUS-M is indicated by a control word sent by the BUSMASTER (CNTR), which is the BUSSLAVES connected to the IMBUS-M the nature of the subsequent message communicates. For identification of the control word and to the call to the BUSSLAVES, this Checking control words for "valid" is from the BUSMASTER for the duration of the control word transmission the line "IMBUS-SYNC = true ".

• • Im Fall „CNTR = valid" wird die kommandierte Botschaft vom angesprochenen BUSSLAVE abgewickelt, wobei während der Durchführung das Signal IMBUS-SYNC nicht weiter abgefragt wird. Dabei wird das Steuerwerk zu den nächsten States weitergeschaltet und die benötigten Kontrollsignale zur Steuerung des Datentransfers zwischen IMBUS-M und DPR erzeugt. Das dafür benötigte Fortschaltsignal „ISW-Clock" des IMBUS-Steuerwerks wird aus der logischen Verknüpfung der beiden Synchronisiersignale gewonnen und zwar: ISW-Clock = IMBUS-CLK & IMBUS-SYNC
• • Im Fall „CNTR = invalid" verbleibt das IMBUS-Steuerwerk weiterhin im Zustand „Wait: CNTR = valid". Dies bedeutet, daß bei jedem Fortschalten des Steuerwerks das Signal „IMBUS-SYNC = true" abgefragt wird. Um sicherzustellen, daß auch während der Abarbeitung einer, an einen anderen BUSSLAVE adressierten Message das Signal „IMBUS-SYNC" immer zum Zeitpunkt „IMBUS-SYNC = false" abgefragt wird, darf in diesem Fall nicht mit ISW-Clock = IMBUS-CLK & IMBUS-SYNC abgetastet werden, sondern mit: ISW-Clock = IMBUS-CLK

This means that the control unit IMBUS-CONTROL (ISW), if not with the settlement of a Message is busy, it must be in the state "Wait: CNTR = valid", in which the line IMBUS-SYNC is queried continuously.With recognition "IMBUS-SYNC = true" the IMBUS lines (B0 ... B7) are simultaneously examined on "CNTR = valid", whereby two cases can be distinguished:

• • In the case of "CNTR = valid", the commanded message is handled by the addressed BUSSLAVE, whereby the IMBUS-SYNC signal is no longer queried during execution, whereby the control unit is forwarded to the next states and the necessary control signals are used to control the data transfer between IMBUS The required "ISW-Clock" progress signal of the IMBUS control unit is obtained from the logical combination of the two synchronizing signals: ISW-Clock = IMBUS-CLK & IMBUS-SYNC
• • In case of "CNTR = invalid", the IMBUS control unit still remains in the state "Wait: CNTR = valid". This means that the signal "IMBUS-SYNC = true" is queried each time the control unit is moved in. To ensure that even during the processing of a message addressed to another BUSSLAVE, the signal "IMBUS-SYNC" is always sent at the time "IMBUS-SYNC = true". SYNC = false "is not allowed to be scanned with ISW-Clock = IMBUS-CLK & IMBUS-SYNC, but with: ISW-Clock = IMBUS-CLK

• • CNTR = valid ⇒ ISW-Clock = IMBUS-CLK & IMBUS-SYNC
• • CNTR = invalid ⇒ ISW-Clock = IMBUS-CLK

The progress signal of the IMBUS control unit "ISW-Clock" is thus generated differently depending on the received control word (CNTR), namely:

• • CNTR = valid ⇒ ISW-Clock = IMBUS-CLK & IMBUS-SYNC
• • CNTR = invalid ⇒ ISW-Clock = IMBUS-CLK

The Progress signal "ISW-Clock" itself is from the programmable IC "IMBUS DECODER" generated.

9.2.1.1.2 Execution of a IMBUS-M data transfers

By commanding a data transfer message to the external interface (XI), 16-bit data is transferred from or to the guidance computer (GC). If a data transfer message addressed to the external interface is detected, the 11-bit dual port RAM address is first written byte by byte into the IMBUS ADDRESS REGISTER, in the case of a data transfer to the XI, as in 3 represented by the states "DAWRADH" and "DAWRADL" or in the case of a data transfer from the XI by the states "DARDADH" and "DARDADL". Subsequently, the associated data are either pushed through the states "DAWRDIH" and "DAWRDIL" into the dual-port RAM (DPR) or read from the DPR by the states "DAWRDOH" and "DAWRDOL".

at Simultaneous access of IMBUS-M (IMBUS-CONTROL) and MIL-BUS (SSIU-BUS-CONTROL) to the Dual port ram, it is necessary to give the IMBUS access the higher priority because it is not possible is to pause or interrupt IMBUS access. The result resulting access arbitration between IMBUS and MIL-BUS, that the MIL-BUS access control on the DPR during IMBUS access be brought into the so-called "hold state" got to. simultaneously must during the Hold phase of the MIL-BUS controller "SSN-BUS-CONTROL", the enable signal "SSN-CHIP-ENABLE → false" is switched, to avoid that one IMBUS sequence is blocked by DPR-Busy.

to Control of this access arbitration is performed by the control unit IMBUS-CONTROL (State: DARDADH or DAWRADH) during A data transfer from / to the dual-port RAM generates the signal "IMBUS-BUSY (! SSIU-Busy)." This signal should the control unit SSN-BUS-CONTROL cause, during IMBUS access into the hold state. However, one MIL-BUS access started immediately before IMBUS access complete to be able to becomes the enable signal for the dual-port Ram "IMBUS-CHIP-ENABLE" only after reception the IMBUS address is true. (State: DARDDOH or DAWRDIH).

9.2.1.2 Function group "IMBUS ADDRESS REGISTER"

The Programmable IC "IMBUS ADDRESS REGISTER" is provided around the for Read / Write Operations in Dual Port Ram Required 11-Bit IMBUS Address save their bytewise transmission at the beginning of a Data transfer message performed becomes.

9.2.1.3 Function group "IMBUS BUFFER"

• • Erzeugung der „ENABLE-SIGNALE" zu Steuerung der IMBUS-Receiver/Transmitter.
• • Erzeugung des Signals „IMBUS-Reset", das zur Initialisierung des EXTERNAL-INTERFACE via Software vorgesehen ist, wobei der Reset vom Bit #0 des Daten-Bytes einer Synchronisations-Message abgeleitet wird.
• • Erzeugung des Signals „Interrupt-Reset", wobei der Reset vom Bit #2 des Daten-Bytes einer Command-Message abgeleitet wird.
• • Ankopplung des „XI-Interrupts" an die dafür vorgesehenen Busleitungen des IMBUS-M während der Daten-Transfer-Phase einer Interrupt-Vector- oder Status-Message.

The programmable IC "IMBUS BUFFER" fulfills several functions:

• • Creation of the "ENABLE-SIGNALS" to control the IMBUS-Receiver / Transmitter.
• • Generation of the signal "IMBUS Reset", which is intended to initialize the EXTERNAL INTERFACE via software, the reset being derived from bit # 0 of the data byte of a synchronization message.
• • Generation of the signal "interrupt reset", whereby the reset is derived from bit # 2 of the data byte of a command message.
• • Coupling of the "XI-Interrupt" to the intended bus lines of the IMBUS-M during the data transfer phase of an interrupt vector or status message.

9.2.1.4 Function group "IMBUS DECODER"

• • Erzeugung der Kontroll-Signale, die den Daten-Transfer zwischen dem IMBUS-M und dem Dual-Port-Ram steuern
• • Erzeugung des Fortschalt-Signals für das Steuerwerk „IMBUS-CONTROL" (siehe Abschnitt: 9.2.1.1.1)

The programmable IC "IMBUS-DECODER" fulfills a double task though:

• • Generation of control signals controlling the data transfer between the IMBUS-M and the dual-port Ram
• • Generation of the indexing signal for the control unit "IMBUS-CONTROL" (see section: 9.2.1.1.1)

9.2.2 Structure and function of the MIL-BUS interface

• • Steuerwerk „SSIU-BUS-CONTROL"
• • Funktionsgruppe „CLOCK-SYNCHRONISATION"
• • Funktionsgruppe „INPUT-SYNCHRONISATION"
• • Funktionsgruppe „SSIU-ADDRESS-REGISTER"
• • Funktionsgruppe „SSIU-ADDRESS-CONTROL"

The MIL-BUS interface consists of the following functional groups (see 1 ), the function of which will be described individually below:

• • Control unit "SSIU-BUS-CONTROL"
• • "CLOCK SYNCHRONIZATION" function group
• • "INPUT SYNCHRONIZATION" function group
• • "SSIU ADDRESS REGISTER" function group
• • Function group "SSIU-ADDRESS-CONTROL"

9.2.2.1 Control Unit (State Machine) "SSIU-BUS-CONTROL"

9.2.2.1.1 General functional description

• • 1553-Command-Word-Transmit ⇒ Lese-Zugriff
• • 1553-Command-Word-Receive ⇒ Schreib-Zugriff

The task of the "SSIU-BUS-CONTROL" control unit is to carry out the data transfer between the MIL-BUS controller and the Dual-Port-Ram (DPR), whereby the associated read / write actions with reception of a " 1553 command words ". The nature of the "1553 Command Word" (Transmit or Receive) determines the type of memory access, namely:

• • 1553 Command Word Transmit ⇒ Read Access
• • 1553 Command Word Receive ⇒ Write access

• • T/!R-Bit
• • Sub-Address
• • Word-Count

In both cases, the received "1553 command word" is first stored in the DPR, and the DPR address of the associated data block, which must either be written to the DPR or read out according to the type of "1553 command word" received, turns off derived from the received "1553 Command Word" namely:

• • T /! R bit
• • Sub-Address
• • Word count

9.2.2.1.2 Description a MIL-BUS data transfer RTU → BCU (Transmit-Cmd)

Receive "1553 Command Word"

at Receiving a valid "Transmit-Commands" answers the MIL-BUS controller after a specified "Response-Time" with a "1553-Status-Word". During the transfer of the "1553 status word", the MIL-BUS controller switches for the Duration of 8.5 μs the signal "! CMD-STRB → active low "in synchronicity with a "1 MHz reference clock signal. "During this Time span, the MIL-BUS controller sets the "1553 command word" on its data output ports (D0 ... D15) available. The The task of the function groups "SSN-BUS-CONTROL", "SSN-ADDRESS-CONTROL" and "SSN-ADDRESS-REGISTER" now consists of the "1553 command word" into the dual port ram transferred to.

• • „IMBUS-Busy = false": In diesem Fall wird das „1553-Command-Word" durch den State „CMDSTSS" ins Dual-Port-Ram auf die voreingestellte Adresse übertragen.
• • „IMBUS-Busy = true": In diesem Fall wird ein Halt-State „CMDWRBY" eingefügt, in dem die State-Machine solange verharrt, bis die Bedingung „IMBUS-Busy = false" detektiert wird. Danach wird das „1553-Command-Word" durch den State „CMDSTSS" ebenfalls ins Dual-Port-Ram auf die voreingestellte Adresse übertragen.

The process of transferring the "1553 command word" into the dual port ram can be the state diagram 4 and will be described below as follows. After the "Power-On-Initiali sation "and if no data traffic takes place via the MIL-BUS, the state machine" SSN-BUS-CONTROL "remains in idle state" WAITRQ ", while at the beginning of a data transfer with change of the signal"! CMD-STRB → true "is being serviced. When this condition is met, the state machine changes to the "CMDTRUE" state, which is provided to set the "SSN-ADDRESS-REGISTER" and "SSN-ADDRESS-CONTROL" function groups to the DPR address used to save the "1553 -Command-Words "is intended to preset. The next state "CMDBUSY" is a branch state, in which it is queried whether the dual port RAM was set by an IMBUS access "Busy". Depending on the result of this query, different actions are initiated:

• • "IMBUS-Busy = false": In this case, the "1553-Command-Word" is transferred to the default address by the state "CMDSTSS" in the dual port ram.
• • "IMBUS-Busy = true": In this case, a halt state "CMDWRBY" is inserted, in which the state machine remains pending until the condition "IMBUS-Busy = false" is detected, after which the "1553- Command Word "through the state" CMDSTSS "also transferred to the dual port Ram to the default address.

To the Purpose of addressing the individual data words during their transfer from / to the DPR, will follow with state "CMDSTAC" transfer the "1553-Command-Word" into the "SSN-ADDRESS-REGISTER" and at the same time "SSN-ADDRESS-CONTROL" for initialization reset the "Word-Count".

To Receiving and saving the "1553 command word" branches the state machine in dependence whether a "Data-Transmit-Command" or a "Data-Receive-Command" was received. In both cases the state machine waits in the corresponding state "TCMDEND" or "RCMDEND" until the condition "! CMD-STRB = false "detected becomes.

Transmit "1553-Data-Words"

To Generation of the "! CMD-STRB" signal and transmission of the "1553 Command Word" into the Dual Port Ram through the control unit "SSN-BUS-CONTROL" the MIL-BUS-Controller holds the subsequent data transfer sequence until the connected subsystem receives the first 16-bit data word placed on the data bus (D0 .. D15) and its readiness with signal "! SSIU-STRB → true". In addition, the condition that the Signal "! SSIU-STRB" synchronous to "1 MHz Reference clock signal " which is supplied by the MIL-BUS controller.

Of the MIL-BUS controller stores the received 16-bit data word internally temporary in a so-called "FIFO message buffer", in order subsequently to the right time over send the MIL-BUS. So now the number commanded by the "1553-Command-Word" surpass 16-bit data words can, must Subsystem this process with a maximum allowable transfer rate of 1 MHz Repeat until the entire data block is transferred.

The Principle of data transmission from the dual port ram to the MIL bus with the possibility of arbitration concurrent IMBUS access is that everyone from the control unit "SSIU-BUS-CONTROL initiated data transfer to the MIL-BUS controller generally as long is prevented by holding the "! ENABLE-SSIU-STROBE → false" and "ISSIU-CHIP-ENABLE → false" signals, until it is ensured that no Simultaneous IMBUS-Zugrfff exists.

• • „IMBUS-Busy = false": In diesem Fall wird der Transfer des ersten Datenwortes vom Dual-Port-Ram zum FIFO des MIL-BUS-Controllers freigegeben, indem die Steuersignale „!ENABLE-SSN-STROBE (!ESSTB) → .true" und „!SSN-CHIP-ENABLE → .true" erzeugt werden.
• • „IMBUS-Busy = true": In diesem Fall wird der Transfer des ersten Datenwortes vom Dual-Port-Ram zum FIFO des MIL-BUS-Controllers gesperrt, indem das Steuersignal „!ENABLE-SSN-STROBE → false" erzeugt wird. Gleichzeitig wird ein Warte-Zyklus eingefügt nachdem erneut IMBUS-Busy überprüft wird.

The sequence of this data transfer is in the state diagram 5 and will be described in detail below. The control unit "SSN-BUS-CONTROL" starts a sequence "Data-Transmit" starting from the state "TCMDEND" when detecting "! CMD-STRB → false". Thereafter, the state machine waits for a specified period of time of 1.5 μs before the first data word is transferred with the following states "TDTAINIT", "TDAWAIT" and "TDTABUSY." The reason is that the MIL-BUS Controller requires a time delay of at least 1 μs between the two events "! CMD-STRB → false" and "! SSN-STRB → true." Then, before the first data transfer can be released, the state "TDTABUSY" checks whether There is no IMBUS bus. Depending on the result of this query, different actions are initiated:

• • "IMBUS-Busy = false": In this case, the transfer of the first data word from the dual port ram to the FIFO of the MIL-BUS controller is enabled by the control signals "! ENABLE-SSN-STROBE (! ESSTB) →. true "and"! SSN-CHIP-ENABLE → .true "are generated.
• • "IMBUS-Busy = true": In this case, the transfer of the first data word from the dual-port RAM to the FIFO of the MIL-BUS controller is disabled by generating the control signal "! ENABLE-SSN-STROBE → false". At the same time, a wait cycle is inserted after IMBUS-Busy is checked again.

• • „MSG-CPLT = false": Weil dies bedeutet, daß zusätzliche Datenworte übertragen werden müssen, kehrt die State-Machine zum State „TDTABUSY" zurück und wiederholt diesen Zyklus.
• • „MSG-CPLT = true": Dies bedeutet, daß die kommandierte Anzahl von Datenworten transferiert worden ist und damit der Übertragungs-Zyklus „Data-Transmit" abgeschlossen ist. Die State-Machine kehrt somit zum Ruhe-State „WAITRQ" zurück.

With the next state "TDTAREAD", which the state machine assumes, as long as the signal "1 MHz reference clock = high" is detected, the transmission of the first data word takes place. In addition, in this state, the increment of the word count is prepared in the "SSUI-ADDRESS-CONTROL" with the signal "ENABLE-COUNT → true". As soon as the state machine detects the signal "1 MHz reference clock = low", the dual port RAM is released again according to the arbitration principle by the signals "! ENABLE-SSN-STROBE (! ESSTB) → .false "and"! SSN-CHIP-ENABLE (! SSCE) → .false ", followed by a branch depending on the state of the" MESSAGE-COMPLETE (MSG-CPLT) "signal, namely:

• • "MSG-CPLT = false": Because this means that additional data words have to be transmitted, the state machine returns to state "TDTABUSY" and repeats this cycle.
• • "MSG-CPLT = true": This means that the commanded number of data words has been transferred and that the transmission cycle "Data-Transmit" has been completed. The state machine thus returns to the idle state "WAITRQ".

9.2.2.1.2.1 Computational verification on Adherence to the time window for data transmission

Around ensure that no Access collisions with a higher priority IMBUS access are possible as well as a already started MIL-BUS read access to the DPR within of the available a specific time window can be processed Signal "! ENABLE-SSIU-STROBE (! ESSTB) ", with the help of which read transfers are arbitrarily released or stopped can be.

The actual read signal "! SSIU-STRB", which is the MIL-BUS-CONTROLLER and to generate synchronous with the "1 MHz reference clock signal", is through a logical link of the signal "! ENABLE-SSIU-STROBE" with the "1 MHz reference clock signal" obtained in such a way, that this Read signal "! SSIU-STRB" during the positive half-period of the 1 MHz reference clock is set to "active".

Since the "! ENABLE-SSIU-STROBE" signal is also synchronized with the "1 MHz reference clock", these measures allow the MIL-BUS controller (SW) to transfer data from the DPR to the MIL-BUS within Three (3) SW Clock Periods Complete Thus, even considering a time delay of T (Syn) = 62.5 ns when synchronizing the 16 MHz IMBUS Busy signal, the condition is satisfied: T (MIL-BUS-Read) <T (time window) with: T (MIL-BUS-Read) = 3 × T (SW-cycle) + T (Syn)
T (time window) = 2 × T (IMBUS clock)

9.2.2.1.3 Description a MIL-BUS data transfer BCU → RTU (Receive-Cmd)

Receive "1553 Command Word"

Of the Receipt of a valid "1553 receive command word" means that then until to 32 data words buffered in the FIFO message buffer of the MIL-BUS controller until their validation is complete. As soon as this happens is the "1553 Status Word" from the MIL-BUS controller automatically transferred. While the transmission of the "1553 Status Word" is for a period of time of 8.5 μs the signal "! CMD-STRB → active low "switched in sync with the signal "1 MHz reference clock ". During this Time, the MIL-BUS controller sets the "1553 Command Word" on its data ports (D0 ... D15), being for its storage in the dual-port ram in this case the same thing applies, as already described under 9.2.2.1.2.

Receive "1553-Data-Words"

After the signal "! CMD-STRB" has been generated and the "1553 command word" has been transferred to the dual-port RAM by the "SSIU-BUS-CONTROL" control unit, it branches to the "RCMDEND" state and remains in this until Detection of the signal ""! CMD-STRB → false ". The MIL-BUS controller then makes the first data word available at its data ports (D0 ... D15) and signals this by means of the signal "! DTA-STRB → active low." The connected subsystem can interrupt this process by keeping this signal externally "active low". As soon as the sub-system has released the "! DTA-STRB" signal, the MIL-BUS controller transmits the next data word and this process, if it is not is interrupted again, as long as repeated until the commanded number of data words has been transferred, the maximum data rate is 1 MHz.

The Principle of data transmission from the MIL-BUS to the dual-port Ram with the possibility of arbitration concurrent IMBUS access is that everyone from the MIL-BUS controller initiated data transfer to the dual-port ram generally first as long is stopped by the signal "! DTA-STRB → active low" is switched, until it is ensured that no simultaneous IMBUS access is available.

The sequence of this data transfer is in the state diagram 6 and will be described in detail below. The control unit "SSIU-BUS-CONTROL" starts a "Data-Receive-Sequence", starting from the state "RCMDEND" when detecting "! CMD-STRB → false". This switches the state machine to the state "RDAWAIT" with simultaneous switching of the signal "ENABLE-DATA-STROBE-HOLD (EDASTHD) → true". This makes it possible that the signal "! DTA-STRB", as soon as generated by the MIL-BUS-CONTROLLER, held externally "active low" and thus the started writing process is stopped.

• • „IMBUS-Busy = false": In diesem Fall wird der Transfer des ersten Datenwortes zum Dual-Port-Ram freigegeben, indem zum State „RDAWRITE" gewechselt, das Signal „!DTA-STRB" freigegeben sowie das Signal „!SSIU-CHIP-ENABLE → .true" erzeugt wird. Gleichzeitig erfolgt die Erzeugung des nächsten DPR-Adresse mit „ENABLE-COUNT → true".
• • „IMBUS-Busy = true": In diesem Fall wird der Transfer des ersten Datenwortes zum Dual-Port-Ram gesperrt, indem zum State „RBYWAIT" gewechselt und weiterhin das Signal „!DTA-STRB = active low" gehalten wird. In diesem State verbleibt das Steuerwerk solange bis „IMBUS-Busy = false" erkannt wird. Die State-Machine wechselt dann zum State „RBYWRITE" und gibt den Transfer des Datenwortes zum Dual-Port-Ram frei.

In the state "RDAWAIT", the state machine remains pending until the start of a data transfer with "! DTA-STRB → true" is detected. At the same time, the signal IMBUS-Busy is queried and branches differently depending on its state:

• • "IMBUS-Busy = false": In this case, the transfer of the first data word to the dual-port RAM is enabled by changing to the "RDAWRITE" state, enabling the "! DTA-STRB" signal and the "! SSI- CHIP-ENABLE → .true "is generated. At the same time, the next DPR address is generated with "ENABLE-COUNT → true".
• • "IMBUS-Busy = true": In this case, the transfer of the first data word to the dual-port RAM is disabled by changing to the "RBYWAIT" state and still holding the "! DTA-STRB = active low" signal the control unit remains in this state until "IMBUS-Busy = false" is detected. The state machine then changes to the state "RBYWRITE" and releases the transfer of the data word to the dual port ram.

• • „MSG-CPLT = false": Weil dies bedeutet, daß zusätzliche Datenworte übertragen werden müssen, wird die State-Sequenz „RDAWAIT", „RDAWRITE" und „RDANADR" solange wiederholt, bis die kommandierte Anzahl von Datenworten übertragen worden ist. Dabei wird vor jedem Durchlauf der State-Sequenz zunächst das Signal „ENABLE-DATA-STROBE-HOLD (EDASTHD) → true" geschaltet. Damit wird ermöglicht, daß das Signal „!DTA-STRB", sobald vom MIL-BUS-CONTROLLER erzeugt, von extern „active low" gehalten und somit der gestartete Schreib-Vorgang angehalten wird, bis erkannt wird, daß kein IMBUS-Busy vorliegt.
• • „MSG-CPLT = true": Dies bedeutet, daß die kommandierte Anzahl von Datenworten transferiert worden und damit der Übertragungs-Zyklus „Data-Receive" abgeschlossen ist. Die State-Machine kann somit zum Ruhe-State „WAITRQ" zurückkehren.

In both cases, after the data transfer is complete, the controller will switch to the "RDANADR" state by querying whether or not the data receive sequence is complete, as provided by the "MSG-CPLT" signal:

• • "MSG-CPLT = false": Since this means that additional data words have to be transmitted, the state sequence "RDAWAIT", "RDAWRITE" and "RDANADR" are repeated until the commanded number of data words has been transmitted. The signal "ENABLE-DATA-STROBE-HOLD (EDASTHD) → true" is first switched before each pass of the state sequence, thus enabling the signal "! DTA-STRB" as soon as it is generated by the MIL-BUS-CONTROLLER , held externally "active low" and thus the started writing process is stopped until it is recognized that there is no IMBUS busy.
• • "MSG-CPLT = true": This means that the commanded number of data words has been transferred and thus the "Data-Receive" transmission cycle has been completed. The state machine can thus return to the idle state "WAITRQ".

9.2.2.1.3.1 Computational verification on Adherence to the time window for data receive

Of the MIL-BUS-CONTROLLER signals the beginning of a write transfer to the DPR by means of the signal "! DTA-STRB → true". This writing process can be stopped externally by the signal "! DTA-STRB = true " becomes. The signal "! DTA-STRB" is therefore with the signal "ENABLE-DATA-STROBE-HOLD (EDASTHD) "like this logically linked, that in the Case "ENABLE-DATA-STROBE-HOLD = false "and"! DTA-STRB → true "the signal"! DTA-STRB = true " and thus the write transfer is interrupted.

There the MIL-BUS controller under the condition "IMBUS-Busy = false" write transfers with a data rate of 1 MHz and the associated signal "! DTA-STRB" a pulse duration of ζa 500 ns has enabled this fact the MIL-BUS control unit a data transfer from the MIL-BUS to complete the DPR within two (2) SW clock periods.

Thus, even taking into account a time delay of T (Syn) = 125 ns when synchronizing the signal "! DTA-STRB" with 8 MHz, the condition is fulfilled: T (MIL-BUS-Write) <T (time window) with: T (MIL-BUS-Write) = 2 × T (SW-cycle) + T (Syn)
T (time window) = 2 × T (IMBUS clock)

9.2.2.2 Function group "CLOCK SYNCHRONIZATION"

The Programmable IC "CLOCK SYNCHRONIZATION" is provided by dividing the 16 MHz oscillator frequency clock signals from 8th; 4; 2 and 1 MHz to produce. These clock signals are intended to be internal Bus controller that handles the data transfer between MIL bus controller and Dual port ram controls to clock. Because these clock signals are phase locked to "1 MHz reference clock signal "of the MIL-BUS controller will be generated to accomplish this requirement used special comparator.

• • Synchronisation des Signals „IMBUS-Busy" mit 16 MHz bevor es dem Steuerwerk „SSIU-BUS-CONTROL" aufgeschaltet wird.
• • Erzeugung eines „PRESET-SIGNALS" zur Initialisierung des Steuerwerks „SSN-BUS-CONTROL".

Other tasks of this function group are:

• • Synchronization of the signal "IMBUS-Busy" with 16 MHz before it is switched to the control unit "SSIU-BUS-CONTROL".
• • Generation of a "PRESET SIGNAL" for initialization of the control unit "SSN-BUS-CONTROL".

9.2.2.3 Function group "INPUT SYNCHRONIZATION"

The Programmable IC "INPUT SYNCHRONIZATION" is provided to synchronize the input signals of the control unit "SSN-BUS-CONTROL". These input signals are at twice the frequency (T [1] = 125 ns), such as the stepping clock (T [2] = 250 ns) of the state machine, sampled. The reason for this measure lies in the fact that the Time duration T of the input signal to be synchronized "! DTA-STRB" may be smaller as the period of the indexing cycle (T [2]), but greater than the period of the double frequency T [1]. This means that the synchronized Output signal "! SYDAST" to make it safe from the state machine can be recognized for at least 2 sampling periods must be kept.

9.2.2.4 Function group "SSIU ADDRESS REGISTER"

The Programmable IC "SSIU ADDRESS REGISTER" is provided by one part (9 bits, ie: A10 .. A2) of the 11 bits required for read / write accesses Save dual port ram address. (the remaining two address bits (A1, A0) are stored by the function group "SSN-ADDRESS-CONTROL").

• • Speicherung „1553-Command-Word": Zum Abspeichern dieses „Interrupt-Descriptors" für den GUIDANCE-COMPUTER an der dafür vorgesehenen Adresse im Dual-Port-Ram, wird diese durch einen „Preset" der Adress-Bits (A10 .. A5) erzeugt. Gleichzeitig werden die restlichen Adress-Bits (Word-Count A4 .. A2) rückgesetzt, um eine unerwünschte Erzeugung des Signals „MSG-CPLT" in diesem Fall zu vermeiden.
• • Speicherung „1553-Data-Words": Zur Übertragung des kommandierten Datenblocks vom/zum Dual-Port-Ram wird die dafür benötigte 11-Bit Adresse vom empfangenen „1553-Command-Word" abgeleitet, wobei 9 Bit (T/R-Bit, Sub-Adresse, Word-Count-Bits A4 .. A2) in der Funktionsgruppe „SSN-ADDRESS-REGISTER" selbst und die restlichen 2 Bits (Word-Count-Bits A1, A0) in der Funktionsgruppe „SSN-ADDRESS-CONTROL" gespeichert werden.

The generation of the address is initiated by the MIL-BUS controller and performed by the control unit "SSIU-BUS-CONTROL", whereby a distinction must be made between two different types of address generation:

• • "1553-Command-Word" storage: To store this "interrupt descriptor" for the GUIDANCE-COMPUTER at the designated address in the dual-port-RAM, this is replaced by a "preset" of the address bits (A10 .. At the same time, the remaining address bits (word count A4 .. A2) are reset in order to avoid unwanted generation of the signal "MSG-CPLT" in this case.
• • "1553-Data-Words" storage: To transfer the commanded data block from / to the dual-port ram, the required 11-bit address is derived from the received "1553-command-word", whereby 9-bit (T / R) A2, in the function group "SSN-ADDRESS-REGISTER" itself and the remaining 2 bits (Word-Count-Bits A1, A0) in the function group "SSN-ADDRESS- CONTROL ".

9.2.2.5 Function group "SSN-ADDRESS-CONTROL"

• • Erzeugung „Word-Count": Die Adressen (A4 .. A0) zur Adressierung der einzelnen diskreten Datenworte innerhalb des zu übertragenden Datenblocks (max. 32 Worte) werden ausgehend vom Word-Count = 0 durch Inkrementierung der vorangegangenen Adresse gewonnen, wobei die Inkrementierung vom Steuerwerk „SSN-BUS-CONTROL" gesteuert wird.
• • Erzeugung „Message-Complete": Bei Identität zwischen dem im „SSN-ADDRESS-REGISTER" abgespeicherten Word-Count des „1553-Command-Words" und dem in der „SSN-ADDRESS-CONTROL" durch Inkrementierung erzeugten Word-Count (A4 .. A0), wird das Signal „MESSAGE-COMLETE (MSG-CPLT) = true erzeugt. Damit wird dem Steuerwerk „SSN-BUS-CONTROL" signalisiert, daß die kommandierte Anzahl von Datenworten transferiert worden und damit der Übertragungs-Zyklus „Data-Receive" oder „Data-Transmit" abgeschlossen ist
• • Erzeugung „XI-Interrupt": Nach Abschluß des kommandierten Datentransfers wird gleichzeitig das Signal „XI-Interrupt = true" erzeugt, das damit dem GUIDANCE-COMPUTER dieses Ereignis mitteilt.

The programmable IC "SSIU-ADDRESS-CONTROL" is intended for several tasks:

• • Generation "Word-Count": The addresses (A4 .. A0) for addressing the individual discrete data words within the data block to be transmitted (up to 32 words) are obtained from Word-Count = 0 by incrementing the previous address, the Incrementation is controlled by the control unit "SSN-BUS-CONTROL".
• • "Message Complete" generation: For identity between the word count of the "1553 command word" stored in the "SSN ADDRESS REGISTER" and the word count generated by incrementing in the "SSN ADDRESS CONTROL" ( A4 .. A0), the signal "MESSAGE-COMLETE (MSG-CPLT) = true is generated. This signals to the control unit "SSN-BUS-CONTROL" that the commanded number of data words has been transferred and thus the transmission cycle "Data-Receive" or "Da ta-Transmit "is completed
• • Generation "XI-Interrupt": At the end of the commanded data transfer, the signal "XI-Interrupt = true" is generated at the same time, which informs the GUIDANCE-COMPUTER about this event.

9.2.3 Structure and function the "SUB SYSTEM INTERFACE UNIT (SSIU) "

The Dual Port Ram (DPR) is a so-called "Temporary Data Memory (Data Buffer)" between MIL-BUS and IMBUS provided. Because between both interfaces 16-bit data words The DPR is made up of two 2K × 8 memory ICs in a so-called master / slave configuration. The DPR's have 2 independent ports with separate address data and control connections, the one simultaneous, two-sided read / write access allow any memory location, but the exception applies that one simultaneous access to the same memory address either avoided or arbitrated by special access mechanisms got to.

in the In the present case, such an access collision is caused by the Collaboration between the two control units "IMBUS CONTROL" and "SSIU BUS CONTROL" avoided by in a MIL-BUS access to the DPR during a simultaneous IMBUS access the MIL-BUS access is stopped to allow IMBUS access carried out unhindered can be. Thereafter, the MIL-BUS access is released again and finished.

List 1: "Text-Design-File" of the control unit "SSIU-BUS-CONTROL"

List 2: "Text-Design-File" of the control unit "IMBUS-CONTROL"

Claims (8)

A method for solving the so-called "Busy problem in the simultaneous access of IMBUS and MIL bus to a dual-port Ram" in an external interface with a bus system for information exchange between an aircraft and a missile, characterized in that with simultaneous access of IMBUS and MIL-BUS on the dual-port RAM, the access priority for IMBUS access is set higher and that a time window of two IMBUS clock periods, ie from the beginning of IMBUS access to the beginning of the actual IMBUS data transfer at the conclusion of a used shortly before and thus taking place within this time window MIL-BUS access that a special MIL-BUS control unit (SW) is provided to control the MIL-BUS accesses to the DPR, which is clocked with a clock signal , which is generated in phase with a supplied by the MIL-BUS controller "1 MHz reference clock signal" and whose frequency an even multiple (Fa ktor: 4) corresponds to this reference clock, and that in order to avoid access conflicts with the IMBUS before each data transfer from the DPR to the MIL-BUS controller queried the "IMBUS-Busy signal" by the MIL-BUS control unit and also the " 1 MHz reference clock "also sampled in order to synchronize the" MIL-BUS-Read-Enable "signals to be generated by the control unit and" MIL-BUS-Chip-Enable "with the" 1 MHZ reference clock ". Method according to Claim 1, characterized in that the following measures are taken to determine the access priorities: - Generation of a "special IMBUS busy signal", the "IMBUS busy signal" generally occurring at each IMBUS access, independently of the IMBUS Address, is generated, - Generation of the "IMBUS Busy signal" at the earliest possible time t, ie immediately upon detection of a IMBUS data traffic addressed to the external interface (XI), generation of the "IMBUS busy signal" for the entire duration of the IMBUS access, generation of the enable signal "IMBUS chip enable required for IMBUS access to the DPR "only after receiving the IMBUS address with the beginning of the IMBUS data transmission, - activating the enable signal" IMBUS chip enable "only for the duration of the IMBUS data transmission, and - using the time window obtained from two (2) IMBUSs Clock periods, ie from the beginning of IMBUS access to the beginning of the actual IMBUS data transfer to the conclusion of a recently started and thus taking place within this time window MIL-BUS access. Method according to claim 2, characterized in that that to Control of IMBUS accesses to the DPR a special IMBUS control unit (ISW), which is clocked with a clock signal, the dependent on is generated differently by the received control word (CNTR) in fact: - • CNTR = valid ⇨ ISW-Clock = IMBUS-CLK & IMBUS-SYNC - • CNTR = invalid ⇨ ISW clock = IMBUS CLK. Method according to claim 3, characterized that the Access of the MIL-BUS to the DPR under the following measures to control the MIL-BUS read / write accesses: - the MIL-BUS-side In the idle state, the DPR is controlled in such a way that IMBUS access to the DPR is unhindered at all times carried out can be - the transfer of a MIL-BUS data block from / to the DPR is performed word by word, wherein before each single-word transmission the IMBUS busy signal is polled and then in dependence from the state of the IMBUS busy signal the data transfer is started or is stopped - Read / write accesses of the MIL-BUS on the DPR are before and after each single-word transmission locked by the associated Enable signal "MIL-BUS-Chip-Enable → false" is switched, to the DPR for IMBUS accesses release and - to Control of MIL-BUS accesses to the DPR is provided by a special MIL-BUS controller (SW), which is clocked with a clock signal that is phase locked a generated by the MIL-BUS controller "1 MHz reference clock signal" is generated and whose frequency is an even multiple (factor: 4) this Corresponds to reference clocks. Method according to Claim 3, characterized in that the MIL-BUS accesses the DPR under the following measures for carrying out the MIL-BUS read accesses: • To ensure that access collisions with a higher prioritized IMBUS access are not possible, as well as an already started MIL-BUS read access to the DPR within the available time window can be handled, a special signal "MIL-BUS-Read-Enable" is generated, with the help of read transfers can be freely enabled or stopped and thus the desired word-wise data traffic is made possible, • the actual read signal "read-strobe", which aufzuschalten the MIL-BUS controller and which is to be generated synchronously with the "1 MHz reference clock signal", by a logic operation of the signal "MIL-BUS-Read-Enable" with the "1 MHz reference clock signal" obtained such that the read signal "Read Strobe" during the positive half-P • the "MIL-BUS-Read-Enable" signal is also synchronized with the "1 MHz reference clock", which causes the MIL-BUS controller (SW ) terminates a data transfer from the DPR to the MIL bus within three (3) SW clock periods, and thus, even taking into account a time delay of T (Syn) = 62.5 ns, when synchronizing the IMBUS Busy signal at 16 MHz, the condition is fulfilled: T (MIL-BUS-Read) <T (time window) with: T (MIL-BUS-Read) = 3 × T (SW-cycle) + T (Syn) T (time-window) = 2 × T (IMBUS-cycle) Method according to Claim 5, characterized in that the processing of the IMBUS-Busy signal in the case of MIL-BUS read accesses takes place under the following measures: To avoid access conflicts with the IMBUS, the DPR to the MIL-BUS controller is precluded before each data transfer "IMBUS Busy signal" queried by the MIL-BUS control unit and also the "1 MHz reference clock" also sampled to the signals to be generated by the control unit "MIL-BUS-Read-Enable" and "MIL-BUS -Chip-Enable "to synchronize with the" 1 MHZ reference clock ", in case IMBUS busy = false & 1MHz reference clock = low (0) the MIL-BUS read transfer by generating the signals: - enable read strobe by "MIL-BUS-Read-Enable → true" - enable access DPR by " MIL-BUS-Chip-Enable → true "is enabled and in case of IMBUS-Busy = false & 1MHz-reference clock = high (1) the MIL-BUS read transfer by holding the signals: -" MIL-BUS-READ " Enable = true "-" MIL-BUS-Chip-Enable = true "is performed and the read access, as soon as" 1 MHz reference clock = low (0) "is detected, by generating the signals: - Disable Enable read-strobe by "MIL-BUS-Read-Enable → false" - locks access DPR with "MIL-BUS-Chip-Enable → false" is terminated and in case of IMBUS-Busy = true & (1MHz reference clock = low # 1MHz reference Block = high) the MIL-BUS read transfer by generating the signals: - disable enable read strobe by "MIL-BUS-Read-Enable → false" - disable access DPR with "MIL-BUS-Chip-Enable → false" prevented and egg n Waiting cycle is inserted from a reference clock period after the "IMBUS busy signal" is again requested. Method according to one of the preceding claims, characterized in that the execution of the MIL-BUS write accesses takes place under the following measures: in order to ensure, in the case of a write access of the MIL-BUS to the DPR, that no access collision with a higher-priority IMBUS Access is possible, as well as an already started MIL-BUS access can be performed within the available time window, the block transfer from the MIL-BUS to the DPR is also released only word by word. The criterion for enabling a word transfer to the DPR is provided by the "IMBUS-Busy-Signal", wherein for release itself a special signal "MIL-BUS-Write-Enable" is generated, with the help of which the writing process is enabled "MIL-BUS -Write-Enable → true "or can be stopped, since it is generally the case that the MIL-BUS side of the DPR in idle state, ie no MIL-BUS traffic takes place, is controlled in such a way that IMBUS accesses the DPR can be performed unhindered at any time, this means that write accesses of the MIL-BUS to the DPR before and after each single-word transmission are blocked by the signals "MIL-BUS-Write-Enable → false" and "MIL-BUS -Chip-Enable → false "because the MIL-BUS controller signals the beginning of a write transfer to the DPR by means of the signal" Write-Strobe → true "and this writing process is stopped externally (state:" Hold ") can by holding the signal "Write-strobe = true""Write-strobe" is logically linked to the signal "MIL-BUS-Write-Enable" in such a way that in the case of "MIL-BUS-Write-Enable = false" and "Write-strobe → true" the signal "Write -Strobe = true "and the write transfer is interrupted. Since the MIL-BUS controller carries out write transfers with a data rate of 1 MHz under the condition "IMBUS-Busy = false" and the associated signal "Write-strobe" has a pulse duration of approximately 500 ns, this fact enables the MIL BUS controller to complete a data transfer from the MIL-BUS to the DPR within two (2) SW clock periods. Thus, even taking into account a time delay of T (Syn) = 125 ns when synchronizing the signal "Write Strobe" with 8 MHz, the condition is met: T (MIL-BUS-Write) <T (time window) with: T (MIL-BUS-Write) = 2 × T (SW-cycle) + T (Syn) T (time-window) = 2 × T (IMBUS-cycle) Method according to Claim 7, characterized in that the processing of the IMBUS-Busy signal in the case of MIL-BUS write accesses takes place under the following measures: To avoid access conflicts with the IMBUS, the MIL-BUS controller is in front of the data transfer from the MIL-BUS controller to the DPR "IMBUS Busy signal" queried by the MIL-BUS control unit and also sampled the 8 MHz synchronized signal "Write Strobe" to detect the beginning of a write transfer, in the case Write-strobe = false (IMBUS -Busy = X) the control unit remains in the wait state "Wait: Write strobe → true" and blocks the write access to the DPR by generating the signals: - Disable access DPR with "MIL-BUS-Chip-Enable = false" - Enable hold Write-strobe = true with "MIL-BUS-Write-Enable = false" and in case Write-strobe = true & IMBUS-Busy = false a write access to the DPR is performed with: - Enable access DPR by "MIL-BUS-Chip-Enable → true" - Enable write-strobe by "MIL-BUS-Write-Enable → true" and in the case of Write-strobe = true & IMBUS-Busy = true Write access to the DPR by generating the signals: - Disable access DPR with "MIL-BUS-Chip-Enable → false" - Hold Write-Strobe = true with "MIL-BUS-Write -Enable → false "is prevented and the control unit then remains in the wait state" Wait: IMBUS-Busy → false "until the condition" No-Busy "is detected and the write operation can be performed.