DE10322588B4 - Method for producing a resistance layer - Google Patents

Abstract

Method for producing a resistance layer (38) on a substrate (30, 31), comprising the following steps:
Depositing (10) a polycrystalline layer (32) having a crystal structure on the substrate, the crystal structure having a crystallite grain structure having a first average grain size;
at least partially destroying (12) the crystal structure in a first region (35) of the polycrystalline layer (32), whereby an amorphous material is obtained in the first region;
after the step of destroying (12), performing (13a) an implantation such that a second area of the polycrystalline layer deposited in the step (10) different from the first area (35) in which the crystal structure is destroyed, is doped to a predetermined level; and
after the step of performing (13a) implantation, annealing (14) the first region (35) until the first region (35) has a predetermined crystallite grain structure having a second mean grain size different from the first mean grain size which makes the resistance layer ...

Description

The The present invention relates to integrated circuits and in particular to the manufacture of resistors in integrated circuits.

In an analog integrated circuits play with resistors Good electrical properties are crucial. In the Silicon technology, these resistors, for example, from polysilicon layers produced with suitable doping. However, significant electrical parameters are dependent not only of the dopant and its concentration, but also from the grain structure, and especially from the average size of the crystallites. One important parameter is the so-called matching. Under matching one understands the width of the distribution of the resistance values of neighboring ones resistors due to statistical fluctuations in the number of crystallites in a given resistance.

One second important parameter is the smallest possible specific resistance, which also by a further increase the dopant concentration can not be reduced, and the in the following as saturation resistance is designated.

One good matching is for various analog circuits, e.g. Differential amplifier or A / D converter, important. Low specific resistances on the other hand are for Low-resistance connections and connections, but also for the realization of precise resistors with small values, e.g. 50 ohm terminators, in RF circuit technology important.

One integrated polysilicon resistance is usually realized by that a polysilicon layer with a certain crystal structure on a insulating substrate is applied. You already have one Resistor layer generated, their specific resistance without further activities for the However, most applications are too high (> 100 ohm cm) and fluctuates too much. to Lowering and more precise adjustment of the specific resistance and hence the sheet resistance is therefore by means of ion implantation made a doping of the polysilicon. This is followed in a healing or annealing step, which is also referred to as "annealing", an annealing of the affected by the implantation crystal structure of polysilicon, to "activate" the doping atoms.

at the above mentioned Implantation becomes the crystallite structure of the originally applied polycrystalline Layer, ie the mean grain size of the crystallites in the polysilicon, not changed. Implanting causes only crystal injuries to the extent that the mean grain size in the originally applied polycrystalline layer is not affected.

This Concept is disadvantageous in that the grain structure of the finally obtained Resistance layer already from the outset, so by the application the polycrystalline layer is determined. If you bring a polycrystalline layer with a small crystallite size, So a fine-grained polycrystalline layer, so leads this, to the extent that a better matching is achieved, on the other hand is the minimum resistivity, that is, the resistance can be achieved minimally, if maximum doping, down limited. With a fine-grained Polysilicon layer can Therefore, no small resistance values can be achieved, as for example for HF circuits needed become.

Becomes however, from the outset a coarse-grained polycrystalline layer applied, so although a smaller minimum resistance can be achieved become. However, it has turned out that the matching suffers.

Become now requires two different types of resistors, namely on the one hand resistors, the have a good match with each other, and on the other hand, resistances that have small resistance values, then these are two opposing goals not available. Nevertheless, to achieve both goals as well as possible therefore, it usually becomes a compromise on the grain size of the originally applied Polycrystalline layer chosen, at least approximate both goals to reach. However, it is immediately apparent that both goals only approximate be achieved, so not as good as it would be desirable.

The U.S. Patent No. 4,762,801 discloses a method of manufacture of resistances polycrystalline silicon with desired temperature coefficients, being first a polycrystalline silicon layer is applied, which subsequently in amorphizes a region and then annealed, so that polycrystalline Silicon with new grain structure arises.

US Pat. No. 6,524,924 B1 discloses a method of manufacturing a semiconductor device comprising a conductive structure, such as a polycrystalline silicon resistor, whose resistance value is controlled. Here, a two-layered structure with a first layer of polycrystalline silicon of large grain size and a second layer of polycrystalline Sili used with small grain size, wherein the first layer has a positive temperature coefficient, while the second layer has a negative temperature coefficient.

The U.S. Patent No. 5,548,132 A discloses a thin film transistor having a DRW offset region, which has a high grain size and source and drain regions having a small grain size.

The EP 1 065 704 A2 discloses a polysilicon low temperature coefficient resistor. In particular, a polysilicon layer is used which is provided with a BF2 implant.

The Object of the present invention is to provide a more flexible To provide method for producing a resistance layer.

These The object is achieved by a method according to claim 1.

The present invention is based on the finding that a more flexible concept is achieved in that initially a polycrystalline layer is applied, but then the crystal structure is destroyed at least in a region of the polycrystalline layer, so that in this region of the polycrystalline layer an amorphous material is obtained, ie, a material in which no crystalline order is present. By properly annealing the layer, the amorphous region is recrystallized in such a manner that the region has a predetermined crystallite grain structure having an average grain size different from the mean grain size of the originally deposited polycrystalline layer. You can choose the annealing so that the grain structure of the non-amorphized area remains unchanged. With the usual substrates (eg silicon wafer with SiO ₂ insulation layer), it is therefore expedient to heat the entire sample homogeneously; technically difficult local heating is not required.

The inventive concept is advantageous in that a developer is not a priori on a chosen from a compromise crystallite structure of originally has to leave applied polycrystalline layer, but that he the crystal structure of the polycrystalline layer in regions, So you can always set it locally as needed for the specific purpose. Does he need at a location of an integrated circuit, e.g. a fine-grained structure, since a good matching is required here, but only relatively high impedance resistors need to be implemented, so is according to the invention at this Place after the destruction the crystal structure of the original applied polycrystalline layer in the step of tempering a fine-grained Structure generated. Requires the Developers at another point in the integrated circuit small Resistance values only with a coarse-grained polycrystalline layer are achievable, so after a complete destruction in the Range, ie after an amorphization in this area, the local is limited, produced in the step of tempering a coarse-grained crystallite grain structure, through the low-impedance resistors feasible, in which case, before the annealing step, So after the step of destroying the Crystal structure is still performed its own implantation.

In a preferred embodiment of the present invention, an implantation with heavy ions in a sufficiently high dose is performed to destroy the crystal structure. In a preferred embodiment, the ions are already dopants, such as As (arsenic) or BF ₂ (boron difluoride, boron is used as a dopant), so that the second implantation can be dispensed with. Alternatively, ions can be used to destroy the crystal structure, which do not affect the conductivity of silicon within the required doses. For example, germanium (Ge) may be mentioned here.

The inventive concept of destruction of the crystal structure and the subsequent adjustment the crystallite structure delivers to a desired grain size the required flexibility to the effect that for resistors applied with different properties only a single polysilicon layer must be, their grain structure then changed locally as needed will, so for each resistance type is selected the optimum grain size. You do not have to more compromises are made, but it can be the required accordingly resistors always realized with the optimum grain size become.

at a preferred embodiment of Present invention, the polysilicon layer already with applied to a particle size, the for requires a resistance type becomes. In areas of the polysilicon layer, where another Resistance must be realized, so for example, a lower resistivity of the resistive layer becomes the crystal structure destroyed, while the other area, which is, for example, fine-grained and already has the desired granularity for the has another resistance type is masked. This will be two realized different resistance types, their properties to the respective needs are optimally adapted.

preferred embodiments The present invention will be described below with reference to FIGS attached drawings explained in detail. Show it:

1 a sequence of steps for the inventive method for producing a resistance layer;

2 a sequence of steps for the inventive method for producing a resistance layer according to a preferred embodiment;

3a to 3d a sequence of steps of the preferred method including the intermediate structures obtained between the steps.

Before detailing the present invention with reference to the 1 . 2 and 3a to 3d First, consider an approach that could be chosen to optimally design each type of resistor. For this purpose, two types of resistances could be realized by depositing and patterning two different polysilicon layers with corresponding properties. In this case, the LPCVD process with dichlorosilane as precursor could be used as the deposition process. The morphology of the layer essentially depends on the deposition temperature. A "fine-grained" polycrystalline layer with a crystallite size of, for example, 50 nm is formed at temperatures above approximately 600 ° C.

A "grainy" texture with a Crystallite size of some receives one hundred nm on the other hand, if the layer is first deposited amorphously, So at temperatures below about 550 ° C, and then in another Tempering step up to 700 ° C is crystallized out slowly. The latter layer has one around about the factor 3 lower saturation resistance as the former. Therefore shows the fine-grained Layer, as stated has been a much better matching.

Furthermore would it be also possible, to further reduce the resistivity the resistance paths to silicate or also generally certain metal layers, such as e.g. Tantalum Nitride (TaN), to use.

One Another concept would be in it, resistances not made of poly but of monosilicon layers. Here receives Optimal matching and at the same time realize low specific resistances. The electrically optimal case of decoupling from the substrate is obtained with so-called. SOI substrates (Silicon on insulator), which are significantly more expensive than standard Si wafers. moreover in monosilicon the temperature coefficient is always negative while it is in polysilicon depending resistivity and dopant also have positive values can accept and at a certain spec. Resistance in first approximation disappears, which is a special advantage.

The The prior art method described above in detail so dar. First For example, a layer of amorphous silicon is deposited on a substrate. Then an implantation and a tempering is performed to after all to get a low resistance. This first applied Polysilicon layer (poly 1) thus serves that in her low-impedance resistors will be realized. Then a first lithography is performed to the areas where finally a low resistance layer should be left standing, in front of you subsequent Plasma etching to protect. After the plasma etching step a photoresist removal is performed, followed by a subsequent cleaning followed. Then the remaining first polysilicon is annealed. Then an oxide is applied. After the oxide application, the second polysilicon layer deposited. For this purpose, a crystalline polysilicon layer used. The second polysilicon layer is intended to serve high-impedance resistors to realize, why in the sense of a better matching an im Compared to the first polysilicon layer finer crystalline material is applied. Then an implantation is performed to high-impedance resistors with a specially desired To reach resistance value. Finally, the second polysilicon layer with a corresponding photoresist structure on photolithographic Provided ways. Thereupon, unnecessary areas of the second Layer by plasma etching removed, finally to obtain an integrated circuit after photoresist removal, which includes two types of resistances, depending on the circumstances can be optimally adapted.

The concept according to the invention described below leads to a substantial simplification compared to the use of two different polysilicon layers, by first of all, as shown in FIG 1 at 10 is shown, a polycrystalline layer is applied with a certain first grain size. In a subsequent step 12 Then, the crystal structure is destroyed in a portion of the deposited polycrystalline layer. The step 12 may further comprise an optional doping, if necessary, to finally reach a certain resistance of the resistive layer. In a final step 14 the layer or the entire sample is annealed to a locally be in the amorphized region To achieve limited morphology, in which the average size of the crystallites is given by a second grain size, which differs from the first grain size of the originally applied polycrystalline layer. As mentioned above, if the process parameters (temperature and duration of tempering) are suitably chosen, the grain structure of the undamaged regions of the polysilicon layer does not change or does not change significantly.

According to the invention, the process management is thus simplified compared to the technique by means of two polysilicon layers in that only a single layer is deposited, and that then their grain structure is changed locally. For this purpose, the crystal structure of the layer at the desired locations is preferably destroyed by implantation of heavy ions in a sufficiently high dose. The minimum dose required depends on the ion species and can be found in the literature [WE Beagle, JC Tsai and RD Plummer: Quick Reference Manual for Silicon Integrated Circuit Technology, Wiley, New York, 1985]. For As it is for example about 2 × 10 ¹⁴ cm ^-2 . In practice, slightly higher doses are to be preferred, since it must be ensured that no crystalline residues remain in the amorphized layer at which a fine-grained recrystallization would take place in the subsequent heat treatment step. The implantation energy is preferably to be chosen so that the mean penetration depth corresponds to about half the layer thickness.

The Now locally amorphous layer is then depending on the embodiment directly or after appropriate doping so annealed that that ultimately for the resistance layer desired grain structure is formed.

A crucial factor for the present invention is that the heat treatment can be chosen within wide limits so that the structure of the undamaged areas of the layer does not change. Depending on requirements, one can start with either a fine-grained texture, ie an initially fine-grained polysilicon layer in the step 10 Apply and bring the amorphized areas by annealing in the coarse polycrystalline state. Alternatively, in the step of applying 10 a coarse-grained texture may be started, and the amorphized regions may then be converted to the fine-grained polycrystalline state by, for example, a hot RTP (Rapid Thermal Processing) annealing step. A choice between these two variants depends on the overall process and other details of the resistor specifications. Later, based on the 3 set forth the former variant, which is started with a fine-grained polycrystalline material.

Compared to the described method with two polysilicon layers, the in 1 only one deposition step (instead of three deposition steps in the two-layer process) and only one dry etching step (instead of two dry etching steps in the two-layer process).

One another important advantage is that it is not necessary a second layer over to structure an already structured first layer. In In fact, such a scenario often results in unwanted etching residues on the edges, the Also referred to as a "spacer".

Furthermore have low-resistance non-silitated resistors, as they by the inventive concept can be obtained, benefits in matching and scattering. Although TaN resistors have good device properties, but are in litigation more complex and need often additional Process steps.

By the inventive concept can also more than two different grain structures in a single polycrystalline Layer can be realized so that a developer not only between two crystalline structures but the locally varying crystal structure depending on the particular Can interpret needs, thus for Any resistance with regard to the required resistance value to achieve optimal matching.

The inventive concept in other words, is that amorphization is preferably used by ion implantation, in one Polysilicon layer produce locally different grain structure, and thus to realize in a layer two or more independently optimizable resistors. Especially for Products in which precision resistors are needed such as. Analog circuits, mixed-signal circuits, ie circuits, process the analog and digital signals, and become HF products the resistance production according to the invention used advantageously. The inventive method is suitable for all silicon-based Semiconductor technologies, e.g. for CMOS, BiCMOS and bipolar technologies, and above out for all the technologies associated with the polysilicon deposition and the mentioned annealing steps are compatible.

The following is based on 2 and on the basis of 3a to 3d an overview of the sequence of process steps according to a preferred embodiment of the present invention given. First, in the step 10 on a typically semiconductor substrate 30 , that with an oxide layer 31 is provided, a fine-grained polysilicon 32 applied. In 3a is the fine grain of the layer 3a characterized by a narrow hatching. Further, to destroy the crystal structure in a region of the layer 32 first a lithography step 12a and a subsequent implantation step 12b carried out. The lithograph in step 12a ensures that, as it is in 3b a part through a photoresist mask can be seen 33 before implantation atoms (or molecules) 34 is protected while another area 35 the implantation atoms 34 is fully exposed. While in by the photoresist 33 protected area of the polysilicon layer 32 Thus, no changes in the crystal structure takes place in the area 35 as shown by the no longer existing hatching, preferably a complete destruction of the crystal structure by the implantation 34 achieved with a correspondingly selected dose.

It should be noted again that the bombardment of the silicon layer in the range 35 can be carried out such that already electrically effective doping atoms are implanted. If the implantation achievable thereby is not yet sufficiently large, then a second implantation step can be made before referring to FIG 3c described photoresist removal take place around the area 35 especially to dope, so make low-impedance. Here, preferably, the still existing photoresist mask 33 be exploited so as not to dope the fine-grained polysilicon region, if the same is to remain, for example, high impedance.

After this in the step 12b from 2 optionally to be performed doping is then in one step 12c performed a photoresist removal, so that also at the area 35 adjacent region of the polysilicon layer 32 is exposed. Typically, the fine-grained polysilicon will serve to realize higher resistance resistors. However, the resistance of the resistive layer typically still needs to be adjusted accordingly. Therefore, take place in one step 13 an implantation of in 3b Instead, this implantation can be based on the desired resistance value for the high-resistance resistors. Out 3b It can be seen that this also affects the area 35 is implanted. The implantation of this area, however, will have no effect, since this area is already covered by the already 3b shown implantation has been doped before the photoresist removal such that its doping is higher than that in the step anyway 13 effected implantation of the area in which eventually high-impedance resistors are to be realized. In any case, by (partial) use of non-doping substances (eg Ge) for amorphization always the desired resistance values (above the minimum possible) can be generated in all sub-areas.

In one step 13b then the substrate is cleaned. In one step 14 as already stated by 1 is then remedied. The structure present after the healing is in 3b shown. It can be seen that while the fine-grained polysilicon layer has not been affected by the annealing, but from the area 35 (the area with the amorphous silicon) now a coarse-grained polysilicon layer is formed. Finally, there will be a final lithograph 15a for defining ultimate resistances, then in one step 15b a preferably plasma etching, which then, after a photoresist removal in one step 15c finally in 3d he holds the object. The further process control (for the generation of contacts and the wiring) can be done by known methods.

3d shows the case where on a single substrate and by the application of a single polysilicon layer 32 a first high resistance resistor 37 and a second low resistance 38 have been realized. The first high-impedance resistor 37 includes a fine-grained crystal structure, which is characterized by a good matching, but has the property that no arbitrarily low-resistance resistors are feasible.

The second resistance 38 On the other hand, it has a coarse-grained crystalline structure which causes this resistance to be low-resistance. However, the matching of the second resistor may be worse than the matching of the first resistor.

Starting from amorphous silicon, as in 3b in the area 35 is shown, it is preferable to the annealing step 34 at temperatures between 600 to 800 degrees Celsius for a certain (longer) period to perform long, with the exact choice of temperature or temperature profile, the average grain size can be adjusted. Will be different from the in 3a to 3d shown embodiment, first as a polysilicon layer 32 applied a coarse-grained layer, it is preferred to perform a short annealing (RTP) at temperatures above 800 ° C.

With regard to crystallite sizes, it should be noted that fine-grained polysilicon layers typically have crystallite sizes of 30 to 100 nanometers, with small values being preferred for optimal matching, while coarse-grained textures have crystallite sizes of over 200 nanometers, preferably in the range from 300 to 600 nanometers [T. Kamins: Polycrystalline Silicon for Integrated Circuit Applications, Kluwer, Boston, 1988, p.53ff]. On the other hand, amorphous materials are said to exist when the "crystallites" consist of only a few atoms, or in other words, if the distances of the atoms in the solid are statistically distributed around the mean distance and if there is no long - range order of the atoms with the fixed atomic distance of the Crystal lattice gives more.

10

apply a polycrystalline layer

12

Destroy the Crystal structure in an area of

layer

12a

lithograph for the amorphization

12b

implantation

12c

Photolackenfernung

13a

implantation

13b

Clean

14

temper of the area

15a

lithograph for the resistance paths

15b

plasma etching

15c

Photoresist removal

30

substratum

31

oxide

32

polysilicon

33

Photoresist mask

34

implanting atoms or molecules

35

Area, in which the crystal structure is destroyed

37

High impedance Resistance with fine-grained

polysilicon structure

38

Low impedance Resistance with coarse grained

polysilicon structure

Claims (11)

Method for producing a resistance layer ( 38 ) on a substrate ( 30 . 31 ), with the following steps: application ( 10 ) a polycrystalline layer ( 32 ) having a crystal structure on the substrate, the crystal structure having a crystallite grain structure having a first average grain size; at least partial destruction ( 12 ) of the crystal structure in a first region ( 35 ) of the polycrystalline layer ( 32 ), whereby an amorphous material is obtained in the first region; after the step of destroying ( 12 ), Carry out ( 13a ) implantation, so that a second area of the in the step ( 10 ) applied polycrystalline layer extending from the first area ( 35 ) in which the crystal structure is destroyed is doped to a predetermined level; and after the step of performing ( 13a ) implantation, annealing ( 14 ) of the first area ( 35 ) until the first area ( 35 ) has a predetermined crystallite grain structure having a second mean grain size different from the first mean grain size, whereby the resistive layer (10) 38 ). The method of claim 1, wherein in the step ( 12 ) of destroying an ion implantation ( 12b ) is carried out. Method according to Claim 1 or 2, in which the polycrystalline layer ( 32 ) before the step ( 12 ) of destroying with a mask ( 33 ) is masked ( 12a ), whereby a destruction of the crystal structure only in the first area ( 35 ) passing through the mask ( 33 ) is defined. Method according to one of the preceding claims, wherein the polycrystalline layer has a fine-grained crystal structure and by the step of tempering ( 14 ) a coarser-grained structure is obtained. Method according to one of Claims 1 to 3, in which the polycrystalline layer ( 32 ) has a coarse-grained structure and by the step of annealing ( 14 ) a fine-grained structure is obtained. The method of claim 5, wherein the step of Annealing comprises a rapid thermal processing annealing step. Method according to one of the preceding claims, in which in the step of destroying ( 12 ) at the same time a doping ( 12b ) is carried out. Method according to one of the preceding claims, wherein before the step ( 14 ) of the annealing a further implantation is performed in the first area ( 35 ) in which the crystal structure in the step ( 12 ) of destroying, to obtain a high dopant concentration, whereby finally the resistance layer ( 38 ) is obtained with a low ohmic resistance. Method according to one of claims 1 or 2, in which the polycrystalline layer ( 32 ) before the step ( 12 ) of destroying with a mask ( 33 ) is masked, whereby a destruction of the crystal structure only in the first area ( 35 ) passing through the mask ( 33 ), and after which step ( 14 ) annealing a structuring sequence ( 15a . 15b . 15c ), whereby from the first area ( 35 ) a low resistance ( 38 ), and whereby from a part of the polycrystalline layer ( 32 ) passing through the mask ( 33 ) has been masked, and in which no destruction of the polycrystalline structure has taken place, a high resistance is obtained. Method according to claim 9, in which the step ( 14 ) is carried out so that the crystallite grain structure in the first region of which the low resistance is formed is different from the crystallite grain structure having the high resistance. Method according to one of the preceding claims, in which an average size of the crystallites in a region of the semiconductor layer ( 32 ) after the step ( 14 ) of the annealing is less than 100 nm, and an average size of the crystallites in another region of the semiconductor layer ( 32 ) after the step ( 14 ) of annealing is greater than 150 nm.