DE10313645A1 - Data processing system for a program controlled unit in which memory access processes by different elements of the data processing system are combined to reduce the number of memory accesses and increase data transfer rates - Google Patents

Abstract

Data processing system has a data processing core (C) or CPU for processing data (Dx). Data is written to or read from a memory (S) by a read or write access to the memory and such an access process combines access requests of a first data processing unit with those of a second data processing unit (L).

Description

The The present invention relates to a device according to the preamble of claim 1, i.e. a system with a data processing device for processing data, and a storage device for storing of data, whereby the data processing device transfers the data from it processing data by appropriate read access to the memory device reads from the memory device, and / or in the data processing device generated data by appropriate write access to the memory device writes to the storage device.

On such a system is, for example, a program-controlled unit such as a microprocessor, microcontroller, or signal processor, or a system containing a program-controlled unit.

The mentioned The data processing device is the core or the CPU of the program-controlled unit; said storage device can one inside the program-controlled unit or one outside the memory device provided in the program-controlled unit his.

Programmatic Systems are units and program-controlled units for many years in countless embodiments known so that on further explanations is waived.

On known problem of program-controlled units and program-controlled Systems containing units are that they are often not work as fast as you would like.

It are different options known the working speed of program-controlled units and systems containing program-controlled units. The best known way consists in the increase the clock frequency. As is known, the clock frequency is not arbitrary chosen high can also be found here relatively quickly to not or only with a great deal of effort to overcome Limits. One more way consists in using a program-controlled unit that contains several cores or CPUs working in parallel. The construction and operation such a program-controlled unit, however, with a very huge Associated effort.

The The present invention is therefore based on the object Preamble of claim 1 claimed system with as much as possible to develop with little effort such that its performance can increase.

This The object is achieved by the System claimed in claim 1.

The system according to the invention is characterized in that the Data generated by a read access of the data processing device read from the storage device to the storage device be processed by both the data processing device Data as well as to be processed by a second data processing device Data include, and / or that through a write access of the first data processing device the storage device is written into the storage device Data both data generated in the first data processing device as well as data generated in the second data processing device include.

By the provision of these features eliminates the need to read out that to be processed by the second data processing device Data from the storage device and / or to write the data generated by the second data processing device in the storage device has its own access to the storage device must be done. Because of that fewer accesses to the storage device than are the case would be if both the first data processing device and the second Access data processing device on the storage device would and this in turn has the positive effect that the amount of data between the storage device and the data processing devices can be transferred per unit of time is larger than would be the case if both the first data processing device and the second Access data processing device on the storage device would. By the higher one Amount of data between the storage device and the data processing devices The data processing devices can be transferred per unit of time work faster, and accordingly the performance increases of the system.

advantageous Developments of the invention are the dependent claims following description, and the figures.

The The invention is described below with reference to exemplary embodiments closer to the figures explained. Show it

1 a first embodiment of the system described below,

2 a second embodiment of the system described below,

3 a third embodiment of the system described below,

4 a fourth embodiment of the system described below, and

5 a fifth embodiment of the system described below.

The The system described below is a system with a first Data processing device for processing data, a second data processing device for processing data, and a storage device for storing the data to be processed by the data processing devices and the data generated by the data processing devices.

The The first data processing device is in the example considered formed by the core or the CPU of a program-controlled unit, the second data processing device by an outside logic provided by the program-controlled unit, and by the storage device a data memory provided within the program-controlled unit.

The program-controlled unit is, for example, a microprocessor, a microcontroller, or a signal processor.

The program-controlled unit, more precisely the core of it introduces Program. The program determines the core for execution Operations. These operations involve processing data, the program specifies where the data to be processed is stored, such as the data to be processed and what to do with the the data generated data processing has to happen. The core fetches the data to be processed by it through the Program specified position, processes this data to that of Program specified way, and writes the generated here Data to the location specified by the program.

The Data to be processed by the core is shown in the example in the aforementioned storage device stored, and in this storage device also from the Core generated data written. Are in this storage device also the data stored by that formed by the logic second data processing device to be processed, and in this storage device also becomes the data generated by the logic written.

The Storage device is volatile memory such as RAM and includes multiple memory banks, where with each read access to the memory device, data from several or all memory banks are output from the memory device, and with each write access data is written to several or all of the memory banks on the memory device become.

The second data processing device implemented by the logic can be much simpler than the core of the represented program-controlled unit first data processing device: in particular, it does not have to relate to the Storage device can access in which the data to be processed are stored and in which the data generated by it are to be stored, and it must also do not run a program can; it "only" has to be supplied with data can process in a given way. Reading the from the logic data to be processed from the storage device and writing the data generated by the logic into the memory device is done by the core of the program-controlled unit. More accurate it is said that the Data that is read by the core to the storage device can be read from the memory device, both to be processed by the core Data, as well as data to be processed by logic, and that the by write access by the core to the memory device in the memory device written data both generated in the core Data as well as data generated in logic include.

The the logic forming the second data processing device can, but need not, be configurable logic that can be reconfigured if necessary can.

in the The following are various embodiments of such Arrangement described.

The first embodiment is in 1 shown. The in the 1 The arrangement shown contains a first data processing device formed by a core C of a program-controlled unit, a second data processing device formed by logic L, a storage device S, and a multiplexer MUX3.

• – werden über den Write Port WP der Speichereinrichtung zugeführte Daten D1 in die Speicherbank B1, und der Speichereinrichtung zugeführte Daten D2 in die Speicherbank B2 geschrieben, und
• – werden über den Read Port RP aus der Speicherbank B1 stammende Daten D3 und aus der Speicherbank B2 stammende Daten D4 ausgegeben.

In the example considered, the memory device S contains two memory banks B1 and B2 and has a write port WP and a read port RP on. The data to be written into the memory device are fed via the write port WP, and the data to be output from the memory device are output from the memory device via the read port RP. More specifically

• - Data D1 supplied to the memory device are written to the memory bank B1 via the write port WP, and data D2 supplied to the memory device are written to the memory bank B2, and
• - Data D3 originating from memory bank B1 and data D4 originating from memory bank B2 are output via the read port RP.

The Storage device S is about it also supplied an address A generated by the core C. The address A is both to the first memory bank B1 as well as to the second memory bank B2 created.

The Storage device S is a so-called interleaved memory. that is, the memory banks B1 and B2 are connected so that successive Addresses different memory banks be addressed. In terms of closer Details of such a storage device can be found in John L. Hennessy & David A. Patterson, Computer architecture: a quantitative approach, 1990, Morgan Kaufmann Publishers, ISBN 1-55880-069-8, page 429.

in the Considered example, the memory bank B1 is the even one Addresses are assigned, and the memory bank B2 is the odd one Addresses.

The Core C contains a command execution unit EU, and multiplexers MUX1 and MUX2.

The command execution unit EU executes a program that is in a in the 1 program memory, not shown, is stored. The commands representing the program are indicated by a in the 1 fetched instruction fetch unit, also not shown, provided in the core C from the program memory. The program executed by the command execution unit EU tells the command execution unit EU which of the data stored in the memory device S it has to process and how and to which position within the memory device S the data to be written is to be written. The core C fetches the data to be processed by the command execution unit EU from the storage device S; the data then supplied to the command execution unit EU and to be processed by it are in the 1 designated D34. The command execution unit EU processes this data in the manner specified by the program and thereby generates data D11 and / or D21.

Then writes the core C stores the data D11 and / or D21 in the storage device S.

The aforementioned multiplexer MUX1 is arranged between the read port RP of the memory device S and the command execution unit EU. The multiplexer MUX1 has two input ports, one output port, and one in the 1 Control port, not shown, with the data D3 and D4 output from the memory device S being applied to the input ports, the data D34 being output from the output port, and the control port determining whether the output data D 34 is the data D3 or the data D4 are.

The aforementioned multiplexer MUX2 is arranged between the command execution unit EU and the write port WP of the memory device S. The multiplexer MUX2 has two input connections, one output connection, and one in the 1 Control port, not shown, applied to the input ports, the data D11 output from the command execution unit EU and data D12 output from the logic, the data D1 are output from the output port, and the control port determines whether the output data D1 is the data D11 or the data is D12.

The Logic L are the data D34 and the output from the multiplexer MUX1 the data D4 are supplied as input data. The logic L processes at least parts of this data in a predetermined manner and as a result generates the data D12 and / or data already mentioned D22.

The aforementioned multiplexer MUX3 is arranged between the core C and the logic L and the write port WP of the memory device S. The multiplexer MUX3 has two input connections, one output connection, and one in the 1 Control port, not shown, are applied to the input ports, the data D21 issued from the command execution unit EU and data output from the logic D22, the data D2 are output from the output port, and the control port determines whether the output data D1 is the Data D21 or data D22.

in the considered example include all data, i.e. D1, D2, D3, D4, D11, D12, D21, D22, and D34 each have 16 bits. It should however, it is clear that the Number of bits that each include the specified data, too any much larger or can be smaller.

When the Core C is caused to do so by an appropriate command, it is in memory direction S to process stored data, it carries out a corresponding read access to the storage device S in order to read out the data to be processed from the storage device S. The execution of the read access comprises the generation of an address for addressing the memory device S. Of this address, the least significant bit is applied to the control connection of the multiplexer MUX1, and the remaining bits are used as address A for addressing the memory device S.

By read access to the memory device S will be simultaneous Data D3 from memory bank B1 and data D4 from memory bank B2 is output, the data D4 being stored under the address which follows the address at which the data D3 is stored are.

The from the memory device S in response to a read access amount of data output is greater than the amount of data that the instruction execution unit EU at one time can process; the command execution unit can in the example considered only process either data D3 or data D4.

Of the data output from the memory device S, only the data to be processed, ie either the data D3 or the data D4, are supplied to the command execution unit EU. The data supplied to the instruction execution unit EU are selected by the multiplexer MUX1 depending on the least significant bit of the address generated by the core. The one in the 1 In the example shown, the data D3 are supplied to the command execution unit EU.

simultaneously with the feeder that of the command execution unit EU imported Data is also output to the logic L from the storage device S. Data supplied, in the example considered, both the data D3 and D4.

The Instruction execution unit EU generates from the supplied Data the ones already mentioned Data D11 and / or the data already mentioned above D21; the logic L already generates the above from the data supplied to it mentioned Data D12 and / or the data already mentioned above D22.

The from the command execution unit EU and / or the data generated and output by logic L. are about the multiplexers MUX2 and MUX3 are written in the memory device S. The MUX2 and MUX3 multiplexers can independently of each other can be controlled as desired. The multiplexers are controlled through the Core C.

in the Examples considered are those from the storage device at the same time S output data D3 and D4 representing different information Elements of a data record comprising data D3 and D4. The same applies to the data D1 and D2 written in the storage device S. present represent the data D1 and D3 the real part of a complex number, and the data D2 and D4 the imaginary part this complex number.

The Core C processes the data D3, and representing the real part generates data D11, and the logic L processes those representing the imaginary part Data and thereby generates data D22. The MUX2 and MUX3 multiplexers are controlled so that the Data D11 are written into memory bank B1, and the data D22 into memory bank B2.

If the command execution unit EU the imaginary part representing Data D4 supplied would be she would generate the data D21 when processing this data, and the Logic L would that represent the real part Process data D3 and thereby generate data D12. The multiplexers MUX2 and MUX3 would then be controlled so that the Data D21 are written into memory bank B2, and the data D12 into memory bank B1.

It would be too possible, that the Logic L both the data D3 representing the real part and the the imaginary part representing Processed data D4 and generated data D12 and D22. The multiplexers MUX2 and MUX3 would then be controlled so that the Data D12 are written into memory bank B1, and the data D22 into memory bank B2.

It might illuminate and need no closer Explanation, that the Data D3 and D4 also any other related information represent can, for example the x and y coordinates of a point, or certain Elements of a matrix.

The data D3 and D4 representing a data record are read out of the memory device S by a single read access by the core C, and are processed in part by the command execution unit EU of the core C and in part by the logic L. The data generated and output during the processing of the data D3 and D4 by the command execution unit EU of the core C and by the logic L are written into the memory device S by a single write access by the core C to the memory device S. This means that a minimal number of read accesses and / or write accesses to the memory device S is sufficient. This means less access to the Storage device S takes place as would be the case if both the core C and the logic L would access the storage device S, and this in turn has the positive effect that the amount of data that can be read out from the storage device S per unit time and the amount of data that can be written into the memory device S per unit of time is greater than would be the case if both the core C and the logic L were to access the memory device. Due to the more efficient access to the memory device S, the core C and the logic L can work faster, and accordingly the performance of the system increases.

The above with reference to the 1 The arrangement described can be modified in various ways.

A first variation is in 2 shown.

The in the 2 arrangement shown largely corresponds to that in the 1 shown arrangement. Components identified by the same reference numerals are identical or corresponding components.

The in the 2 arrangement shown differs from that in 1 shown arrangement that it has no multiplexers MUX1 and MUX3.

The omission of the multiplexer MUX1 has the consequence that only the data D3 or only the data D4 can be supplied to the command execution unit; in the in the 2 In the example shown, only the data D3 are supplied to the command execution unit EU. This in turn means that the command execution unit EU can only generate data D11 and no data D21.

Because If no data D21 are generated, the multiplexer MUX3 can also be omitted and will always be the data D22 generated by the logic L. written in the memory bank B2 of the memory device S.

Another modification of the in the 1 arrangement shown is in 3 shown.

The in the 3 arrangement shown also largely corresponds to that in the 1 shown arrangement. Components identified by the same reference numerals are identical or corresponding components.

The in the 3 arrangement shown differs from that in 1 shown arrangement in that it has no multiplexer MUX2 and that only the data D4 are supplied to the logic L.

Because the data L3 cannot be supplied to the logic L, it cannot Generate data D12. this makes possible it to omit the multiplexer MUX2 and always that of the instruction execution unit generated data D11 in the memory bank B1 of the memory device S to write.

Another modification of the in the 1 arrangement shown is in 4 shown.

The in the 4 arrangement shown also largely corresponds to that in the 1 shown arrangement. Components identified by the same reference numerals are identical or corresponding components.

The in the 4 arrangement shown differs from that in 1 arrangement shown by the structure of the storage device S. More specifically, the storage device S is in the 4 shown arrangement is not formed by an interleaved memory, but by successive memory banks in the address space.

Another modification of the in the 1 arrangement shown is in 5 shown.

The in the 5 arrangement shown also largely corresponds to that in the 1 shown arrangement. Components identified by the same reference numerals are identical or corresponding components.

At the in the 5 As shown, the data record read from the memory device by a single read access to the memory device S comprises four data elements D3, D4, D7 and D8, and the data record written to the memory device by a single write access to the memory device S comprises four data elements D1, D2, D5 , and D6.

consequently

• - Includes the storage device S four memory banks B1 to B4
• - points the multiplexer MUX1 has four input connections, to which connections the Data D3, D4, D7 and D8 are created,
• - becomes the multiplexer MUX1 through the two least significant bits of the controlled the core generated address,
• - processed the command execution unit EU the data D3 and thereby generates data D11, or processes the command execution unit EU the data D4 and generates data D21, or processes the command execution unit EU the data D7 and thereby generates data D31, or processes the command execution unit EU the data D8 and thereby generates data D41,
• - points the logic L four input connections for the feed the data to be processed,
• - become the logic L is supplied with the data D34, D4, D7 and D8,
• - processed the logic L the data D34 and thereby generates data D12, or processes the logic L the data D4 and thereby generates data D22, or processes the logic L the data D7 and thereby generates data D32, or processes the logic L generates the data D8 and thereby generates data D42,
• - are two further multiplexers MUX4 and MUX 5 are provided, the multiplexer MUX4 the data D31 and D32 supplied gets, and either the data D31 or the data D32 to the storage device S, more specifically to the third memory bank B3, and the multiplexer MUX5 receives the data D41 and D42, and either the data D41 or the data D42 to the storage device S, more specifically to the fourth memory bank B4.

The data D1, D2, D5 and D6 or D3, D4, D7 forming a data record and D8 represent for example one defined by four 16-bit integers Vector.

The completeness for the sake of note it should be noted that a Record include any number of related data elements can. This number must also be neither a power of 2 nor an even number.

The above with reference to the 2 to 5 Variations described in the 1 The arrangement shown can be combined with one another as desired.

Furthermore further modifications are possible.

For example can be provided that the Logic L is part of the program-controlled unit.

The second data processing device also need not be logic, but can also a second core or a second CPU of the program-controlled Unity.

The second data processing device can also be a second command execution unit of the Be core C.

The The system described can also have several second data processing devices exhibit.

Furthermore there is also no imperative that the storage device, into which those generated by the two data processing devices Data is written which is the storage device in which the data to be processed by the data processing devices are saved.

The Storage device can also be outside the program-controlled Unit may be provided.

As Storage device can also be a reprogrammable non-volatile Memory such as flash memory can be used.

Further there is no imperative to those shown in the figures To provide multiplexers; these can for example by providing memory bank selection lines and Tristate data buses are replaced.

The The system described above is independent of the details of the practical implementation considerably more powerful than conventional systems , but only slightly more complicated.

A

address

Bx

memory bank

C

Core

dx

Data

EU

Instruction execution unit

L

logic

muxx

multiplexer

RP

Read port

S

memory device

WP

Write port

Claims (21)

System with a data processing device (C) for processing data (D3, D4; D3, D4, D7, D8), and a storage device (S) for storing data, the data processing device using the data to be processed by corresponding read accesses to the Reads the memory device from the memory device, and / or writes data generated in the data processing device (D11; D11, D12; D11, D21, D31, D41) by corresponding write accesses to the memory device in the memory device, characterized in that the data (D3, D4 ; D3, D4, D7, D8), which are read out from the storage device by a read access of the data processing device (C) to the storage device (S), both data to be processed by the data processing device and data to be processed by a second data processing device (L) include, and / or that by a write When the first data processing device (C) accessed the storage device (S), data (D1, D2; D1, D2, D5, D6) written in the first data processing device and data generated in the second data processing device. System according to claim 1, characterized in that the first Data processing device (C) the core of a program-controlled Unity is. System according to claim 1, characterized in that the second Data processing device (L) outside the program-controlled unit intended facility is. System according to claim 1, characterized in that the second Data processing device (L) within the program-controlled unit intended facility is. System according to claim 1, characterized in that the second Data processing device (L) is a logic that the data supplied to it undergoes predetermined operation. System according to claim 1, characterized in that of the Data (D3, D4; D3, D4, D7, D8), which are read by the first data processing device (C) onto the storage device (S) can be read out from the memory device by the first Data processing device (C) to process data of the first Data processing device are supplied, and by the second data processing device (L) data to be processed are fed to the second data processing device. System according to claim 6, characterized in that at least Parts of the data supplied to the first data processing device (C) also are fed to the second data processing device (L). System according to claim 6, characterized in that at least Parts of the data supplied to the second data processing device (L) can also be fed to the first data processing device (C). System according to claim 1, characterized in that the quantity the data generated by a read access by the first data processing device (C) to the storage device (S) from the storage device is read out, is larger than the amount of data that the first data processing device can process at once. System according to claim 6, characterized in that the to be fed to the first data processing device (C) Data and those to be fed to the second data processing device (L) Data are output simultaneously from the memory device (S). System according to claim 6, characterized in that the to be fed to the first data processing device (C) Data and those to be fed to the second data processing device (L) Data are supplied to the data processing devices simultaneously. System according to claim 1, characterized in that the Data (D3, D4; D3, D4, D7, D8), which are read by the first data processing device (C) onto the storage device (S) are read from the memory device, related data elements of a data set comprising several data elements, and that a part of the data elements by the first data processing device (C) is processed, and part of the data items by the second Data processing device (L) is processed. System according to claim 1, characterized in that the Data (D1, D2; D1, D2, D5, D6) by a write access of the first data processing device (C) onto the storage device (S) are written to the memory device, related data elements of a data set comprising several data elements, and that a part of the data elements by the first data processing device (C) is generated, and part of the data elements by the second Data processing device (L) is generated. System according to claim 12 or 13, characterized in that that one the data elements represent the real part of a complex number, that another Part the imaginary part represents this complex number, and that one of the data elements by the first data processing device (C) is processed, and that the other data element by the second data processing device (L) is processed. System according to claim 12 or 13, characterized in that that the several data elements represent the coordinates of a point. System according to claim 12 or 13, characterized in that that the represent a vector from several data elements. System according to claim 12 or 13, characterized in that that the several data elements are elements of a matrix. System according to claim 12 or 13, characterized characterized in that the memory device has a plurality of memory banks and that the different data elements of a data record are stored in different memory banks. System according to claim 18, characterized in that by read access by the first data processing device (C) the memory device (S) reads data from several or all memory banks become. System according to claim 18, characterized in that by write access by the first data processing device (C) data is written to several or all memory banks on the memory device (S) become. System according to claim 18, characterized in that the Storage device (S) is formed by an interleaved memory.