DE10255847B3 - Production of a trench capacitor for a semiconductor memory cell comprises using an auxiliary agent consisting of an insulating side wall spacer and a further conducting filler during filling of an upper trench region and mask opening - Google Patents

Abstract

Production of a trench capacitor comprises using an auxiliary agent (22) consisting of an insulating side wall spacer and a further conducting filler during filling of an upper trench region and mask opening. A connecting region (KS) is exposed by partially removing the side wall spacer on the side wall.

Description

The present invention relates to a production method for a trench capacitor with an insulation collar which is electrically connected on one side to a substrate via a buried contact, in particular for a semiconductor memory cell according to the preamble of claim 1 DE 198 43 641 A1 known.

The EP 1 022 782 A2 discloses a manufacturing method for a trench capacitor with an insulation collar which is electrically connected on one side to a substrate via a buried contact, wherein an insulation layer is deposited as in the case of a contact connected on all sides and then a partial region of the insulation layer and the contact connected on all sides is removed.

The US 6,335,247 B1 discloses a manufacturing method for a trench capacitor with an insulation collar that is electrically connected on one side to a semiconductor substrate via a buried contact, wherein the upper trench region within the insulation collar is filled with a conductive material and then a portion of the conductive material and the insulation collar is removed to create the buried contact connected on one side.

Although in principle on any Integrated circuits applicable, the present invention as well as the underlying problem with regard to integrated Memory circuits in silicon technology explained.

1 shows a schematic sectional view of a semiconductor memory cell with a trench capacitor and an associated planar selection transistor (so-called. Inferner prior art). In 1 denotes reference numerals 1 a silicon semiconductor substrate. Provided in the semiconductor substrate 1 are trench capacitors GK1, GK2, which have trenches G1, G2, their electrically conductive fillings 20a . 20b form first capacitor electrodes. The conductive fillings 20a . 20b are in the lower and middle trench area by a dielectric 30a . 30b compared to the semiconductor substrate 1 isolated, which in turn forms the second capacitor electrodes (possibly in the form of a buried plate, not shown).

In the middle and upper area of the trenches G1, G2 are all-round insulation collars 10a . 10b provided above which buried contacts 15a . 15b are attached to the conductive fillings 20a . 20b and the adjacent semiconductor substrate 1 to be in electrical contact. The buried contacts 15a . 15b are only on one side of the semiconductor substrate 1 connected (cf. 2a . b ). isolation regions 16a . 16b isolate the other side of the substrate from the buried contacts 15a . 15b or isolate the buried contacts 15a . 15b to the top of the trenches G1, G2.

This enables simple structuring of the trench capacitors GK1, GK2 and the associated selection transistors with high packing density, which will now be explained. In this context, reference is mainly made to the selection transistor which belongs to the trench capacitor GK2, since only the drain region D1 and the source region S3 are drawn in from adjacent selection transistors. The selection transistor belonging to the trench capacitor GK2 has a source region S2, a channel region K2 and a drain region D2. The source region S2 is connected via a bit line contact BLK to a bit line (not shown) arranged above an insulation layer I. The drain region D2 is on one side of the buried contact 15b connected. A word line WL2 runs above the channel region K2 and has a gate stack GS2 and a gate insulator GI2 surrounding it. The word line WL2 is an active word line for the selection transistor of the trench capacitor GK2.

Parallel to the word line WL2 run word lines WLl consisting of gate stacks GS1 and Gate insulator GI1 and word line WL3 consisting of a gate stack GS3 and gate isolator GI3, which for the selection transistor of the trench capacitor GK2 passive word lines are. These word lines WL1, WL3 are used to control selection transistors, those in the third dimension compared to the sectional view shown are moved.

Obviously 1 is the fact that the one-sided connection of the buried contact brings about a direct juxtaposition of the trenches and the adjacent source regions or drain regions relating to selection transistors. The length of a memory cell can thus be 4F and the width 2F, where F is the minimum technologically realizable length unit (cf. 2a . b ). A particular advantage of the possible arrangements is the optimal expandability in the lower trench area.

2A shows a plan view of a memory cell array with memory cells according to 1 in a first arrangement option.

DT in 2A denotes trenches, which are arranged row by row with a distance of 3 F to each other and column by row with a distance of 2 F. Adjacent rows are shifted by 2 F to each other. UC in 2A denotes the area of a unit cell, which is 4 F × 2 F = 8 F ² . STI denotes isolation trenches which are arranged at a distance of 1 F from one another in the row direction and isolate adjacent active areas from one another. Bit lines BL also run at a distance of 1 F from one another in the row direction, whereas the word lines in the column direction run at a distance of 1 F to each other. In this arrangement example, all the trenches DT on the left side have a contact area KS of the buried contact with the substrate and an isolation area IS on the right side (areas 15a, b respectively. 16a, b in 1 ).

2 B shows a plan view of a memory cell array with memory cells according to 1 in a second arrangement option.

In this second arrangement possibility, the rows of trenches have alternating connection areas or isolation areas of the buried contacts. So are in the bottom row of 2 B the buried contacts each have a contact area KS1 on the left-hand side and an insulation area IS1 on the right-hand side. On the other hand, in the row above, all the trenches DT are provided with each isolation area IS2 on the left side and with a contact area KS2 on the right side. This arrangement is alternating in the column direction.

The object of the present invention is a simple and safe manufacturing process for one to specify such a trench capacitor connected on one side.

According to the invention, this object is achieved by solved manufacturing method specified in claim 1.

The advantages of the method according to the invention lie in particular in the fact that there is a precise definition of the connection area or the complementary Isolation area at the respective buried contact of the trench capacitor allows. Either an additive creation of the buried contact (piece by piece Structure) as well as a subtractive creation (piecewise dismantling) of the buried contact are by the inventive method allows.

There are advantageous ones in the subclaims Developments and improvements to that specified in claim 1 Manufacturing process.

According to another preferred The insulating sidewall spacer consists of silicon nitride, the conductive filling as well as the further conductive filling made of polysilicon and the insulation collar made of silicon oxide. At the The silicon nitride is exposed to the polysilicon and the Etched silicon oxide.

According to another preferred Further training will be the auxiliary material and the material that the Refill step is used after filling lowered to below the top of the substrate. Then will the trench filled with another insulating fill.

An embodiment of the invention is shown in the drawings and in the description below explained in more detail.

Show it:

1 is a schematic sectional view of a semiconductor memory cell with a trench capacitor and a planar selection transistor connected thereto;

2A . B a respective plan view of a memory cell array with memory cells according to 1 in a first and second arrangement possibility; and

3A-F schematic representations of successive process stages of a manufacturing process as an embodiment of the present invention.

In the figures denote the same Reference numerals same or functionally identical components.

The ones described below embodiments will for reasons the clarity on a description of the manufacture of the planar selection transistors waived and only the formation of the unilaterally connected buried contact of the trench capacitor discussed in detail. The steps of making the planar selection transistors are the same, unless expressly stated otherwise as in the prior art.

3A-F are schematic representations of successive process stages of a manufacturing process as a first embodiment of the present invention.

In 3A denotes reference numerals 5 a trench in the silicon semiconductor substrate 1 is provided. On the top OS of the semiconductor substrate 1 a hard mask consisting of a pad oxide layer is provided 2 and a pad nitride layer 3 , In the lower and middle part of the trench 5 is a dielectric 30 provided an electrically conductive filling 20 compared to the surrounding semiconductor substrate 1 isolated. In the upper and middle part of the trench 5 is an all-round insulation collar 10 provided at about the same height as the conductive fill 20 in the trench 5 is sunk. An exemplary material for the insulation collar 10 is silicon oxide and 20 polysilicon for the electrically conductive filling. Of course, other material combinations are also conceivable.

Regarding 3B then finds an oxidation of the substrate exposed in the upper trench region to form a pad oxide region 2a instead of and subsequently the formation of a nitride spacer 3b in the upper trench area and in the area of the hard mask consisting of the layers 2 . 3 , The spacer 3b has approximately the same thickness as the insulation collar in this example 10 ,

Regarding 3C polysilicon is then deposited over the resulting structure and planarized so that the upper trench region and the region of the layers 2 . 3 in the ditch 5 with another conductive filling 22 which is in electrical contact with the filling 20 stands.

Next (not shown here) the active areas of the selection transistors belonging to the memory cells and the isolation trenches STI (cf. 2a . b ) can be provided.

Regarding 3D then becomes a mask 222 formed over the resulting structure so that only one side of the nitride spacer 3b is exposed through appropriate openings. The nitride spacer is applied to this exposed side by a selective etching process using the mask 222 to the top of the insulation collar 10 away.

Then, as in 3E shown a filling ( 260 ) deposited from polysilicon over the resulting structure and planarized to fill up the exposed spacer area after the pad oxide 2A has been removed there. In principle, the buried contact is due to the filling 260 created.

Finally, the leading areas are etched back 22 . 260 , removing the remaining spacer 3b and a deposition and etching back of an oxide insulation layer 250 around the one-sided connection area KS of the capacitor filling 20 over the areas 22 . 260 to the semiconductor substrate 1 to isolate upwards and towards the insulation side IS, as in 3F shown.

Although the present invention described above with reference to a preferred embodiment it is not limited to this, but in a variety of ways and modifiable.

In particular, the selection of the Layer materials are only exemplary and can be varied in many ways become.

Claims (3)

Manufacturing process for a trench capacitor with an insulation collar ( 10 ; 10a . 10b ) in a substrate ( 1 ) that has a buried contact ( 15a . 15b ) on one side with the substrate ( 1 ) is electrically connected, in particular for a semiconductor memory cell with a in the substrate ( 1 ) provided and via the buried contact ( 15a . 15b ) connected planar selection transistor, with the steps: providing a trench ( 5 ) in the substrate ( 1 ) using a hard mask ( 2 . 3 ) with a corresponding mask opening; Providing a capacitor dielectric ( 30 ) in the lower and middle trench area, the insulation collar ( 10 ) in the middle and upper trench area and an electrically conductive filling ( 20 ) in the lower and middle trench area, with the top of the electrically conductive filling ( 20 ) in the upper trench area opposite the top of the substrate ( 1 ) is sunk; completely fill the upper trench area and the mask opening using at least one auxiliary material ( 3b . 22 ) so that the filled trench ( 5 ) an even surface with the hard mask ( 2 . 3 ) forms; Providing a mask ( 222 ) on the hard mask ( 2 . 3 ) with the filled trench ( 5 ) to define a one-sided connection area (KS; KS1, KS2) or another isolation area (IS; IS1, IS2) of the buried contact ( 15a . 15b ); Exposing the one-sided connection area (KS; KS1, KS2) of the buried contact ( 15a . 15b ) by partially removing the auxiliary material ( 3b . 22 ) using the mask ( 222 ); and filling the one-sided connection area (KS; KSl, KS2) with a conductive material ( 260 ); characterized in that the auxiliary material ( 3b . 22 ) an insulating sidewall spacer ( 3b ) and another conductive filling ( 22 ) inside, which is in electrical contact with the conductive filling ( 20 ) stands; and exposing the one-sided connection area (KS; KS1, KS2) by partially removing the insulating side wall spacer ( 3b ) is carried out on the side wall. A method according to claim 1, characterized in that the insulating side wall spacer ( 3b ) consists of silicon nitride, the conductive filling ( 20 ) and the other conductive filling ( 22 ) are made of polysilicon and the insulation collar ( 10 ) consists of silicon oxide; and selectively etch the silicon nitride over the polysilicon and silicon oxide when exposed. Method according to one of the preceding claims, characterized in that the auxiliary material ( 3b . 22 ) and the material used in the padding step after padding to below the top of the substrate ( 1 ) are lowered and then the trench ( 5 ) with another insulating filling ( 250 ) is filled.