DE10254076A1 - DRAM circuit has refresh sequence adjusting device with electrically programmable trim circuit in which frequency-determining network fuse elements are selectively changed to set state by overvoltage - Google Patents

Abstract

The DRAM circuit has memory cells and an access controller, a refresh device and a trim circuit for adjusting the refresh oscillator frequency to a desired value with an electrically programmable trim circuit in which fuse elements of a frequency-determining network are selectively changed from an unset state to a set state by applying an overvoltage and a fuse selection device for connecting an overvoltage source in accordance with selection. The Dynamic Random Access Memory or DRAM circuit has a number of memory cells (21) and an access controller (22), a refresh device (24) and a trim device (30,40,60,70) for adjusting the refresh oscillator (25) frequency to a desired value with an electrically programmable trim circuit (30) in which fuse elements of a frequency-determining network are selectively changed from an unset state to a set state by applying an overvoltage and a fuse selection device (70) for connecting an overvoltage source in accordance with selection data. AN Independent claim is also included for the following: (a) a method of adjusting the oscillation frequency of the refresh oscillator for a DRAM circuit.

Description

DRAM memory circuit with one Device for adjusting the refresh frequency and method for execution The adjustment relates to a DRAM memory circuit, which contains funds around the repetition frequency of those that run automatically during operation Adjust refresh cycles according to the generic term of claim 1. The invention relates to circuit means and also a procedure for performing the adjustment. preferred, however not exclusive Field of application are synchronized DRAMs (S-DRAMs), in particular embodiments with multiplied data rate (DDR-DRAMus, DDR-II-DRAMs, etc.).

The common one Acronym DRAM means dynamic digital memory with random Access (Dynamic Random Access Memory), the memory cells of which Information is only available for a limited time, even with a permanent power supply reliable can keep so that the stored data must be refreshed regularly. In particular with the most commonly used capacitive DRAMs lose the capacitors used as memory elements their information descriptive charge relatively quickly. The so-called Retention time Tr, which indicates how long a newly written one Information on a cell that is still clearly legible can be read from cell be very different from cell within the same DRAM; often the range extends from a few seconds down to a few tens Milliseconds. The empirically ascertainable lower limit of this Span, i.e. the minimum retention time Tr (min) heard to the important specifications of a DRAM.

The "Refresh" mode required for refreshing usually exists in that, nested with the useful operation of the DRAM, all cells at intervals, the shorter are automatically controlled as the minimum retention time Tr (min) to feel the memory state at each cell that Recognize the relevant storage date and re-in the relevant Write back cell. Every refresh process is similar a normal reading process, which also includes an automatic write-back of the reading date, only that the selection and Forwarding of the read data to the data output of the DRAM is omitted.

DRAM memory circuits included thus in addition to the memory cell fields and the various facilities, to provide various supply voltages and currents and to Control selective cell access for writing and reading Storage data are required in utility operation, a facility for automatic execution the refresh cycles. This device contains a so-called refresh oscillator, from its working frequency the repetition frequency for the refresh cycles is derived, usually by frequency division around a fixed divisor. The oscillator frequency should be within a narrow range being held. A specified lower limit must be observed to guarantee that the interval between refresh cycles does not widen than the minimum retention time. On the other hand, the oscillator frequency not much higher than this lower limit to avoid the refresh cycles frequently carried out than is actually necessary. Every refresh cycle is blocked namely temporarily the commercial operation, at least in part.

As refresh oscillators for DRAMs are common digital oscillators used, preferably in the form of a feedback odd inverter chain, which has the advantage of a simple and space-saving integrability on the chip of the memory circuit Has. The vibration frequency is determined by the number of consecutive times switched inverter and from the gate cycle time of each Inverter, the latter greatly dependent on the level of the supply voltage or the supply current depends.

This dependency, by the way even with other types of oscillators, it cannot always be ruled out, means no problem with the conventional "regulated" DRAM chips. Such chips are for operation with a narrowly specified external chip supply voltage VDD designs and contains a higher-level voltage regulator, that from this VDD voltage using a bandgap reference ("Band gap") derives a highly stable internal reference voltage Vint, which in turn serves as a reference for the stabilization of the secondary and supply voltages or currents of the DRAM is used. This also applies to the supply of the refresh oscillator, whose Frequency is therefore sufficient is firm.

The use of ever newer technologies leads to Lowering the supply voltage. While a DRAM that works with a Data rate is operated equal to the simple clock frequency (SDR-DRAM = Single Data Rate DRAM), an external voltage of 3.3 volts required, required a Type operated with doubled data rate (DDR-DRAM = Double Data Rate DRAM) only 2.5 volts and one operated at a quadruple data rate Type (DDR-II-DAM) even only 1.8 volts. In the further developments (DDR-III, etc.) the external supply voltage becomes even lower to be dimensioned.

Even with the DDR-II DRAMs, it is hardly possible due to the low external supply voltage to derive an internal reference voltage Vint using a bandgap reference, which could serve as a common reference for the regulation of all internal supply voltages on the chip. As a result, the chip is left "unregulated", that is, the internal voltages are allowed to match the external supply voltage to change. Basically, the actual useful operation of a DRAM mostly works satisfactorily over a relatively wide range of internal supply voltages, so that the majority of the circuit components do not have to be redesigned in order to adapt the DRAM to a reduced VDD voltage.

amendments in the supply voltage of the refresh oscillator can to unacceptable changes the refresh frequency. To counter this, it is common become a trim circuit for the refresh oscillator on unregulated chips to integrate, which allows the oscillator frequency by laser bombardment of melting bridges (so-called "fuse" elements or "fuses" for short). This trim is in the "Front End" carried out, i.e. if the chip is still on the wafer. At least in the wafer tester one of the chips is selected as a representative, and is attached to that chip the nominal value of the external supply voltage with which all Chips later to be operated. Then the frequency of the refresh oscillator measured, and from a deviation of the measured frequency from the The test device determines the target frequency e.g. based on a lookup table information indicating which fuses have to be shot in order to adjust the oscillator frequency to compensate for the deviation. The fuses in question are then corresponding to this information shot on all chips of the wafer by laser beam.

As we know, the individual After the wafer test has been completed, the chips are cut off and encapsulated in housings. Then usually follow the individual exams, before the chips with the specifications, which among other things too the tolerance range for call the external supply voltage VDD, delivered to customers become. In terms of the external supply voltage of DRAM chips, however, the customer requirements more and more differentiated. For The installation of the chips in mains-operated devices usually results in higher supply voltages required or tolerated as for Installation in mobile devices such as notebooks or cellular phones that run on batteries because there it is particularly important to reduce energy consumption preferably lower low supply voltage. Adapting the specification to different customer requests but requires retrofitting the front-end trimming on the wafer described above and is worth it economically only for relative size numbers (a wafer contains hundreds of chips). Furthermore follows inevitably through the adjustment also a delay in delivery, because from the trim it usually takes weeks until the individual chips in encapsulated form for the final exam and the subsequent delivery available. For these reasons the chip manufacturer is only flexible to differentiated customer requirements with regard to the external supply voltage inexpensive and to satisfy quickly.

The object of the invention is in flexibility regarding the provision of DRAM memory circuits the adaptation to a desired one increase external supply voltage. This object is achieved according to the invention the embodiment of a DRAM memory circuit described in claim 1 and solved by the adjustment method specified in claim 15.

Accordingly, the invention is implemented on a DRAM integrated circuit that includes: one Variety of memory cells and an access control device for selective control of the memory cells to get data into the controlled Write cells and saved data to the selected Reading cells; a refresh device that has a refresh oscillator has and in response to periodically recurring, from the Oscillation frequency of the refresh oscillator derived refresh commands causes the access control device to the content of each memory cell at regular intervals Read the saved date and rewrite it refresh, the oscillation frequency of the refresh oscillator kept at a setpoint dictated by the storage technology have to be; a trimming device for adjusting the oscillation frequency the refresh oscillator to the dictated setpoint by selective Actuation of fuse elements in a vibration frequency determining Network. The invention is that the trimmer has an electrical programmable trim circuit in which the Fuse elements of the frequency-determining network selectively Applying an overvoltage are permanently transferable from an unset state of predetermined first impedance to a set one State of predetermined second impedance, and that a fuse selection device is provided for connecting a source supplying the overvoltage with a selection of the fuse elements determined by a setting information.

The design of a DRAM memory circuit according to the invention expands the possibilities for the time of adaptation to the desired external supply voltage. The laser-programmable fuse elements previously used exclusively, briefly referred to as "laser fuses", can only be fired if the surface of the chip is exposed and the chip is positioned with micrometer precision in an associated clamping device. This can practically only be realized in the front end, i.e. on the wafer, for which high-precision clamping devices already exist. Electrically settable fuse elements, briefly referred to as "electrical fuses", on the other hand, can be programmed via electrical lines, which are not only accessible in the front end but also later can be, even on the finished encapsulated chips. Electrical fuses are known per se from the art of programmable read-only memories (PROMs), their use for trimming in DRAM memory circuits has not previously been suggested.

With a memory circuit equipped according to the invention the manufacturer is flexible not only in his decision, whether and what measure he the frequency of the refresh oscillator should adjust, but also when deciding when to do this should, i.e. at what point on the production line. The latest possible To take a point, i.e. when the encapsulated chip is present the advantage that customer requests quickly to be satisfied. Thus opened an inventive training a DRAM memory circuit the possibility of a new advantageous adjustment method, which is characterized in that the electrical fuses can only be set when the one containing the DRAM memory circuit Chip is encapsulated.

A chip with the trim circuit according to the invention is electrically adjustable, but is not yet adjusted, can marketable Be the subject. The manufacturer of such an adjustable chip could be one Namely customers allow adjustment to the encapsulated chip itself to make and thus flexible in its uses for the to make acquired chip. On the other hand, the manufacturer can reserved, the adjustment before delivery of the chip to one Customers. Such a customized one Chip therefore has the particular advantage of being economically producible for smaller quantities.

In an advantageous embodiment of the Invention contains the memory circuit additionally another trimming circuit in which the frequency of the refresh oscillator can also be adjusted by setting fuse elements. This further trimming circuit does not need to be adjustable on the encapsulated chip but can be like conventional laser fuses included to make an adjustment at the front end as before. This opens up the possibility, at the front end an adjustment of the oscillator frequency to a "standard" supply voltage make that for relatively large numbers may be required. From the correspondingly trimmed "standard" chips, that can be manufactured and encapsulated in stock can be then possibly one adapt narrowly limited number of individual pieces to special customer requests, by making an appropriate adjustment to the other trim circuit their electrical fuses is made.

Details of these and other special configurations a DRAM memory circuit according to the invention are marked in subclaims. To the closer explanation The invention is an embodiment with reference to drawings described.

1 shows in a block diagram the structure of a DRAM memory circuit with an inventive arrangement for adjusting the oscillation frequency of the refresh oscillator;

2 shows more details of the arrangement for adjusting the oscillation frequency of the refresh oscillator.

In the 1 DRAM memory circuit fragmented within a dashed frame 10 , which is, for example, an S-DRAM, is integrated on a single semiconductor chip and has external connections 11 to 15 for data bits, address bits and external control signals and an external connection 16 for applying an external supply voltage VDD. The matrix in individual cell fields 21 Arranged memory cells (not shown individually) are selective via an access control device 22 accessible to data through the data port 11 to write in or read out, the respective cell selection depending on address bits that are at the address connection 12 be created. The access control device 22 contains decoders for decoding the address bits and a switchable network of data paths to the connections between the respectively selected memory cells and the data connection 11 manufacture. This is done in a well-known manner time-controlled under the influence of control signals, which in the case of an S-DRAM from a command decoder 23 be supplied, the an external clock signal CLK on an external clock connection 13 and command bits CMB on an external command connection 14 receives.

A refresh device is provided for periodically refreshing the contents of the memory cells 24 provided a refresh oscillator 25 and a refresh control device 28 contains to the access control device 22 to cause the content of each memory cell to be refreshed at regular intervals, as is known per se. These time intervals should be kept constant within narrow limits; under no circumstances may they exceed the minimum retention time of the storage cells, which is determined by the storage technology used. The time standard for the said time intervals is derived from the oscillation frequency of the refresh oscillator 25 which must also be kept within a narrow range at a setpoint.

The supply voltage V25 of the oscillator 25 as well as various other internal supply voltages of the memory circuit 10 from a supply unit 17 derived, which in turn is fed by the external supply voltage VDD. If the internal supply voltages are unregulated for the reasons described above, which is assumed here, they change with the external voltage VDD, which therefore also influences the frequency of the oscillator 25 Has. So about the memory circuit 10 To be able to adapt to any specially selected external supply voltage, a trimming device must be provided in order to adjust the oscillator frequency by manipulating the frequency-determining network of the oscillator. Of course, it depends on the type of oscillator which electrical operating parameters or circuit parameters are suitable for a suitable manipulation.

Let us consider here the example case that the refresh oscillator 25 a feedback chain 26 from an odd number of inverters, as is known per se and common in digital integrated circuits and as it is in the detailed circuit diagram of the oscillator 25 to 2 is shown. The individual inverters in the chain 26 are fed by the internal oscillator supply voltage V25; the corresponding supply connections to the individual inverters are not shown for reasons of clarity. The oscillation frequency is determined by the total running time along the chain 26 , it therefore depends on the sum of the gate delays in the inverters, which in turn depend heavily on the supply voltage V25. The total runtime of the chain 26 can be adjusted, for example, by adding additional delaying elements to the chain 26 selectively effective or ineffective. The output signal FR of the oscillator 25 will be at any node in the inverter chain 26 derived.

In the 2 these delaying elements are shown as four parallel capacitors CO to C3 within a capacitance network 27 that is between any node in the inverter chain 26 and ground potential. The four capacitors C [0: 3] can be selectively switched into the circuit by making transistor switches S [0: 3] conductive in order to determine the effective total capacitance and thus the extent of the delay effect of the capacitance network 27 adjust and thereby adjust the oscillator frequency. The transistor switches S [0: 3] are shown as MOS field-effect transistors with an n-conducting channel (N-FETs), ie they are only conducting if there is positive potential ("high" or "1" potential) at the gate electrode ) to ground ("low" or "0" potential). The capacitance values of the four capacitors C [0: 3] are preferably graded according to the dual number system, so that the bundle of the four gate leads of the transistor switches S [0: 3] can be controlled in parallel by a 4-bit actuating signal to switch between 2 ⁴ = 16 different total capacities and thus 16 different frequency settings to choose.

The four gate leads of the transistor switch S [0: 3], ie the control inputs of the oscillator 25 , are via a switching device, as a multiplexer 80 shown, optionally with four outputs of a first trim circuit 30 or with four outputs of a second trim circuit 40 connectable. Any trim circuit 30 . 40 contains four fuse circuits 30 [ 0: 3] or 40 [0: 3]. The control signal for the multiplexer 80 is by a separate fuse circuit 90 delivered. The fuse circuits 30 [ 0: 3] and 90 each contain an electrically settable fuse element EF and are of the same design, so that it is sufficient to use only the fuse circuit 30 [ 0] to be described: The electrically settable fuse element EF is high-resistance in the non-set state and is set in a permanently low-resistance state by applying an overvoltage once, which must exceed a certain value in order to "burn out" the element. One end of the fuse element EF is connected to the 0 potential (ground) and its other end is connected via the channel of a P-FET (MOS field effect transistor with p-channel) P4 to a potential source for the said overvoltage (internal voltage) VBR connected. To set the fuse element EF, a pulse SET with 0 potential is applied to the gate of P4, so that this transistor conducts temporarily and the fuse element EF goes into a low-resistance permanent state.

The far end of the fuse element is also connected to the 1 potential (VDD +) via the channel of an N-FET (MOS field effect transistor with n-channel) N1 and then the channel of a P-FET P1. The node K between N1 and P1 is connected to the output via two inverters connected in series, each containing an N-FET N2 or N3 and a P-FET P2 or P3, which leads to the multiplexer 80 leads. The output is also fed back to node K, so that the two inverters act as a latch.

To read out the fuse circuit first a precharge signal PRC (preload) with 0 potential to the gate of P1 placed, whereby P1 relatively low-resistance and the node precharged to 1 potential becomes. The precharge signal PRC is brought back to 1 potential, and then an evaluation pulse EVL (evaluate) with 1 potential connected to the gate of N1, making this transistor low-resistance and will and as N-FET represents a much lower impedance than the P-FET P1. If the fuse element EF has not been set and therefore high impedance, then the node K and thus the output remains on the preloaded 1 potential, which is locked by the latch formed remains, so the control potentials from the gates of the transistors can be taken away. Is the fuse element EF has been set and thus has low resistance, then the node changes K and thus also the output to the 0 potential, that too is locked by the latch formed and is thus retained, even after the control potentials are removed from the gates of the transistors have been.

All fuse circuits 30 [ 0: 3] of the trim circuit 30 are formed in the manner described above, as is the fuse circuit 90 for setting the multiplexer 80 , The fuse scarf obligations 40 [ 0: 3] of the other trim circuit 40 The only difference from this is that the P-FET P4 is missing and that its fuse elements LF cannot be set electrically but by laser bombardment. Such laser fuses are conductive bridges that can be destroyed by lasers; they are therefore low-resistance in the non-set state and high-resistance in the set state. Each of the laser programmable fuse circuits 40 [ 0: 3] returns a "1" at its output when the relevant fuse element LF is set, otherwise a "0" is returned.

The readout of all fuse circuits 30 [ 0: 3] 40 [0: 3] and 90 takes place in the manner described above by applying the precharge signal PRC and the evaluation signal EVL. These signals are preferably every time the memory circuit is initialized 10 automatically delivered to all fuse circuits shortly after the supply voltage VDD is applied. The signaling device used for this purpose and the associated line connections are shown in the 1 and 2 not shown.

The laser programmable trim circuit 40 is integrated in a known manner on the chip to the memory circuit 10 to be able to adapt to a standard value of the external supply voltage VDD in the front end together with the other memory circuits which are formed on the same wafer. In the front end, all fuse elements are in both trim circuits 30 and 40 as well as in the multiplexer setting circuit 90 in the unset original condition. After the supply voltage VDD has been applied, the trim circuit delivers 40 at all four outputs a "0", the trim circuit 30 returns a "1" at four outputs. Also the multiplexer setting circuit 90 returns a "1". This will make the multiplexer 80 kept in a switching state in which the four of the outputs of the trim circuit 40 with the four control inputs of the refresh oscillator 25 combines. So only the trim circuit 40 Influence on the oscillator 27 take the trim circuit 30 remains without influence. All control inputs of the oscillator are in this state 25 to 0 potential, so all transistor switches S [0: 3] are in the oscillator 25 blocked, and all capacitors C [0: 3] in the frequency-determining capacitance network 27 of the oscillator 25 are ineffective.

In the front end, according to the prior art, as described above, the standard trimming can now be carried out by first selecting one of the memory circuits on the wafer as a proxy and applying the standard supply voltage. The actual frequency of the refresh oscillator 25 is measured, and on the basis of a look-up table, positioning information is provided which indicates which fuse elements LF in the trimming circuit 40 must be set in order to activate exactly that combination of the capacitors C [0: 3] that the oscillator 25 to the dictated target frequency. This setting information is then used to set the relevant fuse elements LF in all memory circuits of the wafer by laser bombardment.

The trim circuit 30 and the multiplexer setting circuit 90 , which contain electrically programmable fuse elements EF, enable the oscillator frequency to be trimmed after the wafer has been cut on the encapsulated memory circuit chips, in particular in order to adapt individual chips to specially selected supply voltages which differ from the standard value. To carry out this special trimming, the selected supply voltage is applied and the SET signal with 0 potential is sent to the multiplexer setting circuit 90 placed in order to set the fuse element EF there. This is the output signal of the circuit 90 to "0" so the multiplexer 80 the control inputs of the oscillator 25 from the trim circuit 40 decouples and instead connects them to the outputs of the trim circuit 40 combines. Since all fuse elements EF of the trim circuit 40 are still in the unset original state (i.e. high impedance), are all control inputs of the oscillator 25 to 1 potential, so all transistor switches S [0: 3] are in the oscillator 25 conductive, and all capacitors C [0: 3] in the frequency-determining capacitance network 27 of the oscillator 25 are effective.

The actual frequency of the refresh oscillator becomes similar to the described front-end trimming 25 is measured, and on the basis of a look-up table, actuating information is given which specifies which fuse elements EF in the trimming circuit 30 must be set in order to leave only the combination of the capacitors C [0: 3] effective that the oscillator 25 to the dictated target frequency. This control information is then used to the relevant fuse elements EF in the trim circuit 30 by applying the burning voltage VBR.

It is preferably ensured that the trimming operation on the encapsulated chip by means of the electrically programmable trimming circuit 30 can be carried out without the need for additional external connections on the chip. For this purpose, according to the 1 Further additional devices integrated on the chip, namely a source 50 for the overvoltage (internal voltage) VBR for setting the fuse elements EF, a setpoint generator 60 for the dictated target frequency of the refresh oscillator and a fuse selection device 70 , The surge source 50 can be realized, for example, by means of a charge pump which is fed by the external supply voltage VDD and supplies a burning voltage which is substantially higher than VDD and is sufficient to set (burn out) the electrical fuses EF.

The fuse selection device 70 is indicated closed to receive the oscillator output signal FR and the frequency setpoint from the setpoint generator 60 and contains means for measuring the actual frequency of the oscillator signal FR and for comparing the measured actual frequency with the target value. It has four output lines leading to the gates of the P-FETs P4 in the four fuse circuits 30 [0: 3] the trim circuit 30 lead (see 2 ). The fuse selection device 70 also contains a look-up table which, depending on the difference between the actual value and the target value, provides actuating information which indicates those fuse elements whose setting would bring the oscillation frequency of the refresh oscillator from the measured actual value to the dictated target value. The fuse selection device generates this information 70 the set pulses SET with 0 potential on exactly those output lines that lead to the relevant fuse circuits in the trimming device 30 to lead. As a result, the fuse elements EF specified by the positioning information with the overvoltage source 50 connected and therefore set in the low impedance state, which is the oscillator 25 to the dictated target frequency.

For the initialization and sequence control of this trimming operation, control means are desirable which can be activated by external commands via the usual connections of the chip. In a preferred embodiment of the invention, the so-called test block is used for this 29 , which is present in every integrated DRAM memory circuit for test purposes anyway, is designed accordingly. The test block 29 is usually via a test mode pin 15 switchable on the chip by a test mode signal TMD to the memory circuit 10 to work in different programmed test modes, for example by externally created command bits CMB via the command decoder 23 can be selected.

In the exemplary embodiment of the invention described here, the test block contains 29 in addition a trim program installation 29a which, when activated, initially the surge source 50 switches on, then the SET command with the 0 potential to the fuse circuit 90 for switching the multiplexer 80 and then the fuse selection device 70 for setting the trim circuit 30 turns. Activation of the trim program installation 29a in the test block 29 is done via the command decoder 23 in response to a selected bit combination of the command bits CMB.

The based on the 1 and 2 described memory circuit 10 is only one embodiment to which the invention is of course not limited. Numerous modifications and alternatives are possible within the basic idea of the invention, only a few of which are mentioned below: The frequency-determining capacitors on the inverter chain of the refresh oscillator can also be connected at several different locations between the inverters, and their number and the number of fuses -Elements in each trim circuit can also be larger or smaller than 4 in order to achieve a greater or less fine adjustment. Instead of the selectively switchable capacitors or additionally selectively switchable bridges can also be provided in parallel to individual inverters in order to change the number of effective inverters, which are also frequency-determining because of their gate delay, by the selective setting of the fuse elements (in pairs, for preservation the odd number) and thus to adjust the oscillation frequency of the oscillator. Basically, fuse elements can be used to influence the effectiveness of any type of frequency-determining circuit parameters on a refresh oscillator of any type and thus to adjust the oscillation frequency. This also includes the possibility of influencing the effective oscillator supply voltage, for example via a voltage divider that can be changed by means of the fuse circuits.

In the described embodiment the laser fuses FL in the unattached original state with low resistance and in the set state high resistance, while for the electrical fuses FE Opposing applies. For the electrically programmable trimming circuit can use electrical fuses are used, which are in the original state with low impedance the surge are destructible. In this case, the setting of the fuse elements works in both trim circuits "in the same direction" to the oscillator frequency, which has the advantage that in both cases the same lookup table can be used when adjusting. Such a "coincidence" leaves if necessary, but also in the opposite direction of the Achieve fuses FL and FE simply by going for an inversion of the outputs one of the two trim circuits ensures.

If the electrically programmable trimming circuit according to the invention is provided, the additional possibility of trimming on the wafer has certain advantages, but is not absolutely necessary in every case. If you want to do without the possibility of laser trimming on the wafer, you can use the trimming circuit 40 and the multiplexer 80 together with its setting circuit 90 be omitted. In this case there is a fixed direct connection between the outputs of the electrically programmable trim circuit 30 and the control inputs of the refresh oscillator 25 provided.

10

DRAM memory circuitry (Chip)

11

data connections

12

address connections

13

clock terminal

14

command terminals

15

Test mode pad

16

supply terminal

17

supply circuit

21

The memory cell arrays

22

Access control device

23

instruction decoder

24

Refresh facility

25

Refresh oscillator

26

inverter chain

27

Capacity Network

28

Refresh controller

29

test block

29a

Trimming program installation

30

trimming circuit with electric fuses

40

trimming circuit with laser fuses

50

Surge source

60

Frequency setpoint generator

70

Fuse-selection device

80

multiplexer

90

Multiplexer control means

Claims (15)

Integrated DRAM memory circuit, comprising: a multiplicity of memory cells ( 21 ) and an access control device ( 22 ) for selectively actuating the memory cells in order to write data into the actuated cells and to read stored data at the actuated cells; a refresh facility ( 24 ) which has a refresh oscillator ( 25 ) and in response to periodically recurring refresh commands derived from the oscillation frequency of the refresh oscillator, the access control device ( 22 ) causes the content of each memory cell to be refreshed at regular intervals by reading the stored date and rewriting this date, the oscillation frequency of the refresh oscillator ( 25 ) must be kept at a setpoint dictated by the storage technology; a trim device ( 30 . 40 . 60 . 70 ) to adjust the oscillation frequency of the refresh oscillator ( 25 ) to the dictated setpoint by selectively applying fuse elements (EF, LF) in a network that determines the oscillation frequency ( 27 . 30 [0: 3] 40 [0: 3]), characterized in that the trimming device ( 30 . 40 . 60 . 70 ) contains the following: - an electrical programmable trim circuit ( 30 ), in which the fuse elements (EF) of the frequency-determining network ( 27 . 30 [0: 3]) can be selectively and permanently transferred by applying an overvoltage from an unset state of predetermined first impedance to a set state of predetermined second impedance, - a fuse selection device ( 70 ) for connecting a source supplying the overvoltage ( 50 ) with a selection of the fuse elements (EF) determined by a setting information. DRAM memory circuit according to claim 1, characterized in that the fuse selection device ( 70 ) for setting the electrically settable fuse elements (EF) a measuring device for measuring the actual frequency of the refresh oscillator ( 25 ) and contains a look-up table which, in the event of a deviation of the actual frequency from the dictated target frequency, provides actuating information which contains those fuse elements (EF) whose setting the oscillation frequency of the refresh oscillator ( 25 ) from the measured actual value to the dictated setpoint for the connection to the overvoltage source ( 50 ) selects. DRAM memory circuit according to claim 1 or 2, characterized in that the overvoltage source ( 50 ) for setting the electrically settable fuse elements (EF) on the chip of the memory circuit ( 10 ) is integrated. DRAM memory circuit according to claim 3, characterized in that the overvoltage source ( 50 ) contains a charge pump fed from the external supply voltage (VDD) of the chip. DRAM memory circuit according to one of the preceding claims, characterized in that the trimming device ( 30 . 40 . 60 . 70 ) a laser-programmable trimming circuit ( 40 ) in which the fuse elements (LF) of the frequency-determining network ( 27 . 40 [0: 3]) can be selectively and permanently transferred by laser bombardment from an unset state of predetermined first impedance to a set state of predetermined second impedance, and that a switching device ( 80 . 90 ) is provided, which in a first switching state ( 1 ) the frequency-determining network ( 27 . 40 [0: 3]) activated, which contains the laser-programmable fuse elements (LF), and which in a second switching state ( 0 ) the frequency-determining network ( 27 . 30 [0: 3)] activated, which contains the electrically programmable fuse elements (EF). DRAM memory circuit according to claim 5, characterized in that the switching device ( 80 . 90 ) contains an electrically settable fuse element (EF), the unset state of which is the switching device for assuming the first switching state ( 1 ) conditioned and its set state the switching device for taking the second switching state ( 0 ) conditioned. DRAM memory circuit according to one of the preceding claims, characterized in that the frequency-determining network delaying circuit elements ( 27 ) that is in the feedback loop ( 26 ) of the refresh oscillator ( 25 ) are included and their effectiveness can be influenced by setting the fuse elements (EF, LF). DRAM memory circuit according to one of Claims 1 to 6, characterized in that that the frequency-determining network comprises circuit elements, which determine the supply voltage of the refresh oscillator and their effectiveness can be influenced by setting the fuse elements is. DRAM memory circuit according to one of Claims 1 to 8, characterized by a trim mode control device ( 29a ), which is accessible via external standard connections (TMD, CMB) of the memory circuit provided for the useful operation and / or the test operation of the memory circuit ( 10 ) to the trim device ( 30 . 60 . 70 ) to select the fuse elements (EF) and to set the selected fuse elements (EF). DRAM memory circuit according to Claim 9, with a test block ( 29 ), the means for setting various operating states of the memory circuit ( 10 ) depending on the operating mode commands that can be created via external command connections (CMB), characterized in that the trim mode control device ( 29a ) in the test block ( 29 ) is installed and can be activated by applying a special trim command to the external command connections (CMB). DRAM memory circuit according to one of the preceding claims, characterized in that the fuse elements (EF) of the electrically programmable trim circuit ( 30 ) are brought into a state in which the oscillation frequency of the refresh oscillator ( 30 ) has the dictated setpoint if the external supply voltage (VDD) of the memory circuit ( 10 ) has a value intended for commercial use. DRAM memory circuit according to one of Claims 5 to 10, characterized in that the fuse elements (LF) of the laser-programmable trimming circuit ( 40 ) are brought into a state in which the oscillation frequency of the refresh oscillator ( 25 ) has the dictated setpoint if the external supply voltage (VDD) of the memory circuit ( 10 ) has a default value. DRAM memory circuit according to claim 12, characterized in that the switching device ( 80 . 90 ) to take the first switching state ( 1 ) is conditioned. DRAM memory circuit according to Claim 12, characterized in that the fuse elements (EF) of the electrically programmable trim circuit ( 30 ) are brought into a state in which the oscillation frequency of the refresh oscillator ( 25 ) has the dictated setpoint if the external supply voltage (VDD) of the memory circuit ( 10 ) has a value intended for the commercial operation that deviates from the standard value, and that the switching device ( 80 . 90 ) to assume the second switching state ( 0 ) is conditioned. Method for adjusting the oscillation frequency of the refresh oscillator of the DRAM memory circuit according to claim 9, characterized in that the trim mode control device ( 29a ) for selective setting of the fuse elements (EF) in the electrically programmable trim circuit ( 30 ) is activated after the memory circuit ( 10 ) containing the chip has been encapsulated.