DE10250364A1 - Filling irregularities and intermediate cavities during surface structuring on semiconductor, employs flow-fill process using filler of low dielectric constant - Google Patents

Abstract

Irregularities and intermediate spaces (4) are filled by a flow-fill process using a filler (9) of low dielectric constant (k). An Independent claim is included for the semiconductor element obtained.

Description

Process for filling gaps in The structuring of semiconductor surfaces The invention relates a process of filling of bumps and gaps between structures when structuring surface structures on a semiconductor surface.

In modern semiconductor technology the structures on the surface of the semiconductor substrates, which the integrated circuits carry, getting smaller and smaller. In order to are also constantly increasing the requirements for structuring technology. So it is special important that in getting closer together advancing Structures, for example individual conductor tracks on the semiconductor substrate surface, are safe insulating fillings be made in between so that there are no short circuits or Malfunction of the structured circuit elements can occur. The physical and especially the electrical Properties ever higher Requirements regarding subjected to their reproducibility and quality.

In structuring technology for example for isolation and stabilization between and on individual interconnects the spaces between adjacent interconnects previously closed by means of a two-layer passivation. The Two-layer passivation consists of one between the spaces and Bumps on the substrate surface filling oxide layer (silicon oxide, SiO), which by a PECVD process ("Plasma Enhanced Chemical Vapor Deposition ", PECVD) is applied, and one protecting the oxide layer to the outside impermeable Nitride layer (silicon nitride, SiN). It is for the function of the layer system is essential that the nitride layer completely closed over the oxide layer.

Now the narrowing structuring leads to follow the miniaturization and circuit-related approximation of the individual structures on the semiconductor substrate surface to that the ones to be filled interspaces and bumps are very close to each other modern procedures to be filled interspaces of less than 0.11 µm. The previous method of deposition leads the silicon oxide layer with such tight spaces to form open or partially closed cavities ("voids"). The subsequently separated Silicon nitride layer can then no longer grow homogeneously on the surface of the oxide layer and thus openings and gaps exhibit. A complete covering of the oxide layer is then no longer guaranteed. It can be used in further fabrication steps or in the operation of the semiconductor circuit to damage and to destruction the circuit due to diffusion of foreign matter and moisture.

In 2 shows a cross section through a semiconductor circuit in which such a failure has occurred due to the formation of voids.

The one on the substrate 2 manufactured structures 1 (in the example conductor tracks) are with a silicon oxide layer 5 been surrounded. There is the space 4 between the individual structures have not been completely filled. Due to the small distances between the neighboring structures, there are cavities 6 emerged. These cavities per se are not completely malfunctioning because they have a very low dielectric constant (approx. 1.0), that is, they have an even lower dielectric constant than the oxide itself (approx. 4.0). The blowholes, however, lead to the surface of the oxide layer 5 to weak points that the applied nitride layer 7 Openings, so mistakes 8th has, whereby the underlying oxide layer 5 lies open. In further process steps that require the nitride layer, the structures will be destroyed. Penetrating moisture can pass through the permeable oxide layer and lead to corrosion or damage to the metal tracks.

3 shows a cross section through a manufactured using a conventional method for semiconductor structures> 0.11 μm.

Therefore, in the usual Structuring technique minimal distances between the structures on the semiconductor substrate surface complied with, so that the formation of the process Blowholes also remain minimal. The miniaturization are thereby Set limits that are undesirable are.

The object of the invention is therefore a process of filling of bumps and gaps between structures when structuring surface structures on a semiconductor surface to create a consistent, reproducible quality of the fillings guaranteed is, and the spatial Limitations of the previous procedures no longer exist.

This task is accomplished through a process solved with the features of claim 1.

According to the invention, it is provided that the interspaces are filled with a filler material of low dielectric constant ("low k material") using a flow fill process. This has the advantage that uniform filling with material of low dielectric constant (dielectric constant approx. 3.0) a defined material is inserted between the structures, no longer a mixture of oxide, nitride, cavities and imide as before. The flow fill process means that there are almost no layout restrictions. A final nitride layer can be placed on the flat surface The structures that are now possible limit the runtime effects due to the shorter electrical lines that are now possible and enable the reduced capacities between the lines higher clock rates. Together with the new technology for filling interstices, the known photoresist and the known etching materials can continue to be used. A quick and therefore inexpensive application of the new method has been opened.

The filling material is preferably chosen so that its dielectric constant is less than or equal to 3.

The structures are advantageously between which the space is filled, metal tracks, which are designed as conductor tracks. This is where the advantages come from the procedure is particularly effective.

The structures that exist between themselves form the intermediate space, preferably have a distance of less than 110 nanometers.

Preferably after filling with the filling material a closed silicon nitride layer on the surface of the filler applied. This protects the filling layer.

The silicon nitride layer is advantageous by means of a PECVD process (“Plasma Enhanced Chemical Vapor Deposition ", PECVD) applied.

This is preferably the layer system of the structured semiconductor final passivation layer generated by the process.

Other advantages, special features and appropriate further training the invention result from the further subclaims or their sub-combinations.

The invention is explained below the drawing further explained.

It shows:

1 a cross section through a semiconductor structure produced by means of the method according to the invention;

2 a cross section through a semiconductor structure produced by means of a conventional method with errors occurring in the process; and

3 a cross section through a manufactured using a conventional method for semiconductor structures> 0.11 microns.

In the figures denote the same Identical elements or elements having the same effect.

1 shows a semiconductor device produced by means of the method according to the invention 10 in cross-sectional representation. On the substrate 2 are structures first 1 in the form of metal tracks 3 been formed, in the example a silicon substrate was used for this. The spaces extending between the metal tracks 4 were then using the method according to the invention with a filler 9 filled with a low dielectric constant ("low k material"). Finally, a nitride layer 7 applied over the very flat surface of the filling material, which can be done without any problems since no disturbances due to unevenness are to be expected.

The nitride layer was in the Example using a PECVD process (“Plasma Enhanced Chemical Vapor Deposition ", PECVD) applied, which can be applied in a standardized manner. As Material for the nitride layer was silicon nitride.

1

structure on substrate surface

2

substratum

3

strakes

4

gap

5

silicon oxide

6

Lunker

7

Silicon nitride layer

8th

error in the surface

9

filling material

10

Semiconductor device

Claims (8)

Method for filling bumps and gaps between structures when structuring surface structures on a semiconductor surface, characterized in that the gaps and bumps are filled by a flow fill process with a filler material of low dielectric constant ("low k material"). A method according to claim 1, characterized in that the filler so chosen is that its dielectric constant is less than or equal to 3. A method according to claim 1 or 2, characterized in that that the structures between which the gap is filled Are metal tracks, which are designed as conductor tracks. Method according to one of the preceding claims, characterized characterized that the structures that are between them the gap form, have a distance of less than 110 nanometers. Method according to one of the preceding claims, characterized characterized that after filling with the filling material a closed silicon nitride layer on the surface of the filler is applied. Method according to one of the preceding claims, characterized characterized in that the silicon nitride layer by means of a PECVD process ("Plasma Enhanced Chemical Vapor Deposition ", PECVD) is applied. A method according to claim 6, characterized in that the passivation finishing the layer system of the structured semiconductor layer is generated by the method. Semiconductor component, characterized in that it has been produced by a method according to any one of claims 1 to 7 is.