DE10231965B4 - Method for producing a T-gate structure and an associated field effect transistor - Google Patents

Abstract

Method for producing a T-gate structure with the steps:
a) forming a sacrificial gate stack (2, 3, 4) on a semiconductor substrate (1);
b) forming a sidewall isolation structure (5S, 6S) on the sidewalls of the sacrificial gate stack (2, 3, 4);
c) removing the sacrificial gate stack (2, 3, 4) to form a gate recess (A);
d) removing a part (5S) of the sidewall insulating structure (5S, 6S) in the upper region (I) to form a widened gate recess (AA); and
e) filling the widened gate recess (AA) with a highly conductive material (12),
characterized in that in step c) the sacrificial gate stack (2, 3, 4) for exposing the semiconductor substrate (1) is completely removed;
a gate dielectric (9) is formed at least on the exposed semiconductor substrate (1);
a gate layer (10) is formed on the gate dielectric (9); and
the gate layer (10) in an upper area (I) is removed again.

Description

The The present invention relates to a method of manufacture a T-gate structure and an associated field effect transistor according to the generic term of claim 1

Such a generic method is for example from the document US Pat. No. 6,346,450 B1 known.

With the progressive integration density of semiconductor circuits The critical dimensions and smallest ones are also increasingly decreasing Structure sizes of Semiconductor devices. A type of transistor widely used in such semiconductor circuits is widespread, is the so-called field effect transistor, in which a current between a source region and a drain region via a so-called control electrode or a gate is driven.

The capacity and in particular the electrical properties of this transistor type however, essentially determined by its size, where especially for Structure sizes below 100 nanometers significant problems occur. In particular are for field effect transistors Here, the electrical resistance of the control layer or the gate as well as a gate capacitance to call. The ones shrinking with the progressive miniaturization However, structure sizes lead to increased gate capacities and increased Gate resistors, the the electrical properties such as the switching speed and affect the power consumption of the circuit.

More accurate said gate resistance is due to the shortening gate lengths or channel lengths bigger, thereby in particular, the clock rates are limited.

to Elimination of such negative effects has therefore become a so-called T-gate structure introduced, wherein the control layer or the gate has a T-shape. By this T-shape can be used in lower area continues to realize the desired low channel lengths be while due to the widening in the upper area sufficiently small Gate resistors are enabled.

In order to realize such T-gate structures, a broad but shallow first trench is usually first formed in a dielectric material and then a narrow but deep second trench is formed in the first trench and filled with a conductive semiconductor material, thereby obtaining the desired T-gate structure , Such a conventional method for the production of T-gate structures is for example from the document US Pat. No. 6,159,781 known. However, structural widths below 100 nanometers are particularly difficult to produce. Furthermore, with such small feature widths, the required low gate resistances can no longer be realized with the commonly used polysilicon as the filling material.

Furthermore, from the publications DE 199 36 005 A1 and JP 2000124228 A Each method for producing a T-gate structure is known in which sacrificial gate stacks or so-called dummy gates are formed on a semiconductor substrate, a sidewall insulating structure is formed on the side walls of the sacrificial gate stack, at least an upper region of the victim Gate stack is removed to form a gate recess and the gate recess is filled with a highly conductive material. Again, however, structure widths below 100 nanometers are difficult to produce.

From the publication US Pat. No. 6,235,627 B1 a method for producing a T-gate structure and an associated field effect transistor is known, wherein only an upper region of a sacrificial gate stack for the realization of a widening or T-gate structure is removed.

Further, according to the generic method for producing a T-gate structure according to the document US Pat. No. 6,346,450 B1 completely removes a sidewall isolation structure at the top of the sacrificial gate stack, but significantly increases the potential for shorting to adjacent elements.

Of the The invention is therefore based on the object, a process for the preparation a T-gate structure and an associated field effect transistor to create which cost is and also for Sub-100 nanometer structures have useful electrical properties having.

According to the invention this Task regarding the T-gate structure through the measures of Patent claim 1 and with respect to the field effect transistor the measures of claim 13.

In particular, by completely removing the sacrificial gate stack to expose the semiconductor substrate, forming a gate dielectric and a gate layer on the exposed semiconductor substrate, and removing the gate layer at the top of the gate stack, high quality and to a respective semiconductor material can be achieved created customized control layers and thus improves the electrical properties and the risk of a short circuit from the gate to adjacent elements can be reduced.

Preferably becomes a sacrificial gate stack a sacrificial gate and a cover layer formed and structured why you after removing the cover layer adequate isolation of the top edge of the sacrificial gate and thus of the later Gates receives.

at Use of a first spacer and a second spacer, for example with a first etch stop layer are separated from each other receives a particularly easy-to-implement side wall insulation structure, wherein the widening of the gate recess in the upper region of the first Spacer using the first etch stop layer and the remaining Victim gates can be easily trained.

Preferably can for the padding the widened gate recess a so-called damascene method, wherein a diffusion barrier layer and / or a germination layer to prevent unwanted Indiffusion of dopants and to improve a growth process be formed in the widened recess.

Preferably will be at this padding the widened gate recess copper as a highly conductive material deposited and planarized, with another protective layer designed to prevent outdiffusion of undesired dopants becomes.

alternative can be considered highly conductive Material but also so-called doped metal deposited and (e.g., CuIn, CuAl, CuMg, CuSn, CuAg, CuZr), wherein then through a thermal treatment self-adjusting the diffusion barrier layer through at the surface Outdiffusion of the dopants is formed.

Further may be another thermal treatment to produce a grain growth in highly conductive Material performed be, whereby in particular a conductivity can be further improved and the electromigration properties can be improved.

Especially when Ta or TaN is used as the gate metal layer, a necessary adaptation of a work function of the gate metal layer to a respective doping of the semiconductor substrate by a nitrogen implantation be adjusted.

Regarding of the method for producing a field effect transistor can in Forming the sidewall isolation structure one or more implantations for forming connection areas and / or source / drain areas performed in the semiconductor substrate which makes it particularly easy and self-adjusting Way these areas can make. Further, after the Forming the sidewall isolation structure highly conductive connection areas for the Self-adjusting source / drain regions by means of a silicide method be formed, which is why this method, in particular for field effect transistors in the sub-100 nanometer range is suitable.

In the further subclaims Further advantageous embodiments of the invention are characterized.

The Invention will now be described by way of embodiments with reference closer to the drawing described.

It demonstrate:

1A to 1H simplified sectional views for illustrating essential method steps according to a first embodiment;

2 a simplified sectional view illustrating a final method step according to a second embodiment; and

3A to 3C simplified sectional views to illustrate essential process steps according to a third unclaimed example.

The 1A to 1H show simplified sectional views illustrating essential process steps in the production of a T-gate structure, as it is preferably used in field-effect transistors in a sub-100 nanometer range. In principle, however, the T-gate structure can also be used for other semiconductor components, such as non-volatile semiconductor memory elements.

According to 1A is first in a standard process on a semiconductor substrate 1 (For example, monocrystalline Si), for example, a pad oxide (not shown) and pad nitride deposited and for forming active regions in the semiconductor substrate 1 a shallow trench isolation STI (Shallow Trench Isolation) is formed. Subsequently, wells, also not shown, can be implanted are performed and on the surface of the semiconductor substrate 1 an unillustrated sacrificial oxide layer (sacrificial oxides) may be formed.

The following is a sacrificial gate layer 2 deposited over the entire surface, wherein preferably amorphous or polycrystalline semiconductor material such as silicon is deposited. On the surface of the sacrificial gate layer 2 becomes a hardmask layer 3 formed as a cover layer, for example, a TEOS hardmask is deposited. Subsequently, a structuring of the covering layer is carried out with a conventional photolithographic process 3 and by the structured covering layer 3 a structuring of the sacrificial gate layer 2 preferably selective to the sacrificial oxide layer present on the semiconductor substrate surface.

In particular, in the realization of T-gate structures for field effect transistors, the cover layer 3 on the sacrificial gate layer 2 remain for the time being and not be removed, resulting in improved insulation properties at a later date. By an optional additional sidewall oxidation of the sacrificial gate layer 2 for forming a sidewall insulation layer 4 from eg 3 to 6 Nanometer thermal oxide gives the in 1A illustrated sacrificial gate stack.

The following are on the sidewalls of the sacrificial gate stack 2 . 3 and 4 Sidewall isolation structures formed. For example, by means of a conventional spacer method, for example, a silicon nitride layer is deposited over the whole area and then anisotropically etched, whereby the in 1a illustrated first spacer 5S and first residual layers 5 ' on the flanks of the trench isolation STI receives. Due to the remaining covering layer 3 The first spacer is enough 5S up to the upper edge of the hard mask or covering layer 3 why is obtained for the final gate stack sufficient insulation to adjacent elements such as contact terminals. As the anisotropic etching method, for example, reactive ion etching (RIE) is used.

Optionally, after formation of the sacrificial gate stack 2 . 3 and 4 and the spacer 5S a first implantation I _{1 are} performed, whereby connecting regions LDD for a respective channel region are formed self-aligning in the semiconductor substrate.

After this manufacturing step for the realization of the first spacer 5S Optionally, it may further include an etch stop layer (not shown) in the form of a thin oxide on the side flanks of the first spacer 5S be formed. By way of example, an approximately 2 nanometer thick CVD silicon dioxide layer is deposited or this etch stop layer is thermally realized, for example, by converting part of the Si ₃ N ₄ layer by means of an oxidation process.

For the production of T-gate structures in the sub-100 nanometer range, the sacrificial gate stack 2 . 3 and 4 preferably formed sublithographically and thus may have a width of typically 30 to 50 nanometers. The height of the sacrificial gate layer 2 is for example 100 to 200 nanometers and the thickness of the first spacer 5S 10 to 20 nanometers.

Of course you can too other dimensions depending set by a particular application and the materials used become.

According to 1B In a subsequent step of completing the sidewall isolation structure, a second spacer is formed 6S analogous to the first spacer 5S again formed by means of a conventional spacer method, wherein, for example, a second silicon nitride layer is deposited and anisotropically etched. The thickness of this second spacer 6S is for example 50 to 70 nanometers, while its height preferably again up to the top of the hard mask or cover layer 3 extends, thereby improving isolation in this area.

According to 1B can be done using the first and second spacer 5S and 6S and the sacrificial gate stack, a second implantation I _{2 are} performed, whereby the actual source / drain regions S / D are formed in the semiconductor substrate. Again, this gives you a self-adjusting process that is particularly suitable for very small structures.

In particular, in the manufacture of a field effect transistor with T-gate structure can already at this time highly conductive connection areas 7 for the source / drain regions S / D, for example by means of a self-adjusting silicide process (Salicide Process) are formed. For the realization of such highly conductive connection areas 7 is according to 1C For example, first silicatable material or a silizierfähige metal layer such as cobalt, nickel or platinum over the entire surface deposited. Subsequently, a conversion of the crystalline surface layer of the semiconductor substrate 1 using the silicatable material to form highly conductive connection areas 7 carried out, wherein on the not with semiconductor material (silicon) in contact surfaces no Si lizid is formed, but the deposited material (metal) remains, wes In turn, a selective etching back of the deposited metal layer can be carried out by means of a preferably wet-chemical etching process. In this way, using only one etching chamber, a plurality of structuring steps for forming the spacer structures as well as the terminal regions can be carried out in a self-adjusting manner, which further reduces the manufacturing costs.

When using cobalt, nickel, titanium or platinum arise as highly conductive connection areas 7 Cobalt, nickel, titanium or platinum silicide layers, which can be formed self-aligning. The above-described embodiment of the connection areas 7 However, it can also be carried out at a later time, for example after completion of the field effect transistor and formation of contact openings.

According to 1D becomes a protective layer in a subsequent step 8th formed and together with the side wall insulation structure and the two spacers 5S and 6S until the sacrificial gate layer 2 planarized. More specifically, for example, a high density plasma (HDP) oxide layer, a BPSG (Boron Phosphorus Silicate Glass) layer or a TEOS layer is deposited over the entire surface and planarized by a CMP (Chemical Mechanical Polishing) method using as the stop layer the polysilicon of the sacrificial gate layer 2 serves.

According to 1E In the following, essentially a special gate replacement process can be carried out. For example, first the victim gate layer 2 completely removed with a wet-chemical polysilicon etching and then with an oxide etch formed on the semiconductor substrate surface semiconductor sacrificial oxide layer and on the side walls and the first spacer 5S remaining sidewall insulation layer 4 completely removed. Subsequently, at least in the bottom region of the recess or on the exposed surface of the semiconductor substrate 1 a gate dielectric 9 formed, wherein, for example, silicon oxide, silicon nitride, oxynitride or a so-called high-k dielectric is deposited. Such gate dielectrics have a sufficiently high dielectric constant and accordingly can realize a sufficiently high gate capacitance. Subsequently, the gate recess A with the actual gate layer 10 filled, for example, undoped polysilicon can be used. After poly-CMP planarization, the gate layer can be doped 10 or for the realization of a sufficient conductivity of the gate layer 10 a gate implantation not shown are performed.

alternative However, in-situ doped to the process sequence described above Materials such as e.g. Polysilicon or poly-SiGe for NFET and PFET can be used or gate metal layers with suitable Work functions.

If the highly conductive silicide layers 7 not yet been formed, they are made at this time. This is the isolation layer 8th removed, for example by means of a wet chemical etching process. Subsequently, the desired metal layer such as Co, Ni, Ti, or Pt is deposited and silicided. Then the insulation layer becomes 8th reapplied and planarized.

Finally, the introduced gate layer 10 in the upper region I again removed, for example, to a depth of 50 nanometers above the gate dielectric 9 a so-called CDE (Chemical Dry Etching) method is performed.

According to 1F In order to form a widened gate recess AA, the side wall insulation structure or the first spacer exposed in the upper region I will now be visible 5S away. This removal can be done either after a period of time or until the optionally inserted etch stop layer. Here, the serves between the first spacer 5S and second spacer 6S formed thin oxide layer as Ätzstoppschicht.

At typical thicknesses of the first spacer 5S of 10 nanometers is thus achieved a broadening of the gate stack in its upper region I by 20 nanometers, which represents a significant broadening of the gate, especially for feature sizes below 100 nanometers. In future to be realized field effect transistors with a small gate length of, for example, less than 40 nanometers thus obtained a widening of the gate in its upper region I by 50% or more.

Furthermore, as the first spacer 5S and the second spacer 6S were formed at a time when the sacrificial gate stack with its from the sidewall oxide layer 4 and the sacrificial gate layer 2 existing layers nor the cover layer 3 had, made sure of the second spacer 6S a sufficiently thick insulating layer or nitride layer extends to the upper edge of the widened gate recess AA. This insulating layer or the second spacer 6S thus prevents a possible short circuit in a later process step for the realization of contact holes for gate and source / drain areas.

According to 1G can be formed in the further process control at this point, the desired material for the upper region I of the gate become. This may be, for example polysilicon, but with improved process control at this point highly conductive material 12 such as Cu used. In particular, reference is made at this point to a so-called damascene method, as described, for example, by T. Matsuki et. al. "Cu / poly Si damascene gate structured MOSFET with Ta and TaN stacked barrier", IEDM 1999, pages 261 to 264 is known.

According to 1G can therefore in the widened gate recess AA first a layer 11 (For example, TiN, Ta, TaN, TaC, WN, WC, WCN) are formed, the diffusion barrier layer and / or as a germ or growth layer on the one hand, an undesirable in-diffusion of interfering impurities from the highly conductive material 12 prevents and on the other hand allows for improved growth in the very narrow trench. As a highly conductive material 12 For example, Cu (or Al, W, Ag, Au) is subsequently deposited and planarized by means of a CMP process.

According to 1H For the realization of a further protective layer, a so-called cap layer is used 13 and a relatively thick insulating layer 14 formed over the entire surface. The cap layer 13 serves in turn as a diffusion barrier layer to avoid outdiffusion of, for example, Cu atoms and consists for example of silicon nitride, SiC or SiCN. As insulation layer 14 for the contact hole plane, for example, BPSG, TEOS or a low-k material with a low dielectric constant is used. Finally, contact holes V are formed at the positions of the source / drain regions S / D and the gate.

On get that way a T-gate structure with excellent electrical conductivities, which also in a sub-100 nanometer range simple and high can be trained exactly.

2 shows a simplified sectional view of a final manufacturing step according to a second embodiment, wherein like reference numerals represent the same or corresponding layers or elements as in 1 a repeated description is omitted below.

According to 2 may alternatively to the cap layer described above 13 also a selective deposition of a metal as a metallic diffusion barrier can be performed. As such metals, essentially CoP, CoWP, (electrolessly deposited) CoWB, or (CVD-deposited) W or WN are suitable. In this case, there is a further diffusion barrier layer formed thereby 130 only on the highly conductive material 12 and not on the protective layer 8th ,

If doped metal layers and in particular doped Cu layers such as CuAl, CuMg, CuIn, CuSn, CuZr, etc. are used as the material for filling the widened gate recess AA, the deposition of such a cap layer is not necessary, since these layers after a thermal treatment at a temperature less than 400 degrees Celsius, the dopants diffuse to the surface and a self-passivating layer as a further diffusion barrier layer 130 produce.

To reduce the resistance of the highly conductive material 12 Furthermore, in the geometrically very small recesses A and AA, further thermal annealing may be carried out locally or globally in a furnace process, wherein grain growth in the highly conductive material 12 optimized and a number of grain boundaries is minimized. In addition to the improved conductivity, this also allows the electromigration properties of the control layer to be significantly improved.

Thus, according to the invention using a special gate replacement process without execution an additional one critical lithography step a T-gate structure produced, wherein the gate resistance is reduced and the gate capacitances improved are. In particular, when using highly conductive materials such as Cu is obtained especially low gate resistance.

3A to 3C again show simplified sectional views to illustrate essential manufacturing steps according to an unclaimed example, wherein like reference numerals describe the same or corresponding layers as in the embodiments 1 and 2 and therefore a detailed description is omitted hereafter.

In this example, in turn, the sacrificial gate stack, or that of the gate layer 2 and the sidewall insulation layer 4 existing sacrificial gate, completely removed, thereby obtaining improved electrical properties for a respective field effect transistor.

According to the example described below, in the same way as in the first embodiment, the manufacturing steps according to 1A to 1D carried out, but now after the planarization according to 1D the method step according to 3A is carried out.

More specifically, in this example, the sacrificial gate layer becomes 2 not complete, ie until the Semiconductor substrate 1 but only in the upper area I removed and then using this recess A, the first spacer 5S in the same way as in the first embodiment according to 1F removed to form the widened gate recess AA. To avoid repetition, reference is therefore made at this point to the description in the first embodiment.

Thus one receives the in 3A shown widened gate recess AA, the first in its lower region II still with the sacrificial gate or the sacrificial gate layer 2 and the sidewall insulation layer 4 is filled.

According to 3B In a subsequent step, the sacrificial gate is exposed to expose the semiconductor substrate 1 completely removed and the actual gate dielectric 9 at least on the exposed semiconductor substrate 1 educated. Preferably, in this case, a thermal oxidation of the semiconductor substrate 1 performed or a high-k material deposited.

The materials here correspond to the above-described materials for the gate dielectric 9 , Subsequently, before filling with the actual highly conductive material 12 a so-called gate metal layer 100 formed over the entire surface, wherein, for example, Ta or TaN is deposited. This gate metal layer 100 acts both as a diffusion barrier layer as well as a matched metal gate, whereby the electrical properties of a respective field effect transistor can be significantly improved. The gate metal layer 100 is deposited, for example, by a CVD method (Chemical Vapor Deposition) or a PVD sputtering method (Physical Vapor Deposition), wherein in the case of the CVD method a so-called precursor for Ta is used. The growth or the deposition takes place, for example, under NH ₃ atmosphere. In the case of the PVD method, either a TaN target is used, or Ta sputtered, which subsequently reacts to TaN.

To optimize the work function of the gate metal layer 100 Optionally, for example, a nitrogen implantation I _N can be performed.

According to 3C in turn becomes the widened gate recess AA with highly conductive material 12 such as Cu filled and planarized by means of a CMP process. One as a diffusion barrier layer 130 acting cap layer can be formed in the same manner as in the embodiments described above. Finally, in turn, a thick oxide layer can be formed as an insulation layer for the contact hole plane and the contact holes V in the same way as in FIG 1H will be realized.

By using the gate metal layer 100 and the filling of the lower portion II with highly conductive material to obtain much faster cycle times at the same time reducing voltages and a reduced footprint.

The The invention has been described above with reference to a silicon semiconductor substrate and correspondingly adapted materials. It is not limited to this and similarly includes alternative materials with corresponding ones Effects. Likewise, the invention is not limited to field effect transistors limited with T-gate structure, but in the same way comprises further semiconductor components with such T-gate structures.

1

Semiconductor substrate

2

Sacrificial gate layer

3

covering

4

Sidewall insulation layer

5 ', 5S

first Remaining layer, first spacer

6 ', 6S

second Remaining layer, second spacer

7

terminal area

8th

protective layer

9

Gate dielectric

10

gate layer

11

Diffusion barrier layer

12

Highly conductive material

13 130

 Further Diffusion barrier layer

14

insulation layer

V

contact hole

S

source region

D

drain region

LDD

terminal region

STI

grave insulation

A

Gate recess

AA

widened Gate recess

I

upper Area of the gate

II

lower Area of the gate

I ₁ , I _Z , I _N

ion implantation

100

Gate metal layer

Claims (14)

A method for producing a T-gate structure comprising the steps of: a) forming a sacrificial gate stack ( 2 . 3 . 4 ) on a semiconductor substrate ( 1 ); b) forming a sidewall isolation structure ( 5S . 6S ) on the side walls of the sacrificial gate stack ( 2 . 3 . 4 ); c) removing the sacrificial gate stack ( 2 . 3 . 4 ) for forming a gate recess (A); d) removing a part ( 5S ) of the sidewall isolati onsstruktur ( 5S . 6S ) in the upper region (I) for forming a widened gate recess (AA); and e) filling the widened gate recess (AA) with a highly conductive material ( 12 ), characterized in that in step c) the sacrificial gate stack ( 2 . 3 . 4 ) for exposing the semiconductor substrate ( 1 ) is completely removed; a gate dielectric ( 9 ) at least on the exposed semiconductor substrate ( 1 ) is formed; a gate layer ( 10 ) on the gate dielectric ( 9 ) is formed; and the gate layer ( 10 ) is removed again in an upper region (I). Method according to claim 1, characterized in that in step a) as sacrificial gate stack a sacrificial gate ( 2 . 4 ) and a cover layer ( 3 ) for covering the victim gate ( 2 . 4 ) is formed and structured. Method according to claim 1 or 2, characterized in that in step b) a sidewall insulating structure is a first spacer ( 5S ) and a second spacer ( 6S ) is formed. Method according to claim 3, characterized in that in step d) between the first spacer ( 5S ) and the second spacer ( 6S ) a first etch stop layer is formed. Method according to one of the claims 2 to 4, characterized in that in step b) a protective layer ( 8th ) and together with the sidewall isolation structure ( 5S . 6S ) to the sacrificial gate ( 2 . 4 ) for removing the cover layer ( 3 ) is planarized. Method according to one of the claims 3 to 5, characterized in that in step d) the first spacer ( 5S ) is completely removed in the upper area (I). Method according to one of the claims 1 to 6, characterized in that in step e) a diffusion barrier layer ( 11 ) and / or a seed layer is formed. Method according to one of the claims 1 to 7, characterized in that in step e) as highly conductive material ( 12 ) Cu is deposited and planarized and finally a further protective layer ( 13 . 14 ) is formed. Method according to one of the claims 1 to 7, characterized in that in step e) as highly conductive material ( 12 ) doped metal layers are deposited and planarized and then a thermal treatment for producing a further diffusion barrier layer ( 130 ) is carried out. Method according to one of the claims 1 to 9, characterized in that in step e) a thermal treatment for generating a grain growth in the highly conductive material ( 12 ) is carried out. Method according to one of the claims 1 to 10, characterized in that in step e) before filling with the highly conductive material ( 12 ) a gate metal layer ( 100 ) is formed. Method according to claim 11, characterized in that the gate metal layer ( 100 ) Ta or TaN and for adapting a work function of the gate metal layer ( 100 ) a nitrogen implantation (I _N ) is performed. Method for producing a field effect transistor with T-gate structure according to the preceding patent claims, characterized in that in step b) at least one implantation (I ₁ , I ₂ ) for forming connection regions (LDD) and / or source / drain regions (S, D) in the semiconductor substrate ( 1 ) is carried out. Method for producing a field effect transistor with T-gate structure according to claim 13, characterized in that after step b) connection areas ( 7 ) for the source / drain regions (S, D) are formed by a silicide method.