DE10229945A1 - Microprocessor interrupt controller has means for processing interrupts such that requests of lower priority do not execute ahead of higher priority requests, provided they are still within their given latency time - Google Patents

Abstract

Interrupt controller comprises parallel input (30) for receipt of a first interrupt request signal, means (31) for output of a second interrupt request signal as a reaction to the first interrupt request signal, state processing means (32) for determining interrupt priority, memory (37) for storing addresses of interrupt servicing programs whereby each servicing program handles an interrupt signal and means (36) for selection of an address based on the priority.

Description

FIELD OF THE INVENTION

The present invention relates generally to the field of Interrupt request processing. In particular The invention relates to interrupt controllers and the effective Submission of interruptions to a Microprocessor system.

GENERAL PRIOR ART BASED ON THE INVENTION STATE OF THE ART

A device (e.g. a control unit for a Storage drive) of a computer system can with a A system's microprocessor interact to create a specific function (e.g. retrieving data from a Hard disk). During this interaction it z. B. necessary, operations in progress Interrupt microprocessor temporarily so that the Microprocessor can operate the device.

To the. For example, the microprocessor can Instruct a block of data from a controller Get hard drive, and during the Storage drive controller retrieves the data, the Microprocessor perform other operations such as B. one Execute program code. After the controller receives the data called up and the data stored in a system memory the controller can then inform the microprocessor.

A way for the controller to inform the Microprocessor is generating one Interrupt request. In response to that The microprocessor holds the interrupt request in the Rule every operation in progress, e.g. B. reading of data from system memory, and make decisions based on this data.

An interrupt request is usually made via a Interrupt request signal transmitted. For one edge-controlled interrupt request changes that Interrupt request signal logic states (changes z. B. from a state logically "high" to a state logic "deep") to indicate the interrupt request. A height-controlled interrupt request is made in the Rule by logical state (either high or low) of the interrupt request signal is displayed. So will an edge-triggered interrupt request by a predetermined transition of the interrupt request signal displayed, and an elevation interrupt request is determined by a predetermined logical amount of Interrupt request signal displayed.

A typical computer system has many devices that the microprocessor has to watch out for, and so there is many devices that have interrupt requests have to generate. However, the microprocessor possibly only a single input contact pin and therefore can only handle a single interrupt request edit once.

From US-A-6,192,442 an interrupt controller is known which Interrupt request signals from the devices receives the priorities of the interrupt requests, which are indicated by these signals, determined and the Interruption requests individually for each Microprocessor for execution. The interrupt Controller contains conductors for receiving the Interrupt request signals, a memory Register and control logic. Each of the Interrupt request signals are able to receive a Display interrupt request. The store is in the Location, information about the Store interrupt request signals, and that Register can be written to a sentence Identify memory locations for scanning. The Control logic only samples the set of memory locations Interrupt requests and no other storage locations on interrupt requests. In some cases exceeds the number of Interrupt request signals the number of Memory locations. In these cases, information about selected interrupt signals at the storage locations saved.

Furthermore, it is known in the prior art that the Communication between a communication card and one external processor, such as the processor on a host Controller card, or a system unit processor, by means of Interrupts can be executed. For example, US-A- 6,233,643 an apparatus including a host processor and communication adapters, which are interconnected via a bus are. The communication adapters each contain one Number of digital signal processors and network Interface circuits for connecting a multi-channel Telephone line. A bus that is the communication adapter connects data between a network line connected to one of the adapters is connected, and the digital one Send signal processors of the other adapters. The Digital signal processors on each card are connected to a host or controller processor. Everyone Digital signal processor interrupts its host processor by transmitting an interrupt control block as data a data memory of the host processor and through then sending an interrupt that causes the Host processor checks the data storage. Preferably the interrupt control block contains data that is a number represent requested interruptions.

US Pat. No. 4,991,169 describes the use of a dual digital signal processor (DSP) to real-time links between Time multiple channels of a digital carrier system (e.g. T-1) and to provide a host data processor. When working only with digital signals, internally and at its interfaces with the carrier and the host system, the DSP exchanges data and control signal information with the carrier system and data and control information with the host processor the data in different digital forms during the run around. The signals are at the interface to the carrier system recorded and transferred into a form that is different Terminal devices adapted by users and with the Carrier system via the switched public network are remotely connected. Be on the host interface Transmit and receive signals in a suitable form, for the data processing requirements of the host system is suitable (e.g. data bytes that are directly alphanumeric Represent characters). The DSP works as an equivalent Device for multiple different types of modems in the Implementation of required conversions. The DSP can too Provide machining services to the machining load on the Reduce host system (i.e. parity checking of data, Capture specific character functions in data or of specific tones in audio signals, and selective Mute voice-to-host memories for Voice communication system applications.

US Pat. No. 5,553,293 describes an intermediate computer Interrupt unit (IIU) for processing interrupts between a remote processor and a host processor in a multiprocessor system. The IIU calls from Processing interruptions affected tasks by Core of the remote processor. Control blocks with Interrupt information and commands are processed by the Remote processor in data random access memory (DRAM Random access memory). The remote processor packs a buffer of control block memory addresses in the DRAM for the IIU as access to retrieve the control blocks from the DRAM. The IIU receives a control block and loads the control block in Register. The IIU then issues an interrupt request the host processor. The host processor receives the Interrupt request and shows the IIU that the Interrupt was processed. The IIU will then inform the Remote processor that the interrupt was processed. The IIU can be programmed to use the remote processor completion either by an interrupt or by Teaches a status flag in the DRAM.

US Pat. No. 5,572,695 describes a digital one Signal processing system including first and second logical memory mapping units corresponding to first and second digital processors and with one Data storage unit are coupled. The first and the second Imaging units are effective for capturing (i) first and second logical addresses from the first and the second digital processor was generated, and (ii) first and second address mapping information, and generate first and second physical addresses so that each of the digital processors independently access any one Plenty of storage locations in the data storage unit can take.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a improved interrupt controller as well as an improved Method of transmitting an interrupt request provide.

This problem is solved by applying the appropriate Features of the independent claims.

Preferred embodiments of the invention are given by the dependent claims.

The invention provides an effective means of transmission interrupt requirements for a microprocessor system with reduced interrupt latency. With that the Time delay to service the interrupt requests considerably reduced.

According to a preferred embodiment of the invention the priority determination of the interrupt request considerably accelerated and can be modified effectively become.

The invention is particularly advantageous because it enables the processor performance requirement by adding only to reduce a minimal amount of additional circuitry. In particular, this enables the cost-effective Interrupt processing solutions with reduced Requirements for processor performance and features and with only minimal additional hardware for the interrupt controller.

It is a particular advantage of the invention that the load significantly reduced to the operating system of the processor will, d. that is, it is no longer necessary for that Operating system the number of control programs installed determined so that it can process all control programs.

According to a further preferred embodiment of the Invention can process interrupt requests d. i. filtered and / or masked for effectiveness and Flexibility in processing interrupt requests to increase even further.

It is another particular advantage of the invention that it enables the latency induced in the operating system for processing the interruption requests minimize.

According to a preferred embodiment of the invention the interrupt controller by means of a programmable logical arrangement (PLA - programmable logic arrangement) implemented. The PLAs are in front of the interrupt input of the corresponding microprocessor system, such as. B. a central Processing unit (CPU) inserted.

Alternatively, the interrupt controller is entirely by means of a programmable application-specific integrated Circuit (pASIC) and / or by means of a Field programmable gate array (FPGA) that is in front of the Interrupt input of the corresponding microprocessor system is used, realized.

In a further preferred embodiment, the Invention implemented using an ASIC, so that the Interrupt controller to replace the entire standard CPU Interrupt controller is set within the ASIC. With In other words, the interrupt controller can act as one integral part of the microprocessor system on the same Chip are implemented.

A preferred embodiment of the Invention in more detail with reference to the Drawings explained in these:

Brief description of the drawings

Fig. 1 is an illustrative view showing one embodiment of the method for transmitting an interrupt request;

Fig. 2 is a block diagram showing an embodiment of an interrupt controller.

Detailed description of a preferred embodiment

Fig. 1 shows a flow diagram for processing interrupt requests of a number of external devices X, Y, Z. , , Each of the devices X, Y, Z. , , is connected to the interrupt controller, which the interrupt requests via a corresponding separate communication channel X, Y, Z,. , , treated.

In step 10, the device 10 outputs an interrupt request signal. The interrupt request signal of the device X is transmitted to the interrupt controller via the communication channel X. Within the same time slot or in subsequent time slots, the devices Y, Z,. , , via the corresponding communication channels Y, Z,. , , in steps 11 and 12 from further interrupt request signals.

All interrupt request signals are input to the interrupt controller. In step 13 , an interrupt request is detected when at least one of the interrupt request signals is received by the interrupt controller.

In response to detecting one or more of the interrupt requests from one or more of the X, Y, Z devices. , , the corresponding addresses of the devices are output in step 14 . For example, an interrupt request from one of the devices to the interrupt process controller can be signaled by raising a line associated with that device.

Without restricting generality, it is assumed below that the two devices X and Y issued interrupt request signals in steps 10 and 11 . As a result, the addresses of devices X and Y are output in step 14 .

In step 15 , the priorities of devices X and Y are read from a register file using the addresses of devices X and Y. Step 15 is preferably carried out by means of a state machine.

In step 16 , the state machine selects the device with the highest priority. In the example considered here, this is device X.

In step 17 , a memory location is selected that contains the address of an interrupt utility for handling the interrupt request from device X.

In parallel with steps 14 , 15 , 16 and 17 , an interrupt request signal is output in step 18 to the corresponding microprocessor. The microprocessor can be part of a microprocessor system and / or an electronic control unit, for example in a self-moving and / or non-stationary communication and / or data processing system.

In the example considered here, the processor has a contact pin for entering interrupt request signals. The interrupt signal generated in step 18 is applied to this contact pin.

In response to the receipt of the interrupt signal in step 18 , a routine for performing a read operation is called in step 19 in the processor. Using the read operation, the processor reads the location selected in step 17 to access the interrupt utility address to handle the interrupt request of the highest priority device selected in step 16 .

In step 20 , the processor executes the interrupt utility by accessing the address obtained in the read operation in step 19 .

From step 18 , control jumps back to step 13 to acquire further interrupt request signals. This can be done continuously when using height-controlled interruptions. If an interrupt signal is still present, steps 14 through 20 above are repeated until all interrupt request signals from devices X, Y, Z,. , , are deleted.

In the example considered here, the device X deletes it Interrupt request signal once their Interrupt request by performing the Interrupt utility was operated by the processor. The device interrupt request signal is Y. still active "high" to indicate that the device Y still serving their interrupt request waiting.

This is detected in step 13 , and steps 14 , 15 , 16 and 17 are carried out again so that device Y is selected as the device with the highest priority - the device X with the higher priority has already deleted its interrupt request signal. Since device X has deleted its interrupt request signal, the address of device X is no longer output in step 14 and device Y is now selected as the highest priority device in step 16 - provided that no other device with higher priority than device Y is meanwhile has issued an interrupt request signal.

Fig. 2 shows a corresponding block diagram of an interrupt controller.

The interrupt controller receives a number of parallel hardware inputs from a number of subsystems (cf. devices X, Y, Z, ... In FIG. 1).

In the example considered here, the input 30 of the interrupt controller has sixteen separate input pins which are connected to separate input lines. Each of these separate input lines is connected to a subsystem. In addition to receiving the interrupt request signals from the subsystems, input 30 is used for interrupt matching and / or classification and / or prefiltering.

The input 30 is connected to a module 31 . The module 31 is used to record and detect interrupts by detecting every change and / or transition on the 16 adapted and / or pre-filtered interrupt inputs of the interrupt controller (IPC), as they are output by the input 30 .

If a transition occurs, ie one or more of the input lines of input 30 go "high", this is detected by module 31 and the corresponding data are transmitted to state machine module 32 . The data transmitted from module 31 to state machine module 32 indicates the devices that issued an interrupt request. For example, module 31 may transmit the addresses of the corresponding devices and / or the addresses of the corresponding interrupt requests.

This data is entered into a state machine 33 , which works as an IPC controller. The state machine 33 is programmed using a register file 34 which contains the corresponding permanently stored standard program (firmware).

Upon receipt of data from the module 31 in the state machine 33, the state machine 33 performs an access operation to a register file 35th

Register file 35 contains a priority for each of the external devices and their corresponding interrupt requests. The state machine 33 reads the corresponding priorities using the address data, as will be provided by the module 31 . By comparing the priorities, the state machine 33 identifies the highest priority interrupt requests. The corresponding data is written by the state machine 33 into a pointer register 36 .

The pointer register 36 is coupled to a register file 37 . The output of the pointer register 36 determines the register of the register file 37 , which is output after a read request from the system interface 38 .

Each register of register file 37 contains an interrupt utility program address for handling an interrupt request from one of the subsystems / devices. The content of the pointer register 36 determines the selection of the register within the register file 37 and thus the selection of the appropriate interrupt utility.

Both register files, 35 and 37 , can be implemented using non-volatile memory devices to pre-program the corresponding data into the register files.

The module 31 also issues an interrupt signal to a module 39 . Module 39 is used to selectively mask interrupt requests. The module 39 inputs interrupt request signals, which are not masked, into the system interface 38 , which in turn outputs a corresponding interrupt request signal to a microprocessor.

When the microprocessor receives the interrupt request signal, it performs a read access operation on system interface 38 to read one of the registers of register file 37 . The content of this one register of the register file 37 is output from the register file 37 to the system interface 38 , from which the content is output to the microprocessor.

The register of register file 37 from which the data is output is determined by pointer register 36 so that the microprocessor obtains the address of the interrupt utility to handle the interrupt request of the subsystem / device with the highest priority.

In this way, the microprocessor starts this interrupt utility so that the interrupt request of the corresponding device is canceled by this device. This is noted by module 31 so that the content of pointer register 36 in state machine module 32 is changed accordingly to perform another interrupt utility to handle one of the currently activated interrupt requests.

According to a preferred embodiment of the invention, the register file 35 contains additional information in addition to the priorities of the interrupt requests. For example, each priority has a memory location assigned to it for storing additional data.

In one embodiment, the additional data is an indication of the length of time, e.g. B. in milliseconds or as clock cycles. In this case, the state machine 33 has an additional timer for each subsystem. When a subsystem makes an interrupt request, the associated timer starts up.

To determine the interrupt request with the highest priority, the state machine 33 reads both the priority of each interrupt request from the register file 35 and the corresponding additional data, which contain a time value in the example considered here. This is done by means of the address line 40 and the read / write control line 41 .

The state machine 33 determines the interrupt with the highest priority by taking into account the priorities and the time values obtained from the register file 35 for the activated interrupt requests.

In a first step, the priorities of the active interrupt requests are compared and the highest priority value is determined. The corresponding interrupt request is defined as the highest priority interrupt request, except when there is a lower priority interrupt request whose time value has been overtaken by the corresponding state machine 33 timer value associated with that lower priority request.

In the latter case, the lower priority request is defined as the highest priority request and corresponding data is provided to the pointer register 36 so that the microprocessor receives the address of the interrupt utility for handling the subsystem interrupt request as that given by the state machine 33 in the With regard to the priority values and the time values stored in the register file 35 was selected.

In another embodiment, the additional data stored in the register file 35 related to an interrupt request priority includes data indicating a maximum number of execution cycles performed by the higher priority processor to process interrupt requests. If the true number of execution cycles performed by the processor after a lower priority interrupt request increases and exceeds the number of execution cycles indicated by the data stored in register file 35 , the lower priority interrupt request becomes the state machine 33 defined as the highest priority interrupt request.

This avoids a situation in which Lower priority interrupt requests no longer are executed within a reasonable latency period, when interrupt requests of higher priority are ongoing available.

Claims (18)

1. An interrupt controller containing:
Parallel input means ( 30 ) for receiving first interrupt request signals;
Means ( 31 , 32 ) for outputting a second interrupt request signal in response to receiving at least one of the first interrupt request signals;
State machine means ( 33 , 34 , 35 , 36 ) for determining a priority for each of the first interrupt request signals;
Storage means ( 37 ) for storing addresses of interrupt service programs, each of the interrupt service programs being associated with one of the first interrupt request signals;
Means ( 36 ) for selecting one of the addresses based on the priority. 2. The interrupt controller of claim 1, wherein the parallel input means a number of separate Have connection channels, each of the separate Connection channels is designed so that it is one of the first interrupt request signals from one receives external device. 3. The interrupt controller according to claim 1 or 2, the means for adapting the interrupt and / or for Classification of the interrupt and / or for pre-filtering of the interrupt. 4. The interrupt controller according to claim 1, 2 or 3, the first interrupt request signals height-controlled interrupt request signals. The interrupt controller according to any of the preceding claims 1 to 4, further comprising means ( 31 ) for outputting data indicative of one or more of the first interrupt request signals from the parallel input means as an input to the state machine means were received. The interrupt controller according to any one of the preceding claims 1 to 5, wherein the state machine means comprises a register file ( 35 ) for storing a priority for each of the first interrupt request signals. The interrupt controller according to any one of the preceding claims 1 to 6, wherein the state machine means further comprises a pointer register ( 36 ) for selecting one of the addresses of the storage means. The interrupt controller according to any one of the preceding claims 1 to 7, further comprising microprocessor interface means ( 38 ) for outputting the second interrupt request signal to a microprocessor system and receiving a read command from the microprocessor system for reading the selected address from the memory means and for Output of the selected address from the storage means to the microprocessor system. The interrupt controller according to any one of the preceding claims 1 to 8, further comprising means ( 39 ) for masking second interrupt request signals. 10. The interrupt controller according to any of the preceding claims 6 to 9, wherein the register file an additional data value for each of the priorities as an additional selection criterion for the State machine means for determining the break with the highest priority. 11. A method of communicating first interrupt request signals from a plurality of external devices to a microprocessor system, the method comprising the steps of: - detecting at least one of the first interrupt request signals; Determining a priority for each of the first interrupt request signals; - selecting one of the first interrupt request signals with the highest priority; - selecting a memory location to activate the output of an address of an interrupt utility for the selected first interrupt request signal; - Issuing a second interrupt request signal to the microprocessor system; Reading the selected memory location by the microprocessor system; - Execution of the interrupt utility by the microprocessor system. 12. The method of claim 11, wherein the first Interrupt request signals height controlled Signals are. 13. The method of claim 11 or 12, further comprising Output a subsequent second Interrupt request signal to process a another of the first interrupt request signals includes. 14. The method of claim 11, 12 or 13, wherein the Steps of determining a priority, selecting one the first interrupt request signals and selection a storage location from a state machine be carried out. 15. The method according to any of the foregoing Claims 11 to 14, further comprising a step of Adapt the interrupt and / or to classify the Interrupts and / or for pre-filtering for the first Interrupt request signals. 16. The method according to any of the foregoing Claims 11 to 15, further comprising a step of Masking second interrupt request signals having. 17. The method according to any of the foregoing Claims 11 to 16, further testing a additional selection criteria with regard to each activated interrupt request and selection of Interrupt request that meets the criterion as the highest priority interrupt request corresponds, the selection criterion preferably a Time value or a number of execution cycles. 18. An electronic system that is a microprocessor system and an interrupt controller according to any one of the preceding claims 11 to 17, wherein the Microprocessor system to the interrupt controller for Receiving the second interrupt request signals and coupled to read the selected memory locations is.