DE10229066A1 - Production of a floating gate structure comprises applying a first dielectric layer on semiconductor material, applying a first polysilicon layer, applying a second dielectric layer and applying a second polysilicon layer - Google Patents
Production of a floating gate structure comprises applying a first dielectric layer on semiconductor material, applying a first polysilicon layer, applying a second dielectric layer and applying a second polysilicon layer Download PDFInfo
- Publication number
- DE10229066A1 DE10229066A1 DE2002129066 DE10229066A DE10229066A1 DE 10229066 A1 DE10229066 A1 DE 10229066A1 DE 2002129066 DE2002129066 DE 2002129066 DE 10229066 A DE10229066 A DE 10229066A DE 10229066 A1 DE10229066 A1 DE 10229066A1
- Authority
- DE
- Germany
- Prior art keywords
- polysilicon layer
- layer
- applying
- polysilicon
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 239000000463 material Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 16
- 230000015654 memory Effects 0.000 claims description 10
- 230000000873 masking effect Effects 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 3
- 230000008569 process Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000011324 bead Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000003518 caustics Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Die vorliegende Erfindung betrifft ein Verfahren zur Oberflächenvergrößerung einer Floating-Gate-Struktur bei nichtflüchtigen Halbleiterspeichern.The present invention relates to a method for increasing the surface area of a Floating gate structure in non-volatile semiconductor memories.
Bei Halbleiterspeichern mit Flash-Speicherzellen sind in jeder Speicherzelle eine nicht auf definiertes elektrisches Potential gelegte Floating-Gate-Elektrode und eine elektrisch angeschlossene Control-Gate-Elektrode vorhanden. Die Floating-Gate-Elektrode ist sowohl zu dem darunter vorhandenen Halbleitermaterial als auch zu der darüber angeordneten Control-Gate-Elektrode durch dielektrische Schichten elektrisch isoliert. Für die angestrebte Funktionalität muss zwischen der Control-Gate-Elektrode und der Floating-Gate-Elektrode eine gewisse Mindestkapazität vorhanden sein, um eine ausreichend große Kopplung zu gewährleisten. Eine weitere Miniaturisierung derartiger Halbleiterspeicher stößt an eine Grenze, wenn das Problem auftritt, dass die Kapazität zwischen der Control-Gate-Elektrode und der Floating-Gate-Elektrode den geforderten Mindestwert nicht aufweisen kann, weil die zur Verfügung stehende Fläche zu gering ist. Als Zwischendielektrikum wird bisher üblicherweise eine Oxid-Nitrid-Oxid-Schichtfolge eingesetzt. Der Ersatz einer solchen ONO-Schicht durch dielektrisches Material einer größeren relativen Dielektrizitätszahl ist technologisch schwierig, da eine ausreichende Prozesskompatibilität gewährleistet sein muss. Eine Flächenvergrößerung würde beim aktuellen Stand der Technik die erforderliche Chipfläche deutlich vergrößern und eine aufwendige Maskentechnik erfordern.For semiconductor memories with flash memory cells are not defined electrical in each memory cell Floating gate electrode and an electrically connected one Control gate electrode available. The floating gate electrode is both to the existing semiconductor material and to the one above it Control gate electrode electrically through dielectric layers isolated. For the desired functionality must be between the control gate electrode and the floating gate electrode certain minimum capacity be available to ensure a sufficiently large coupling. A further miniaturization of such semiconductor memories is encountering one Limit when the problem occurs that the capacity between the control gate electrode and the floating gate electrode the required May not have minimum value because the available area is too low. So far, one is usually used as an intermediate dielectric Oxide-nitride-oxide layer sequence used. The replacement of such an ONO layer with dielectric Material of a larger relative permittivity is technologically difficult because it ensures sufficient process compatibility have to be. An increase in area would state of the art the required chip area clearly enlarge and require a complex mask technique.
Aufgabe der vorliegenden Erfindung ist es, anzugeben, wie ein Flash-Halbleiterspeicher mit Floating-Gate-Elektrode so hergestellt werden kann, dass trotz einer Verkleinerung der Ab messungen eine ausreichend große Kapazität zwischen der Control-Gate-Elektrode und der Floating-Gate-Elektrode erreicht werden kann.Object of the present invention is to specify how a flash semiconductor memory with a floating gate can be manufactured in such a way that despite a reduction in dimensions, big enough capacity reached between the control gate electrode and the floating gate electrode can be.
Diese Aufgabe wird mit dem Verfahren zur Herstellung einer Floating-Gate-Struktur für nichtflüchtige Halbleiterspeicher mit den Merkmalen des Anspruchs 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.This task is done with the procedure for producing a floating gate structure for non-volatile semiconductor memories solved the features of claim 1. Refinements result themselves from the dependent Claims.
Bei dem Verfahren wird ein Anteil der Oberfläche der für die Floating-Gate-Elektrode vorgesehenen ersten Polysiliziumschicht vor dem Aufbringen des Zwischendielektrikums mit einer diese Oberfläche vergrößernden Erhebung versehen, indem unter Verwendung einer Spacer-Maske eine zunächst dicker aufgebrachte Polysiliziumschicht lokal unterschiedlich weit auf die vorgesehene Dicke der ersten Polysiliziumschicht rückgeätzt wird. Diese Erhebung kann insbesondere durch einen Wulst an den Flanken eines in die erste Polysiliziumschicht geätzten Grabens gebildet werden. Als Zwischendielektrikum kann eine ONO-Schicht aufgebracht werden, auf die die für die Control-Gate-Elektrode vorgesehene zweite Polysiliziumschicht aufgebracht wird. Die übrigen Verfahrensschritte entsprechen der Herstellung herkömmlicher Flash-Speicherzellen und sind an sich bekannt.In the process, a portion the surface the for the first polysilicon layer provided for the floating gate electrode before the application of the intermediate dielectric with an enlarging this surface Provide elevation by using a spacer mask first thicker applied polysilicon layer locally different distances is etched back to the intended thickness of the first polysilicon layer. This elevation can be caused in particular by a bead on the flanks of a trench etched into the first polysilicon layer. An ONO layer can be applied as the intermediate dielectric, on those for the control gate electrode provided second polysilicon layer is applied. The remaining Process steps correspond to the production of conventional ones Flash memory cells and are known per se.
Es folgt eine genauere Beschreibung
eines Beispiels des Verfahrens anhand der
In der
Ausgehend von der so erreichten Struktur wird,
wie in der
In der
In der
Anschließend wird gemäß der
Bei diesem Ausführungsbeispiel des Verfahrens
erhält
man auf Grund des vorhandenen STI-Bereiches
Seitlich angrenzend an eine jeweilige Transistorstruktur einer jeweiligen nach diesem Verfahren hergestellten Speicherzelle befindet sich daher eine Kondensatorstruktur einer ausreichend hohen Kapazität. Mit dem angegebenen Herstellungsverfahren ergibt sich außerdem auf einfache Weise eine elektrische Isolation zwischen den einzelnen Speicherzellen. Vorteile dieses Verfahrens sind insbesondere die einfache Prozessführung ohne zusätzliche Maske und ohne Veränderung herkömmlicher Masken; auf die Verwendung spezieller dielektrischer Materialien kann verzichtet werden.Laterally adjacent to a respective one Transistor structure of a respective manufactured by this method There is therefore a capacitor structure of a memory cell sufficiently high capacity. Using the specified manufacturing process also results in simple way of electrical isolation between each Memory cells. The advantages of this method are particularly simple Litigation without additional Mask and without change conventional masks; on the use of special dielectric materials to be dispensed with.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2002129066 DE10229066A1 (en) | 2002-06-28 | 2002-06-28 | Production of a floating gate structure comprises applying a first dielectric layer on semiconductor material, applying a first polysilicon layer, applying a second dielectric layer and applying a second polysilicon layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2002129066 DE10229066A1 (en) | 2002-06-28 | 2002-06-28 | Production of a floating gate structure comprises applying a first dielectric layer on semiconductor material, applying a first polysilicon layer, applying a second dielectric layer and applying a second polysilicon layer |
Publications (1)
Publication Number | Publication Date |
---|---|
DE10229066A1 true DE10229066A1 (en) | 2004-01-29 |
Family
ID=29795946
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2002129066 Ceased DE10229066A1 (en) | 2002-06-28 | 2002-06-28 | Production of a floating gate structure comprises applying a first dielectric layer on semiconductor material, applying a first polysilicon layer, applying a second dielectric layer and applying a second polysilicon layer |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE10229066A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7129540B2 (en) * | 2003-02-14 | 2006-10-31 | Infineon Technologies Ag | Semiconductor circuit arrangement with trench isolation and fabrication method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323085B1 (en) * | 1999-04-05 | 2001-11-27 | Micron Technology, Inc. | High coupling split-gate transistor and method for its formation |
US6326263B1 (en) * | 2000-08-11 | 2001-12-04 | United Microelectronics Corp. | Method of fabricating a flash memory cell |
-
2002
- 2002-06-28 DE DE2002129066 patent/DE10229066A1/en not_active Ceased
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323085B1 (en) * | 1999-04-05 | 2001-11-27 | Micron Technology, Inc. | High coupling split-gate transistor and method for its formation |
US6326263B1 (en) * | 2000-08-11 | 2001-12-04 | United Microelectronics Corp. | Method of fabricating a flash memory cell |
Non-Patent Citations (1)
Title |
---|
US 2002/0 70 407 A1 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7129540B2 (en) * | 2003-02-14 | 2006-10-31 | Infineon Technologies Ag | Semiconductor circuit arrangement with trench isolation and fabrication method |
US7368341B2 (en) | 2003-02-14 | 2008-05-06 | Infineon Technologies Ag | Semiconductor circuit arrangement with trench isolation and fabrication method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE19612948B4 (en) | A method of manufacturing a semiconductor device with recessed channel structure | |
DE102005037986B4 (en) | Method for producing a non-volatile memory module | |
DE102005061199B4 (en) | Method for producing a memory module | |
DE4220497B4 (en) | Semiconductor memory device and method for its production | |
DE19747776C2 (en) | Flash semiconductor memory with stack gate and method for its production | |
DE19533165C2 (en) | Method for producing a non-volatile memory cell with a stack gate electrode in a cell-shaped oxidation region | |
DE102005025951B4 (en) | A method of manufacturing a multilayer gate stack structure comprising a metal layer and gate stack structure for an FET device | |
DE10355575B4 (en) | A method of making sidewall spacers for a circuit element by increasing etch selectivity | |
DE10030308A1 (en) | Production of a contact pin of a semiconductor element comprises using a gas mixture containing sulfur hexafluoride, trifluoromethane and carbon tetrafluoride in the back etching of the polysilicon layer | |
DE4341698B4 (en) | Semiconductor component with a storage capacitor and method for its production | |
DE10228565A1 (en) | Non-volatile memory device and manufacturing method thereof | |
DE10128718B4 (en) | Trench capacitor of a DRAM memory cell with metallic collarbear and non-metallic conduction bridge to the select transistor | |
DE102006049613B4 (en) | A method of forming row select transistors of a NAND type EEPROM device and devices formed therewith | |
DE102004030172A1 (en) | Manufacture of flash memory device e.g. NAND type flash memory device, involves etching conductive layers and dielectric layers in single etch apparatus using hard mask layer as mask, where a control gate and a floating gate are formed | |
DE102004038874B4 (en) | 1-bit SONOS memory cell and manufacturing process | |
DE4007604A1 (en) | SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF | |
DE10158798A1 (en) | Capacitor and method of making a capacitor | |
DE102005022574A1 (en) | Semiconductor memory device with isolation trench structure and associated manufacturing method | |
DE10120302B4 (en) | Method for producing a semiconductor component | |
DE4447149A1 (en) | Completely planar, concave MOS transistor for VLSI circuit | |
DE102004060668A1 (en) | Semiconductor device, e.g. flash memory device, comprises barrier metal layer formed between metal layer and interlayer insulating film and including tungsten nitride or titanium silicon nitride | |
DE10229065A1 (en) | Method for producing an NROM memory cell array | |
DE10303926B4 (en) | Improved technique for making contacts for buried doped regions in a semiconductor device | |
DE10226964A1 (en) | Method for manufacturing an NROM memory cell arrangement | |
DE10242145B4 (en) | Semiconductor device with local interconnect layer and manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8131 | Rejection |