DE102023204477A1 - Microelectromechanical system (MEMS) - Google Patents

Abstract

A microelectromechanical system (MEMS) for a device with one or more micromirrors (20) comprises a large number of integrated circuits (ICs; 64, 65, 68) for actuator electronics and/or sensor electronics and/or control electronics, the integrated circuits (64 , 65, 68) are arranged stacked.

Description

The invention relates to a microelectromechanical system (MEMS), in particular a MEMS for a device with one or more optical components, in particular in the form of a micromirror. The invention further relates to a micromirror and an optical component which comprises an array of a plurality of micromirrors. The invention further relates to illumination optics and an illumination system for a lithography system, to projection optics for a lithography system and to a lithography system. Finally, the invention relates to a method for producing an optical component.

The constantly increasing demands of the semiconductor market require the further development and continuous improvement of lithography systems, in particular the lighting optics for the lithography systems. Such lighting optics can consist of a facet module with several hundred closely stacked mirror elements, each of which can be tilted in two tilting axes.

Such modules with a large number of individually controllable micromirrors are from WO 2012/130 768 A2 and the WO 2015/028 450 A1 known.

An electronic unit having a first substrate, a second substrate and at least one spacer substrate disposed between the first and second substrates is provided US 10,515,886 B2 known.

The US 2022 / 0 004 107 A1 relates to an optical arrangement and lithography system.

The DE 10 2011 006 100 A1 concerns a mirror array.

The DE 10 2020 120 906 A1 relates to a method for determining a torsion angle of a mirror body of a MEMS device.

The US 2019 / 0 018 114 A1 concerns a chip-scale lidar with a single Mems scanner in a compact optical package.

It is the object of the present invention to improve a microelectromechanical system (MEMS) for a device which comprises one or more optical components, in particular one or more micromirrors, in particular one or more circular gimbal mirrors.

This task is solved by the subject matter of claim 1.

According to one aspect of the invention, the micro-electromechanical system (MEMS) comprises a plurality of integrated circuits (ICs) of different types and/or with different types of silicon vias (TSVs), the ICs being arranged in a stacked manner.

The ICs can in particular include actuator electronics and/or sensor electronics and/or control electronics.

The actuator electronics can in particular consist of or contain amplifiers and/or drivers.

The actuator electronics can in particular comprise or consist of high-voltage electronics (HV), in particular for voltages of at least 50 V, in particular at least 100 V, in particular at least 140 V, in particular at least 180 V, in particular at least 200 V.

The actuator electronics can in particular include or consist of high-voltage ASICs.

The sensor electronics can in particular include or consist of analog front-end electronics.

The sensor electronics can in particular comprise or consist of low-voltage electronics (LV), in particular for voltages of at most 50 V, in particular at most 36 V.

The sensor electronics can in particular include or consist of ASICs with low voltage (NV).

The controller can e.g. B. Provide a closed loop, feedback or feedforward function, can store calibration data and recalculate the control based on this data and several acquired external or internal parameters.

The ICs can also be referred to as chips, dies or wafers, especially as chips with ICs, dies with ICs or wafers with ICs.

The invention is described below with regard to a displaceable micromirror. This should not be construed as limiting. The micromirror serves primarily as an explicit example of an optical component. Instead of a microphone mirror, the invention can be used advantageously with any other movable optical component.

The MEMS can be used particularly advantageously with a circular gimbal mirror (CCM).

By arranging multiple integrated circuits in a stacked form, the available space for electronic circuits within a given footprint of a micromirror is increased. This enables the generation of a larger drive voltage for an actuator for displacing a micromirror and/or improving the electronics for detecting the displacement of a micromirror and/or improving the electronics of a control logic device.

In addition, heat dissipation from a micromirror can be improved.

Advantageously, the electronic circuits of the control devices and/or the sensor devices and/or the control logic devices for a single micro-minus mirror are arranged within the base area of such a micro-mirror. This can meet the need for individual positioning of each mirror and improve the dense population of the array with mirrors.

In particular, a higher drive voltage or a stronger force/torque for displacing a micro light mirror can be achieved through a stacked arrangement of integrated circuits. The integrated circuits can be arranged three-dimensionally or stacked vertically. In particular, they can be arranged in several layers behind the micromirror. The individual layers can be arranged obliquely, in particular perpendicularly, to a surface normal of the micromirror. The dies can in particular be arranged so that their surface runs parallel to that of the mirror.

According to the invention, a strong force for tilting a mirror can be generated even though the space below the mirror is very limited.

In particular, high drive voltages of over 100 V, in particular over 140 V, in particular over 180 V can be generated to move a mirror, although the space below the mirror in which the electronic components are to be arranged to generate and/or amplify the drive voltage, in particular Cross-sectional area is very limited.

In particular, the stacked arrangement of the ICs makes it possible to generate and/or control the necessary drive voltages on the mirror base.

In addition, the sensor signals can be amplified and read as close as possible to the transducer to convert the movement into an electrical signal.

In addition, a control loop can be provided between the sensors and the actuators to keep the alignment of the mirror stable.

It was recognized that higher drive voltages or more power and thus the successful realization of 2D tiltable mirrors for applications with high thermal loads, such as EUV systems, through extended 3D or vertical stacking of the front-end (FE) drivers - and/or FE sensor electronics and/or the back-end (BE) control loop electronics can be achieved.

A stacked arrangement can in particular mean that at least two integrated circuits are arranged in different levels, in particular in parallel levels. This does not exclude the possibility of several integrated circuits being arranged in a common plane.

The microelectromechanical system can comprise at least two, in particular at least three, in particular at least four, in particular at least six, in particular at least 12 separate integrated circuits.

The integrated circuits can be arranged in at least two, in particular at least three, in particular at least four, in particular at least six different layers or levels. A large number of levels allows for a larger number of separate integrated circuits.

The integrated circuits may be application-specific integrated circuits (ASICs).

The integrated circuits may consist of single integrated circuits and/or double-sided integrated circuits. This refers to the arrangement of electronic circuits on the integrated circuits.

The available base area for arranging the integrated circuits can be smaller than 1 cm × 1 cm, in particular smaller than 0.5 cm × 0.5 cm, in particular smaller than 0.3 cm × 0.3 cm, in particular be smaller than 0.2 cm × 0.2 cm, in particular at most 1 mm ² , in particular at most 0.65 mm ² .

The available base area can be given by the dimensions, in particular by a cross-sectional area, of a micromirror, in particular its substrate or its reflection surface.

The integrated circuits can all be at most as large as the available floor space. In particular, they can be at most half the size of the available floor space. The ratio between the available floor space and the size of an individual integrated circuit can be at least 3, in particular at least 4, in particular at least 6.

It is also possible for one or more ICs to extend over the available footprint, in particular over the available footprint defined by a micromirror. One or more ICs can in particular be larger than the available base area, in particular larger than the cross-sectional area of the micromirror, in particular its substrate, or larger than its reflection surface. This can be particularly useful for electronic circuits that drive more than a single micromirror. For example, the ICs can also be up to twice the size of the footprint, since one IC can drive 2 mirrors or 2x1 mirrors, or up to four times the size, since one IC can drive 4 mirrors, especially 2x2 mirrors, or up to 6 mirrors, especially 3x2 mirrors, or up to 9 mirrors, especially 3x3 mirrors, or up to 16 mirrors, especially 4x4 mirrors or more.

According to one aspect of the invention, the MEMS includes a suspension for a micromirror. Preferably, the suspension is made of a material with high thermal conductivity λ such as crystalline silicon, aluminum, gold or copper. The thermal conductivity of the material from which the suspension is made can be at least 140 W/m.K, in particular at least 200 W/m.K, in particular at least 300 W/m.K and in particular at least 380 W/m.K.

The suspension can include or consist of one or more springs, in particular torsion springs or bends.

The suspension can be designed as a bending element or joint, in particular as a cardan joint. The mirrors are accordingly also referred to as gimbal mirrors.

According to one aspect of the invention, the electrical connections between different ICs and/or between an IC and a substrate for suspending one or more micromirrors include through silicon vias (TSVs) and/or wire bonds and/or wire and bump connections . Different ICs can also be electrically connected by stacking bonded dies. Different ICs can also be electrically connected through stacked, electrically connected dies.

In particular, silicon vias (TSVs) can be made from a material with high thermal conductivity, such as the suspension material mentioned above, e.g. B. Cu, Si/Poly-Si, Al, Au. TSVs can in particular be made from copper or poly-Si.

Copper TSVs are particularly good thermal and electrical conductors, while poly-Si TSVs conduct electrical signals well and heat moderately well. On the other hand, poly-Si TSVs enable later high-temperature processes, for example for the implantation and annealing of CMOS circuits. The ICs can be arranged as a three-dimensional tiered stack. The stacking direction can in particular be perpendicular to the surface of the IC chips.

According to one aspect of the invention, the MEMS includes one or more interposer chips. Such interposer chips can only have electrical and/or thermal connections, but no active electronic circuit. An interposer chip can in particular be designed as a wafer with vertical interconnections. The vertical interconnections can be made by TSVs.

The interposer chips can in particular include TSVs of various types. Please refer to the description above for details.

In particular, it is possible that one or more interposer chips can include TSVs of different types. In particular, it is also possible for one or more interposer chips to only include TSVs of a single type.

In particular, electrical and/or thermal connections from and/or to the optical component can be partially or completely guaranteed by the TSVs. The TSVs can in particular form a bridge between the actuator electronics and/or sensor electronics, the optical component and an interface for connection to an external device and/or source. The electrical power supply and possible digital and/or analog input and/or output signals can be sent from/to an electrical connection on the rear through the controller chips, then through the FE chips and then through the body/substrate of the optical component to the sensors and actuators and back. Thermal paths can lead from the optical element through its substrate, through the FE, through the control unit to a heat sink arranged on the rear.

The interposer chips may also contain integrated electronic circuits on one or both sides. It is also possible to use hybrid electronic chips containing single-sided or double-sided electronic circuits and TSVs on a die. The TSVs can in particular have the function of conducting electrical signals and/or heat.

The electronic components, especially the ICs, can be arranged in a cascade.

The electronic components, in particular the ICs, can be partially or completely electrically and/or thermally connected to a mirror element by interposer chips with vertical interconnections (TSVs) and/or via bonds and/or via and bump connections.

According to one aspect of the invention, one or more sensor readout ASICs and/or one or more actuator drivers and/or one or more control logic devices are included on different integrated circuits, these different integrated circuits being arranged in a stacked manner.

This allows the size of the individual ICs to be reduced.

According to one aspect of the invention, the ICs for the actuator electronics can provide driver signals of at least 100 V, in particular of at least 140 V, in particular of at least 170 V, in particular of at least 200 V.

Two driver signals can be provided for each degree of freedom. The optical component can be tilted about two independent tilt axes.

The ICs for the actuator electronics can each have a cross-sectional area of at most 4 mm ² , in particular at most 2.5 mm ² , in particular at most 1 mm ² , in particular at most 0.7 mm ² .

The ICs for the actuator electronics can in particular be amplifier circuits and/or driver circuits.

The ICs for the actuator electronics can be electrically connected to an external voltage generator.

One aspect of the invention is that the MEMS comprises a low-temperature single-cement ceramic (LTCC) carrier with integrated ICs. This technology enables robust assembly and packaging of electronic components. The ceramic components are manufactured using a multi-layer process. The starting material is raw composite tapes, which consist of ceramic particles mixed with polymeric binders. The bands are flexible and can be edited, e.g. B. by cutting, milling, punching and embossing. Metal structures can be added to the layers, usually done through via filling and screen printing. Cavities are reinforced. The individual tapes are then bonded together in a lamination process before the components are fired in an oven, where the polymer portion of the tape burns and the ceramic particles sinter together, creating a hard and dense ceramic component.

The LTCC carrier can serve as a support and/or contribute to electrical and/or thermal conductivity.

The LTCC carrier can consist of different layers, in particular layers with different types of ICs. For details on the various ICs, please refer to the corresponding description.

Different LTCC layers can be arranged horizontally shifted, in particular in such a way that the ICs installed in adjacent layers only partially overlap at most in a vertical projection. In particular, different LTCC layers can be arranged horizontally shifted so that the ICs installed in adjacent layers do not overlap in a vertical projection.

The ICs can be bonded or glued to the respective layers of the LTCC.

According to one aspect of the invention, the MEMS may comprise an actuator and/or a sensor with a comb structure, in particular with a radial comb structure. Details of such a comb structure can be found in the DE 10 2015 204 874 A1 referred to, the content of which is hereby incorporated in its entirety into the present invention.

According to one aspect of the invention, the MEMS may include a heat sink. The cooling core per is preferably in thermal connection with the micromirror.

The heat sink can be arranged on a side that is opposite a reflection surface of the micromirrors with respect to the electronic components. It can also be arranged between different electronic components, in particular between different ICs.

According to a further aspect, the chips, in particular the front-end electronics chip and/or the controller electronics chip, can be made very thin. In particular, they can have a thickness of at most 100 μm, in particular at most 80 μm, in particular at most 60 μm. For example, they can have a thickness in the range of 50 µm to 100 µm. This can be achieved in particular by varying the standard wafer thickness, e.g. B. 525 µm for a wafer with a 100 mm diameter up to 775 µm for a wafer with a 300 mm diameter. Thinning can be done by grinding and optional subsequent polishing.

Thinned wafers are very flexible, similar to thin sheets, and therefore easily conform to the surfaces to which they are bonded. The substrates that contain the front-end electronics and/or the controller electronics can in particular be flexible. In particular, they can be reversibly deformable.

According to a further aspect, adjacent substrates, which are arranged in particular between the micromirrors and the support structure, can be connected by full-surface mechanical/thermal connections; For obvious reasons, electrical connections are usually not over the entire surface. This means that the substrates are bonded to one another over a wide, flat, essentially uninterrupted surface.

• - eine oder mehrere Verbindungsschichten, die insbesondere auf der Vorderseite eines Substrats angeordnet sind,
• - eine oder mehrere Umverteilungsschichten, die insbesondere auf der Rückseite eines Substrats angeordnet sind,
• - eine oder mehrere elektronische Bauelementeschichten, insbesondere mit integrierten Schaltkreisen,
• - mindestens eine Bonding-Interface-Schicht, insbesondere auf seiner Vorderseite und/oder auf seiner Rückseite.

This allows the heat transfer between adjacent substrates to be significantly improved. One or more, in particular all, of the substrates between the mirrors and the support structure can have a selection of one or more of the following layers:

• - one or more connecting layers, which are arranged in particular on the front side of a substrate,
• - one or more redistribution layers, which are arranged in particular on the back of a substrate,
• - one or more electronic component layers, in particular with integrated circuits,
• - at least one bonding interface layer, in particular on its front and/or on its back.

The “front” is the side on which the component layer is located.

The back is the side on which the wafers are processed.

The large-area thermal connection between adjacent substrates greatly reduces the vertical thermal resistance. In the case of a solder bump connection, the thermal resistance across the bonding layer can be between 49 mK/(Wcm ² ) and 280 mK/(Wcm ² ) below the following assumed typical values: The bump height is between 50 µm and 1000 µm , the thermal conductivity of the solder is between 50 W/(m K) and 70 W/(m K), the thermal conductivity of the epoxy filler material is between 0.3 W/(m K) and 0.7 W/(m K) and the surface coverage of the solder bump is between 0.2 and 0.5. This reduces to practically zero, which in practice means several mK/(Wcm ² ).

In addition, the thermal resistance can be kept very homogeneous over the lateral extent of the substrates, since a reduction in the variation of the absolute thermal resistance by the same order of magnitude can be expected.

The thermal resistance can vary across the bonding layer by a maximum of a factor of 6, in particular a maximum of a factor of 4, in particular a maximum of a factor of 2.

A further object of the invention is to improve a micromirror and/or a micromirror array and/or an optical component with a micromirror array.

This task is solved by a micromirror, a micromirror array and an optical component with a micromirror array with a MEMS according to the above description.

In particular, the MEMS can be arranged completely within the footprint of a single mirror substrate.

The MEMS can also be connected into an array of, for example, 2x2, 2x3, 3x3, 4x4 or more mirrors.

The MEMS can have a maximum cross-sectional area of at most 1 cm ² , in particular 0.1 cm ² , in particular at most 1 mm ² .

The integrated circuits can include front-end ASICs with a total size of less than 9 mm ² , in particular less than 5 mm ² , in particular less than 3 mm ² , in particular less than 1 mm ² .

The reflection surface of the mirror substrate may have an EUV reflection coating. The EUV reflection coating can be designed as a Si-Mo multilayer structure.

The micromirror can have a tilt range of at least 50 mrad, in particular of at least 70 mrad, in particular of at least 100 mrad, in particular of at least 120 mrad. The tilting range can be a maximum of 500 mrad.

The tilting accuracy of the micromirror can be better than 100 µrad, in particular better than 50 µrad, in particular better than 30 µrad and in particular better than 10 µrad.

The micromirror can include one or more actuators, in particular electrostatic actuators. The actuators can in particular comprise comb structures, in particular radial comb structures.

The micromirror can be suspended via a gimbal suspension, in particular via a cardan joint. For details see the DE 10 2015 204 874 A1 referred.

Micromirrors with a radial electrode structure and a gimbal are also called circular gimbal mirrors (CCM).

The actuators are preferably made from piezo ceramics. The actuators are preferably designed as electrostatic combs. These can also be made of piezo ceramics.

The micromirror can contain one or more sensors.

The sensors can detect the displacement, in particular the tilting, of the micromirror with an accuracy of better than 100 µrad, in particular better than 50 µrad, in particular better than 30 µrad, in particular even better than 10 µrad.

The sensors can be designed as electrostatic combs or as piezoresistive sensors.

The MEMS can advantageously include a temperature measurement with an accuracy in the mK range.

Preferably, the mirrors are designed so that they are suitable for use in a low-pressure environment, in particular in a vacuum environment, in particular in an environment with a remaining partial pressure of hydrogen of at most a few Pascals, in particular at most 3 Pa.

The micromirror can in particular be designed so that it is suitable for an ionized environment, in particular for an EUV environment.

The aforementioned properties apply to a single micromirror or, in the case of a mirror array, to each of the micromirrors of such an array.

An optical component that includes such an array of micromirrors can be used as a facet mirror of an illumination optics for a lithography system. It can be used in particular as a field facet mirror or as a pupil facet mirror of such lighting optics. Such an optical component can also be used as a condenser mirror.

A further object of the invention is to improve an illumination optics for a lithography system and an illumination system for a lithography system or a projection optics for a lithography system and a lithography system with such illumination optics and/or such projection optics.

These tasks are solved by appropriate lighting optics, lighting systems, projection optics or lithography systems, which include one or more optical components according to the previous description.

The lighting optics offer flexible lighting settings. In particular, it can provide a small pupil filling ratio.

The pupil filling ratio can be at most 50%, in particular less than 25%, in particular less than 10%, in particular less than 5%.

The projection optics can in particular have an object-side numerical aperture of at least 0.3, in particular at least 0.5. This allows a high resolution of the projection optics to be achieved.

Another object of the present invention is to improve a method for producing a MEMS for an optical component.

• Bereitstellen einer Vielzahl von separaten integrierten Schaltkreisen (ICs) oder Chips,
• Anordnen der integrierten Schaltkreise in einer gestapelten Form,
• wobei mindestens zwei unterschiedliche integrierte Schaltkreise mit unterschiedlichen Technologien hergestellt oder bearbeitet werden und/oder wobei mindestens zwei verschiedene integrierte Schaltkreise TSVs unterschiedlichen Typs aufweisen.

This task is accomplished through a process that includes the following steps:

• Providing a variety of separate integrated circuits (ICs) or chips,
• Arranging the integrated circuits in a stacked form,
• wherein at least two different integrated circuits are manufactured or processed using different technologies and/or at least two different integrated circuits have TSVs of different types.

At least two different chips can be manufactured or processed in different temperature ranges.

In particular, it is possible to process at least one chip in a high-temperature process, in particular at a temperature of at least 400 ° C, in particular at a temperature of at least 500 ° C, in particular at a temperature of at least 700 ° C, in particular at a temperature of at least 900°C.

It is in particular possible to process at least one chip in a low-temperature process, in particular at a temperature of at most 400 ° C, in particular at a temperature of at most 350 ° C, in particular at a temperature of at most 300 ° C, in particular at a temperature of at most 250°C.

At least two different ICs can contain TSVs of different types, in particular with different functions and/or made of different materials.

• - TSVs, die nur als thermisch leitende Strukturen dienen,
• - TSVs, die als thermisch leitende Strukturen und zur Übertragung von NV-(digitalen) Signalen dienen,
• - TSVs, die als thermisch leitende Strukturen und zur Übertragung von HV-(Analog-/Treiber-)Signalen dienen,
• - TSVs, die nur zur Übertragung von NV-(digitalen) Signalen dienen und
• - TSVs, die nur zur Übertragung von HV-(Analog-/Treiber-)Signalen dienen.

The TSVs can in particular fulfill at least two of the following functions:

• - TSVs that only serve as thermally conductive structures,
• - TSVs, which serve as thermally conductive structures and for transmitting LV (digital) signals,
• - TSVs, which serve as thermally conductive structures and for transmitting HV (analog/driver) signals,
• - TSVs, which are only used to transmit NV (digital) signals and
• - TSVs that are only used to transmit HV (analog/driver) signals.

• 1 eine schematische Darstellung einer Projektionsbelichtungsanlage und ihrer Bestandteile,
• 2 eine schematische Darstellung eines optischen Bauteils mit einer Aktorvorrichtung und einer Sensorvorrichtung,
• 3 eine alternative Darstellung des optischen Bauteils gemäß 2, bei der die Spiegelplatte mit den darauf angeordneten Gegenelektroden oder Abschirmelementen zur Seite geklappt ist,
• 4 schematisch einen Querschnitt durch einen Mikrospiegel mit einer gestapelten Anordnung von elektronischen Bauteilen,
• 5 schematisch einen Querschnitt durch einen Mikrospiegel mit einer weiteren gestapelten Anordnung von elektronischen Bauteilen,
• 6 schematisch einen Querschnitt durch einen Mikrospiegel mit noch einer weiteren gestapelten Anordnung von elektronischen Bauteilen,
• 7 schematisch einen Querschnitt durch einen Mikrospiegel mit einer weiteren gestapelten Anordnung von elektronischen Bauteilen,
• 8A bis 8G schematisch die Bearbeitungsschritte zur Herstellung eines LTCC-Trägers mit eingebauten Chips,
• 9 schematisch einen Querschnitt durch einen Spiegel, der einen Teil des Signalflusses auf dem Array abbildet,
• 10 schematisch einen Querschnitt durch ein Spiegel-Array, der einige Merkmale der 3D-Architektur der Elektronik veranschaulicht,
• 11A bis 11G schematisch einen Fertigungsablauf für ein elektronisches Bauteil, bei dem zunächst eine Silizium-Durchkontaktierung und dann ASICs erzeugt werden,
• 12A bis 12G schematisch einen Fertigungsablauf für ein elektronisches Bauteil, bei dem zunächst ein ASIC bearbeitet wird und dann Silizium-Durchkontaktierungen erzeugt werden,
• 13A bis 13K schematisch einen Prozessablauf für die Erstellung einer kombinierten Architektur mit ASICs, Poly-Si-Silizium-Durchkontaktierungen und Kupfer-Silizium-Durchkontaktierungen,
• 14 schematisch einen Querschnitt durch einen Mikrospiegel mit einer weiteren gestapelten Anordnung von elektronischen Bauteilen und
• 15 eine Explosionsdarstellung der gestapelten Anordnung gemäß 14 zur Hervorhebung der verschiedenen Teilsubstrate.

Further advantages, details and special features of the invention result from the description of exemplary embodiments with reference to the drawings. Show in these:

• 1 a schematic representation of a projection exposure system and its components,
• 2 a schematic representation of an optical component with an actuator device and a sensor device,
• 3 an alternative representation of the optical component according to 2 , in which the mirror plate with the counter electrodes or shielding elements arranged on it is folded to the side,
• 4 schematically a cross section through a micromirror with a stacked arrangement of electronic components,
• 5 schematically a cross section through a micromirror with a further stacked arrangement of electronic components,
• 6 schematically a cross section through a micromirror with yet another stacked arrangement of electronic components,
• 7 schematically a cross section through a micromirror with a further stacked arrangement of electronic components,
• 8A until 8G schematically the processing steps for producing an LTCC carrier with built-in chips,
• 9 schematically a cross section through a mirror that depicts part of the signal flow on the array,
• 10 schematically a cross section through a mirror array, illustrating some features of the 3D architecture of the electronics,
• 11A until 11G schematically shows a manufacturing process for an electronic component, in which first a silicon via and then ASICs are produced,
• 12A until 12G schematically shows a manufacturing process for an electronic component, in which an ASIC is first processed and then silicon vias are created,
• 13A until 13K schematically shows a process flow for creating a combined architecture with ASICs, poly-Si-silicon vias and copper-silicon vias,
• 14 schematically a cross section through a micromirror stacked with another th arrangement of electronic components and
• 15 an exploded view of the stacked arrangement according to 14 to highlight the different sub-substrates.

First, the general structure of a projection exposure system 1 (also called a lithography system) and its components are described. For details in this regard please refer to WO 2010/049076 A2 referred to, which is hereby incorporated in its entirety into the present application as part of the same. The description of the general structure of the projection exposure system 1 is primarily to be understood as an example. It serves to explain a possible application of the subject matter of the present invention. The subject matter of the present invention can also be used in other optical systems, in particular in alternative variants of projection exposure systems.

1 shows schematically a microlithographic projection exposure system 1 in a meridian section. A lighting system 2 of the projection exposure system 1 has, in addition to a radiation source 3 (also called lighting source), an optical lighting unit 4 (also called lighting optics) for illuminating an object field 5 in an object plane 6. The object field 5 can be designed rectangular or arcuate with an x/y aspect ratio of, for example, 13/1. In this case, a reflective mask (in 1 not shown), which carries a structure to be projected by the projection exposure system 1 for the production of micro- or nanostructured semiconductor components. An optical projection unit 7 (also called projection optics) is used to image the object field 5 into an image field 8 in an image plane 9. The structure on the mask is imaged onto a light-sensitive layer of a wafer, which is not shown in the drawing, and in the area of the image field 8 is arranged in the image plane 9.

The mask, which is held by a mask holder (not shown), and the wafer, which is held by a wafer holder (not shown), are scanned synchronously in the y-direction during operation of the projection exposure system 1. Depending on the imaging scale of the optical projection unit 7, it is also possible for the mask to be scanned in the opposite direction relative to the wafer.

The radiation source 3 is an EUV radiation source with emitted useful radiation in the range between 5 nm and 30 nm. This can be a plasma source, for example a GDPP (Gas Discharge Produced Plasma) source or an LPP ( Laser Produced Plasma source. Other EUV radiation sources, for example based on a synchrotron or a free electron laser (FEL), are also possible.

The EUV radiation 10 emerging from the radiation source 3 is focused by a collector 11. A corresponding collector is, for example, from the EP 1 225 481 A2 known. Downstream of the collector 11, the EUV radiation 10 passes through an intermediate focal plane 12 before hitting a field facet mirror 13. The field facet mirror 13 is arranged in a plane of the optical illumination unit 4, which is optically conjugate to the object plane 6. The field facet mirror 13 can be arranged at a distance from a plane conjugate to the object plane 6. In this case it is generally referred to as the first facet mirror.

The EUV radiation 10 is also referred to below as useful radiation, illumination radiation or as imaging light.

Downstream of the field facet mirror 13, the EUV radiation 10 is reflected on a pupil facet mirror 14. The pupil facet mirror 14 lies either in the entrance pupil plane of the optical projection unit 7 or in a plane optically conjugate thereto. It can also be arranged at a distance from such a plane.

The field facet mirror 13 and the pupil facet mirror 14 are constructed from a large number of individual mirrors, which will be described in more detail below. In this case, the field facet mirror 13 can be divided into individual mirrors in such a way that each of the field facets that illuminate the entire object field 5 itself is represented by exactly one of the individual mirrors. Alternatively, it is possible to construct at least some or all of the field facets using a large number of such individual mirrors.

The same applies to the design of the pupil facets of the pupil facet mirror 14 assigned to the field facets, which can each be formed by a single individual mirror or by a plurality of such individual mirrors.

The EUV radiation 10 impinges on the two facet mirrors 13, 14 at a defined angle of incidence. In particular, the two facet mirrors are exposed to EUV radiation 10 in the area of normal incidence, ie with an angle of incidence that is less than or equal to 25° to the mirror normal. Also exposure to stripes the idea is possible. The pupil facet mirror 14 is arranged in a plane of the optical illumination unit 4, which represents a pupil plane of the optical projection unit 7 or is optically conjugate to a pupil plane of the optical projection unit 7. With the aid of the pupil facet mirror 14 and imaging optics in the form of an optical transfer unit 15 with mirrors 16, 17 and 18, which are designated in the order of the beam path of the EUV radiation 10, the field facets of the field facet mirror 13 are imaged superimposed on the object field 5. The last mirror 18 of the optical transfer unit 15 is a grazing incidence mirror. The optical transfer unit 15, together with the pupil facet mirror 14, is also referred to as a sequential optical unit for transmitting the EUV radiation 10 from the field facet mirror 13 into the object field 5. The illumination light 10 is guided from the radiation source 3 to the object field 5 via a large number of illumination channels. Each of these illumination channels is assigned a field facet of the field facet mirror 13 and a pupil facet of the pupil facet mirror 14, the pupil facet being arranged downstream of the field facet. The individual mirrors of the field facet mirror 13 and the pupil facet mirror 14 can be tilted by an actuator system, so that a change in the assignment of the pupil facets to the field facets and a corresponding changed configuration of the lighting channels can be achieved. This results in different lighting settings that differ in the distribution of the illumination angles of the illumination light 10 over the object field 5.

In order to make it easier to explain the positional relationships, a global Cartesian xyz coordinate system is used below. The x-axis runs perpendicular to the drawing plane in the direction of the viewer 1 . The y-axis runs in 1 To the right. The z-axis runs in 1 up.

Different lighting systems can be achieved by tilting the individual mirrors of the field facet mirror 13 and a corresponding change in the assignment of these individual mirrors of the field facet mirror 13 to the individual mirrors of the pupil facet mirror 14. Depending on the tilting of the individual mirrors of the field facet mirror 13, the individual mirrors of the pupil facet mirror 14 newly assigned to the individual mirrors are tracked by tilting, so that an image of the field facets of the field facet mirror 13 in the object field 5 is again ensured.

Further aspects of the optical lighting unit 4 are described below.

The field facet mirror 13 in the form of a multi- or micromirror array (MMA) forms an example of an optical assembly for guiding the useful radiation 10, i.e. the EUV beam. The field facet mirror 13 is designed as a microelectromechanical system (MEMS). The field facet mirror 13 is composed of several hundred MEMS MMA (micro mirror array) or MMA components. Each MMA has a plurality of individual mirrors 20, which are arranged in a matrix-like manner in rows and columns in a mirror array 19. Another arrangement is also possible, for example hexagonal. The mirror arrays 19 can be designed to be modular. They can be arranged on a support structure that is designed as a base plate. It is possible to arrange essentially any number of mirror arrays 19 next to each other. The total reflection surface, which is formed by the entirety of all mirror arrays 19, in particular their individual mirrors 20, can therefore be expanded as desired. In particular, the mirror arrays are designed in such a way that they enable a substantially gap-free tessellation of a plane. The ratio of the sum of the reflection surfaces 26 of the individual mirrors 20 to the total area covered by the mirror arrays 19 is also referred to as the integration density or filling factor. In particular, this integration density is at least 0.5, in particular at least 0.6, in particular at least 0.7, in particular at least 0.8, in particular at least 0.9.

The mirror arrays 19 are attached to the base plate by means of fastening elements 29. For details please refer to, for example WO 2012/130768 A2 referred.

The individual mirrors 20 are designed so that they can be tilted by an actuator system, as will be explained further below. In total, the field facet mirror 13 has approximately 100,000 individual mirrors 20. Depending on the size of the individual mirrors 20, the field facet mirror 13 can also have a different number of individual mirrors 20. The number of individual mirrors 20 of the field facet mirror 13 is in particular at least 1000, in particular at least 5000, in particular at least 10,000. It can be up to 100,000, in particular up to 300,000, in particular up to 500,000, in particular up to 1,000,000.

A spectral filter can be arranged in front of the field facet mirror 13 and separates the useful radiation 10 from other wavelength components of the emission from the radiation source 3 that cannot be used for the projection exposure. The spectral filter is not shown.

The field facet mirror 13 is supplied with useful radiation 10 with a power of, for example 840 W and a power density of 6.5 kW/m ² applied.

The entire individual mirror array of the facet mirror 13 has, for example, a diameter of 500 mm and is densely packed with the individual mirrors 20. Insofar as a field facet is realized by exactly one individual mirror, the individual mirrors 20 represent the shape of the object field 5, apart from the scaling factor. The facet mirror 13 can be formed from 500 individual mirrors 20, each of which represents a field facet and has a dimension of approximately 5 mm in the y-direction and 100 mm in the x-direction. As an alternative to realizing each field facet by exactly one individual mirror 20, each of the field facets can be approximated by groups of smaller individual mirrors 20. A field facet with dimensions of 5 mm in the y-direction and 100 mm in the x-direction can, for example, be formed by a 1 × 20 array of individual mirrors 20 with dimensions of 5 mm × 5 mm up to a 10 × 200 array of individual mirrors 20 Dimensions of 0.5 mm × 0.5 mm can be constructed.

To change the lighting settings, the tilt angles of the individual mirrors 20 are adjusted. In particular, the tilt angles have a displacement range of at least ± 50 mrad, in particular at least ± 100 mrad, in particular at least ± 120 mrad. When adjusting the tilt position of the individual mirrors 20, an accuracy of better than 0.2 mrad, in particular better than 0.1 mrad, is achieved. When adjusting the tilt position of the individual mirrors 20, an accuracy of better than 0.1 mrad, in particular better than 0.05 mrad, in particular better than 0.02 mrad is required. The individual mirrors 20 of the field facet mirror 13 and the pupil facet mirror 14 carry in the embodiment of the optical illumination unit 4 according to 1 Multiple coatings to optimize their reflectivity at the wavelength of the useful radiation 10. The temperature of the multiple coatings should not exceed 1 425 K during operation of the projection exposure system. This is achieved by a suitable structure of the individual mirrors 20. For details see the DE 10 2013 206 529 A1 referred to, which is hereby incorporated in its entirety into the present application.

The individual mirrors 20 of the optical illumination unit 4 are housed in an evacuable chamber 21, the boundary wall 22 of which is in 2 is indicated. The chamber 21 is connected to a vacuum pump 25 via a fluid line 23 in which a shut-off valve 24 is accommodated. The operating pressure in the evacuable chamber 21 is a few Pascals, in particular 3 Pa to 5 Pa (partial pressure H ₂ ). All other partial pressures are well below 1 × 10 ^-7 mbar.

The mirror with the large number of individual mirrors 20, together with the evacuable chamber 21, forms an optical assembly for guiding a bundle of EUV radiation 10.

Each of the individual mirrors 20 can have a reflection surface 26 with dimensions of 0.1 mm × 0.1 mm, 0.5 mm × 0.5 mm, 0.6 mm × 0.6 mm or up to 5 mm × 5 mm or have larger. The reflection surface 26 can also have smaller dimensions. In particular, it has side lengths in the µm range or in the low mm range. The individual mirrors 20 are therefore also referred to as micromirrors. The reflection surface 26 is part of a mirror substrate 27 of the individual mirror 20. The mirror substrate 27 carries the multiple coating.

With the help of the projection exposure system 1, at least a part of the mask is imaged onto an area of a light-sensitive layer on the wafer for the lithographic production of a micro- or nanostructured component, in particular a semiconductor component, for example a microchip. Depending on the design of the projection exposure system 1 as a scanner or as a stepper, the mask and the wafer are moved in a time-synchronized manner in the y direction continuously in scanner mode or stepwise in stepper mode.

Further details and aspects of the mirror array 19, in particular the optical components that comprise the individual mirrors 20, are described below.

First, with reference to the 2 and 3 a first variant of an optical component 30 is described, which includes an individual mirror 20 and in particular the displacement device 31 for displacing, in particular for pivoting, the individual mirror 20.

The representation according to 3 corresponds to that according to 2 , where in 3 the mirror substrate 27 of the individual mirror 20 is folded away to the side. This makes the structures of the displacement device 31 and the sensor device more visible.

The optical component includes the individual mirror 20, which is designed in particular as a micromirror. The individual mirror 20 includes the mirror substrate 27 described above, on the front of which the reflection surface 26 is formed. The reflection surface 26 is formed in particular by a multi-layer structure. In particular, it has a radiation-reflecting property the lighting radiation 10, in particular for EUV radiation.

According to the variant shown in the figures, the reflection surface 26 has a square design; However, it is shown partially cut in order to also show the actuator system. It generally has a rectangular design. It can also have a triangular or hexagonal shape. In particular, it has such a tile-like design that a gap-free tessellation of a plane via the individual mirrors 20 is possible. The individual mirror 20 is attached by means of a joint 32, which will be described in more detail below. In particular, it is mounted in such a way that it has two degrees of freedom of tilting. In particular, the joint 32 enables the individual mirror 20 to be tilted about two tilt axes 33, 34. The tilt axes 33, 34 are perpendicular to one another. They intersect at a central intersection called the effective pivot point 35.

As long as the individual mirror 20 is in a non-pivoted neutral position, the effective pivot point 35 lies on a surface normal 36 which runs through a central point, in particular the geometric center of gravity of the mirror surface 26.

Unless otherwise stated, the direction of the surface normal 36 in the following text is always to be understood as the direction of the surface normal in the non-tilted neutral position of the individual mirror 20.

First, the displacement device 31 will be described in more detail below.

The displacement device 31 comprises an electrode structure with actuator-transducer stator electrodes 37; and actuator-transducer mirror electrodes 42. According to the in the 2 and 3 In the variant shown, the electrode structure comprises four actuator-transducer stator electrodes 37 ₁ , 37 ₂ , 37 ₃ and 37 ₄ . In general, the number of actuator-transducer stator electrodes is 37; at least 2, but can also be 3, 4 or more.

All actuator-transducer electrodes _37i , 42 are designed as comb electrodes with a large number of comb fingers 38. The complementary comb fingers of the mirror and stator interlock. The combs of the individual actuator electrodes 37; each include 30 actuator-transducer-stator comb fingers 38, which are also abbreviated below as stator comb fingers or simply as comb fingers. A different number is also possible. The number of comb fingers 38 of the actuator-transducer stator electrodes 37; is in particular at least 2, in particular at least 3, in particular at least 5, in particular at least 10. It can be up to 50, in particular up to 100.

The combs of the actuator-transducer-mirror electrodes 42 accordingly consist of actuator-transducer-mirror comb fingers 43, which are also abbreviated below as mirror comb fingers or simply as comb fingers. The number of mirror comb fingers 43 corresponds to the number of stator comb fingers. It can also differ by one from the number of stator comb fingers.

The comb fingers 38 are arranged so that they extend in the radial direction with respect to the surface normal 36 or the effective pivot point 35. According to a variant not shown in the figures, the comb fingers 38, 43 can also be arranged tangentially to circles around the effective pivot point 35. They can also have an embodiment that corresponds to sections of concentric circular cylinder side surfaces around the surface normal 36.

All actuator-transducer stator electrodes _37i are arranged on a support structure in the form of a substrate 39. In particular, they are arranged stationary on the substrate 39. In particular, they are arranged in a single plane, which is defined by the front of the substrate 39. This level is also referred to as the actuator level 40 or the comb level.

A wafer in particular serves as substrate 39. The substrate 39 is also referred to as a base plate.

The actuator-transducer stator electrodes 37; are each arranged in an area on the substrate 39, which has a square outer contour and a circular inner contour. Alternatively, the actuator-transducer stator electrodes 37; also be arranged in an annular area on the substrate 39. In this case, the outer contour is also circular. In particular, the individual actuator-transducer stator electrodes 37; each arranged in circular ring segment-shaped areas. The electrode structure as a whole, i.e. all actuator-transducer-stator electrodes 37, is arranged in an area that has an outer contour that essentially corresponds to that of the reflection surface of the individual mirror 20. It can also be arranged in a slightly smaller area, in particular in an area that is approximately 5% to 25% smaller.

The electrode structure has radial symmetry. In particular, it has fourfold radial symmetry. The electrode structure can also have a different radial symmetry sen. In particular, it can have a threefold radial symmetry. In particular, it has a k-fold radial symmetry, where k is the number of actuator-transducer stator electrodes 37; indicates. Apart from the subdivision of the electrode structure into the various actuator-transducer-stator electrodes 37; the electrode structure has an n-fold radial symmetry, where n is exactly the total number of comb fingers 38 of all actuator-transducer stator electrodes 37; corresponds.

Apart from their different arrangement on the substrate 39, the individual actuator-transducer stator electrodes 37; identically designed. This is not absolutely necessary. They can also have a different design. In particular, they can be carried out depending on the mechanical properties of the joint 32.

The comb fingers 38 are arranged radially with respect to the effective pivot point 35 or radially with respect to the alignment of the surface normals 36 in the non-pivoted neutral state of the individual mirror 20.

In the case of individual mirrors 20, the mirror substrates 27 of which have dimensions of 1 mm x 1 mm, the comb fingers 38 have a thickness d of at most 5 μm at their outer end in the radial direction. In general, the maximum thickness d of the comb fingers 38 at their outer end in the radial direction is in the range of 1 μm to 20 μm, in particular in the range of 3 μm to 10 μm.

The comb fingers 38 have a height h, i.e. an extension in the direction of the surface normal 36, which is in the range from 10 μm to 300 μm, in particular in the range from 50 μm to 150 μm. Other values are also conceivable. The height h is constant in the radial direction. It can also decrease in the radial direction. This makes it possible to make larger tilt angles possible without causing the comb fingers of the actuator mirror electrode 42 to hit the base plate.

Adjacent comb fingers 38, 43 of the actuator electrodes 37; on the one hand and the actuator mirror electrodes 42 on the other hand, in the non-pivoted state of the individual mirror 20, have a minimum distance in the range of 1 µm to 20 µm, in particular in the range of 3 µm to 10 µm, in particular approximately 5 µm. These values can be scaled accordingly for individual mirrors 20 with smaller or larger dimensions.

This minimum distance m is the minimum distance between adjacent mirror comb fingers and stator comb fingers, measured in the neutral, non-pivoted state of the individual mirror 20. The comb fingers can approach each other when the individual mirror 20 is tilted. The minimum distance m is chosen so that there is no collision between adjacent mirror comb fingers and stator comb fingers even when the individual mirror 20 is tilted to the maximum. Manufacturing tolerances have also been taken into account. Such manufacturing tolerances are a few micrometers, in particular at most 3 µm, in particular at most 2 µm, in particular at most 1 µm.

The maximum possible approach of adjacent comb fingers 38, 43 can be easily determined from the geometric details of the same and their arrangement as well as the maximum possible tilting of the individual mirror 20. In the present embodiment, the maximum approach of adjacent comb fingers 38, 43 is approximately 2 μm when the individual mirror 20 is tilted by 120 mrad. In particular, the maximum approximation is smaller than 10 µm, in particular smaller than 7 µm, in particular smaller than 5 µm, in particular smaller than 3 µm.

The actuator-transducer stator electrodes 37; each interact with an actuator mirror electrode 42. The actuator mirror electrode 42 is connected to the mirror substrate 27. In particular, the actuator mirror electrode 42 is mechanically firmly connected to the mirror substrate 27. The actuator mirror electrodes 42 form a counter electrode to the actuator transducer stator electrodes 37;. They are therefore also simply referred to as counter electrodes.

The actuator mirror electrode 42 forms a passive electrode structure. This should be understood to mean that the actuator mirror electrode 42 is subjected to a fixed, constant voltage.

The actuator mirror electrode 42 is designed to complement the stator electrodes _37i of the actuator converter. In particular, it forms a ring with actuator-transducer mirror comb fingers 43, which are also referred to below as mirror comb fingers or just as comb fingers 43 for simplicity. The geometric properties of the mirror comb fingers 43 of the actuator mirror electrode 42 essentially correspond to the stator comb fingers 38 of the actuator converter stator electrodes 37;.

All comb fingers 38, 43 can have the same height, i.e. identical dimensions in the direction of the surface normal 36. This simplifies the manufacturing process.

In the direction of the surface normal 36, the mirror comb fingers 43 of the actuator mirror electrode 42 can also have a different height than the height gate comb fingers 38 of the active actuator-transducer stator electrodes 37;.

The comb fingers 38, 43 can have a height h that decreases in the radial direction. It is also possible to make the comb fingers 38, 43 shorter in the area of the corners of the optical component 30 than the remaining comb fingers 38, 43. This enables a larger tilt angle of the individual mirror 20.

In particular, the actuator mirror electrode 42 is designed such that one of the comb fingers 43 of the actuator mirror electrode 42 is inserted into a space between two of the comb fingers 38 of the actuator transducer stator electrodes 37; can immerse.

The actuator mirror electrode 42 is connected to the mirror substrate 27 in an electrically conductive manner. Their comb fingers 43 are therefore equipotential. The mirror substrate 27 is connected to the base plate in a low-resistance manner via an electrically conductive joint spring. In principle, it is also possible to individually electrically connect the mirror substrate, i.e. the mirror substrate 27, the actuator mirror electrodes 42 and the sensor mirror electrodes 45, with separate supply lines via the joint 32 and thus, for example, to set them to different potentials or with regard to To decouple interference and/or crosstalk. The base plate can, but does not have to, be grounded. Alternatively, the mirror can be connected to a voltage source at a different potential via a conductive hinge spring, but electrically isolated from the mirror plate. This makes it possible to apply a fixed or variable bias voltage to the mirror.

To the actuator-transducer stator electrodes 37; An actuator voltage U _A can be applied in order to pivot the individual mirror 20. Therefore, the actuator-transducer stator electrodes 37; also as active actuator-transducer stator electrodes 37; designated. To apply the actuator voltage U _A to the actuator-transducer stator electrodes 37; A voltage source, not shown in the figures, is provided. The actuator voltage U _A can be up to 200 volts or more. In particular, it can be greater than 100 volts. By appropriately applying the actuator voltage U _A to a selection of the actuator-transducer stator electrodes 37; The individual mirror 20 can be tilted by up to 50 mrad, in particular by up to 100 mrad, in particular by up to 150 mrad, from a neutral position. Alternatively, the actuators can also be controlled by a charge source (current source).

On the various actuator-transducer stator electrodes 37; different actuator voltages U _A ; to pivot the individual mirror 20. To control the actuator voltages U _A ; A control device (not shown in the figures) is provided.

To tilt one of the individual mirrors 20, an actuator voltage U _A is sent to one of the actuator-transducer stator electrodes 37; created. At the same time, an actuator voltage U _A2 ≠ U _A1 that deviates from this is applied to the actuator-transducer stator electrode 37 _j , which is opposite in relation to the surface normal 36. U _A2 can be 0 volts. In particular, it is possible to send the actuator voltage U _A1 to only one of the actuator-transducer stator electrodes 37; to be applied, while all other actuator-transducer stator electrodes 37 _j are kept at a voltage of 0 volts.

When the individual mirror 20 is tilted, the comb fingers of the actuator mirror electrode 47 dip deeper on one side between the comb fingers 38 of the actuator transducer stator electrode 37; a, in particular in the area of this actuator-transducer-stator electrode _37i , to which the actuator voltage U _A was applied. On the opposite side of the tilt axis 33, the actuator mirror electrode 42 is immersed less deeply in the actuator transducer stator electrodes 37 _j . The actuator mirror electrode 42 can even protrude from the actuator transducer stator electrodes 37 _j at least in some areas.

The comb overlap, i.e. H. the immersion depth of the actuator mirror electrode 42 between the actuator transducer stator electrodes 37 is between 0 µm and 50 µm, preferably between 5 µm and 30 µm, preferably 10 µm in the neutral position of the individual mirror 20 with a mirror dimension between 0.5 mm2 × 0.5 mm2 and 1.0 mm2 × 1.0 mm2.

When the mirror 20 is tilted by 120 mrad, the (lateral) distance between the comb fingers 43 of the actuator mirror electrode 42 and the comb fingers 38 of the actuator transducer stator electrodes 37 decreases; by a maximum of 1 µm to 10 µm or 3 µm to 7 µm compared to the neutral position. Thus, the comb fingers 43 of the actuator mirror electrode 42 and the comb fingers 38 of the actuator transducer stator electrodes _37i are spaced apart from one another in every pivoting position of the mirror 20, in particular without contact. In particular, the immersion depth, ie the ridge overlap, is chosen to ensure this.

According to an alternative, the comb fingers 38, 43 are somewhat shorter in the outer region and therefore have a relatively small overlap, ie a smaller immersion depth. For example, the immersion depth in the outermost area can be approximately half as deep as the immersion depth in the inner area. This information also refers to the neutral position of the mirror 20.

The characteristics, in particular the linearity of the control, can also be influenced by depending on the immersion depth of the comb fingers 38, 43 on their radial position. Since all actuator-transducer stator electrodes 37; are arranged in a single level, the actuator level 40, complicated series kinematics can be dispensed with. The displacement device 31 is characterized by parallel kinematics. In particular, the displacement device 31 has no movably arranged active components. All actuator-transducer stator electrodes 37, to which the actuator voltage U _A can be applied, are arranged immovably and stationarily on the substrate 39. A sensor device is provided to detect the pivoting position of the individual mirror 20. The sensor device can form part of the displacement device 31.

The sensor device includes sensor-transducer mirror electrodes 45 and sensor-transducer stator electrodes 44;.

The sensor unit consists of four sensor-transducer stator electrodes 44 ₁ to 44 ₄ . To simplify matters, the sensor-transducer stator electrodes 44; also referred to as sensor electrodes. For the control, it is advantageous if the number of sensor-transducer stator electrodes 44; almost exactly the number of actuator-transducer-stator electrodes 37; corresponds. The number of sensor-transducer stator electrodes 44; but can also depend on the number of actuator-transducer-stator electrodes 37; differ.

The sensor-transducer stator electrodes 44 ₁ to 44 ₄ are in the variant according to 2 and 3 each arranged along the diagonal of the substrate 39. At the in the 2 and 3 In the variant shown, the sensor-transducer stator electrodes 44 ₁ to 44 ₄ are arranged offset by 45 ° to the tilt axes 33, 34 of the joint 32.

The actuator-transducer stator electrodes 37 _i are each arranged in quadrants 54 ₁ to 54 ₄ on the substrate 39. The sensor-transducer stator electrodes 44; are each arranged in the same quadrant 54 ₁ to 54 ₄ as one of the actuator-transducer stator electrodes 37;. The actuator device 31, in particular the arrangement and design of the actuator-transducer stator electrodes 37;, has essentially the same symmetry properties as the reflection surface 26 of the individual mirror 20. The sensor device, in particular the sensor-transducer stator electrodes 44;, essentially has the the same symmetry properties as the reflection surface 26 of the individual mirror 20.

Two sensor-transducer stator electrodes 44, which lie opposite each other with respect to the effective pivot point 35, are differentially connected to one another. However, such an interconnection is not absolutely necessary. In general, it is advantageous if two sensor electrodes _44i , which are opposite one another with respect to the effective pivot point 35, are designed and arranged in such a way that they can be read out differentially.

The sensor-transducer stator electrodes 44; are designed as comb electrodes. In particular, the sensor-transducer stator electrodes 44; corresponding to the actuator-transducer stator electrodes 37; be designed, the description of which is hereby referred to. The sensor-transducer stator electrodes 44; each include a sensor-transducer-stator-transmitter electrode 47, which is also abbreviated below as transmitter electrode, and a sensor-transducer-stator-receiver electrode 48, which is also abbreviated below as receiver electrode. Both the sensor-transducer-stator-transmitter electrode 47 and the sensor-transducer-stator-receiver electrode 48 have a comb structure. In particular, they consist of a large number of comb fingers. In particular, the comb fingers of the sensor-transducer-stator-transmitter electrode 47 are arranged alternately with the comb fingers of the sensor-transducer-stator-receiver electrode 48.

The sensor device includes a sensor transducer mirror electrode 45 for each of the sensor transducer stator electrodes 44;. According to an advantageous embodiment, the sensor-transducer mirror electrodes 45 each form a shielding unit for the sensor-transducer stator electrodes 44;. The sensor-transducer mirror electrode 45 each comprises comb elements with a plurality of comb fingers 46. The sensor-transducer mirror electrode 45 is corresponding to one of the sensor-transducer stator electrodes 44; suitable counter electrode is formed. In particular, the sensor-transducer mirror electrodes 45 can be designed corresponding to the actuator-transducer mirror electrodes 42, the description of which is hereby referred to.

The sensor-transducer mirror electrodes 45 are each firmly connected to the mirror substrate 27. They are arranged in the area of the diagonal of the mirror substrate 27. When the individual mirror 20 is tilted, the sensor-transducer mirror electrode 45 can dip to different depths between the comb fingers of the sensor-transducer stator electrodes 44, in particular between the transmitter electrode 47 and the receiver electrode 48. This results in variable shielding of adjacent comb fingers, in particular variable shielding of the receiver elect rode 48 relative to the transmitter electrode 47. This leads to a change in capacitance between the adjacent comb fingers of the sensor-transducer stator electrodes 44 when the individual mirror 20 is pivoted. This change in capacity can be measured. For this purpose, the inputs of a measuring device are alternately connected to the comb fingers of the sensor-transducer stator electrodes 44; tied together.

The initial immersion depth of the sensor-transducer mirror electrodes 45 between the sensor-transducer stator electrodes 44, in particular between the transmitter electrodes 47 and the receiver electrodes 48, is between 10 µm and 100 µm, in particular between 20 µm and 60 µm, for a mirror with 1 mm size preferably about 40 µm. This ensures that the comb fingers 46 still have a residual immersion depth everywhere between the transmitter electrodes 47 and the receiver electrodes 48, even in the maximum tilted pivot position, i.e. they never come out completely. This ensures the differential sensor function over the entire tilting range. On the other hand, the immersion depth of the sensor-transducer-mirror electrode 45 is selected so that there is no collision between the individual mirror 20 and the substrate 39 even in the maximum tilted pivot position.

To measure the capacitance between the transmitter electrode 47 and the receiver electrode 48 of the sensor-transducer stator electrodes 44; an electrical voltage, in particular a sensor voltage Us, is applied to the transmitter electrode 47. In particular, an alternating voltage serves as the sensor voltage Us.

The sensor device is sensitive to the immersion depth of the comb fingers 46 between adjacent comb fingers of the sensor-transducer stator electrodes 44;.

The sensor device is insensitive to a mere pivoting of the comb finger 46 relative to the transmitter electrode 47 and the receiver electrode 48.

The sensor device is insensitive to a lateral displacement of the shielding element, which changes its distance from the transmitter electrode 47 and the receiver electrode 48, but leaves the immersion depth of the comb finger 46 between the adjacent transmitter and receiver electrodes 47, 48 unchanged.

Further details of the sensor device are in the WO 2016/146541 A1 which are hereby incorporated by reference in their entirety.

The sensor-transducer stator electrodes 44; are within the ring of the actuator-transducer-stator electrodes 37; arranged. In this area, the absolute movements of the comb fingers 46 in the direction parallel to the surface normal 36 are smaller than outside the ring of the actuator-transducer-stator electrodes 37;. The absolute range of motion refers to the distance to the effective pivot point 35.

In the embodiments shown in the figures, the sensor-transducer stator electrodes 44; in the radial direction inwards over the inner contour of the actuator-transducer stator electrodes 37; out. It is also possible to use the sensor-transducer stator electrodes 44; to be carried out in such a way that they do not extend beyond the inner contour of the actuator-transducer-stator electrodes 37; stand out.

The sensor-transducer stator electrodes 44; are designed and arranged radially to the effective pivot point 35. In particular, they have comb fingers that extend in the radial direction. This reduces the sensitivity to possible thermal expansion of the individual mirror 20.

As already explained above, due to its structure, the sensor device has at best a low sensitivity to parasitic movements of the individual mirror 20, in particular to displacements perpendicular to the surface normal 36 and / or rotations about the surface normal 36. Due to the shielding principle of the sensor device, it also has a minimal sensitivity at best Sensitivity to possible thermal expansion of the individual mirror 20. In addition, the sensor principle is not very sensitive to thermal deformation of the mirror.

Two sensor units opposite each other with respect to the effective pivot point 35, each with a transmitter electrode 47 and a receiver electrode 48, are differentially connected to one another or at least can be read out differentially. This makes it possible to exclude errors when measuring the position of the mirror 20, in particular due to intrinsic modes of the individual mirror 20.

The active components of the sensor device are arranged on the substrate 39. This makes it possible to measure the angle of inclination of the individual mirror 20 directly relative to the substrate 39. In addition, the length of the signal line 56 and/or the supply lines 57 can be reduced, in particular minimized, by arranging the transmitter electrodes 47 and the receiver electrodes 48 on the substrate 39. This avoids possible disruptions inflows reduced. This ensures constant operating conditions.

The transmitter electrodes 47 are each designed as an active shield, in particular as a shielding ring, around the receiver electrodes 48. This causes capacitive crosstalk between the actuator-transducer stator electrodes 37; and the sensor device reduced, in particular minimized, in particular prevented.

An alternating voltage from a voltage source 48 can be applied to the transmitter electrode 47. The voltage source 58 has a low impedance. In particular, the voltage source 58 has an output impedance which, in the excitation frequency range, is less than 1 per mille of the coupling capacitances of the actuator-transducer stator electrodes 37; to the transmitter electrodes 47. The output impedance of the voltage source is less than 1 per mille of the capacitances between the transmitter electrodes 47 and the sensor-transducer mirror electrodes 45 or the receiver electrodes 48. This ensures that the alternating voltage applied to the transmitter electrodes 47 does not differ, or at least not significantly, from the variable actuator voltages U _A or the variable sensor capacity is influenced.

A network analyzer can generally be used to read the sensor transducer. With this it is possible to determine the impedance of the sensor transducer and from this to determine the position of the displacement of the individual mirror 20 using a conversion factor. Such a network analyzer usually consists of an excitation source, for example the voltage source 58 described above, and a response measurement, for example a current measurement or a measurement of the transported charge during a signal period. The network impedance and thus the sensor capacity can be determined from the quotient of the excitation voltage and current.

Two variants of the joint 32 are described in more detail below.

The joint 32 can be designed as a cardan joint.

According to a first variant, the joint 32 is designed as a torsion spring element structure. In particular, it includes two torsion springs 50, 51. The two torsion springs 50, 51 are formed in one piece. In particular, they are aligned at right angles to one another and form a cross-shaped structure 49.

The torsion springs 50, 51 have a length of approximately 100 μm, a width of approximately 60 μm and a thickness of approximately 1 μm to 5 μm. Such torsion springs 50, 51 are suitable as individual mirrors 20 with dimensions of 0.6 mm x 0.6 mm. The dimensions of the torsion springs 50, 51 depend on the dimensions of the individual mirrors 20. In general, larger mirrors require larger, in particular stiffer, torsion springs 50, 51.

The torsion spring 50 extends in the direction of the tilt axis 33. The torsion spring 50 is mechanically connected to the substrate 39. Connection blocks 52 are used to connect the torsion spring 50 to the substrate 39. The connection blocks 52 each have a cuboid design. They can also be cylindrical, in particular circular cylindrical. Other geometric shapes are also possible.

The connection blocks 52 are each arranged in an end region of the torsion spring 50.

In addition to connecting the joint 32 to the substrate 39, the connection blocks 52 also serve as spacers between the torsion spring 50 and the substrate 39.

Corresponding to the connection of the torsion spring 50 to the substrate 39, the torsion spring 51 is mechanically connected to the mirror substrate 27 of the individual mirror 20. Connection blocks 53 are provided for this purpose. The connection blocks 53 correspond in their design to the connection blocks 52. The connection blocks 53 are each arranged in an end region of the torsion spring 51.

In the direction of the surface normal 36, the connection blocks 53 and the connection blocks 52 are arranged on opposite sides of the cross-shaped structure 49.

The torsion springs 50, 51 of the joint 32 have a T-shaped profile in the area of the legs of the cross-shaped structure 49 adjacent to the central area. As a result, the torsion springs 50, 51 are stiffened, in particular against deflections in the direction of the surface normal 36. This ensures that the natural frequency of the mirror 20 is shifted in the vertical direction to high frequencies and thus a frequency spacing of the regulated tilting modes and the parasitic vertical oscillation modes of more than a decade in the frequency space is achieved, which is advantageous from a control theory perspective. In addition, the thermal conductivity of the joint 32 can be increased by the cross-shaped stiffening element 55.

In principle, it is possible to have a corresponding stiffening element 55 on the opposite side of the cross-shaped structure door 49 to be arranged. In this case, the legs of the torsion springs 50, 51 have a cross-shaped cross section.

By specifically designing the stiffening elements 55, the mechanical and/or thermal properties of the joint can be specifically influenced. The profile, in particular the stiffening elements 55, serve to increase the rigidity in the actuator level. They serve in particular to realize a binding rigidity of the individual mirror 20 relative to the base plate 39 in the horizontal degrees of freedom, i.e. during a horizontal displacement and a rotation about the vertical axis. This increases the natural frequencies of the parasitic modes of the individual mirror 20. This results in a mode spacing that is advantageous in terms of control theory between the controlled tilting modes and the parasitic modes. In particular, the natural frequencies of the parasitic modes are preferably at least a decade above the activated tilting modes.

In addition, the forces acting between the mirror 20 and the actuator-transducer-stator comb fingers 38 and the resulting electrostatic softening (negative rigidity) should be absorbed by the high horizontal rigidity. In particular, it can be ensured that, from the perspective of the comb fingers 38, no transversal retraction occurs.

The stiffening elements 55, which are also referred to as stiffening ribs, in particular as vertical stiffening ribs, serve to shift the deflection stiffness and thus to shift the natural frequency of vertical vibrations, i.e. vibrations in the direction of the surface normal 36, to higher frequencies.

The joint 32 is stiff with regard to rotations about the surface normal 36. The joint 32 is stiff with regard to the linear displacement in the direction of the surface normal 36. In this context, stiff means that the natural frequency of the torsional vibrations about the surface normal 36 and the natural frequency of the Oscillations in the direction of the surface normal are more than a frequency decade above the controlled modes. The controlled tilting modes of the individual mirror are in particular at frequencies below 1 kHz, in particular below 600 Hz. The natural frequency of the torsional vibrations around the surface normal 36 is more than 10 kHz, in particular more than 30 kHz.

The joint 32 has a known flexibility with regard to pivoting about the two tilting axes 33, 34. The rigidity of the joint 32 with regard to pivoting about the tilting axes 33, 34 can be influenced by a targeted design of the torsion springs 50, 51.

The joint 32, in particular the connection blocks 52, 53 and the torsion springs 50, 51, serve to dissipate heat from the mirror substrate 27. The components of the joint 32 form heat conduction sections.

The joint 32 with the connection blocks 52, 53 has a variety of functions. First: the binding of the non-controlled degrees of freedom, second: the heat transport from the mirror 20 to the base plate 39 and third: the electrical connection between the mirror 20 and the base plate 39. The blocks 52, 53 primarily serve to provide space for vertical movement of the joint element. It goes without saying that the blocks 52, 53 then also have to take over the mechanical, thermal and electrical functions of the springs 50, 51.

The base plate 39 can form a heat sink. It is also possible to provide a separate heat sink. Such a heat sink is preferably thermally connected to the base plate 39, in particular to the mirror 20.

The torsion springs 50, 51 consist of a material with a thermal conductivity coefficient of at least 50 W/(mK), in particular of at least 100 W/(mK), in particular of at least 140 W/(mK).

The torsion springs 50, 51 can be made of silicon or a silicon compound. The joint 32 is preferably made from highly doped monocrystalline silicon. This opens up process compatibility of the manufacturing process with established MEMS manufacturing processes. In addition, this leads to an advantageously high thermal conductivity and good electrical conductivity.

With an absorbed power density of 10 kW/(m ² ) and mirror dimensions of 600 µm × 600 µm, the specified values of the dimensions, in particular with a thickness of the torsion springs 50, 51 of 4 µm, and the thermal conductivity of the torsion springs 50, 51 a temperature difference of 11 K between the mirror substrate 27 and the substrate 39.

The torsion springs 50, 51 can also have a smaller thickness. If the torsion springs 50, 51 have a thickness of 2.4 μm, then there is a temperature difference of 37 K between the mirror substrate 27 and the substrate 39 - with otherwise the same parameter values.

In particular, the thermal conductivity of the torsion spring is in the range from 0.5 K/kW/m ² to 10 K/kW/m ² , where the thermal power density refers to the average thermal power absorbed by the mirror. Such torsion springs could ensure that the temperature difference between the mirror substrate 27 and the substrate 39 is less than 50 K, in particular less than 40 K, in particular less than 30 K, in particular less than 20 K.

In another variant of the joint 32, leaf springs are provided instead of the torsion springs 50, 51. For further details please refer to the WO 2016/146 541 A1 referred to, which is hereby incorporated in its entirety by reference into the present application. It will focus in particular on the 10 this application and the associated description are referred to.

The joint 32 also has a high level of rigidity in the horizontal degrees of freedom in this variant. In this regard, reference is made to the description of the alternative above. The design aspects with regard to the horizontal stiffness and with regard to the frequency spacing of the parasitic eigenmodes also correspond to those described above.

The variant of the joint 32 is a cardan joint with orthogonally arranged, horizontal bending springs, which are designed as leaf springs. Two of the bending springs are connected to each other via a plate-shaped structure, which is also referred to as an intermediate plate.

The joint 32 has the following advantages: It is soft in the control direction. It is very stiff in the restricted DoF degrees of freedom. It enables a clear demarcation of the eigenmodes. It leads to a practically perfect separation of the Rx and Ry tilts.

Horizontal leaf springs are advantageous from a process engineering perspective. In particular, they simplify the production of the joint 32.

In the variant, the connection blocks 52, 53 are each elongated and rod-shaped. They extend essentially over the entire extent of the joint 32 in the direction of the tilt axes 33, 34.

A separating slot can be provided between two of the connection blocks 52, 53. The joint 32 can therefore be designed in two parts.

The joint 32 is preferably axially symmetrical with respect to the surface normal 36. It can therefore have double rotational symmetry. In particular, the spiral springs can each be designed to be mirror-symmetrical to the surface normal 36.

The different variants of the displacement device 31, the sensor device, the joint 32 and the other components of the optical component 30 can essentially be freely combined with one another.

According to a further variant, the actuators can also be used as sensors at the same time. For this purpose, it is intended to read out the tilt angle-dependent capacity of the actuator at a frequency that is significantly higher, in particular by at least a decade, than the control frequency (control bandwidth). In this case, a separate sensor device can be dispensed with. It is also possible to additionally provide a separate sensor device, in particular in accordance with the previous description.

The displacement device 31 can preferably be produced using a MEMS process. In particular, it has a structure that is designed for production using MEMS process steps. In particular, it has predominantly, in particular exclusively, horizontal layers, which can be structured in a vertical direction.

In particular, the electrodes 37, 42, ₄₄ , 45 can be produced using MEMS process steps. The joint 32 can preferably also be produced using MEMS process steps.

The field facet mirror 13 and/or the pupil facet mirror 14 can consist of one or more modules of MEMS multi-mirror array components (MMA), each of which can be, for example, B. includes 24x24 micromirrors, each of which has its own independent electrostatic comb actuators for tilting the mirror in two orthogonal directions and comb sensors for reading the alignment. Each mirror can be equipped with two, four or more actuators and/or two, four or more sensors.

Further details of the micromirrors, in particular the electronic parts of the micromirrors, are described below. These details can be advantageously combined with the structural details described above. However, they are independent and not necessarily linked to these details. The following exemplary embodiments also serve to illustrate various aspects of the invention. However, the invention is not limited to these examples. Also any combinations between the examples or parts of the Embodiments shown there are the subject of the present invention.

In the exemplary embodiment of 4 a mirror 20 is shown schematically with its mirror substrate 27 and the reflecting surface 26, the comb alignment sensor 61, the comb actuator 62 and the substrate 39 of the mirror 20.

4 shows an implementation of vertical stacking of chips with an active area. An active area is the area in which the electronics/integrated circuits are housed. It is not the area where the wiring and bond/bump/connection pads are located.

The substrate 39 includes TSVs 63 (through silicon vias 63 = silicon vias 63).

On the back of the substrate 39, two types of chips, type 1 chips 64, also referred to as chips_1 64, and type 2 chips 65, also referred to as chips_2 65, are attached and electrically connected by bumps 66. The bumps 66 can consist of CuSn, for example.

The chips can be made of silicon. They feature ICs (integrated circuits) formed by etching, deposition and local doping through selective implantation, and have resolution/features as low as 10nm to 100nm. The chips are also called ICs, dies or wafers designated. The active side 67 of the chips, on which CMOS circuits in particular are formed, is highlighted in the figures by a dashed contour. Both chips 64 and 65 have an active area.

The Chips_1 64 has the active side 67 facing up (in the direction of the mirror 20), which is connected to the actuator TSV 63 by bumps. In addition, the Chips_1 64 have pass-through TSVs 63, which transmit the electrical signals from the Chips_2 65 through the Chips_1 64 to the sensor TSVs 63 and, if necessary, to the wiring pads for other structures, thus enabling vertical stacking.

In 5 Connection options for chips_1 64 with an active area and chips_2 65 also with one active side or type 3 chips 68 with two active sides are shown schematically.

Chips_2 64 and Chips_3 68 are located behind Chips_1 63. They can be connected using interposer chips 69. Unlike in the previous example, the chips _2 and chips_3 behind chips_1 are not connected by TSVs in chips_1, but with the help of interposer chips 69.

The interposer chips 69 may not have active electronic circuits, but only TSVs 63 to connect the signals through the layer of Chips_1 63 towards the substrate 39 of the mirror 20.

The electronics on the second level behind it can be designed as a single chip, but also on a complete controller/CMOS wafer 70 (shown as a black dashed rectangle) and connected by the interposer chips 69.

The interposer chips 69 and Chip_4 68 are shown with only one bump 66 for the sake of simplicity. This would lead to mechanical instability.

For all metal/metal bonded or bumped chips, two rows in the x/y direction can advantageously be used.

Preferably, the chips 64, 65, 68, 69 have a size that allows machining. Smaller dies are advantageous for higher yield, but it may be better to use chips of a similar size to the MEMS mirror 20. This results in simplified stacking (fewer chips).

The TSVs 63 of the substrate 39 of the mirror 20 and these of the chips 64, 65, 68, 69 can also have another important function in addition to the electrical one: They can conduct the heat absorbed on the mirrors 20 backwards and away in order to protect the mirrors 20 to be kept at an appropriate temperature, in particular below 200 °C, preferably below 100 °C. This ensures that the reflectivity of the coating does not decrease and the life of the mirror 20 is extended. This point is particularly important for EUV systems, where even the best coatings only reflect about 2/3 of the incident radiation.

Depending on the material of the TSV 63 and its isolation from the substrate of the chip, the TSVs 63 may have thermal, electrical, or both conductive functions.

Accordingly, the bumps 66 or the connection areas can be made from thermally, electrically or thermally and electrically conductive material.

In the exemplary embodiment according to 5 Both possibilities are shown schematically by considering the TSVs 63 and the corresponding bumps 66_1 as electrically conductive in order to transfer the electrical signals from the back to the front side of the chips _2 64, while the TSVs 63 and the bumps 66 2 are provided to transfer the heat to a heat sink 71 (or other large thermal reservoir).

The heat conduction structure is only shown schematically. Additional elements such as rewiring plates, holding plates, controllers, etc. can be arranged between the chips_2 65, the chips_3 68 and the heat sink 71, paying attention to the correct propagation of the electrical and thermal paths.

The TSVs 63 can be made of or contain copper, poly-Si or other materials. Copper TSVs are particularly good thermal and electrical conductors, while poly-Si TSVs conduct electrical signals well and conduct heat moderately well. On the other hand, poly-Si TSVs allow later high-temperature processes, for example for the implantation and annealing of CMOS circuits.

Another important aspect is the quality of the lateral insulation of the TSVs 63 if they have an electrical function. The TSVs 63 can be fabricated in three main steps: etching the hole by DRIE (deep reactive ion etching), insulating the sidewalls, and filling (particularly with Cu/Poly-Si).

When a die contains both electronics and TSVs 63, the processes must comply with the overall thermal budget, which requires the highest thermal steps such as dry thermal oxidation (high voltage (HV) isolation) and highly doped implantation and annealing (at temperatures in the range of approximately 1000 °C to 1100 °C) can be carried out at the beginning. This is followed by processes with lower temperatures, such as wet oxidation, implantation and annealing of (piezo) resistors, etc., at approx. 950 °C, then the LPCVD coating (Low Pressure Chemical Vapor Deposition). 650-800°C for medium quality insulation at moderate temperatures. The deposition and annealing of A1 for contacts and wiring takes place at 420 °C to 450 °C. PECVD (Plasma Enhanced Chemical Vapor Deposition) deposition of dielectrics also occurs at lower temperatures, around 250°C to 400°C, and is used for passivation and low voltage insulation (up to 200V). The lower the deposition temperature of the insulation, the worse its dielectric strength (the breakdown voltage). Therefore, TSVs manufactured after the CMOS part have lower insulation ability and are suitable for low voltage (digital part) and thermal conductivity. The high voltage drivers would be better placed on the side of the chips facing the mirrors 20 (e.g. on Type 1 chips 64) and not routed through hybrid chips with CMOS and TSVs. Power for the HV digital-to-analog converters (DACs) can be connected from the rear via poly-Si TSVs or generated on-chip through a cascade of lower voltages.

In the 5 Chips_3 68 shown have both sides as active electrical surface 67. The signals formed by the back of the Chips_3 68 are routed to the front through the TSVs in the same Chips_3 68 - the electrical TSVs (66_1). The electrical path then runs through the interposer chips 69 and the TSVs in the mirror substrate.

Chips _3 68 with double-sided active electrical area/electronics can be produced by double-sided CMOS processing of the Si wafers or by connecting two single-sided chips back-to-back, e.g. B. can be implemented using glue or adhesive tape.

Another solution for connecting chips is in 6 shown. Here, part of the signals formed on the back of the chips_3 68 are connected by wire bonds 72 to the back of the chips_1 64, where they can be processed and/or further transmitted, e.g. B. on the top of the chips_1 64 for further processing or on the mirror substrate 27.

The electrical connections may be such that the signal can be routed through TSVs and bumps and wire bonding through the chips to one or more wiring/stacking levels.

Other contacts on the back of the chips_3 68 are wire-connected to the pads 73 provided for this purpose on the mirror substrate 27. The signals from the front of Chips_3 68 can be connected to the back of Chips_1 64 or routed through Chips_1 64, as in 6 is shown schematically.

In the in 6 In the example shown, Chips_1 64 also has two active pages 67.

The structures from the top are applied to the mirror substrate 27 with bumps.

The structures from the back are routed to the opposite side of the chip via TSVs 63.

A Chip_4 74 is shown as a one-sided active flip chip, which is connected to the substrate 27 of the mirror element via bumps 66 or by metal-metal bonding.

Another example is in 7 shown. Here the chips 75 are installed in a carrier 76.

The carrier 76 can z. B. made of ceramic, e.g. B. low-temperature single-firing ceramic (LTCC). This can be used for robust assembly and packaging of electronic components, especially for multilayer packaging.

Single-firing ceramic components are manufactured using a multi-layer process. The starting material is green composite tapes, which consist of ceramic particles in combination with polymeric binders. The bands are flexible and can be processed, for example by cutting, milling, punching and embossing. Metal structures can be added to the layers, usually done through via filling and screen printing. Cavities are reinforced. The individual tapes are then bonded together in a lamination process before the components are fired in an oven, where the polymer portion of the tape burns and the ceramic particles sinter together, creating a hard and dense ceramic component.

The steps for producing such an LTCC carrier 76 with built-in chips 75 are in the 8A until 8G shown schematically.

First, a first shell 81 of the LTCC 76 with contact holes 77 and wire-spread layers 78 as well as cavities 79 is created for the first row 80 of the electronic chips 75 (cf. 8A) .

The chips 75 are bonded or provided with bumps 66 (“bumped”).

A second LTCC shell 82 with contact holes 77, wiring layers 78 and cavities 79 is then attached and electrically connected by lamination over the first shell 81 or by face-to-face bonding, bumps, etc. (cf. 8B) .

Fine wire bonding with small wire loops is also an option, as in this case the bond pads of the chips must be on their back and therefore must be bonded up to the corresponding pads in the LTCC cavities.

The 2nd and 3rd rows of chips are attached and bonded F2F (face-to-face) (cf. 8C ), followed by the connection of the next shell 83 (cf. 8D ), renewed bumping/bonding of chips (cf. 8E) , etc. Finally, an LTCC cap 84 can be attached (cf. 8F and 8G) .

It has been recognized that higher on-die integration can be achieved by combining TSVs 63 and ASICs or other CMOS circuits on the same die (chip).

The individual process steps are preferably carried out in the order of decreasing process temperature.

• 1) - Ätzen von Kontaktlöchern (DRIE),
• 2) - Seitenisolierung,
• 3) - Auffüllen und
• 4) - Planarisierung, insbesondere durch chemisch-mechanisches Polieren (CMP).

TSVs 63 can be manufactured through the following process sequence:

• 1) - etching of contact holes (DRIE),
• 2) - side insulation,
• 3) - Fill up and
• 4) - Planarization, especially by chemical mechanical polishing (CMP).

The TSVs 63 can first be isolated with SiO2 and then filled with doped poly-Si or with metal, especially Cu.

Alignment mark compatibility is possible. Before or together with the fabrication of the TSVs, markings are created on the wafer for the alignment of the various lithography steps. These markings ensure compatibility and fine alignment of the TSV process with subsequent MEMS or CMOS processing.

1. a) durch nasse thermische Oxidation bei 1100 °C: -400V @ 1µm thermisches SiO2
2. b) durch PECVD (plasmaunterstützte chemische Gasphasenabscheidung) von SiO2 bei 300 °C bis 350 °C: <~100V @ 1µm PECVD SiO2

The dielectric strength (short circuit voltage) of TSVs 63 side insulation can be achieved in the following ways:

1. a) by wet thermal oxidation at 1100 °C: -400V @ 1µm thermal SiO2
2. b) by PECVD (plasma-assisted chemical vapor deposition) of SiO2 at 300 °C to 350 °C: <~100V @ 1µm PECVD SiO2

It has been found that ASICs can survive the thermal stress and RF and MW electromagnetic fields during the DRIE (deep RIE / reactive ion etching) process.

1. a) TSVs als rein thermisch leitende Strukturen. Keine Anforderungen an die Seitenisolation. Material: z.B. Cu.
2. b) TSVs als thermisch leitende Strukturen und Übertragung von Niederspannungs- (digitalen) Signalen. Geringe Anforderungen an die Seitenisolation. Material: z.B. Cu.
3. c) TSVs als thermisch leitende Strukturen und Übertragung von HV-(Analog-/Treiber-) Signalen. Hohe Anforderungen an die Seitenisolation. Eine mögliche Lösung umfasst: Poly-Si-TSVs vor CMOS für die HV-Signale und separate Cu-TSVs vor/nach CMOS für die thermische Verbindung. Material: Poly-Si und Cu.
4. d) TSVs nur zur Übertragung von NV (digitalen) Signalen. Geringe Anforderungen an die Seitenisolation. Material: z.B. Cu oder Poly-Si.
5. e) TSVs nur zur Übertragung von HV-(Analog-/Treiber-)Signalen. Hohe Anforderungen an die Seitenisolation (nur thermische Oxidation, 1 µm SiO2 -400V). Material: z.B. Cu oder Poly-Si. Die ASICs müssen als nächstes kommen.

The TSVs 63 mentioned above can be classified according to their structure and procedure:

1. a) TSVs as purely thermally conductive structures. No side isolation requirements. Material: e.g. Cu.
2. b) TSVs as thermally conductive structures and transmission of low voltage (digital) signals. Low side isolation requirements. Material: e.g. Cu.
3. c) TSVs as thermally conductive structures and transmission of HV (analog/driver) signals. High demands on side insulation. A possible solution includes: Poly-Si TSVs before CMOS for the HV signals and separate Cu TSVs before/after CMOS for the thermal connection. Material: Poly-Si and Cu.
4. d) TSVs only for transmitting LV (digital) signals. Low side isolation requirements. Material: e.g. Cu or Poly-Si.
5. e) TSVs only for transmitting HV (analog/driver) signals. High requirements for side insulation (thermal oxidation only, 1 µm SiO2 -400V). Material: e.g. Cu or Poly-Si. The ASICs have to come next.

• Wenn die TSVs zuerst bearbeitet werden und dann die ASICs:
  • Isolierung der TSV bis 400V, aber TSV muss alle folgenden Hochtemperatur-CMOS-Prozesse überstehen TSV-Material: zum Beispiel Poly-Si.
  • Wenn zuerst ASICs und dann TSVs bearbeitet werden. Eine Herausforderung ist das direkte Testen der ASICs nach der CMOS-Gießerei. Die ICs können nicht an der Oberfläche mit Verdrahtung und Pads fertiggestellt werden, da eine CMP-Planarisierung (chemisch-mechanisches Polieren) für die TSVs, die später erforderlich ist, diese zerstören würde. Daher sind zusätzliche Maßnahmen notwendig: Bearbeitung eines Teils der Wafer, um die Ausbeute der ASICs zu testen, oder Einbeziehung von komplett fertigen Test-ASICs neben den funktionalen Chips, die für Zwischentests verwendet und durch die TSV-Bearbeitung verkratzt werden. Vorzugsweise werden keine Hochtemperaturprozesse, z.B. thermische Oxidation für die TSVs verwendet, um die Isolation der TSVs nicht zu verschlechtern, was zu Kurzschlüssen der HVs führen könnte. ASICs müssen den TSV-Prozess überstehen; DRIE mit MW- und RF-Feldern, Plasma, Hitze, Gase, späteres Bonden, etc.

With regard to the order of processing, the following is proposed according to the invention:

• If the TSVs are processed first and then the ASICs:
  • Isolation of the TSV up to 400V, but TSV must survive all the following high temperature CMOS processes TSV material: for example Poly-Si.
  • If ASICs are processed first and then TSVs. One challenge is testing the ASICs directly after the CMOS foundry. The ICs cannot be surface finished with wiring and pads as CMP (chemical mechanical polishing) planarization for the TSVs, required later, would destroy them. Therefore, additional measures are necessary: processing part of the wafers to test the yield of the ASICs, or including completely finished test ASICs alongside the functional chips used for intermediate tests and scratched by TSV processing. Preferably, no high-temperature processes, such as thermal oxidation, are used for the TSVs in order not to deteriorate the insulation of the TSVs, which could lead to short circuits in the HVs. ASICs must survive the TSV process; DRIE with MW and RF fields, plasma, heat, gases, later bonding, etc.

1. 1. zuerst werden Poly-Si-TSVs bearbeitet und dann ASICs
2. 2. Poly-Si-TSVs werden für die HV-Speisung für die HV-/Treibersignale, dann CMOS-ASICs und schließlich Cu-TSVs für NV und für die thermische Leitfähigkeit vorgesehen.
3. 3. ASICs und dann PECVD-SiO2/Cu-TSVs sind für die NV-Signale (digital) und als thermisch leitende Strukturen vorgesehen. HV-Signale werden durch eine Kaskade von NV-Speisungen erzeugt.

Three preferred solutions according to the present invention include the following sequence of processing steps:

1. 1. Poly-Si TSVs are processed first and then ASICs
2. 2. Poly-Si TSVs are intended for HV power for the HV/driver signals, then CMOS ASICs and finally Cu TSVs for NV and for thermal conductivity.
3. 3. ASICs and then PECVD SiO2/Cu TSVs are intended for the NV signals (digital) and as thermal conductive structures. HV signals are generated by a cascade of LV supplies.

A particularly advantageous embodiment is in 9 and 10 shown. 9 shows a schematic representation of the signals on the array for a single mirror 20.

10 schematically shows an exemplary 3D architecture of the electronics for an array or part of it.

Out of 9 and 10 It can be seen that the only high voltage signal 88 (HVacti; HVset _j ) that needs to be passed through the stack of electronic chips (the TSVs 63*) is the high voltage supply 85 (HVsup) for the analog ASICs used to establish the drive voltages for the Actuators are used (HV driver 86).

The TSVs 63 can be connected directly to the MMA chip 87 via bumps 66 and within the MMA chip via poly-Si TSVs for each actuator for each mirror from the array.

On the top of the middle wafer are the cores (outputs of the ADCs), which form the drive voltages.

With 4 actuators for a synthetic mirror, 4 control voltages are required. For 24 × 24 mirrors, 4 × 24 × 24 control signals are required. They are connected to the mirror substrate and the TSVs HVact _j via bumps. No additional HV-TSVs are required in the front-end ASICs.

But these ADCs require an HV supply, or two: left and right, for greater safety - provided by TSVs 63*. Only these 2x2 or 2x1 TSVs need to be HV compatible. The remaining HV signals are routed directly to the mirror element via the bumps.

The remaining TSVs 63 are made of Cu to conduct the amplified sensor NV signals 89 (sens; sens _j ).

They can also have a connection function between the front-end electronics 91 and the back-end electronics 92, in particular the controller 90.

You can also form dummy TSVs that only have a heat conduction (thermal) function.

Below is a simplified manufacturing flow for chips with TSVs and CMOS circuits with reference to the 11A until 11G and 12A until 12G described.

The 11A until 11G show schematically a simplified and shortened manufacturing process, first for TSVs and then for ASICs in an exemplary variant.

The production of 11A starts with an Init-Si wafer 100.

Alignment marks 101 are then formed for various structuring levels: deposition of photoresist (PR), lithography, development, etching (RIE) of the markings in the silicon and PR stripping (cf. 11B) .

In step 3 (cf. 11C ) contact holes 102 are defined lithographically and etched through using DRIE. To do this, the wafer can be fixed on an adhesive tape or be part of an SOI (silicon on insulator) holder wafer, which is then polished away (not shown here).

Furthermore, the wafer 100 with the contact holes 102 is oxidized for TSV insulation (formation of a thermal SiO2 layer 103 at 1100 ° C (cf. 11D ).

Then the TSVs are filled by (multiple) deposition of a filler 104, which e.g. B. consists of highly doped poly-Si and CMP with a polishing stop on the oxide (cf. 11E) .

In the next step (cf. 11F) thermal insulation 105 is applied to both surfaces. The thermal insulation 105 can be formed as a SiO2 layer deposited at 1100 °C.

This is followed by CMOS processing for the ASICs 106, which is completed with a surface passivation made of PECVD-SiO2 at 350 °C (cf. 11G) .

The 12A until 12G show schematically a simplified and shortened manufacturing process, first for ASICs and then for TSVs in an exemplary variant.

The manufacturing process in 12 starts with the same first two steps as in 11 : Init wafer 100 (cf. 12A) and lithography alignment marks 101 etched in Si with RIE (cf. 12B) .

Afterwards (cf. 12C ), the surface is insulated by thermal oxidation (thermal SiO2 103 at 1100 °C) and the CMOS circuits (ASICs 106) are fabricated, followed by further surface insulation, in particular by low-temperature PECVD SiO2 at 350 °C.

Now the wafers are ready for the formation of contact holes 102 (cf. 12D ) TSV lithography + DRIE through the wafer. For this purpose, the wafer 100 can be fixed on an adhesive tape or is part of an SOI (silicon on insulator) holder wafer that is polished away (not shown here).

The TSVs must be isolated in the next process (cf. 12E) . For this purpose, a PECVD SiO2 is carried out at 350 °C. The CMOS circuits (ASICs 106) remain intact.

Furthermore, the TSVs are filled by a filler 107, in particular by galvanic deposition of Cu and Cu CMP with a stop on the oxide (cf. 12F) .

Finally, the surface is passivated again by PECVD of SiO2 at 350 °C (cf. 12G) .

Both processes are shortened and simplified. What is not shown are steps such as forming the contacts and planar interconnects, bonding/bumping pads, etc.

The 13A until 13K show schematically the implementation of a combined solution with ASICs 106, Poly-Si-TSVs 104 for the HV signals and Cu-TSVs 107 for the NV signals and thermal conductivity.

Processing begins as in 11A first for Poly-Si-TSVs and then for CMOS ASICs: Init-Wafer 100 (cf. 13A) , Alignment Marks 101 (cf. 13B) , DRIE for the contact holes 102 (cf. 13C ), high-temperature insulation (cf. 13D ), filling with highly doped Poly-Si 104 and CMP (cf. 13E) , surface high-temperature oxidation (cf. 13F) and formation of the CMOS part (ASIC 106) (cf. 13G) . Processing then continues with steps 8 to 11, which follow the steps in 12D until 12G correspond to the steps described, namely lithography and DRIE of the NV or thermal TSVs (cf. 13H) , PECVD oxide side insulation at low temperature (cf. 13I ), filling and CMP of Cu (cf. 13y) and final surface passivation at low temperature by PECVD of SiO2 at 350 °C (cf. 13K) .

Below is another example of the arrangement of the electronic components of the microphone rospiegel 20, in particular the front-end electronics 91 and the controller electronics 92, with reference to the 14 and 15 described.

The general details correspond to those of the variants described above and referred to.

In the in the 14 and 15 schematically illustrated embodiment are adjacent chips 205, 206; 206, 207; 207, 208 connected to one another by bonding interface layers 209, 210, 211, 212, 213, 214. This increases the contact area between adjacent chips 205, 206; 206, 207; 207, 208, in particular the contact surface between the MEMS mirror chip 205 and the front-end electronics chip 206 and / or the contact surface between the front-end electronics chip 206 and the controller electronics chip 207 and / or the contact area between the controller electronics chip 207 and an interposer chip 208 is greatly increased.

The contact area between two of these adjacent structures can be at least 50%, in particular at least 70%, in particular at least 90% of their cross-sectional area.

To differentiate between the interposer chip 69 and the interposer chip 208, the latter is also referred to below as interposer 208.

The chips 205, 206, 207 between the mirror substrate 27 and the interposer 208 are preferably thin. In particular, they can have a thickness of at most 100 μm. Their thickness can, for example, be in the range from 50 µm to 200 µm.

The chips 205, 206, 207, 208 can be flexible to allow for out-of-plane bending and twisting. In particular, they can be reversibly deformable.

These chips 205, 206, 207, 208 are connected to each other using hybrid bonding. In particular, they can have one or more full-surface connections.

This greatly reduces the vertical thermal resistance. The main function of the TSVs and the electrical bond pads is to form an electrical contact and a vertical path for signal flow. The mechanical and/or thermal connection between adjacent chips 205, 206, 207, 208 can be established over the entire lateral extent of the chips 205, 206, 207, 208. In particular, the dielectric areas can also contribute to the mechanical and/or thermal connection of adjacent chips. This allows a very low thermal resistance to be achieved. In addition, the thermal resistance can be kept very homogeneous over the lateral extent of the chips 205, 206, 207, 208.

With regard to the mechanical stability of the micromirrors 20, in particular their precise positioning, in particular relative to the tilting axes, they are related to the underlying support structure 60.

The arrangement of the stacked chips can be at least partially, in particular predominantly, in particular completely, decoupled from the carrier structure 60 by means of the interposer 208.

Details of the interposer 208 can be found in the DE 10 2022 209 935.4 referred to, which is incorporated by reference in its entirety. The details of the interposer 208 can also be advantageously combined with the details of other variants of the present application, in particular other variants of the stacked arrangement of electronic components.

Like in the 14 and 15 shown schematically, each substrate (chip) can be provided with one or more connection layers 201 and its front side. The connection layers 201 can serve for the lateral flow of electrical signals and/or for connecting the electrical components and the TSVs.

Each of the substrates (chips) may have at least one redistribution layer 202. The redistribution layer 202 can be attached to the back of the substrate (chip). The redistribution layers 202 enable placement of electrical bonding points independent of the positioning of the TSVs. In contrast to the 14 and 15 The bonding points, in particular the Cu-Cu bonding points, do not have to be arranged above the areas in which the electronic components are positioned. In particular, the bonding points can be moved laterally with respect to the areas in which the electronic components are arranged.

The Cu-Cu bonding points are preferably arranged laterally offset from the electronic components of the electronic component layers 203.

This increases the robustness and reliability of the arrangement.

The substrates (chips) may further contain one or more electronic component layers 203.

The electronic circuits of the controller electronics 92 can be integrated into the controller electronics chip 207. They can be contained in particular in the electronic component layers 203 of the controller electronics chip 207.

The electronic circuits of the front-end electronics 91 can be integrated into the front-end electronics chip 206. They can be contained in particular in the electronic component layers 203 of the front-end electronic chip 206.

Additional electronic circuits can be integrated into the interposer 69. In particular, they can be integrated into the layout of the electronic components 203 of the interposer 69.

The connection layers 201 can ensure a lateral distribution of signals within a substrate (chip).

The chips can span the area of an array of mirrors 20. In particular, the chips can have lateral dimensions that correspond to at least twice, in particular at least four times, in particular at least six times, in particular at least ten times the diameter of an individual mirror substrate 27.

Even if the flat connection between adjacent substrates can lead to advantages with regard to the mechanical and/or thermal conductivity of neighboring substrates, in addition to one or more flat connections, connections through bumps 66 and/or wire connections 72 as described above are also possible.

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• WO 2012/130768 A2 [0003, 0127]
• WO 2015/028450 A1 [0003]
• US 10515886 B2 [0004]
• US 2022/0004107 A1 [0005]
• DE 102011006100 A1 [0006]
• DE 102020120906 A1 [0007]
• US 2019/0018114 A1 [0008]
• DE 102015204874 A1 [0067, 0089]
• WO 2010/049076 A2 [0113]
• EP 1225481 A2 [0117]
• DE 102013206529 A1 [0132]
• WO 2016/146541 A1 [0189, 0223]
• DE 102022209935 [0326]

Claims (16)

Microelectromechanical system (MEMS) for a device with one or more optical components (20) with 1.1. a suspension for an optical component (20), 1.2. one or more actuator elements (62) for displacing the optical component (20) and/or one or more sensor elements (61) for detecting a displacement of the optical component (20) and 1.3. a variety of integrated circuits (ICs) (64, 65, 68), 1.4. wherein the integrated circuits (64, 65, 68) are arranged in a stacked manner and 1.5. where the integrated circuits (64, 65, 68) 1.5.1. at least two different types from the following list: actuator electronics, sensor electronics and control electronics and/or 1.5.2. at least two different types of silicon vias (TSVs), characterized in that it includes different types of electrical connections between different ICs (64, 65, 68), the types of electrical connections from the list of silicon vias (63 ), wire bonds (72) and wire and bump connections (66) are selected. Microelectromechanical system (MEMS). Claim 1 , characterized in that it comprises various ICs (64, 65, 68) having at least two different types of silicon vias (TSVs) selected from the list of - TSVs that serve only as thermally conductive structures - TSVs, which serve as thermally conductive structures and for transmitting LV (digital) signals, - TSVs which serve as thermally conductive structures and for transmitting HV (analog/driver) signals, - TSVs which only serve to transmit NV - (digital) signals and - TSVs, which only serve to transmit HV (analog/driver) signals, are selected. Microelectromechanical system (MEMS). Claim 1 or 2 , characterized in that it comprises different ICs (64, 65, 68) with at least two different types of silicon vias (TSVs) made of different materials and / or with different technologies. Microelectromechanical system (MEMS) according to one of the preceding claims, with one or more interposer chips (69) which only contain connections but no active electronic circuit. Microelectromechanical system (MEMS) according to one of the preceding claims, characterized in that one or more sensor readout ASICs and / or one or more actuator drivers (86) and / or one or more control logic devices (90) are each on different integrated circuits are included, these different integrated circuits being arranged stacked one behind the other. Microelectromechanical system (MEMS) according to one of the preceding claims, characterized in that an IC for the actuator electronics can supply driver signals of at least 100 V. Microelectromechanical system (MEMS) according to one of the preceding claims, with a low-temperature penetration ceramic (LTCC) carrier (76) made of several shells (81, 82, 83) with contact holes 77 and/or wiring layers 78 and/or cavities 79, which serve as pockets for the arrangement of chips 75, the shells (81, 82, 83) being stacked on top of each other. Optical component (20). 8.1. a microelectromechanical system (MEMS) according to one of the preceding claims, 8.2. wherein the MEMS is arranged completely within a base area of the optical component (20). Optical component Claim 8 , characterized in that it comprises a mirror substrate (27) defining a reflection surface (26), the reflection surface (26) having an EUV-reflective coating. Optical component Claim 9 , characterized in that it has an electrode structure with a plurality of radially arranged comb fingers and / or the mirror substrate (27) is suspended on a cardan joint. Optical component according to one of the Claims 8 until 10 , characterized in that it comprises an array of a plurality of micromirrors (20). Illumination optics (4) for a lithography system (1) with one or more optical components Claim 9 . Lighting system (2) with 13.1. a lighting source (3) and 13.2. a lighting optics (4). Claim 10 . Projection optics (7) for a lithography system (1) with one or more optical components Claim 9 . Lithography system (1) with one or more optical components according to one of Claims 9 until 11 . Method for producing a MEMS according to one of Claims 1 until 7 with the following steps: 16.1. Providing a plurality of separate integrated circuits (64, 65, 68), 16.2. Arranging the integrated circuits (64, 65, 68) in stacked form, 16.3. wherein at least two different integrated circuits (64, 65, 68) are manufactured using different technologies and/or processed using different methods and/or wherein at least two different integrated circuits (64, 65, 68) have TSVs of different types.

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