DE102023126167A1 - QRNG with PRNG usage, associated procedure and associated data processing system - Google Patents

Abstract

The invention relates to a quantum process-based generator (28) for true random numbers (411, 418) (English: Quantum Random Number Generator: QRNG). The quantum process-based generator (28) for true random numbers (411, 418) has an entropy source (401). The quantum process-based generator (28) for true random numbers (411, 418) evaluates a signal (405) of the entropy source (401) by means of a time-to-pseudo-random number converter (TPRC) (404.3) and generates one or more random bits (411) and possibly random numbers (418).

Description

priorities

This patent application takes priority over the German patent application EN 10 2022 125 574.3 from 04.10.2022.

Field of invention

The invention is directed to a microcontroller that includes at least one quantum process-based generator for true random numbers (QRNG) as a random number generator, in particular for encryption. The present invention includes in particular a random number generator (RNG), in particular a true random number generator (TRNG) of an improved type based on quantum processes and the evaluation of the signal of the entropy source by means of pseudorandom number generators (PRNG) that are located within the entropy extraction.

The present invention thus relates to a data processing device with a quantum technology-based random number generator.

Background of the invention

The automotive industry and other industries are increasingly exposed to various piracy attacks. The counterfeiters copy the spare parts and products of the industrial producers concerned and usually use their brand names. Another point of attack is the data transfer within the products and/or the data transfer to the product and back.

The entropy properties of common random number generators for such systems are typically inadequate. Quantum process-based generators for true random numbers (QRNGs) are known from the state of the art, but they are difficult to integrate or show a poor quantum yield.

It is well known that random number generators are currently used in many applications ranging from science to cryptography.

From the state of the art, in particular the technical teaching of EP 3 529 694 B1 known, in which the time duration between pulses of an entropy source consisting of two SPAD diodes is used. Disadvantage of the technical teaching of EP 3 529 694 B1 is the low quantum efficiency in the transfer of photons from the first SPAD diode, which operates as silicon, to the second SPAD diode, which operates as a photodiode. The document presented here therefore quotes sections of statements by the authors and inventors in the EP 3 529 694 B1 The document presented here uses the technical teaching of EP 3 529 694 B1 and builds on the technical teaching of the WO 2023 072 956 A1 , the technical teaching of which is repeated in the document presented here in connection with the solution of the problem.

“A typical example of the first case is computer science, which requires the generation of a certain number of random initial states that serve as a description of the initial state of the simulation.

For this type of application, it is generally necessary that the initial configurations are not strictly correlated with each other, but can be reproduced in a deterministic way, for example to check the effects of variations on the codes that perform the simulations. For this reason, these sequences are more correctly called pseudorandom numbers (PRN), since they are defined by complex algorithms that start from an initial value. In other words, given an initial random number, known in technical jargon as a "seed", a formula, no matter how complex, will always reproduce the same sequence of random numbers. The corresponding generators are called pseudorandom number generators (PRNG).

In the second case, however, i.e. when random numbers are used in cryptography techniques to perform e.g. banking operations, the approach described above seems to be weak, since it must be ensured that the generated sequences are absolutely unpredictable in order to be able to guarantee the security of highly sensitive information. In this case, the safest approach is to generate generation of random numbers that come from a generation process that must be truly random and must not allow any prediction of the generated sequence. These generators are called True Random Number Generators (TRNG). In particular, quantum mechanisms, such as the generation of photons by a light source, are among the best studied methods for obtaining said sequences of true random numbers and are based on the uncertainty of the measured event, which is one of the properties of the quantum system itself.

From the point of view of information theory, the degree of unpredictability of the random numbers generated using the two techniques mentioned above can be expressed by the parameter “entropy”, which is known as the uncertainty or information present in a random variable.

In addition, it is important to emphasize that the National Institute of Standards and Technology (NIST) in its NIST SP800-22 guideline specifies about fifteen statistical tests that can be used to determine whether a given random number generator has a sufficient level of entropy or not.

As mentioned above, using PRNGs for cryptographic purposes is dangerous not only because certain algorithms have weaknesses that may not become apparent until some time after their introduction, but also because a malicious person who could recover the seed from which all random sequences are generated could predict all subsequent outputs based on the same seed with absolute certainty.

A solution based on physical phenomena, and in particular quantum phenomena, is therefore much more suitable, given the inherent unpredictability of these events, even for people with a thorough knowledge of the algorithms used and with a high computational capacity. However, while the algorithms for generating pseudorandom numbers can be chosen to generate sequences with certain statistical properties that can be determined with absolute certainty due to their deterministic nature, the random numbers obtained from physical phenomena are subject to practical limitations due, for example, to variations in the production quality of the equipment, to variations in the power supply, to environmental factors such as external fields and temperature variations. These deviations from the ideal case generally entail a deviation from a statistical uniform distribution that is independent of the events that can be measured in a sample space. As a result, it is possible to observe even a reduction in the entropy of the said true random number generators.

To avoid this drawback, the said True Random Number Generators require a further step, the so-called post-processing, which is carried out after the extraction of the random code sequence, starting from the specific physical phenomenon. This post-processing step indeed makes it possible to improve the uniformity of the probability distribution of the random code sequence. The disadvantage, however, is that this post-processing step affects the bit rate that the generator can guarantee.

As already mentioned, it is also known that one of the physical phenomena most used to generate truly random numbers is quantum photonics. For this reason, these generators, which belong to the macro category of TRNGs, are also called by the acronym QRNG (Quantum Random Number Generator). In these generators, an attenuated light source generates a few photons (low value of the detected photon flux λ) that are detected by one or more single-photon detectors, each of which is known by the acronym SPAD (Single Photon Avalanche Diode). In addition, the system includes appropriate electronic circuits downstream of the aforementioned SPADs, consisting of auxiliary circuits and, usually, one or more TDCs (Time to Digital Converters) or counters capable of extracting a random bit sequence from each of the SPADs by measuring the arrival time of the detected photons or by counting them.

In these generators, the light source and the detector(s) are separate devices that must be coupled and shielded in an appropriate manner. The disadvantage, however, is that this design is of course not immune to the influence of uncontrolled external environmental factors. In addition, the fact that the light source and the detector(s) are separate devices that are coupled one after the other makes the entire random number generator very vulnerable to any kind of influence or manipulation.

Another disadvantage is that this implementation entails high costs for the device because the two devices have to be optically aligned.

Having said the above, it should be noted that there are several types of random number generators based on the QRNG concept available on the market. These generators cover a wide range of applications, from portable USB devices that deliver only a few hundred kbit/s to large electronic systems that can guarantee a bit rate of hundreds of Mbit/s. In addition, in the existing literature on the subject, several logics and architectures have been proposed that are designed to determine sequences of truly random numbers starting from a physical phenomenon, in particular from photon detection. Most of them record the “arrival time”, or the number of photons that hit the sensitive surface of the SPAD detector(s). An example of a well-known quantum random number generator based on arrival time can be found in the international publication WO 2016 016 741 A1 .

In particular, the technique based on the so-called arrival time has been proposed to measure the time elapsed between the moment when a photon comes into contact with a single SPAD and the moment when the subsequent photon comes into contact with the same SPAD. Although this technique allows a high bit rate to be achieved, it suffers from significant distortion because, as explained above, the photon source obeys the Poisson process.

To overcome this drawback, the state of the art proposes to act directly on the photon source to control the flux of photons produced by this source. This operation involves in particular varying the pilot current of the photon source in order to make its statistical distribution over time as uniform as possible.

The disadvantage of this approach, however, is that a special electronic circuit must be built into the random number generator that can control the photon source, as explained above, which increases the complexity and size of the generator itself."

Task

The present invention aims to overcome all the above-mentioned drawbacks. In particular, an object of the invention is to provide a true random number generator that makes it possible to guarantee a high level of entropy, so that it at least passes the statistical tests defined by NIST.

A further aim of the invention is to provide a generator for true random numbers which makes it possible to achieve an even higher bit rate in the generation of random sequences of bits and to ensure the randomness of the measurement result even if the entropy source fails.

Another object of the invention is to provide a true random number generator having a more compact, robust and less complex structure than the random number generators known in the prior art, so that this random number generator can be accommodated in the pad edge of a monolithically integrated semiconductor circuit.

Another object of the invention is to provide a true random number generator that offers a high level of security against any attempt to forcibly alter or tamper with its internal components.

Another object of the invention is to provide a true random number generator that offers a high level of security by detecting and reporting any attempt to forcibly alter or tamper with its internal components.

A further, but no less important, object of the invention is to provide a true random number generator which is more economical compared to the generators of the known prior art.

The device of the independent claim solves this problem. Further developments are the subject of the subclaims.

Solution to the task

The automotive industry and other industries are increasingly exposed to various types of piracy attacks. Counterfeiters copy the spare parts and products of the industrial producers concerned and usually use their brand names. Another point of attack is the data transfer within the products and/or the data transfer to the product and back.

The entropy properties of common random number generators for such systems are typically inadequate. Quantum process-based generators for true random numbers (QRNGs) are known from the state of the art, but they are difficult to integrate or show a poor quantum yield.

It is known in the art to provide an integrated circuit which includes, among other features, a processor. In some applications, it is necessary to ensure that the data being processed, including the executable code, cannot be modified by unauthorized persons accessing data stored outside the integrated circuit or, if such access does occur, that it cannot be done unnoticed.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, there is provided a device comprising: a preferably one-piece, preferably monolithic, micro-integrated circuit comprising one or more processors (10-1, 10-2) and one or more non-volatile memories, preferably storing at least one security code; a first preferably read/write memory external or internal to the integrated circuit for storing data, the data preferably being cryptographically protected in a first format; and preferably a second read/write memory external or internal to the integrated circuit for storing data; the device being arranged to transfer data from the first memory to the second memory via a device of the integrated circuit for access by the processor from the second memory; the integrated circuit is arranged to validate the data read from the first memory during transmission using a security code stored in the non-volatile memory and, when the data is validated, to apply cryptographic protection in a second format to the validated data using a security code stored in the non-volatile memory and to store the data protected in the second format in the second memory. The proposed device uses a quantum technology-based micro-integrated random number generator (QRNG 28) for encryption. Such a random number generator delivers a true random number because the process of random number generation is based on an unpredictable quantum process.

By transmitting data over the integrated circuit devices and using the integrated circuit devices to validate data and protect the transmitted data, security is maintained because validation occurs and protection is applied within the integrated circuit.

The data is secured by cryptographically protecting the data in the first and second memories based on one or more security codes in the non-volatile memory of the integrated circuit.

In one embodiment, only validated data from the first memory is processed, and when data is read by the processor from the second memory, only validated data from the second memory is processed.

In one embodiment, the second memory is a random access memory (RAM) for the processor that allows the processor to store and retrieve individual words that are individually protected, as opposed to the first memory, which is a read-only memory (ROM) that allows only read access to a record.

• Eine integrierte Schaltung mit einem Prozessor, einem nichtflüchtigen Speicher, der mindestens einen Sicherheitscode speichert, einem Hash-Rechner und einer Schnittstelle an der Grenze der integrierten Schaltung; und einen Speicher innerhalb oder außerhalb der integrierten Schaltung zum Speichern von Daten zur Verwendung durch den Prozessor, wobei der Speicher, wenn er außerhalb der integrierten Schaltung liegt, vorzugsweise über eine Schnittstelle an der Grenze der integrierten Schaltung mit dem Prozessor gekoppelt ist, um Daten beispielsweise in Form von Datenwörtern vom Prozessor zu empfangen und Datenwörter an den Prozessor zu liefern. Der Prozessor und der Hash-Rechner sind so angeordnet, dass sie die Schritte
  1. a. Berechnen des Hashs mittels einer Hash-Funktion für jedes Datenwort in Abhängigkeit von einem in dem nichtflüchtigen Speicher gespeicherten Sicherheitscode und Speichern des Hashs in Verbindung mit dem Datenwort,
  2. b. Abrufen gespeicherter Datenwörter aus dem Speicher, Neuberechnen einer Hash-Funktion für jedes abgerufene Datenwort unter Verwendung des Sicherheitscodes und Vergleichen des neu berechneten Hash-Wertes mit dem gespeicherten Hash-Wert, und
  3. c. Zulassen des Verarbeitens des abgerufenen Datenworts durch die Datenverarbeitungsanlage nur dann, wenn die neu berechneten Hashes und die gespeicherten Hashes eine vorher festgelegte Beziehung aufweisen.

The invention also provides a data processing device comprising:

• An integrated circuit comprising a processor, a non-volatile memory storing at least one security code, a hash calculator and an interface at the boundary of the integrated circuit Circuit; and a memory inside or outside the integrated circuit for storing data for use by the processor, the memory, when outside the integrated circuit, preferably being coupled to the processor via an interface at the boundary of the integrated circuit for receiving data, for example in the form of data words, from the processor and for supplying data words to the processor. The processor and the hash calculator are arranged to carry out the steps
  1. a. Calculating the hash using a hash function for each data word depending on a security code stored in the non-volatile memory and storing the hash in connection with the data word,
  2. b. retrieving stored data words from the memory, recalculating a hash function for each retrieved data word using the security code and comparing the recalculated hash value with the stored hash value, and
  3. c. Allowing the data processing system to process the retrieved data word only if the newly calculated hashes and the stored hashes have a predetermined relationship.

Embodiments of the proposal will now be described by way of example with reference to the accompanying drawings.

In particular, the true random number generator (quantum random number generator 28) according to the invention comprises a photon source 54 with a flux of detected photons λ of light 58 transported horizontally in an optical fiber 44, one or more photon detectors 55, preferably single photon detectors (SPADs), and electronic sampling means (403, 2022, 402, 403, 404.2) operatively connected to the one or more photon detectors 55 to generate a bit sequence of quantum random bits 411 (random bit sequence) based on the number of photons detected in the photon detectors 55.

The said generator for true random numbers, hereinafter referred to as quantum random number generator 28 (QRNG), is characterized in particular in that the photon source 54 and the photon detector(s) 55 are arranged as close to one another as possible and optically directly or indirectly coupled and are integrated in a single semiconductor substrate 49. Preferably, the photon source 54 and the photon detector(s) 55 are manufactured in a common semiconductor substrate 49 using CMOS technology, preferably BCD technology. Preferably, the photon source 54 comprises a silicon LED and/or a silicon laser. For example, the photon source 54 can comprise a first SPAD diode 54. For example, the photon detector 55 can comprise a photodiode. For example, the photon detector 55 can comprise a second SPAD diode 55.

The quantum random number generator 28 according to the invention preferably comprises a photon source 54 with a detected photon flux equal to A

It cannot be ruled out that the quantum random number generator 28 in an alternative embodiment comprises more than one photon source 54. However, this has the disadvantage of requiring a larger chip area.

According to the preferred embodiment of the proposal, the proposed quantum random number generator 28 preferably further comprises an arrangement of one or more photon detectors 55.

Preferably, but not necessarily, each of these photon detectors 55 is a single photon detector 55. When one or more photon detectors 55 are implemented as reverse biased PN diodes in a semiconductor substrate 49 with a bias voltage close to the breakdown voltage of the respective PN diode and a limitation of the breakdown current of the respective PN diode, one generally speaks of single photon avalanche photo diodes, which the document presented here also refers to with the acronym SPAD.

As already mentioned, a single photon detector 55 is capable of detecting and providing as output information on the incidence of a single photon in its sensitive volume and possibly on the arrival time of the latter within an observation window of predetermined duration.

Between two consecutive observation windows, each photon detector 55 (every second SPAD diode 55) goes through a phase of restoring the initial conditions, which the document presented here hereinafter refers to as dead time. During the dead time of a second SPAD diode 55, this second SPAD 55 can no longer reliably detect any subsequent photon.

Typically, in the SPAD-type array of photon detectors 54, each respective SPAD diode 55 operates independently and in parallel with the other SPAD diodes 55. Typically, the array of SPAD diodes 55 has a single common output for reading the respective signal generated by the same array of SPAD diodes 55 from the outside.

The typical advantage of an arrangement of closely spaced SPAD diodes 55 is typically that the solid angle of the photons 58 generated by the photon source 55 is increased and that any dead times are reduced, thereby increasing the generation rate of the quantum random bits 411 of the quantum random number generator 28 and thus the rate of the quantum random data words 418 themselves. This in turn enables the encryption of larger amounts of data.

While the technical teaching of the EP 3 529 694 B1 still assumes a coupling via the semiconductor substrate 49, the technical teaching presented here proposes a first improved coupling of the photon source, i.e. for example the first SPAD diode 54 and/or the silicon LED, with the photon detector 55, i.e. here for example with the second SPAD diode 55, via a light-optical system, for example an optical waveguide 44, which should have a significantly lower absorption rate than the common semiconductor substrate 49 in which the photon source 54 and the photon detector 55 are manufactured. As a result, the generation rate of the quantum random bits 411 of the quantum random number generator 28 increases dramatically again compared to a device according to the technical teaching of EP 3 529 694 B1 at.

However, it cannot be ruled out that according to an alternative embodiment of the proposal, the quantum random number generator 28 always comprises an array of second SPAD diodes 55 as an array of photon detectors 55, but each SPAD diode 55 or each photon detector 55 is independent of the others, which means that these device parts can each individually generate a respective signal to the outside, which is typically independent of the signals of the other SPAD diodes 55 or of the other photon detectors 55. According to another embodiment of the proposed quantum random number generator 28, the arrangement can be divided into subgroups of SPAD diodes 55 or subgroups of photon detectors 55, each subgroup comprising a predetermined number of SPAD diodes 55 or photon detectors 55, which are preferably each connected in parallel to one another such that they each generate a single signal outwardly related to the entropy source 401 of the quantum random number generator 28.

In the latter case, each of the subgroups of SPAD diodes 55 or photon detectors 55 can be connected to the outside world of the entropy source 401 of the quantum random number generator 28 independently of the other subgroups of SPAD diodes or photon detectors.

This independence has the advantage that the extraction of the binary random sequences from quantum random bits 411 from the quantum random number generator 28 can be parallelized, whereby the bit rate of the quantum random number generator 28 is further increased by spatial multiplexing.

According to another embodiment, the quantum random number generator 28 of the proposal can also comprise only exactly one second SPAD diode 55 or only exactly one photon detector 55.

Again, a further embodiment of the quantum random number generator 28, as already mentioned, can comprise a plurality of photon sources 54 or silicon LEDs 54 or first SPAD diodes 54, which are each optically connected to an array of photon detectors 55 or second SPAD diodes 55 via an optical system (44) outside the semiconductor substrate 49. Preferably, this optical system 44 comprises micro-optical device parts. Preferably, these micro-optical device parts comprise one or more optical waveguides 44 and/or one or more reflective layers 53 and/or reflective and/or optically refractive structures 53. Preferably, the optical waveguide 44 is manufactured in the metallization stack on the semiconductor substrate 49 of the microelectronic circuit, which typically comprises the photon source or the silicon LED 54 or the first SPAD diode 54 and the photon detector 55 or the second SPAD diode 55. The optical system - for example the Optical waveguides 44 - the photon sources 54 and the photon detectors 55 are therefore preferably part of the integral quantum random number generator 28.

In other words, if the combination of a photon source 55 or a silicon LED 54 or a SPAD diode 54 on the one hand with one or more photon detectors 55 or one or more SPAD diodes 55 on the other hand defines pixels in the sense of the document presented here, one embodiment of the entropy source 401 of the proposed quantum random number generator 28 can be viewed, for example, as a pixel matrix which makes it possible to parallelize the process of extracting random numbers.

As regards the photon source 54 or the silicon LED 54 or the first SPAD diode 54, according to a preferred embodiment, this also preferably comprises one or more SPAD diodes 54. In this case, both the arrangement of the photon detectors 54 or the second SPAD diodes 54, which serve as receivers, and the photon sources 54 or the silicon LEDs 54, which preferably comprise one or more SPAD diodes 54, are configured and polarized such that they operate in the so-called Geiger mode with the same polarization voltage.

As already mentioned above, the quantum random number generator 28 of the proposal preferably also comprises electronic sampling means (403, 2022, 402, 403, 404.2) which are preferably functionally connected to the common output 417 in order to read the signal 405 generated by the arrangement of the photon detectors 54 or the second SPAD diodes 54.

It is conceivable that in another embodiment, one or more of the respective electronic sampling means (2022, 402, 403, 404.2) are instead provided for each respective photon detector 54 or each respective second SPAD diode 54, respectively, which each belongs to the array, while individual electronic sampling means of the electronic sampling means (2022, 402, 403, 404.2) are present for the respective individual photon detector 54 or for the respective individual second SPAD diode 54. Finally, in one embodiment, some or more respective sampling means of the electronic sampling means (2022, 402, 403, 404.2) can be provided for each pixel, the sampling signals (407, 407) of which are combined into a common quantum random bit data stream 411 by means of electronic post-processing.

The document presented here proposes to manufacture these electronic scanning means (403, 2022, 402, 403, 404.2) together or at least in large parts with the photon sources 54 or silicon LEDs 54 or first SPAD diodes 54 and together with the photon detectors 55 or the second SPAD diodes 55 in a common semiconductor substrate 49 as a one-piece micro-integrated circuit. The document presented here proposes electrically connecting these electronic scanning means (403, 2022, 402, 403, 404.2) together with the photon sources 54 or silicon LEDs 54 or first SPAD diodes 54 and together with the photon detectors 55 or the second SPAD diodes 55 via the metallization stack of the one-piece micro-integrated circuit thus manufactured on the surface of the semiconductor substrate 49 by means of metallic electrical conductors. The document presented here proposes optically connecting these photon sources 54 or silicon LEDs 54 or first SPAD diodes 54 and together with the photon detectors 55 or the second SPAD diodes 55 via the metallization stack of the one-piece micro-integrated circuit thus manufactured on the surface of the semiconductor substrate 49 by means of dielectric optical waveguides 44. The metallization stack of the one-piece micro-integrated circuit thus manufactured on the surface of the semiconductor substrate 49 typically comprises structured metal layers which typically form the electrical conductor tracks (141, 142) in different levels of the metallization stack. The metallization stack of the one-piece micro-integrated circuit thus manufactured on the surface of the semiconductor substrate 49 typically comprises electrical insulation layers between these structured metallization layers (141, 142), which electrically insulate the electrical lines (141, 142) formed in the structured metallization layers between different metallization levels. The electrical insulation layers of the metallization stack of the one-piece micro-integrated circuit thus produced on the surface of the semiconductor substrate typically comprise electrical vias 140 between the electrical lines (141, 142) of the structured metallization layers, which electrically connect (via-contact) the electrical lines (141, 142) formed in the structured metallization layers between these different metallization levels. The metallization stack of the one-piece micro-integrated circuit thus produced on the surface of the semiconductor substrate 49 typically comprises optically transparent electrical insulation layers between these structured metallization layers. As a result, one or more electrical insulation layers can perform the function an optical waveguide 44 for the photons of the first SPAD diode 54 or the photon source 54 or the silicon LED 54 during their transport to the second SPAD diode 55 or the photon detector 55. The respective insulation layers are preferably structured for this purpose.

In any case, the electronic sampling means (403, 2022, 402, 403, 404.2) of such a one-piece microelectronic circuit are preferably configured to implement a predefined logical method or a computer or hardware implemented algorithm for extracting a binary sequence of quantum random bits 411 based on the arrival times of the photons at the level of the respective photon detectors 55 or SPAD diodes 55. Some preferred examples of the logical extraction method are described in detail in the document presented here below.

According to the proposal, in the quantum random number generator 28, the photon source 54 or the silicon LED 54 or the first SPAD diode 54 and the array of photon detectors 55 or of second SPAD diodes 55 or the individual SPAD detector 54 are arranged next to one another or one below the other and preferably close to one another with a short optical connection for optical coupling via the shortest possible optical path and integrated into a single semiconductor substrate 49 as a microelectro-optical system.

This results in the photon current λ generated by the photon source 54 or the silicon LED 54 or the first SPAD diode 54 flowing, for example, through the optical waveguide 44 in the metallization stack of the microelectronic circuit in the direction of the preferably nearby arrangement of photon detectors 55 or second SPAD diodes 55 (a phenomenon actually known as "optical crosstalk"), unlike in the known random number generators in which the same photons flow through the empty coupling gap between the two components, which are physically separated from each other, i.e. are typically not manufactured in one piece with the scanning means on a semiconductor substrate 49.

Advantageously, this integrated configuration makes the quantum random number generator 28 proposed in this document more compact and structurally less complex than random number generators of the known type.

Thanks to the integral integration of all components of the quantum random number generator 28, it is also more robust and immune to external environmental influences and to any attempts at manipulation by malicious persons.

A metal cover 142 made of a preferably soft metal and/or a material with good electrical conductivity, for example a gold layer on an iron layer, can shield the entropy source. Preferably, an electrical connection, which can also include vias (e.g. 140), connects the metal cover 142 to a defined electrical potential, for example a ground line or a supply voltage line.

This integrated configuration and thus the direct and/or indirect coupling between the photon source 54 or the silicon LED 54 or the first SPAD diode 54 on the one hand and the photon detector(s) 55 or the second SPAD diodes 55 on the other hand are advantageous over solutions using, for example, discrete beam splitters, since they enable uniform illumination of the photon detectors 55 or the second SPAD diodes 55 without having to ensure that the beam splitter is always perfectly aligned.

According to the preferred embodiment of the invention, the photon source 54 or the silicon LED 54 or the first SPAD diode 54 and the array of photon detectors 55 or the second SPAD diodes 55 are manufactured on the semiconductor substrate 49 in the same manufacturing steps, so that the elements have the same chemical-physical structure with respect to the doping profiles. More precisely, as mentioned above, even the photon source 54 or the silicon LED 54 or the first SPAD diode 54 can be manufactured with the same chemical-physical structure as another photon detector 55 or another second SPAD diode 55. The photon source 54 or the silicon LED 54 or the first SPAD diode 54 is, in terms of design and implementation, completely identical to the photon detectors 55 or the second SPAD detectors 55 belonging to the array in certain embodiments of the proposal, except for usual variations of components on a wafer.

This has the advantage that the manufacturing costs of the various components of the proposed quantum random number generator 28 can be drastically reduced, since it is possible to manufacture one or more photon sources 54 or silicon LEDs 54 or first SPAD diodes 54 and/or one or more photon detectors 55 or SPAD diodes 55 on the same semiconductor substrate 49 without the number of manufacturing steps having to be changed, in particular increased. The manufacturing costs therefore remain approximately the same.

According to the preferred embodiments of the proposal, the semiconductor substrate 49 is a silicon substrate 49.

However, it cannot be ruled out that in various embodiments of the invention the semiconductor substrate 49 is made of a semiconductor material other than silicon in order to increase the efficiency of the emitter-source coupling. The document presented here mentions in this context in particular the use of direct semiconductors with a direct transition for the electrons without lattice collision for momentum change.

As regards the arrangement of the photon detectors 55 or the second SPAD diodes 55, it is known that preferably each of them mainly comprises a favourably doped p-n junction, so that the phenomenon known in technical terms as "avalanche formation" can occur when the same photon detector 55 or SPAD diode 55, which is favourably polarized, is subjected to the impact of a photon in its photon-sensitive volume.

The photon source 54 or silicon LED 54 or first SPAD diode 54 is also defined by an appropriately doped p-n junction such that the detected photon flux λ is generated when the photon source 54 or silicon LED 54 or first SPAD diode 54 is appropriately biased in the forward direction or (better) in the reverse direction. When a first SPAD diode 54 is polarized in the reverse direction, a pulsed dark current of the diode current is produced, the so-called dark current, which is associated with a pulsed emission of photons that the photon detector 54 or the second SPAD diode 55 can detect.

In particular, according to the preferred embodiment of the invention, the photon source 54 or silicon LED 54 or first SPAD diode 54 is configured to obtain an emission spectrum of the detected photon flux λ which lies mainly between 800 nm and 1000 nm. In this spectrum, the efficiency of each photon detector 55 or each second SPAD diode 55 cannot be considered to be excessively high and is less than 10%. Therefore, it is estimated that in order to achieve a detection rate of, for example, about 500,000 counts/sec. a usable photon rate (photon current that reaches the sensitive volume of the photon detector 55 or the second SPAD diode 55 or the photon detectors 55 or the second SPAD diodes 55 from the photon source 54 or silicon LED 54 or first SPAD diode 54) of more than 5,000,000 ph/sec is required.

Returning to the fabrication of the quantum random number generator 28, the fact that the structures of the photon source 54, the silicon LED 54, and the first SPAD diode 54 both have a p-n junction as their main feature confirms the advantage described above, i.e. the possibility of performing the same fabrication steps for the photon source 54, the silicon LED 54, and the first SPAD diode 54 and the photon detectors 55, and the second SPAD diodes 55, respectively.

Preferably, but not necessarily, according to the preferred embodiment of the invention, the photon source 54 or the silicon LED 54 or the first SPAD diode 54 and the photon detectors 55 or the second SPAD diodes 55, which are obtained by the same manufacturing steps, have the same chemical-physical structure. However, it cannot be ruled out that in different embodiments of the quantum random number generator 28 according to the invention, the photon source 54 or the silicon LED 54 or the first SPAD diode 54 and the photon detectors 55 or the second SPAD diodes 55 can be manufactured with different chemical-physical structures, in particular with different sizes and/or different doping levels, even if they are obtained by the same manufacturing steps.

As far as the technology for integrating these components into the semiconductor substrate 49 is concerned, according to the preferred embodiment of the invention, it is the CMOS or CMOS-compatible technology of microfabrication of microintegrated circuits. Very particularly preferred for the manufacture of the above The one-piece microelectronic circuit of the quantum random number generator 28 also uses so-called BCD technologies.

BCT technologies are key technologies for integrated power circuits. A BCD technology is the combination of bipolar electronic components (e.g. bipolar transistors and/or PN diodes) with CMOS components (e.g. CMOS transistors or CCD arrays) with DMOS components (e.g. a DMOS transistor)

The DMOS transistor typically comprises a double-diffusion structure in which the p-region and the n-region serve as lines. It is a type of DMOS power transistor designed for radio frequency (RF) applications. It can operate with relatively high supply voltages of 50 to 100 V and is characterized by high reliability, peak performance and robustness. A DMOS transistor (double-diffused metal-oxide-semiconductor transistor) is a crucial element in integrated microelectronic circuits. In contrast to conventional CMOS transistors, a DMOS transistor is characterized by specific features that define its function and areas of application.

A DMOS transistor has a special structure. In this structure, doping regions with different electrical charge carrier concentrations are present in the semiconductor material. These doping regions enable the DMOS transistor to switch higher powers and offer a lower on-resistance compared to CMOS transistors. These properties are particularly advantageous in high-performance applications. In the present case, DMOS transistors are suitable for use in the voltage converters 91 of the monolithic integrated circuit. At the same time, BCD technologies enable the compact manufacture of the first SPAD diodes for the photon sources 54 and the second SPAD diodes 55 for the photon detectors 55. Since the first SPAD diodes 54 typically require a higher supply voltage when used as photon sources 54, the voltage converters 91 very often comprise a charge pump or the like to supply the first SPAD diodes 54 with the required high supply voltage. The DMOS transistors mentioned are particularly suitable for these charge pumps in the voltage converters 91 of the one-piece micro-integrated circuit of the quantum random number generator 28. Therefore, a co-integration of the entropy source 401 with at least one DMOS transistor or several DMOS transistors on a common semiconductor substrate 49 is particularly advantageous. Preferably, therefore, a voltage converter 91 of a one-piece microelectronic integrated circuit of a quantum random number generator 28 comprises at least one, preferably several DMOS transistors. Preferably, the DMOS transistors of a respective voltage converter 91 of a one-piece microelectronic integrated circuit of a quantum random number generator 28 are located in a half-bridge or an H-bridge circuit within this voltage converter 91. Preferably, in the case of a half-bridge, an energy storage device, for example a capacitor, is connected with a connection to the output node of this half-bridge and can then be recharged by this. Preferably, in the case of an H-bridge, an energy storage device, for example a capacitor, is connected with a first connection to the output node of the first half-bridge of the H-bridge and with a second connection to the output node of the second half-bridge of the H-bridge and can then be recharged by this. Preferably, such a voltage converter 91 then comprises an electronically controlled transfer switch which, after switching up the voltage at one connection of the capacitor, can connect the other connection to a photon source 54 or a silicon LED 54 or a first SPAD diode 54. This step-up technology for the supply voltage can also be multi-stage in order to achieve larger voltage swings. A further voltage converter 91 and an energy storage device, for example a further capacitor, can be connected downstream and upstream of the entropy source 401 or the photon source 54 or the silicon LED 54 or the first SPAD diode 54 in order to stabilize the supply voltage of the photon source 54 or the silicon LED 54 or the first SPAD diode 54. Preferably, the half-bridge and/or the H-bridge and/or the transfer switches of the voltage converter 91 comprise DMOS transistors in order to be able to provide higher supply voltages and thus increase the quantum random bit data rate of the quantum random bits 411, since the increase in the supply voltage leads to an increase in the pulse density of the entropy source.

Another characteristic feature of a DMOS transistor is its ability to handle higher voltages, making it ideal for such high voltage applications. This aspect distinguishes it from CMOS transistors, which are usually designed for lower voltages.

The word BCD technology stands for Bipolar CMOS-DMOS technology. BCD technology is a family of silicon processes that each combine the strengths of three different process technologies on a single chip, enabling compact, one-piece quantum random number generators in the form of a single micro-integrated circuit 2.

The advantage of the CMOS microfabrication technology, more precisely the BCD microfabrication technology, is that it is possible to integrate the sampling means (403, 2022, 402, 403, 404.2) for the output signals of the array of photon detectors 55 or the second SPAD diodes 55 into the semiconductor substrate 49.

An example of a possible quantum random number generator 28 of the proposal obtained by the BCD microfabrication technique preferably uses a p-type doped substrate/epitaxial structure 100. The manufacturing process typically creates a deep n-well in the p-type doped substrate/epitaxial structure 100 and the connections defining the photon source 54, the silicon LED 54 and the first SPAD diode 54, respectively, are made with a p+ type implant 102. In order to avoid electric fields that are higher at the edges of the sensitive region than in the center thereof, “guard ring” structures are preferably provided, forming a p-well ring around the p+ implant 47.

However, it cannot be excluded that in various embodiments of the invention, the technique used to manufacture the photon source 54 or the silicon LED or the first SPAD diode 54 may be a custom-made type technique. The advantage of this last solution is that the manufacturing steps of the quantum random number generator 28 according to the invention can be optimized to obtain the photon source 55 and/or the silicon LED 55 or the second SPAD diode 55.

According to an example of implementing a quantum random number generator 28 with a custom manufacturing technique, the photon detectors 55 or the second SPAD diodes 55 and the photon source 54 or the silicon LED 54 or the first SPAD diode 54 may be integrated into a doped p-type epitaxial structure/substrate, wherein a so-called “flat” implant and an enhancement implant are defined in the epitaxial structure, wherein the “flat” implant is more superficial, of n+ type and concentric to the epitaxial structure, but has a smaller extension, and the enhancement implant is of p- type and has a lower doping, but in any case a higher doping than that of the epitaxial structure.

In this way, a so-called "virtual guard ring" structure is created. In order to avoid problems related to "charge crosstalk" or "charge injection" caused by the common epitaxial structure of the two implants, it is possible either to separate the photon source 55 or the silicon LED 55 or the SPAD diodes 55 and the photon detector(s) 54 or silicon LED 54 or first SPAD diodes 54 by arranging them at suitable distances, or to create deep trenches which surround both the region of the photon source 54 or silicon LED 54 or first SPAD diode 54 and the region of the photon detector(s) 55 or second SPAD 55. Finally, it is possible to create an auxiliary connection which, when suitably biased, collects the excess charge that can be transferred from the photon source 54 or the silicon LED 54 or the first SPAD diode 54 to the photon detector(s) 55 or the second SPAD diode(s) 55. The creation of trenches would also reduce optical crosstalk, which is again a desired property. However, this reduction does not exceed a percentage of the order of 30-50%, so it is acceptable if it has the advantage of completely eliminating the problem.

As already explained above, the proposed quantum random number generator 28 is configured such that the photon source 54 or the silicon LED 54 or the first SPAD diode 54 can be biased either in the forward direction or in the reverse direction to generate the detected photon flux λ.

In the case of reverse bias, photoluminescence is used in the avalanche formation in the photon source 54, here the silicon LED 54 or the first SPAD diode 54, which occurs in a controlled manner but at quantum mechanically random time intervals.

At a forward bias, the photons generated behave very similarly to a reverse bias, and the generation efficiency (photons per electrical charge passed) is relatively similar or higher, but at a forward bias, the power dissipation can be reduced compared to a reverse bias because a lower voltage is applied.

To give an order of magnitude, a forward-directed photon source 54 or silicon LED 54 or first SPAD diode 54 requires a voltage of several volts, while a backward-directed photon source requires a voltage of several dozen volts. When developing the technical teaching of this document, it was recognized that the use of DMOS transistors is particularly advantageous for the co-integration of preferably all relevant electronic components of a quantum random number generator 28. Such DMOS transistors make it possible to provide a voltage of several dozen volts for operating the backward-directed photon sources 54, i.e. here the silicon LEDs 54 or first SPAD diodes 54 operated in the reverse direction, by means of a voltage converter 91, which in the sense of the document presented here can include any form of suitable voltage converter 91 and which is preferably in the semiconductor substrate 49 of the one-piece microelectronic integrated circuit of the quantum random number generator 28 presented here. When developing the technical teaching of this document, it was thus recognized that the use of a BCD semiconductor technology for the production of the quantum random number generator 28 presented here is particularly advantageous for the co-integration of these DMOS transistors with the other relevant electronic components of the quantum random number generator 28 presented here. The document presented here thus proposes a quantum random number generator 28 which may comprise a voltage converter 91 with one or more DMOS transistors and an entropy source 401 with one or more photon sources 54 and/or silicon LEDs 54 and/or first SPAD diodes 54 and one or more photon detectors 55 and/or second SPAD diodes 55 and preferably one or more processors (10-1, 10-2) and/or one or more data bus interfaces 64 and/or one or more volatile and/or non-volatile memories (30, 6, 16, 8) and/or a test interface 12.

A forward biased photon source 54 or silicon LED 54 or first SPAD diode 54 in a device variant would therefore advantageously make it possible to also reduce the space necessary to electrically isolate the photon source 54 or silicon LED 54 or first SPAD diode 54 itself from the arrangement of photon detectors 55 or second SPAD diodes 54. As a result, the forward biased photon source 54 or silicon LED 54 or first SPAD diode 54 advantageously enables a more compact design of the quantum random number generator 28 and lower costs due to the smaller amount of semiconductor material used to manufacture the generator itself. However, since the structure and manufacturing technology of the photon source 54 or silicon LED 54 or first SPAD diode 54 and the photon detectors 55 or second SPAD diodes 55 are similar or even identical, the advantage of reverse bias is that the same voltage can be used to bias both components.

In particular, this last device variant makes it possible to reduce the complexity and overall dimensions of both the structure and the external circuitry that may still be necessary: the photon source 54 or silicon LED 54 or first SPAD diode 54 and the photon detectors 55 or second SPAD diodes 55 can in fact share the same semiconductor substrate 49 since they have a common connection. This allows them to be arranged close to each other (on top of each other and/or next to each other) in the semiconductor substrate 49, thus reducing the space occupied while improving their optical coupling.

In any case, the low efficiency of the photoluminescence process in generating a few photons suggests a “quantum detection” since the photon detector(s) 55 or second SPAD diodes 55 are by definition sensitive to a single photon.

As already mentioned, in the preferred embodiment of the proposal, the electronic scanning means (403, 2022, 402, 403, 404.2) together with the photon source 54 or silicon LED 54 or first SPAD diode 54 and the arrangement of photon detectors 55 or second SPAD diodes 55 are also integrally integrated into the semiconductor substrate 49.

In this case, the electronic scanning means (403, 2022, 402, 403, 404.2) can be configured not only to read the signal(s) 405 generated by the array of photon detectors 55 or second SPAD diodes 55, but also to detect the operating conditions of one or more photon sources 54 or one or more silicon LEDs 54 or one or more first SPAD Diode 54 can be controlled directly and easily and any bias parameters can be corrected by changing the parameters of one of said voltage converters 91 for supplying energy to one or more photon sources 54 or one or more silicon LEDs 54 or one or more first SPAD diodes 54 or activate or deactivate one or more photon sources 54 or one or more silicon LEDs 54 or one or more first SPAD diodes 54 in order to obtain the desired photon flux or the desired random bit rate of the quantum random bits 411.

In this case, the electronic sampling means (403, 2022, 402, 403, 404.2) can be configured to directly and easily control the operating conditions of one or more photon detectors 55 or one or more second SPAD diodes 54 and to correct any bias parameters by changing the parameters of one of said voltage converters 91 for supplying energy to one or more photon detectors 55 or one or more second SPAD diodes 55 or to activate or deactivate one or more photon detectors 55 or one or more second SPAD diodes 55 in order to obtain the desired receivable portion of the photon flux or the desired random bit rate of the quantum random bits 411.

According to a preferred embodiment of the proposal of the document presented here, the quantum random number generator 28 is preferably provided with a light protection filter or a cover, for example a metal layer (53, 142), at the level of the top side of the semiconductor substrate 49. In particular, preferably but not necessarily, the light protection filter comprises a metallization layer (53, 142) which can be produced directly during the production process, for example by the sequence of the process steps of a BCD technology, for example as the last metallization level. This metal layer (53, 142) does not necessarily have to be produced last. It is typically sufficient if the relevant device parts of the entropy source 401 are covered. Preferably, further device parts of the one-piece, micro-integrated circuit of the quantum random number generator 28 are covered with this metal cover (53, 142), so that it also protects these circuit parts from manipulation by means of electromagnetic radiation and/or thermal, local stress and/or by means of magnetic fields and/or other interventions by influencing physical parameters of such other circuit parts of the quantum random number generator 28. This protection should preferably in particular cover the memories (e.g. 404.9, 30, 6, 8, 16, 22, 20) and/or the processor (10-1, 10-2) and/or the monitoring devices - such as watchdog 404.5, ADC 403, voltage monitor 413, amplifier 402, finite state machine 404.8. This solution has the function of shielding the photon detector(s) 55 or second SPAD diodes 55 or the other circuit parts of the quantum random number generator 28 from external light and other physical interference signals. This solution therefore also has the function of making the photon detector(s) 55 or second SPAD diode(s) 55 sensitive only to the photons that pass through the semiconductor substrate 49 to the photon detectors 55 or second SPAD diodes 55 due to crosstalk from the photon source 54 or silicon LED 54 or first SPAD diode 54. In addition, the metallization layer (53, 142) also has the function of improving the coupling of the photons emitted by the semiconductor substrate 49, in particular the silicon substrate. For this purpose, the metallization layer 53 reflects the electromagnetic radiation generated by the same photon source 54 or silicon LED 54 or first SPAD diode 54 after exiting the semiconductor material of the semiconductor substrate 49 back into the insulation layers of the metallization stack on the semiconductor substrate 49, so that these photons cannot leave the micro-optical system of the one-piece microelectronic circuit of the quantum random number generator 28. This increases the number of photons that reach the photon detector(s) 55 or the second SPAD diode 55 or the second SPAD diodes 55. This in turn increases the random bit data rate of the quantum random bits 411 of the quantum random number generator 28. This thus strengthens the optical coupling between the photon source 54 or silicon LED 54 or first SPAD diode 54 on the one hand and the array of photon detectors 55 or second SPAD diodes 55 on the other hand.

Furthermore, the metal cover 53 of the optical waveguide 44 in the metallization stack of the microelectronic circuit on the semiconductor substrate 49 advantageously also has the function of protecting the quantum random number generator 28 from any attempts by malicious persons to influence the functionality of the system of the proposed device.

Consequently, the presence of the metallization in the form of a metal cover (53, 143) makes it possible to ensure greater security and reliability of the random numbers generated by the quantum random number generator 28 according to the invention.

Finally, the proposed quantum random number generator 28 may optionally also comprise electronic post-processing means (404.3, 404.4, 404.8) configured to receive as input the binary sequences extracted by the electronic sampling means (403, 2022, 402, 403, 404.2), which in turn are connected to the array of photon detectors 55 and second SPAD diodes 55, respectively.

Said electronic post-processing means (404.3, 404.4, 404.8) are preferably configured to process said binary sequences 409, 415 in such a way that a so-called "whitening" operation is carried out. This last word designates a plurality of compression operations that serve to improve the statistical properties of the generated binary sequences (415, 409). Consequently, it is advantageous that this further post-processing step makes it possible to increase the entropy level of the proposed quantum random number generator 28.

As already mentioned above, the sampling means (403, 2022, 402, 403, 404.2), which according to the preferred embodiment are directly or indirectly connected to the array of photon detectors 55 or second SPAD diodes 55 or alternatively to a subset of the photon detectors 55 or second SPAD diodes 55 or even to a single pixel, are configured to implement a logical extraction method intended to extract a binary sequence of random bits (409, 415) based on the number of photons detected in the array of photon detectors 55 or second SPAD diodes 55, in the subset, in the only one of the photon detectors 55 or in the only second SPAD diode 55 or even in the single pixel. According to the proposal, a first logical extraction method, which is implemented by the sampling means (2022, 402, 403, 404.2) of the proposed quantum random number generator 28, comprises the division of the observation window of each photon detector 55 or of every second SPAD diode 55 into a plurality of successive observation sub-windows Tw, typically having the same duration. If the entropy extraction generates a pulse on its output line 405, a synchronization stage (403, 2022) synchronizes the pulse with the system clock 2106 of the quantum random number generator 28. An observation sub-window Tw typically corresponds to the temporal period of the system clock 2106.

According to the methods commonly used in the state of the art, the post-processing means would typically have to determine the arrival times of the photons at the photon detectors 55 or the photons detected by the second SPAD diodes 55 in relation to a reference time as a digital numerical value using a time counter. However, this has the disadvantage that an attacker may be able to manipulate this time via a so-called side channel, without any information being given as to how this could be done. In the context of the document presented here, it is assumed that the attacker succeeds in carrying out this manipulation in an unknown way. The attacker would then be able to manipulate the supposed "random bits", which would give them a deterministic character that would possibly enable encryption and/or locks to be broken. The proposal presented here prevents this.

The one-piece, integrated microelectronic circuit of the quantum random number generator 28 typically generates these successive observation subwindows Tw starting from the system clock 2106. An observation window Tw in the sense of the document presented here can, for example, begin with a first edge of the system clock 2106 in a first edge direction, which can be rising or falling, and end with the next directly following edge of the system clock 2106 in the same edge direction (rising or falling). The duty cycle of this system clock 2106 typically defines the time in which the photon detector 55 or the second SPAD diode 55 is at the dead time level (system clock 2106 = H [= high level]).

The special feature of the method proposed here for entropy extraction at the level of each sub-window Tw is the generation of a first pseudo-random number which corresponds to the arrival time of a second photon from the photon source 54 or the silicon LED 54 or the first SPAD diode 54 at a photon detector 55 or a second SPAD diode 55, respectively, in relation to the arrival time of a preferably immediately preceding first photon from the photon source 54 or the silicon LED 54 or the first SPAD diode 54 at a photon detector 55 or a second SPAD diode 55. The device proposed here of the one-piece integrated microelectronic circuit of the proposed quantum random number generator 28 generates this first pseudo-random number by means of a time-to-random number converter (TPRC). Such a time-to-random number converter (TPRC) can also be composed of several stages. For example, the time-to-pseudo-random number converter (TPRC) can 404.3) may include an analog instrument, a Time to Analog Converter (TAC), which would then be followed by an Analog to Pseudorandom Number Converter (APRC) in the data path to again result in a Time to Pseudorandom Number Converter (TPRC, 404.3).

This in 22 The diagram shown represents the detection of the pulses (2201, 2202, 2203, 2204) on the voltage signal 405 of the entropy source 401. The entropy source 401 preferably comprises the one or more photon sources 54 or the one or more silicon LEDs 54 or the one or more SPAD diodes 54 and the light transmission path 44 between them. The entropy source 401 is preferably manufactured in or on the semiconductor substrate 49 and is thus preferably part of the micro-integrated circuit of the quantum random number generator 28. The output signal 405 of the entropy source 401 is typically the said voltage signal 405 of the entropy source 401. The voltage signal 405 of the entropy source 401 is preferably the signal of one or more photon detectors 55 or one or more second SPAD diodes 55 of the entropy source 401.

The voltage signal 405 shows exemplary pulses 2201, 2202, 2203, 2104 for random events of the voltage signal 405. These can be spontaneous voltage pulses of the photon detector 55 or the second SPAD diode 55 of the entropy source 401, which are not related to the activity of the photon source 54 or the silicon LED 54 or the first SPAD diode 54 of the entropy source 401. However, the pulses 2201, 2202, 2203, 2204 of the photon detector 55 or the second SPAD diode 55 of the entropy source 401 can also be based on stimulated emission, which causes the detection of a photon of the one or more photon sources 54 or the one or more silicon LEDs 54 or the one or more SPAD diodes 54 by the photon detector 55 or by the second SPAD diode 55 of the entropy source 401.

The time interval is random. However, after the reception of a photon by the photon detector 55 or by the second SPAD diode 55 of the entropy source 401, a dead time occurs during which the photon detector 55 or the second SPAD diode 55 of the entropy source 401 is no longer able to receive. If the magnitude of the voltage signal 405 of the entropy source 401 exceeds a threshold value 2105, an analog-to-digital converter (ADC, 403), here an exemplary one-bit analog-to-digital converter 403, generates

Pulse extension circuit, which is preferably part of the integral microelectronic circuit, generates a pulse with a minimum length of n clock cycles of a system clock 2106 of the quantum random number generator 28, which is preferably one of the system clock cycles of the integral microintegrated circuit, on a synchronized voltage signal 415.

In the example of 21 For example, this pulse extension circuit is designed in such a way that it goes to a first logic level for at least three subsequent clock pulses and then falls back to the second logic level until the next event, here for example with the falling edge of the third clock pulse. Instead of three clock pulses, a to n clock pulses can be used, where is a whole positive number.

In the example of 21 the falling edges of the pulses 2211, 2212, 2213, 2214 of the synchronized voltage signal 415 represent the synchronized signals of the entropy source 401.

With a falling edge of a first pulse 2211 of the synchronized voltage signal 415, the time-to-pseudorandom number converter (TPRC) resets a pseudorandom number generator, for example, to a predefined seed value. For example, the pseudorandom number generator of the time-to-pseudorandom number converter (TPRC) can be a feedback shift register that shifts its values by one place to the left or right depending on the design with each clock pulse of the system clock 2106 and feeds the feedback value of the feedback polynomial back into the bit that becomes free.

It is important that, starting with the starting value of the pseudorandom number generator (seed value), each clock pulse of the system clock 2106 is bijectively assigned exactly one pseudorandom number of the pseudorandom number generator from the falling edge. This means that the value of the pseudorandom number must be able to be used to determine the temporal position of the relevant clock pulse of the system clock 2106 after the falling edge of the synchronized voltage signal 415.

With the next falling edge of the second pulse 2212 synchronized voltage signal 415, a first pseudorandom number register takes over the last status of the pseudorandom number generator and the time-to-pseudorandom number converter (TPRC) preferably resets the pseudorandom number generator to the predefined seed value.

With the next falling edge of the voltage signal 415 synchronized with the third pulse 2213, a second pseudorandom number register takes over the last status of the pseudorandom number generator and the time-to-pseudorandom number converter (TPRC) preferably resets the pseudorandom number generator to the predefined seed value. The entropy extraction 401 compares the value in the first pseudorandom number register with the value in the second pseudorandom number register. If the first value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate a quantum random bit 411 with a first logical level. If the second value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate a quantum random bit 411 with a second logical level that is different from the first level.

With the next falling edge of the fourth pulse 2214 of the synchronized voltage signal 415, the first pseudorandom number register takes over the previous value of a second pseudorandom number register and the second pseudorandom number register instead takes over the last status of the pseudorandom number generator and the time-to-pseudorandom number converter (TPRC) preferably resets the pseudorandom number generator to the predefined seed value. The entropy extraction 401 then compares the value in the first pseudorandom number register with the value in the second pseudorandom number register. If the first value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate another new and here second quantum random bit 411 with a first logic level. If the second value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate another new and here second quantum random bit 411 with a second logic level that is different from the first level.

In this way, the quantum random number generator 28 can continue this process of quantum random bit generation and thus generate a continuous stream of quantum random bits 411, albeit with phase noise.

The key idea here is to use a pseudorandom number generator, which generates the first and second values, instead of a digital counter as in the prior art. The advantage is that even if a disturbance is successfully introduced into the synchronized voltage signal 415, the randomness of the quantum random bit 411 is only marginally disturbed, since the attacker would also have to know the feedback polynomial.

In order to prevent this, it is useful if, for example, the quantum random number generator 28 changes the feedback polynomial of the linearly feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 (TPRC) after the complete determination of a number m of random quantum bits 411 as a function of one or more previously determined random quantum bits 411.

To prevent this, it is also useful if, for example, the quantum random number generator 28 changes the shift register length n of the linear feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 (TPRC) after the complete determination of a number k of quantum random bits 411 depending on one or more previously determined quantum random bits 411. For this purpose, it is useful if the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or a processor (10-1, 10-2) rewrites the value of the feedback polynomial selection register 2112 for this purpose. The value stored in the feedback polynomial selection register 2112 preferably controls the feedback multiplexer 2102 of the time-to-pseudorandom number converter 404.3 (TPRC). Thus, the value stored in the feedback polynomial selection register 2112 preferably selects which feedback polynomial of the m feedback polynomial circuits RKN ₁ to RKN _m determines the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC). Preferably, by means of a line 2022 for preventing the use of a quantum random bit 411 by the finite state machine 404.8, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or one of the processors (10-1, 10-2) or another device prevent the forwarding of a generated quantum random bit 411 by the finite state machine 404.8 when this quantum random bit 411 is used for the feedback polynomial selection register 2112. This prevents double use and thus increases security. Instead, Preferably, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or the processor (10-1, 10-2) or the other device uses this quantum random bit 411 to generate a random data word for storage in the feedback polynomial selection register 2112. This has the advantage that the feedback polynomial of the m feedback polynomial circuits RKN ₁ to RKN _m selected by the feedback polynomial selection register 2112 is completely random. This means that it is no longer possible for an attacker to feed in a deterministic bit data stream instead of the data bit stream of the quantum random bits 411, even if an attack on the entropy source 401 is successful.

• • bei Erreichen einer vorbestimmten Anzahl erfolgreich erzeugter Quantenzufallsbits 411 und/oder
• • bei Erreichen einer vorbestimmten Anzahl erfolgreich erzeugter Zufallsdatenworte 418 und/oder
• • bei Änderung des Werts des Rückkoppelpolynom-Auswahlregisters 2112 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) und damit des ausgewählten Rückkoppelpolynoms der m Rückkoppelpolynome RKN₁ bis RKN_m des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC).

In order to further harden the proposed micro-integrated quantum random number generator 28, it is also useful if, for example, the quantum random number generator 28 changes the start value (seed value) of the linear feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 (TPRC) after the complete determination of a number p of random quantum bits 411 depending on one or more previously determined quantum random bits 411. For this purpose, it is useful if the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or a processor (10-1, 10-2) rewrites the value of a seed reload register in the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) with quantum random bits 411 for this purpose. The bit width of a seed reload register in the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably corresponds to the number n of the shift register bits SB ₁ to SB _n of the time-to-pseudo-random number converter 404.3 (TPRC). The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably counts the number of successfully generated quantum random bits 411. For this purpose, the finite state machine 404.8 preferably signals the generation of a valid quantum random bit 411 to the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC). Instead of counting the valid quantum random bits 411, it is also possible to count the successfully generated random data words 418 in the finite state machine 404.8. The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably loads the new seed value of a seed reload register in the shift register controller 2103 into the shift register bits SB ₁ to SB _n of the time-to-pseudo-random number converter 404.3 (TPRC) at one or more of the following events.

• • upon reaching a predetermined number of successfully generated quantum random bits 411 and/or
• • upon reaching a predetermined number of successfully generated random data words 418 and/or
• • when changing the value of the feedback polynomial selection register 2112 of the time-to-pseudo-random number converter 404.3 (TPRC) and thus of the selected feedback polynomial of the m feedback polynomials RKN ₁ to RKN _m of the time-to-pseudo-random number converter 404.3 (TPRC).

This reliably prevents any kind of predictability.

Preferably, the circuit parts of the quantum random number generator 28 are covered with a metal layer 142, 53 in order to ward off any influence by temperature or electromagnetic radiation or electrostatic fields or magnetic fields. Preferably, the metal layer also comprises a soft magnetic layer to ward off attempts at attack using magnetic fields.

Preferably, by means of a line 2022 for preventing the use of a quantum random bit 411 by the finite state machine 404.8, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or one of the processors (10-1, 10-2) or another device prevent the forwarding of a generated quantum random bit 411 by the finite state machine 404.8 if this quantum random bit 411 is used for the seed reload register in the shift register controller 2103 in the time-to-pseudo-random number converter 404.3 (TPRC). This prevents double use and thus increases security. Instead, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or the processor (10-1, 10-2) or the other device preferably uses this quantum random bit 411 to generate a random data word for storage in the seed reload register in the shift register controller 2103. This has the advantage that the seed value of the linear feedback shift register of the n shift register bits SB ₁ to SB _n selected by the seed reload register in the shift register controller 2103 is completely random. Since a linear feedback shift register has two cycles when using simple primitive feedback polynomials, one of which only includes a shift register value, this one-cycle shift register value must be prevented. If the random reload value of the seed reload register in the shift register controller 2103 corresponds to the one-cycle seed value of the linear feedback shift register with the current feedback polynomial or the next feedback polynomial, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or one of the pro processors (10-1, 10-2) or another device a new random reload value in the seed reload register of the shift register controller 2103.

Preferably, the m feedback polynomials RKN ₁ to RKN _m are selected such that the single-cycle seed values are equal. This reduces the effort for detecting the single-cycle shift register value, since this no longer depends on the selected feedback polynomial of the feedback polynomials RKN ₁ to RKN _m . In any case, it is recommended that the time-to-pseudo-random number converter 404.3 (TPRC) includes a detection circuit 2113 for detecting an illegal value of the state vector of the n shift register bits SB ₁ to SB _n when linear feedback shift registers are used. If the state vector of the n shift register bits SB ₁ to SB _n is in such an illegal state, the detector 2113 preferably signals this illegal state to the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or one of the processors (10-1, 10-2) or another device. The detector 2113 or the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or the processor (10-1, 10-2) or the other device then resets the value of the state value of the state vector of the n shift register bits SB ₁ to SB _n to a predetermined value and/or the value of the seed reload register in the shift register controller 2103. These reload values are preferably different from the one-cycle shift register value. This preferably also occurs when the watchdog 404.5 and/or the voltage monitor 413 detect a fault or a suspected or possible attack. The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably counts the number of these faults. Preferably, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) reduces this counter value again depending on the number of random quantum bits 411 and/or random data words 418 successfully generated, in particular since the last disturbance. If this number and/or the event density of such events exceeds a certain predetermined temporal density and/or a certain numerical value, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably signals to the watchdog 404.5 and/or a processor (10-1, 10-2) a defect in the quantum random number generator 28 or a successful attack on the quantum random number generator 28. Typically, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) signals to the finite state machine 404.8 then that no more random numbers may be generated. Preferably, a processor (10-1, 10-2) must then reactivate the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) by means of a predetermined reactivation code word. The processor (10-1, 10-2) then writes this reactivation code word via the internal data bus 419 of the quantum random number generator 28 into a special reactivation register of the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC), which reactivates the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) and the quantum random number generator 28 and preferably resets all error counters. Preferably, the number of possible reactivations is limited. If the maximum number of reactivations is exceeded, the quantum random number generator 28 can preferably no longer be reactivated. Preferably, the counter for the reactivations of the quantum random number generator 28 can be reset by means of a special reset command before this maximum value is reached. Preferably, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28 or another device of the quantum random number generator 28 issues a warning before this blocking limit is reached.

When the quantum random number generator 28 is started, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) first ensures that the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) first determines a new seed value based on quantum random numbers 411 and a new value of the feedback polynomial selection register 2112 based on quantum random numbers from quantum random bits 411 by means of a predetermined seed value and a predetermined value of the feedback polynomial selection register 2112. Only when the seed value and the value of the feedback polynomial selection register 2112 are based on quantum random numbers is the initialization phase of the quantum random number generator 28 completed and the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) signals the finite state machine 404.8 that it may use and pass on the quantum random bits 411 and the quantum random data words 418 (quantum random numbers). The finite state machine 404.8 preferably signals this fact to one or more processors (10-1, 10-2). This has the advantage that the device only generates quantum random numbers 418 generated with full protection.

By using a time-to-pseudorandom number generator 404.3 (TPRC), an attacker is no longer able to generate a deterministic bit data stream instead of the data bit stream of the quantum ten random bits 411, even if an attack on the entropy source 401 is actually successful for whatever reason.

In order to prevent this, it is also useful if, for example, the quantum random number generator 28 changes this number m after the complete determination of a number m of quantum random bits 411 depending on one or more previously determined quantum random bits 411.

Preferably, the finite state machine 404.8 of the quantum random number generator 28 does not output these already used quantum random bits 411 and does not use them for generating quantum random data words 418.

The logic extraction method also includes three borderline cases, which are described below.

Typically, the time-to-pseudo-random number generator 404.3 (TPRC) uses the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC) as the value of the output 410 of the time-to-pseudo-random number converter 404.3 (TPRC). If necessary, a buffer amplifier can be provided which detects the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC) and outputs it as the value of the output 410 of the time-to-pseudo-random number converter 404.3 (TPRC).

The entropy extraction 404.4 now compares two different pseudorandom numbers generated by the time-to-pseudorandom number converter 404.3 (TPRC) from the output 410 of the time-to-pseudorandom number converter 404.3, a first pseudorandom number 410.1 and a second pseudorandom number 410.2.

If the first pseudorandom number 410.1 and the second pseudorandom number 410.2 are the same, the entropy extraction 404.4 discards one of the two pseudorandom numbers, the first pseudorandom number 410.1 or the second quantum random number 410.2, and replaces it with a new pseudorandom number 410.3 from the time-to-pseudorandom number converter 404.3 (TPRC). The entropy extraction 404.4 preferably uses a counter to count the events in which the two pseudorandom numbers, the first pseudorandom number 410.1 and the second pseudorandom number 410.2, are the same and increases the counter by a first counter step size with each such event. Preferably, the entropy extraction 404.4 also uses this counter to count the events in which the two pseudorandom numbers, the first pseudorandom number 410.1 and the second pseudorandom number 410.2, are unequal and decrements the counter by a second counter step size with each such event, preferably not falling below the value 0. Preferably, the second counter step size is smaller in magnitude than the first counter step size of the counter in the entropy extraction 404.4. If the value of this counter exceeds a predetermined value, the control device of the entropy extraction 404.4 assumes a defect in the time-to-pseudorandom number converter 404.3 (TPRC). Preferably, the control device of the entropy extraction 404.4 then signals a defect in the quantum random number generator 28 or a successful attack on the quantum random number generator 28 to a processor (10-1, 10-2). Preferably, the entropy extraction 404.4 then no longer signals the finite state machine that a quantum random bit 411 has been successfully generated, so that the finite state machine 404.8 can no longer report successful quantum random number generation to a processor (10-1, 10-2) and no longer generates quantum random numbers 1018.

If the first pseudorandom number 410.1 is smaller than the second pseudorandom number 410.2, the entropy extraction 404.4 generates a quantum random bit of a first logical value, for example a logical '1', and signals the successful generation to the finite state machine 404.8.

If the first pseudorandom number 410.1 is greater than the second pseudorandom number 410.2, the entropy extraction 404.4 generates a quantum random bit of a second logical value, for example a logical '0', which is different from the first logical value, and signals the successful generation to the finite state machine 404.8.

The finite state machine converts the successfully generated quantum random bits 411 into quantum random data words 418, each of which represents a quantum random number, and makes these available to the processors (10-1, 10-2) via a RAM or a FIFO 404.9 via the internal data bus 419. The finite state machine 404.8 preferably signals the provision of one or more quantum random numbers to one or more processors (10-1, 10-2).

One problem may be a jitter of the system clock 2106. By using a time-to-pseudo-random number generator 404.3 (TPRC), a monofrequency or otherwise systematic disturbance of the system clock 2106 is spread in the spectrum with a random spreading code, making detection difficult, if not impossible, for an attacker.

This further complicates the vulnerability of the quantum random number generator 28.

By using quantum random numbers for the seed value of the linear feedback shift register of the time-to-pseudo-random number converter and a quantum random number for the selection of the simple primitive feedback polynomial, the behavior of the time-to-pseudo-random number converter 404.3 (TPRC) itself is at a random level of a quantum random number. By regularly changing these values, it is made even more difficult for an attacker to influence the generated quantum random numbers.

Therefore, the proposed quantum random number generator 28 achieves all of the above-mentioned goals.

In particular, the proposal achieves the objective of providing a one-piece, micro-integrated quantum random number generator 28 that makes it possible to guarantee a high level of entropy so that it at least passes the statistical tests defined by NIST.

It is a further object of the proposal to provide a one-piece, micro-integrated quantum random number generator 28 which makes it possible to achieve a high bit rate when generating random sequences of quantum random bits 411 and/or quantum random data words 418.

It is a further object of the proposal to provide a one-piece, micro-integrated quantum random number generator 28 which, compared to the quantum random number generators of the prior art, has a more compact, more robust and less complex and, above all, micro-integrated and CMOS compatible structure, which allows one-piece manufacturing and co-integration into conventional systems such as memories (such as DRAMS, SRAMS, flash memories and the like) or processors (microprocessors and/or microcontrollers and/or SoCs with a processor on the IC).

Here too, the proposal achieves the goal of providing a quantum random number generator 28 with a high degree of security against any attempt to manipulate its internal components. In particular, the use of a time-to-pseudo random number generator 1004.3 (TRNG) prevents the evaluation of successful attacks on the entropy source 401. Furthermore, the many tests enable a reliable detection of an attack on the quantum random number generator 28 and thus prevent the use of manipulated numbers as supposedly secure quantum random numbers.

Finally, the proposal also achieves the objective of providing a quantum random number generator 28 which is more economical than the generators of the known state of the art, in particular due to the ability to be co-integrated into CMOS circuits.

Features of the invention

• Merkmal 1: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) (Englisch: Quantum Random Number Generator: QRNG),
  • - wobei der quantenprozessbasierende Generator (28) für echte Zufallszahlen (411, 418) (Englisch: Quantum Random Number Generator: QRNG) eine Entropiequelle (401) aufweist und
  • - wobei der quantenprozessbasierende Generator (28) für echte Zufallszahlen (411, 418) (Englisch: Quantum Random Number Generator: QRNG) ein Signal (405) der Entropiequelle (401) mittels eines Zeit-zu-Pseudozufallszahlen-Wandlers (TPRC) (404.3) auswertet und ein oder mehrere Zufallsbits (411) erzeugt.
• Merkmal 2: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach Merkmal 1,
  • - wobei der Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418), aus mehreren Zufallsbits (411) eine oder mehrere Zufallszahlen (418) erzeugt und zur Verfügung stellt oder nutzt.
• Merkmal 3: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach Merkmal 1 oder 2,
  • - wobei das Verhalten des P eines Zeit-zu-Pseudozufallszahlen-Wandlers (TPRG) (404.3) von einem oder mehreren Quantenzufallsbits (411) und/oder einer oder mehrerer Quantenzufallszahlen (418) abhängt.
• Merkmal 4: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach einem der Merkmale 1 bis 3,
  • - wobei der quantenprozessbasierende Generator (28) für echte Zufallszahlen (411, 418) einen Watchdog (404.5) umfasst, der die korrekte Funktion des quantenprozessbasierenden Generators (28) für echte Zufallszahlen (411, 418) überwacht.
• Merkmal 5: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach einem der Merkmale 1 bis 4,
  • - wobei der quantenprozessbasierende Generator (28) für echte Zufallszahlen (411, 418) einen Watchdog (404.5) umfasst, der die korrekte Funktion des quantenprozessbasierenden Generators (28) für echte Zufallszahlen (411, 418) überwacht indem er die Zufälligkeit der erzeugten Quantenzufallsbits (411) in Form eines Messwerts misst und mit einem Toleranzintervall oder einem Schwellwert vergleicht und auf einen Fehler bei einer Abweichung schließt.
• Merkmal 6: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach einem der Merkmale 1 bis 5,
  • - wobei der quantenprozessbasierende Generator (28) für echte Zufallszahlen (411, 418) einen Watchdog (404.5) umfasst, der die korrekte Funktion des eines Zeit-zu-Pseudozufallszahlen-Wandlers (TPRC) (404.3) überwacht und bei Abweichungen von einem erwarteten verhalten einen Fehler feststellt und/oder signalisiert.
• Merkmal 7: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach einem der Merkmale 1 bis 6,
  • - wobei der quantenprozessbasierende Generator (28) für echte Zufallszahlen (411, 418) einstückig als Teil eines integrierten Schaltkreises (2) gefertigt ist und
  • - wobei der integrierte Schaltkreis (2) einen Spannungswandler (91) zur Versorgung der Entropiequelle (401) des quantenprozessbasierenden Generators (28) für echte Zufallszahlen (411, 418) umfasst und
  • - wobei der Spannungswandler (91) einen oder mehrere DMOS-Transistoren umfasst.
• Merkmal 8: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach Merkmal 7,
  • - wobei der integrierte Schaltkreis (2) in einer BCD-Technologie gefertigt ist.
• Merkmal 9: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach einem der Merkmale 1 bis 8,
  • - wobei der quantenprozessbasierende Generator (28) für echte Zufallszahlen (411, 418) einstückig als Teil eines integrierten Schaltkreises (2) gefertigt ist und
  • - wobei der integrierte Schaltkreis (2) einer der folgenden Schaltkreise ist oder einen der folgenden Schaltkreise umfasst:
    • - Ein Mikrokontroller,
    • - ein Mikroprozessor,
    • - ein Speicher,
    • - ein DRAM,
    • - ein SRAM,
    • - ein RAM,
    • - ein flüchtiger Speicher,
    • - ein OTP-Speicher,
    • - ein EEPROM,
    • - ein Flash-Speicher,
    • - ein MRAM,
    • - ein FRAM,
    • - ein Sensor-Auswerteschaltkreis,
    • - ein Steuerschaltkreis für eine automobile Steuerschaltung,
    • - ein Grafik-Controller,
    • - ein Auswerteschaltkreis für einen biometrischen Sensor oder ein Eingabegerät,
    • - eine Steuerschaltung,
    • - eine Chip-Karten-Schaltung,
    • - ein Sachaltkreis eines Mobiltelefons oder eines Smart-Phones,
    • - ein Schaltkreis eines Zugangskontrollsystems,
    • - ein Schaltkreis mit einer kodierten Aufzeichnung von Betriebsparametern,
    • - ein Schaltkreis eines Zugriffskontrollsystems,
    • - ein Schaltkreis eines Sicherungssystems elektronischer Sicherungen,
    • - ein Funksystemschaltkreis,
    • - ein Kommunikationsschaltkreis,
    • - ein Schaltkreis eines Verschlüsselungs- und/oder Entschlüsselungssystems,
    • - ein Schaltkreis eines Individualisierungssystems
    • - ein Schaltkreis einer Spielvorrichtung,
    • - ein Schaltkreis eines Simulationssystems,
    • - ein Schaltkreis eines Rechnersystems,
    • - ein Schaltkreis einer Rauschquelle,
    • - ein Schaltkreis mit einer Vorrichtung zur Erzeugung und/oder Nutzung eines Spreizkodes.
• Merkmal 10: Quantenprozessbasierender Generator (28) für echte Zufallszahlen (411, 418) nach einem der Merkmale 1 bis 9,
  • - wobei die Entropiequelle (401) eine Photonenquelle (54) umfasst und
  • - wobei die Entropiequelle (401) einen Photonendetektor (55) umfasst und
  • - wobei die Photonenquelle (54) bei Versorgung mit elektrischer Energie Photonen als Quantensignal emittiert und
  • - wobei die Photonenquelle (54) mit dem Photonendetektor (55) optisch gekoppelt ist und
  • - wobei der Photonendetektor (55) das Quantensignal der Photonenquelle (54) zumindest teilweise empfängt und das Ausgangssignal (405) der Entropiequelle (401) oder ein Vorläufersignal desselben erzeugt.
• Merkmal 11: Sicherer Mikrocontroller zur Steuerung von Vorrichtungen, insbesondere im Automobil
  • - mit einem Halbleiterkristall und
  • - mit Speicherelementen und
  • - mit zumindest einem internen Bus (419) und
  • - mit zumindest einem Prozessor (10-1), insbesondere einem 8/16/32/15-Bit-Microkontrollerkern, und
  • - mit einer oder mehreren Datenschnittstellen und
  • - mit zumindest einem quantenprozessbasierenden Generator (28) für echte Zufallszahlen (411, 418) (Englisch: Quantum Random Number Generator: QRNG) nach einem der Merkmale 1 bis 9, und
  • - wobei die Speicherelemente mit dem internen Bus (419) verbunden sind und
  • - wobei die Datenschnittstelle mit dem internen Bus (419) verbunden ist und
  • - wobei insbesondere der quantenprozessbasierende Generator für echte Zufallszahlen (QRNG) (28) mit dem internen Bus (419) verbunden sein kann und
  • - wobei der Prozessor (10-1) mit dem internen Bus (419) verbunden ist und
  • - wobei der quantenprozessbasierende Generator für echte Zufallszahlen (QRNG) (28), insbesondere auf Anfrage des Prozessors (10-1), eine Zufallszahl (418) erzeugt oder zur Verfügung stellt und
  • - wobei der Prozessor (10-1) mit Hilfe eines Programms aus einem oder mehreren seiner Speicherelemente und mit Hilfe der Zufallszahl einen Schlüssel erzeugt und
  • - wobei der Prozessor (10-1) mit Hilfe eines Programms aus einem oder mehreren seiner Speicherelemente und mit Hilfe des Schlüssels Daten verschlüsselt und entschlüsselt, die er über die Datenschnittstelle mit Vorrichtungen außerhalb des sicheren Mikrocontrollers austauscht und
  • - wobei der Halbleiterkristall diese Teilvorrichtungen des sicheren Mikrocontrollers einstückig umfasst,
  • - wobei diese Teilvorrichtungen des sicheren Mikrocontrollers die Speicherelemente, den internen Bus (419), den zumindest einen Prozessor (10-1), die Datenschnittstellen und den quantenprozessbasierenden Generator für echte Zufallszahlen (Englisch: Quantum Random Number Generator: QRNG) (28) umfassen,
• Merkmal 12: Sicherer Mikrocontroller nach Merkmal 11,
  • - wobei die Speicherelemente ein oder mehrere Schreib/Lese-Speicher RAM und/oder ein oder mehrere beschreibbare nicht flüchtige Speicher, insbesondere EEPROM-Speicher und/oder Flash-Speicher und/oder OTP-Speicher, und/oder ein oder mehrere reine Lesespeicher und/oder ein oder mehrere nicht flüchtige Herstellerspeicher insbesondere ein oder mehrere Hersteller-ROMs und/oder ein oder mehrere Hersteller EEPROMs und/oder ein oder mehrere Hersteller-Flash-Speicher, umfassen.
• Merkmal 13: Sicherer Mikrocontroller nach Merkmal 12,
  • - wobei das Hersteller-ROM die Boot-Software umfasst.
• Merkmal 14: Sicherer Mikrocontrollernach Merkmal 12 oder 13,
  • - wobei eine Hersteller-Speicher Firewall zwischen dem Hersteller-Speicher und dem internen Bus (419) vorgesehen ist.
• Merkmal 15: Sicherer Mikrocontroller nach einem oder mehreren der Merkmale 11 bis 14
  • - mit einer oder mehrerer der folgenden Komponenten:
    • - einen Taktgenerator (92) (u.a. für den Systemtakt 2106)
    • - einer Rücksetzschaltung (83) und/oder
    • - einem oder mehreren Spannungswandlern (91), die die Betriebsspannungen bereitstellen, und/oder
    • - einer Masseschaltung in der negativen Versorgungsspannungsleitung (GND), insbesondere zur Abwehr von Angriffen über Masseversatz, und/oder
    • - einer Eingangs-/Ausgangsschaltung und/oder
    • - einem oder mehreren Verarbeitungsmodulen,
  • - wobei die Verarbeitungsmodule dazu eingerichtet sind, mit dem internen Bus (419) zu kommunizieren, und
  • - wobei die Verarbeitungsmodule eines oder mehrere der folgenden Module umfassen:
    • - ein CRC-Modul (Cyclic Redundancy Check),
    • - ein Taktgeneratormodul,
    • - mit einem DES-Beschleuniger und/oder einem AES-Beschleuniger
    • - ein oder mehrere Zeitgeber-Module,
    • - eine Sicherheitsüberwachungs- und -steuerungsschaltung,
    • - eine Datenschnittstelle, insbesondere einen Universellen Asynchronen Receiver Transmitter (UART).
• Merkmal 16: Sicherer Mikrocontroller 1nach einem oder mehreren der Merkmale 11 bis 15,
  • - mit zumindest einer Photonenquelle (54), insbesondere einer Silizium-LED (54) oder einer ersten SPAD-Diode (54), und
  • - mit zumindest einem Photonendetektor (54), insbesondere einer zweiten SPAD-Diode (55), und
  • - mit zumindest einer Verarbeitungsschaltung und
  • - mit zumindest einer Betriebsschaltung,
  • - wobei der quantenprozessbasierende Generator für echte Zufallszahlen (QRNG) (28) zumindest die Photonenquelle (54) als Lichtquelle für das optische Quantensignal umfasst und
  • - wobei der quantenprozessbasierende Generator für echte Zufallszahlen (QRNG) (28) zumindest den Photonendetektor (55) als Fotodetektor für das optische Quantensignal umfasst und
  • - wobei der quantenprozessbasierende Generator für echte Zufallszahlen (QRNG) (28) zumindest die Verarbeitungsschaltung umfasst und
  • - wobei die zumindest eine Photonenquelle (54) mit dem zumindest einen Photonendetektor (55) optisch gekoppelt ist und
  • - wobei die Betriebsschaltung die Photonenquelle (54) so mit elektrischer Energie versorgt, dass die Photonenquelle (54) Licht emittiert und
  • - wobei die Verarbeitungsschaltung das Signal des Photonendetektors (55) erfasst und daraus die Zufallszahl bildet und dem Prozessor (10-1) zur Verfügung stellt.
• Merkmal 17: Sicherer Mikrocontroller 11 nach Merkmal 16,
  • - mit zumindest einem optischen Lichtwellenleiter (44),
  • - wobei der quantenprozessbasierende Generator für echte Zufallszahlen (QRNG) (28) zumindest den optischen Lichtwellenleiter (44) umfasst und
  • - wobei der zumindest eine optische Lichtwellenleiter (44) die zumindest eine Photonenquelle (54) mit dem zumindest einen Photonendetektor (55) optisch koppelt.
• Merkmal 18: Sicherer Mikrocontroller nach Merkmal 17
  • - wobei der Halbleiterkristall eine Oberfläche (56) aufweist und
  • - wobei der Halbleiterkristall ein halbleitendes Material unterhalb seiner Oberfläche (56) aufweist und
  • - wobei die Oberfläche (56) des Halbleiterkristalls einen Metallisierungsstapel aufweist und
  • - wobei der Metallisierungsstapel eine typischerweise strukturierte und optisch transparente und elektrisch isolierende Schicht (44) aufweist und
  • - wobei zumindest ein Teil dieser typischerweise strukturierten, transparenten und elektrisch isolierenden Schicht (44) der Oberfläche (56) den optischen Lichtwellenleiter (44) bildet und
  • - wobei die Photonenquelle (54) aus dem halbleitenden Material des Halbleitersubstrats in diesen optischen Lichtwellenleiter (44) einstrahlt und
  • - wobei der optische Lichtwellenleiter (44) den Photonendetektor (54) so bestrahlt, dass das Licht von innerhalb des Lichtwellenleiters (44) wieder in das halbleitende Material des Halbeleitersubstrats von der Oberfläche aus eindringt und dort Vorrichtungsteile des Photonendetektors (55) trifft.
• Merkmal 19: Sicherer Mikrocontroller nach Merkmal 17 und/oder 18,
  • - wobei die zumindest eine Betriebsschaltung die zumindest eine Photonenquelle (54) zumindest zeitweise mit elektrischer Energie versorgt und
  • - wobei die zumindest eine Photonenquelle (54) bei Versorgung mit ausreichender elektrischer Energie Photonen in den zumindest einen Lichtwellenleiter (44) einspeist und
  • - wobei der zumindest eine Lichtwellenleiter (44) solche Photonen in den Photonendetektor (55) einstrahlt.
• Merkmal 20: Sicherer Mikrocontroller nach einem oder mehreren der vorausgehenden Merkmale 11 bis 19,
  • - wobei eine Datenschnittstelle der eine oder mehreren Datenschnittstellen eine drahtgebundene automobile Datenbusschnittstelle ist und
  • - wobei die drahtgebundene automobile Datenbusschnittstelle insbesondere
    • - eine CAN-Datenbusschnittstelle und/oder
    • - eine CAN-FD-Datenbusschnittstelle und/oder
    • - eine Flexray-Datenbusschnittstelle und/oder
    • - eine PSI5-Datenbusschnittstelle und/oder
    • - eine DSI3-Datenbusschnittstelle und/oder
    • - eine LIN-Datenbusschnittstelle und/oder
    • - eine Ethernet-Datenbusschnittstelle und/oder
    • - eine LIN-Datenbusschnittstelle und/oder
    • - eine MELIBUS-Datenbusschnittstelle umfasst
• Merkmal 21: Sicherer Mikrocontroller nach einem oder mehreren der vorausgehenden Merkmale 11 bis 20,
  • - wobei eine Datenschnittstelle der eine oder mehreren Datenschnittstellen eine drahtlose Datenbusschnittstelle ist und
  • - wobei die drahtlose Datenbusschnittstelle insbesondere
    • - eine WLAN-Schnittstelle und/oder
    • - eine Bluetooth-Schnittstelle
    umfasst.
• Merkmal 22: Sicherer Mikrocontroller nach einem oder mehreren der vorausgehenden Merkmale 11 bis 21,
  • - wobei eine Datenschnittstelle der eine oder mehreren Datenschnittstellen eine drahtgebundene Datenbusschnittstelle ist und
  • - wobei die drahtlose Datenbusschnittstelle insbesondere
  • - eine KNX-Datenbusschnittstelle und/oder
  • - eine EIB-Datenbusschnittstelle und/oder
  • - eine DALI-Datenbusschnittstelle und/oder
  • - eine PROFIBUS-Datenbusschnittstelle
  ist.
• Merkmal 23: Eine Vorrichtung,
  • wobei die Vorrichtung eine integrierte Schaltung (4) mit einem ersten Prozessor (10-1) und einem nichtflüchtigen Speicher (16) aufweist und
  • wobei die Vorrichtung einen ersten Speicher aufweist,
  • wobei der nicht flüchtige Speicher zumindest mindestens einen Sicherheitscode speichert;
  • wobei der erste Speicher Daten speichert und
  • wobei die Daten in dem ersten Speicher in einem ersten Format kryptografisch geschützt sind und
  • wobei die integrierte Schaltung dazu eingerichtet ist, während einer Übertragung von Daten aus dem ersten Speicher die aus dem ersten Speicher gelesenen Daten zu validieren und,
  • wobei die Vorrichtung einen Quantenzufallszahlengenerator (28) nach einem der Merkmale 1 bis 9 aufweist und
  • wobei die integrierte Schaltung und der Quantenzufallszahlengenerator (28) in einem Halbleiterkristall gefertigt sind und
  • wobei der Halbleiterkristall eine Oberfläche (56) aufweist und
  • wobei der Halbleiterkristall ein halbleitendes Material unterhalb seiner Oberfläche (56) aufweist und
  • wobei die Oberfläche (56) des Halbleiterkristalls einen Metallisierungsstapel aufweist und
  • wobei der Metallisierungsstapel eine typischerweise strukturierte und optisch transparente und elektrisch isolierende Schicht (44) aufweist und
  • wobei zumindest ein Teil dieser typischerweise strukturierten, transparenten und elektrisch isolierenden Schicht (44) der Oberfläche (56) den optischen Lichtwellenleiter 44 bildet und
  • wobei die erste SPAD-Diode (54) aus dem halbleitenden Material des Halbleitersubstrats heraus Photonen (57) in diesen optischen Lichtwellenleiter (44) einstrahlt und
  • wobei der zumindest eine optische Lichtwellenleiter (44) solche Photonen (58) zur zweiten SPAD-Diode (55) transportiert und
  • wobei der optische Lichtwellenleiter (44) die zweite SPAD-Diode (55) so bestrahlt, dass das Licht (59) von innerhalb des Lichtwellenleiters (44) wieder in das halbleitende Material des Halbeleitersubstrats von der Oberfläche (56) aus eindringt und dort Vorrichtungsteile der zweiten SPAD-Diode (55) trifft und
  • wobei die erste SPAD-Diode (54) und die zweite SPAD-Diode (55) und der Lichtwellenleiter (44) Teil des Quantenzufallszahlengenerators (28) sind.
• Merkmal 24: Vorrichtung nach Merkmal 23,
  • wobei die Vorrichtung zumindest eine Betriebsschaltung aufweist und
  • wobei die zumindest eine Betriebsschaltung die zumindest eine erste SPAD-Diode (54) zumindest zeitweise mit elektrischer Energie versorgt und
  • wobei die zumindest eine erste SPAD-Diode (54) bei Versorgung mit ausreichender elektrischer Energie Photonen (57) in den zumindest einen Lichtwellenleiter (44) einspeist und
  • wobei der zumindest eine Lichtwellenleiter (44) solche Photonen (58) zur zweiten SPAD-Diode (55) transportiert und
  • wobei der zumindest eine Lichtwellenleiter (44) solche Photonen (59) in die zweite SPAD-Diode (55) einstrahlt.
• Merkmal 25: Vorrichtung nach Merkmal 24,
  • wobei der Quantenzufallszahlengenerator (28) zumindest die erste SPAD-Diode (54) als Lichtquelle für das optische Quantensignal umfasst und
  • wobei der Quantenzufallszahlengenerator (28) zumindest die zweite SPAD-Diode (55) als Fotodetektor für das optische Quantensignal umfasst und
  • wobei der Quantenzufallszahlengenerator (28) zumindest eine Verarbeitungsschaltung umfasst und
  • wobei der Quantenzufallszahlengenerator (28) zumindest den optischen Lichtwellenleiter (44) umfasst und
  • wobei der zumindest eine optische Lichtwellenleiter (44), die zumindest eines erste SPAD-Diode (54) mit der zumindest einen zweiten SPAD-Diode (55) optisch koppelt und
  • wobei die Betriebsschaltung die erste SPAD-Diode (54) so mit elektrischer Energieversorgt, dass die erste SPAD-Diode Licht (54) emittiert und
  • wobei die Verarbeitungsschaltung das Signal der zweiten SPAD-Diode (55) erfasst und daraus die Zufallszahl bildet und dem Prozessor (10) oder einem anderen Vorrichtungsteil zur Verfügung stellt.
• Merkmal 26: Vorrichtung nach einem der Merkmale 23 bis 24,
  • wobei sich der erste Speicher innerhalb oder außerhalb der integrierten Schaltung befindet und
  • wobei die Vorrichtung einen zweiten Speicher zum Speichern von Daten aufweist
  • und wobei sich der zweite Speicher innerhalb oder außerhalb der integrierten Schaltung; befindet;
  • wobei die Vorrichtung so eingerichtet ist,
  • dass sie Daten vom ersten Speicher über die integrierte Schaltung zum zweiten Speicher überträgt, damit der Prozessor vom zweiten Speicher aus darauf zugreifen kann, und
  • wobei die integrierte Schaltung dazu eingerichtet ist,
  • während einer Übertragung von Daten aus dem ersten Speicher in den zweiten Speicher die aus dem ersten Speicher gelesenen Daten unter Verwendung eines in dem nichtflüchtigen Speicher gespeicherten Sicherheitscodes zu validieren und,
  • falls die Daten validiert werden, einen kryptographischen Schutz in einem zweiten Format auf die validierten Daten unter Verwendung eines in dem nichtflüchtigen Speicher gespeicherten Sicherheitscodes anzuwenden, und
  • die im zweiten Format geschützten Daten im zweiten Speicher zu speichern.
• Merkmal 27: Vorrichtung nach einem der Merkmale 23 bis 26, wobei der erste Speicher einen Festwertspeicher aufweist.
• Merkmal 28: Vorrichtung nach einem der Merkmale 26 bis 27, wobei der zweite Speicher einen Direktzugriffsspeicher aufweist.
• Merkmal 29: Vorrichtung nach einem der Merkmale 26 bis 28, wobei der kryptografische Schutz, der auf die Daten im ersten Speicher angewendet wird, sich von dem kryptografischen Schutz unterscheidet, der auf die Daten im zweiten Speicher angewendet wird.
• Merkmal 30: Vorrichtung nach einem der Merkmale 23 bis 29,
  • wobei die integrierte Schaltung einen Speicher zum Speichern von Daten enthält, die von dem Prozessor verarbeitet werden sollen, und
  • wobei das Gerät so eingerichtet ist, dass es einige Daten des validierten Datensatzes im Speicher und den Rest im zweiten Speicher speichert.
• Merkmal 31: Vorrichtung nach einem der Merkmale 26 bis 30, wobei der erste Speicher Daten in einem ersten Datenformat speichert und der zweite Speicher so angeordnet ist, dass er Daten in einem zweiten, anderen Datenformat speichert.
• Merkmal 32: Vorrichtung nach Merkmal 31,
  • wobei die im ersten Speicher gespeicherten Daten durch eine erste Authentifizierungstechnik geschützt sind und
  • wobei die Vorrichtung so eingerichtet ist, dass sie die Daten im zweiten Speicher durch eine zweite, andere Authentifizierungstechnik schützt.
• Merkmal 33: Vorrichtung nach einem der Merkmale 26 bis 32,
  • wobei die Daten in dem ersten Speicher in mindestens einem Datensatz gespeichert sind und der oder jeder Datensatz als Satz kryptografisch geschützt ist und
  • wobei die Vorrichtung so eingerichtet ist, dass sie in dem zweiten Speicher Wörter oder Wortgruppen eines validierten Datensatzes speichert, wobei jedes Wort oder jede Wortgruppe separat kryptografisch geschützt ist.
• Merkmal 34: Vorrichtung nach Merkmal 33, die so beschaffen ist,
  • dass sie die Wörter oder Wortgruppen aus dem zweiten Speicher liest, und
  • dass sie die gelesenen Wörter oder Wortgruppen unter Verwendung eines in dem nichtflüchtigen Speicher gespeicherten Sicherheitscodes validiert und
  • dass sie die gelesenen und validierten Wörter oder Wortgruppen in dem Prozessor verarbeitet.
• Merkmal 35: Vorrichtung nach Merkmal 34,
  • wobei die integrierte Schaltung einen Hash-Rechner aufweist, und
  • wobei der Prozessor und der Hash-Rechner (Hash-Engine) so angeordnet sind,
  • dass a) für jedes Wort oder jede Gruppe von Wörtern eine Hash-Funktion in Abhängigkeit von einem in dem nichtflüchtigen Speicher gespeicherten Sicherheitscode berechnen und den Hash in Verbindung mit dem Wort oder der Gruppe in dem zweiten Speicher speichern,
  • b) Abrufen eines gespeicherten Worts oder einer Gruppe aus dem zweiten Speicher, Neuberechnen einer Hash-Funktion für das abgerufene Wort oder die abgerufene Gruppe unter Verwendung des Sicherheitscodes und Vergleichen des neu berechneten Hashs mit dem gespeicherten Hash, und
  • c) die Verarbeitung des abgerufenen Worts oder der abgerufenen Gruppe durch die Datenverarbeitungsanlage nur dann zulassen, wenn die neu berechneten und gespeicherten Hashes in einem bestimmten Verhältnis zueinanderstehen.
• Merkmal 36: Vorrichtung nach Merkmal 35, wobei der Hash-Rechner eine Schaltung in der integrierten Schaltung ist.
• Merkmal 37 Vorrichtung nach einem der Merkmale 23 bis 36, wobei der nichtflüchtige Speicher der integrierten Schaltung ein einmalig programmierbarer Speicher ist.
• Merkmal 38 Vorrichtung nach einem der Merkmale 23 bis 37, wobei der oder jeder im ersten Speicher gespeicherte Datensatz durch eine entsprechende digitale Signatur kryptographisch geschützt ist.
• Merkmal 39: Vorrichtung nach einem der Merkmale 23 bis 38, wobei der oder jeder im ersten Speicher gespeicherte Datensatz durch eine entsprechende digitale Signatur kryptographisch unter Zuhilfenahme zumindest einer Zufallszahl des Quantenzufallszahlengenerators geschützt ist.
• Merkmal 40: Vorrichtung nach Merkmal 38 oder 39, wobei in dem nichtflüchtigen Speicher der integrierten Schaltung ein Sicherheitscode gespeichert ist, den die Vorrichtung zumindest teilweise mittels zumindest einer Zufallszahl des Quantenzufallszahlgenerators (28) erzeugt hat.
• Merkmal 41: Vorrichtung nach einem der Merkmale 38 bis 39, wobei die Vorrichtung so eingerichtet ist, dass sie eine digitale Signatur des Datensatzes unter Bezugnahme auf einen oder unter Bezugnahme auf den in dem nichtflüchtigen Speicher der integrierten Schaltung gespeicherten Sicherheitscode validiert.
• Merkmal 42: Ein Datenverarbeitungsgerät,
  • wobei das Datenverarbeitungsgerät eine integrierte Schaltung aufweist und
  • wobei die integrierte Schaltung einen Prozessor aufweist und
  • wobei die integrierte Schaltung einen nichtflüchtigen Speicher und
  • wobei der nichtflüchtige Speicher mindestens einen Sicherheitscode speichert und
  • wobei die integrierte Schaltung einen Hash-Rechner aufweist und
  • wobei die integrierte Schaltung eine Schnittstelle an der Grenze der integrierten Schaltung aufweist und
  • wobei die integrierte Schaltung einen Quantenzufallszahlengenerator nach einem der Merkmale 1 bis 9 aufweist und
  • wobei die integrierte Schaltung und der Quantenzufallszahlengenerator in einem Halbleiterkristall gefertigt sind und
  • wobei der Halbleiterkristall eine Oberfläche (56) aufweist und
  • wobei der Halbleiterkristall ein halbleitendes Material unterhalb seiner Oberfläche (56) aufweist und
  • wobei die Oberfläche (56) des Halbleiterkristalls einen Metallisierungsstapel aufweist und
  • wobei der Metallisierungsstapel eine typischerweise strukturierte und optisch transparente und elektrisch isolierende Schicht (44) aufweist und
  • wobei zumindest ein Teil dieser typischerweise strukturierten, transparenten und elektrisch isolierenden Schicht (44) der Oberfläche (46) den optischen Lichtwellenleiter (44) bildet und
  • wobei die erste SPAD-Diode (54) aus dem halbleitenden Material des Halbleitersubstrats heraus Photonen (57) in diesen optischen Lichtwellenleiter (44) einstrahlt und
  • wobei der zumindest eine Lichtwellenleiter (44) solche Photonen (58) zur zweiten SPAD-Diode 55 transportiert und
  • wobei der optische Lichtwellenleiter (44) die zweite SPAD-Diode (55) so bestrahlt, dass das Licht (59) von innerhalb des Lichtwellenleiters (44) wieder in das halbleitende Material des Halbeleitersubstrats von der Oberfläche (56) aus eindringt und dort Vorrichtungsteile der zweiten SPAD-Diode (55) trifft und
  • wobei die erste SPAD-Diode (54) und die zweite SPAD-Diode (55) und der Lichtwellenleiter (44) Teil des Quantenzufallszahlengenerators (28) sind.
• Merkmal 43: Datenverarbeitungsgerät nach Anspruch 42, wobei der Prozessor und/oder ein anderer Vorrichtungsteil des Datenverarbeitungsgeräts Daten unter Zuhilfenahme zumindest einer Zufallszahl des Quantenzufallszahlengenerators verschlüsselt oder entschlüsselt.
• Merkmal 44: Datenverarbeitungsgerät nach Merkmal 42 oder 43,
  • wobei das Datenverarbeitungsgerät einen Speicher aufweist und
  • wobei der Speicher zum Speichern von Daten bei Verwendung durch den Prozessor dient und;
  • wobei der Speicher mit dem Prozessor gekoppelt ist, um Wörter vom Prozessor zu empfangen und Wörter an den Prozessor zu liefern.
• Merkmal 45: Datenverarbeitungsgerät nach einem der Merkmale 42 bis 44,
  • wobei der Speicher extern von der integrierten Schaltung ist und
  • wobei der Speicher über die Schnittstelle an der Grenze der integrierten Schaltung mit dem Prozessor gekoppelt ist, um Wörter vom Prozessor zu empfangen und Wörter an den Prozessor zu liefern.
• Merkmal 46 Datenverarbeitungsgerät nach einem der Ansprüche 42 bis 45,
  • wobei der Prozessor und der Hash-Rechner sind so angeordnet, dass sie
    • - a) für jedes Wort eine Hash-Funktion in Abhängigkeit von einem in dem nichtflüchtigen Speicher gespeicherten Sicherheitscode berechnen und den Hash in Verbindung mit dem Wort speichern,
    • - b) Abrufen gespeicherter Wörter aus dem Speicher, Neuberechnen einer Hash-Funktion für jedes abgerufene Wort unter Verwendung des Sicherheitscodes und Vergleichen des neu berechneten Hash-Wertes mit dem gespeicherten Hash-Wert, und
    • - c) die Verarbeitung des abgerufenen Wortes durch die Datenverarbeitungsanlage nur dann zuzulassen, wenn die neu berechneten und gespeicherten Hashes eine vorher festgelegte Beziehung aufweisen.
• Merkmal 47: Eine Vorrichtung, die Folgendes umfasst:
  • eine integrierte Schaltung, die ein Datenverarbeitungsmittel und ein nichtflüchtiges Speichermittel enthält, das mindestens einen Sicherheitscode speichert;
  • ein erstes Mittel, das Daten speichert, wobei die Daten in einem ersten Format zumindest durch einen Authentifizierungscode kryptografisch geschützt sind; und
  • einen Quantenzufallszahlengenerator (28) nach einem der Merkmale 1 bis 9 als Teil der integrierten Schaltung,
  • wobei der Quantenzufallszahlengenerator eine Photonenquelle (54) und einen Photonendetektor (55) umfasst, die, insbesondere über einen Lichtwellenleiter (44), der insbesondere außerhalb des Halbleitersubstrats der integrierten Schaltung auf der Oberfläche der integrierten Schaltung gefertigt ist, miteinander gekoppelt sind oder gekoppelt werden können und
  • wobei die Vorrichtung zumindest eine Zufallszahl des Quantenzufallszahlengenerators (28) für eine Verschlüsselung oder Entschlüsselung eines Datums oder des Authentifizierungscodes zumindest zeitweise nutzt.
• Merkmal 48 Eine Vorrichtung nach Merkmal 47,
  • wobei die Vorrichtung eine zweite Einrichtung, insbesondere außerhalb des integrierten Schaltkreises, zur Speicherung von Daten aufweist und
  • wobei die Vorrichtung Mittel zum Übertragen von Daten vom ersten Speicher über die integrierte Schaltung zum zweiten Speicher aufweist, damit der Prozessor vom zweiten Speicher aus darauf zugreifen kann, und
  • wobei die Vorrichtung Mittel zur Validierung der aus dem ersten Speicher gelesenen Daten während der Übertragung unter Verwendung eines in dem nichtflüchtigen Speicher gespeicherten Sicherheitscodes aufweist und
  • wobei die Vorrichtung Mittel zum Anwenden eines kryptografischen Schutzes, der mindestens einen Authentifizierungscode umfasst, auf die validierten Daten in einem zweiten Format unter Verwendung eines in dem nichtflüchtigen Speicher gespeicherten Sicherheitscodes, wenn die Daten validiert werden, aufweist und
  • wobei die Vorrichtung Mittel zum Speichern der geschützten Daten im zweiten Speicher im zweiten Format ausweist.
• Merkmal 49: Vorrichtung, insbesondere nach einem der Merkmale 23 bis 48,
  • wobei die Vorrichtung einen Quantenzufallszahlengenerator (28) nach einem der Merkmale 1 bis 9 umfasst und
  • wobei der Quantenzufallszahlengenerator folgende Vorrichtungsteile umfasst:
    • eine Photonenquelle (54)
    • einen Photonendetektor (55),
    • wobei der Photonendetektor (55) mit der Photonenquelle (55) optisch gekoppelt ist, einen optionalen Lichtwellenleiter (44), für diese optische Kopplung,
    • einen optionalen Verstärker (404) und/oder Filter,
    • einen Analog-zu-Digital-Wandler (403),
    • einen optionalen Komparator (404.2),
    • einen Zeit-zu-Pseudozufallszahlen-Wandler (404.3),
    • eine Entropie-Extraktionsvorrichtung (404.4), die Ausgangswerte des Zeit-zu-Pseudozufallszahlen-Wandlers (403) in erste und zweite Werte wandelt und daraus Quantenzufallsbits 411 erzeugt.
• Merkmal 50: Vorrichtung nach Merkmal 49, wobei die Vorrichtung einen Watchdog (404.5) umfasst, der Vorrichtungsteile des Quantenzufallszahlengenerators (28) überwacht.
• Merkmal 51: Vorrichtung nach einem der Merkmale 49 bis 50, wobei die Vorrichtung einen Spannungsmonitor (413) aufweist, der analoge Werte analoger Signale des Quantenzufallszahlengenerators (28) und/oder für den Betrieb des Quantenzufallszahlengenerators (28) erfasst und überwacht.
• Merkmal 52: Vorrichtung nach einem der Merkmale 49 bis 51, wobei die Vorrichtung einen weiteren Pseudozufallszahlengenerator (404.6), insbesondere in Form eines linear rückgekoppelten Schieberegisters (404.6), umfasst.
• Merkmal 53: Vorrichtung nach einem der Merkmale 49 bis 52, wobei die Vorrichtung einen Signalmultiplexer (404.7) aufweist, der im Falle eines Fehlers von dem Signal des Ausgangs (411) der Entropie-Extraktionsvorrichtung auf ein Signal eines Ersatz-Zufallszahlengenerators oder eines Ersatzpseudozufallszahlengenerators (404.6) umschaltet.
• Merkmal 54: Vorrichtung nach einem der Merkmale 49 bis 53, wobei der Startwert des zusätzlichen Pseudozufallszahlengenerators 404.6 im Fehlerfall von zuvor korrekt erzeugten Quantenzufallsbits 411 des Quantenzufallszahlengenerators (28) abhängt.
• Merkmal 55: Verfahren zur Erzeugung eines Zufallsbits
  • Erzeugen einer Pulsfolge mit zufälligen Abständen mittels einer Photonenquelle (54), insbesondere einer Silizium-LED (54) und/oder insbesondere einer ersten SPAD-Diode (54), und eines Photonendetektors (55), insbesondere einer zweiten SPAD-Dioden (55),
  • Erzeugen (501) eines ersten Werts in Form einer ersten Pseudozufallszahl in Abhängigkeit von dem zeitlichen Abstand zwischen einem ersten Puls und einem zweiten Puls, der vom ersten Puls verschieden ist;
  • Erzeugen (501) zweiten Werts in Form einer zweiten Pseudozufallszahl in Abhängigkeit des zeitlichen Abstands zwischen einem dritten Puls, der vom ersten Puls verschieden ist, und einem vierten Puls, der vom ersten Puls und vom zweiten Puls und vom dritten Puls verschieden ist.
  • Vergleichen (502) des ersten Werts mit dem zweiten Wert und
  • Ausgeben (503) eines ersten logischen Werts als ein Quantenzufallsbit (411), wenn der erste Wert größer als der zweite Wert ist, und
  • Ausgeben (503) eines zweiten logischen Werts, der vom ersten logischen Wert verschieden ist, als das Zufallsbit, wenn der erste Wert kleiner als der zweite Wert ist.
• Merkmal 56: Verfahren (3700) zur Erzeugung einer Quantenzufallszahl QZ (418) mit m Quantenzufallsbits (411) mit den Schritten;
  • Erzeugung (3710) eines zufälligen Einzelphotonenstroms 57, 58, 59, 44 aus Einzelphotonen mittels einer oder mehrerer Photonenquellen, insbesondere einer oder mehrerer Silizium-LEDs (54) und/oder einer oder mehrerer erster SPAD-Dioden (54);
  • Übertragung (3720) des zufälligen Einzelphotonenstroms (57, 58, 59, 44), insbesondere mittels eines vom Halbleitersubstrat (49, 48) verschiedenen Lichtwellenleiters 44 und/oder des Halbleitersubstrats oder durch direkte Übertragung, an einen oder mehrere Photonendetektoren (55), insbesondere eine oder mehrere zweite SPAD-Dioden (55);
  • Wandlung (3730) des zufälligen Einzelphotonenstroms (57, 58, 59, 44) in ein Detektionssignal mittels der einen oder der mehreren Photonendetektoren (55);
  • Aufbereiten (3740) des Detektionssignals in ein aufbereitetes Detektionssignal;
  • Ermittlung (3760) einer ersten Pseudozufallszahl in Abhängigkeit von einem ersten zeitlichen Abstand zwischen einem ersten Puls und einem zweiten Puls eines ersten Paares aus zwei aufeinander folgenden, durch Kopplungen der Emissionen der Photonenquelle (54) und des Photonendetektors (55) entstandenen Pulse des aufbereiteten Detektionssignals und
  • Ermittlung (3765) einer zweiten Pseudozufallszahl in Abhängigkeit von einem zweiten zeitlichen Abstand zwischen einem dritten Puls und einem vierten Puls eines zweiten Paares aus zwei aufeinander folgenden, durch Kopplungen der Emissionen der Photonenquelle (54) und des Photonendetektors (55) entstandenen Pulse des aufbereiteten Detektionssignals;
  • Ermittlung (3770) des Bit-Werts eines Quantenzufallsbits (411) durch Vergleich des Werts des ersten Pseudozufallszahl und des Werts der zweiten Pseudozufallszahl;
  • Sofern die Anzahl (3780) n der ermittelten Zufallsbits kleiner als die gewünschte Zahl m der Zufallsbits der zu erzeugenden Quantenzufallszahl QZ (418) ist, Wiederholung der vorstehenden Schritte (3710 bis 3770) und Beenden des Prozesses zur Erzeugung einer Quantenzufallszahl sofern die Anzahl (3780) n der ermittelten Zufallsbits größer oder gleich der gewünschten Zahl m der Zufallsbits der zu erzeugenden Quantenzufallszahl (418) QZ ist.

The features of the invention summarize these again. Applications of the technical teaching can combine the features with one another, provided that these combinations do not cause factual contradictions. In this respect, the dependencies and relationships presented here only represent particularly preferred, exemplary embodiments.

• Feature 1: Quantum process-based generator (28) for true random numbers (411, 418) (English: Quantum Random Number Generator: QRNG),
  • - wherein the quantum process-based generator (28) for true random numbers (411, 418) (English: Quantum Random Number Generator: QRNG) has an entropy source (401) and
  • - wherein the quantum process-based generator (28) for true random numbers (411, 418) (English: Quantum Random Number Generator: QRNG) evaluates a signal (405) of the entropy source (401) by means of a time-to-pseudo-random number converter (TPRC) (404.3) and generates one or more random bits (411).
• Feature 2: Quantum process-based generator (28) for true random numbers (411, 418) according to feature 1,
  • - wherein the quantum process-based generator (28) for true random numbers (411, 418) generates one or more random numbers (418) from several random bits (411) and makes them available or uses them.
• Feature 3: Quantum process-based generator (28) for true random numbers (411, 418) according to feature 1 or 2,
  • - wherein the behavior of the P of a time-to-pseudorandom number converter (TPRG) (404.3) depends on one or more quantum random bits (411) and/or one or more quantum random numbers (418).
• Feature 4: Quantum process-based generator (28) for true random numbers (411, 418) according to one of features 1 to 3,
  • - wherein the quantum process-based generator (28) for true random numbers (411, 418) comprises a watchdog (404.5) which monitors the correct functioning of the quantum process-based generator (28) for true random numbers (411, 418).
• Feature 5: Quantum process-based generator (28) for true random numbers (411, 418) according to one of features 1 to 4,
  • - wherein the quantum process-based generator (28) for true random numbers (411, 418) comprises a watchdog (404.5) which monitors the correct functioning of the quantum process-based generator (28) for true random numbers (411, 418) by measuring the randomness of the generated quantum random bits (411) in the form of a measured value and comparing it with a tolerance interval or a threshold value and concluding that there is an error in the event of a deviation.
• Feature 6: Quantum process-based generator (28) for true random numbers (411, 418) according to one of features 1 to 5,
  • - wherein the quantum process-based generator (28) for true random numbers (411, 418) comprises a watchdog (404.5) which monitors the correct functioning of a time-to-pseudo-random number converter (TPRC) (404.3) and detects and/or signals an error in the event of deviations from an expected behavior.
• Feature 7: Quantum process-based generator (28) for true random numbers (411, 418) according to one of features 1 to 6,
  • - wherein the quantum process-based generator (28) for true random numbers (411, 418) is manufactured in one piece as part of an integrated circuit (2) and
  • - wherein the integrated circuit (2) comprises a voltage converter (91) for supplying the entropy source (401) of the quantum process-based generator (28) for true random numbers (411, 418) and
  • - wherein the voltage converter (91) comprises one or more DMOS transistors.
• Feature 8: Quantum process-based generator (28) for true random numbers (411, 418) according to feature 7,
  • - wherein the integrated circuit (2) is manufactured using a BCD technology.
• Feature 9: Quantum process-based generator (28) for true random numbers (411, 418) according to one of features 1 to 8,
  • - wherein the quantum process-based generator (28) for true random numbers (411, 418) is manufactured in one piece as part of an integrated circuit (2) and
  • - wherein the integrated circuit (2) is one of the following circuits or comprises one of the following circuits:
    • - A microcontroller,
    • - a microprocessor,
    • - a storage,
    • - a DRAM,
    • - a SRAM,
    • - a RAM,
    • - a volatile memory,
    • - an OTP storage,
    • - an EEPROM,
    • - a flash memory,
    • - an MRAM,
    • - a FRAM,
    • - a sensor evaluation circuit,
    • - a control circuit for an automotive control circuit,
    • - a graphics controller,
    • - an evaluation circuit for a biometric sensor or an input device,
    • - a control circuit,
    • - a chip card circuit,
    • - a circuit of a mobile phone or a smart phone,
    • - a circuit of an access control system,
    • - a circuit with a coded recording of operating parameters,
    • - a circuit of an access control system,
    • - a circuit of a security system of electronic fuses,
    • - a radio system circuit,
    • - a communication circuit,
    • - a circuit of an encryption and/or decryption system,
    • - a circuit of an individualization system
    • - a circuit of a gaming device,
    • - a circuit of a simulation system,
    • - a circuit of a computer system,
    • - a circuit of a noise source,
    • - a circuit comprising a device for generating and/or using a spreading code.
• Feature 10: Quantum process-based generator (28) for true random numbers (411, 418) according to one of features 1 to 9,
  • - wherein the entropy source (401) comprises a photon source (54) and
  • - wherein the entropy source (401) comprises a photon detector (55) and
  • - wherein the photon source (54) emits photons as a quantum signal when supplied with electrical energy and
  • - wherein the photon source (54) is optically coupled to the photon detector (55) and
  • - wherein the photon detector (55) at least partially receives the quantum signal of the photon source (54) and generates the output signal (405) of the entropy source (401) or a precursor signal thereof.
• Feature 11: Secure microcontroller for controlling devices, especially in automobiles
  • - with a semiconductor crystal and
  • - with storage elements and
  • - with at least one internal bus (419) and
  • - with at least one processor (10-1), in particular an 8/16/32/15-bit microcontroller core, and
  • - with one or more data interfaces and
  • - with at least one quantum process-based generator (28) for true random numbers (411, 418) (English: Quantum Random Number Generator: QRNG) according to one of the features 1 to 9, and
  • - wherein the memory elements are connected to the internal bus (419) and
  • - wherein the data interface is connected to the internal bus (419) and
  • - wherein in particular the quantum process-based generator for true random numbers (QRNG) (28) can be connected to the internal bus (419) and
  • - wherein the processor (10-1) is connected to the internal bus (419) and
  • - wherein the quantum process-based true random number generator (QRNG) (28), in particular upon request of the processor (10-1), generates or provides a random number (418) and
  • - wherein the processor (10-1) generates a key using a program from one or more of its memory elements and using the random number and
  • - wherein the processor (10-1) uses a program from one or more of its memory elements and the key to encrypt and decrypt data which it exchanges via the data interface with devices outside the secure microcontroller, and
  • - wherein the semiconductor crystal integrally comprises these sub-devices of the secure microcontroller,
  • - wherein these sub-devices of the secure microcontroller comprise the memory elements, the internal bus (419), the at least one processor (10-1), the data interfaces and the quantum process-based generator for true random numbers (English: Quantum Random Number Generator: QRNG) (28),
• Feature 12: Secure microcontroller according to feature 11,
  • - wherein the memory elements comprise one or more RAM read/write memories and/or one or more writable non-volatile memories, in particular EEPROM memories and/or flash memories and/or OTP memories, and/or one or more read-only memories and/or one or more non-volatile manufacturer memories, in particular one or more manufacturer ROMs and/or one or more manufacturer EEPROMs and/or one or more manufacturer flash memories.
• Feature 13: Secure microcontroller according to feature 12,
  • - where the manufacturer ROM includes the boot software.
• Feature 14: Secure microcontroller according to feature 12 or 13,
  • - wherein a manufacturer memory firewall is provided between the manufacturer memory and the internal bus (419).
• Feature 15: Secure microcontroller according to one or more of features 11 to 14
  • - with one or more of the following components:
    • - a clock generator (92) (among other things for the system clock 2106)
    • - a reset circuit (83) and/or
    • - one or more voltage converters (91) which provide the operating voltages, and/or
    • - a ground circuit in the negative supply voltage line (GND), in particular to prevent attacks via ground offset, and/or
    • - an input/output circuit and/or
    • - one or more processing modules,
  • - wherein the processing modules are arranged to communicate with the internal bus (419), and
  • - wherein the processing modules comprise one or more of the following modules:
    • - a CRC module (Cyclic Redundancy Check),
    • - a clock generator module,
    • - with a DES accelerator and/or an AES accelerator
    • - one or more timer modules,
    • - a safety monitoring and control circuit,
    • - a data interface, in particular a Universal Asynchronous Receiver Transmitter (UART).
• Feature 16: Secure microcontroller 1according to one or more of features 11 to 15,
  • - with at least one photon source (54), in particular a silicon LED (54) or a first SPAD diode (54), and
  • - with at least one photon detector (54), in particular a second SPAD diode (55), and
  • - with at least one processing circuit and
  • - with at least one operating circuit,
  • - wherein the quantum process-based true random number generator (QRNG) (28) comprises at least the photon source (54) as a light source for the optical quantum signal and
  • - wherein the quantum process-based true random number generator (QRNG) (28) comprises at least the photon detector (55) as a photodetector for the optical quantum signal and
  • - wherein the quantum process-based true random number generator (QRNG) (28) comprises at least the processing circuit and
  • - wherein the at least one photon source (54) is optically coupled to the at least one photon detector (55) and
  • - wherein the operating circuit supplies the photon source (54) with electrical energy such that the photon source (54) emits light and
  • - wherein the processing circuit detects the signal of the photon detector (55) and forms the random number therefrom and makes it available to the processor (10-1).
• Feature 17: Secure microcontroller 11 according to feature 16,
  • - with at least one optical waveguide (44),
  • - wherein the quantum process-based true random number generator (QRNG) (28) comprises at least the optical fiber (44) and
  • - wherein the at least one optical waveguide (44) optically couples the at least one photon source (54) to the at least one photon detector (55).
• Feature 18: Secure microcontroller according to feature 17
  • - wherein the semiconductor crystal has a surface (56) and
  • - wherein the semiconductor crystal has a semiconducting material beneath its surface (56) and
  • - wherein the surface (56) of the semiconductor crystal has a metallization stack and
  • - wherein the metallization stack comprises a typically structured and optically transparent and electrically insulating layer (44) and
  • - wherein at least a part of this typically structured, transparent and electrically insulating layer (44) of the surface (56) forms the optical waveguide (44) and
  • - wherein the photon source (54) radiates from the semiconducting material of the semiconductor substrate into this optical waveguide (44) and
  • - wherein the optical waveguide (44) irradiates the photon detector (54) in such a way that the light from within the optical waveguide (44) penetrates back into the semiconducting material of the semiconductor substrate from the surface and there strikes device parts of the photon detector (55).
• Feature 19: Secure microcontroller according to feature 17 and/or 18,
  • - wherein the at least one operating circuit supplies the at least one photon source (54) at least temporarily with electrical energy and
  • - wherein the at least one photon source (54) feeds photons into the at least one optical waveguide (44) when supplied with sufficient electrical energy and
  • - wherein the at least one optical waveguide (44) radiates such photons into the photon detector (55).
• Feature 20: Secure microcontroller according to one or more of the preceding features 11 to 19,
  • - wherein a data interface of the one or more data interfaces is a wired automotive data bus interface and
  • - the wired automotive data bus interface in particular
    • - a CAN data bus interface and/or
    • - a CAN-FD data bus interface and/or
    • - a Flexray data bus interface and/or
    • - a PSI5 data bus interface and/or
    • - a DSI3 data bus interface and/or
    • - a LIN data bus interface and/or
    • - an Ethernet data bus interface and/or
    • - a LIN data bus interface and/or
    • - a MELIBUS data bus interface includes
• Feature 21: Secure microcontroller according to one or more of the preceding features 11 to 20,
  • - wherein a data interface of the one or more data interfaces is a wireless data bus interface and
  • - wherein the wireless data bus interface in particular
    • - a WLAN interface and/or
    • - a Bluetooth interface
    includes.
• Feature 22: Secure microcontroller according to one or more of the preceding features 11 to 21,
  • - wherein a data interface of the one or more data interfaces is a wired data bus interface and
  • - wherein the wireless data bus interface in particular
  • - a KNX data bus interface and/or
  • - an EIB data bus interface and/or
  • - a DALI data bus interface and/or
  • - a PROFIBUS data bus interface
  is.
• Feature 23: A device
  • wherein the device comprises an integrated circuit (4) with a first processor (10-1) and a non-volatile memory (16) and
  • the device comprising a first memory,
  • wherein the non-volatile memory stores at least one security code;
  • where the first memory stores data and
  • wherein the data in the first memory is cryptographically protected in a first format and
  • wherein the integrated circuit is arranged to validate the data read from the first memory during a transfer of data from the first memory and,
  • wherein the device comprises a quantum random number generator (28) according to one of features 1 to 9 and
  • wherein the integrated circuit and the quantum random number generator (28) are manufactured in a semiconductor crystal and
  • wherein the semiconductor crystal has a surface (56) and
  • wherein the semiconductor crystal has a semiconducting material beneath its surface (56) and
  • wherein the surface (56) of the semiconductor crystal has a metallization stack and
  • wherein the metallization stack comprises a typically structured and optically transparent and electrically insulating layer (44) and
  • wherein at least a part of this typically structured, transparent and electrically insulating layer (44) of the surface (56) forms the optical waveguide 44 and
  • wherein the first SPAD diode (54) radiates photons (57) from the semiconducting material of the semiconductor substrate into this optical waveguide (44) and
  • wherein the at least one optical waveguide (44) transports such photons (58) to the second SPAD diode (55) and
  • wherein the optical waveguide (44) irradiates the second SPAD diode (55) such that the light (59) from within the optical waveguide (44) penetrates back into the semiconducting material of the semiconductor substrate from the surface (56) and there strikes device parts of the second SPAD diode (55) and
  • wherein the first SPAD diode (54) and the second SPAD diode (55) and the optical waveguide (44) are part of the quantum random number generator (28).
• Feature 24: Device according to feature 23,
  • wherein the device has at least one operating circuit and
  • wherein the at least one operating circuit supplies the at least one first SPAD diode (54) at least temporarily with electrical energy and
  • wherein the at least one first SPAD diode (54) feeds photons (57) into the at least one optical waveguide (44) when supplied with sufficient electrical energy and
  • wherein the at least one optical waveguide (44) transports such photons (58) to the second SPAD diode (55) and
  • wherein the at least one optical waveguide (44) radiates such photons (59) into the second SPAD diode (55).
• Feature 25: Device according to feature 24,
  • wherein the quantum random number generator (28) comprises at least the first SPAD diode (54) as a light source for the optical quantum signal and
  • wherein the quantum random number generator (28) comprises at least the second SPAD diode (55) as a photodetector for the optical quantum signal and
  • wherein the quantum random number generator (28) comprises at least one processing circuit and
  • wherein the quantum random number generator (28) comprises at least the optical waveguide (44) and
  • wherein the at least one optical waveguide (44) optically couples the at least one first SPAD diode (54) to the at least one second SPAD diode (55) and
  • wherein the operating circuit supplies the first SPAD diode (54) with electrical energy such that the first SPAD diode emits light (54) and
  • wherein the processing circuit detects the signal of the second SPAD diode (55) and forms the random number therefrom and makes it available to the processor (10) or another part of the device.
• Feature 26: Device according to one of features 23 to 24,
  • wherein the first memory is located inside or outside the integrated circuit and
  • wherein the device comprises a second memory for storing data
  • and wherein the second memory is located inside or outside the integrated circuit;
  • the device being arranged so
  • that it transfers data from the first memory via the integrated circuit to the second memory so that the processor can access it from the second memory, and
  • wherein the integrated circuit is arranged
  • during a transfer of data from the first memory to the second memory, to validate the data read from the first memory using a security code stored in the non-volatile memory and,
  • if the data is validated, apply cryptographic protection in a second format to the validated data using a security code stored in the non-volatile memory, and
  • to store the data protected in the second format in the second memory.
• Feature 27: Device according to one of features 23 to 26, wherein the first memory comprises a read-only memory.
• Feature 28: Apparatus according to any one of features 26 to 27, wherein the second memory comprises a random access memory.
• Feature 29: Apparatus according to any one of features 26 to 28, wherein the cryptographic protection applied to the data in the first memory is different from the cryptographic protection applied to the data in the second memory.
• Feature 30: Device according to one of features 23 to 29,
  • wherein the integrated circuit includes a memory for storing data to be processed by the processor, and
  • wherein the device is configured to store some data of the validated data set in memory and the rest in second memory.
• Feature 31: Apparatus according to any one of features 26 to 30, wherein the first memory stores data in a first data format and the second memory is arranged to store data in a second, different data format.
• Feature 32: Device according to feature 31,
  • wherein the data stored in the first memory is protected by a first authentication technique and
  • wherein the device is arranged to protect the data in the second memory by a second, different authentication technique.
• Feature 33: Device according to one of features 26 to 32,
  • wherein the data in the first memory is stored in at least one data set and the or each data set is cryptographically protected as a set and
  • wherein the device is arranged to store words or groups of words of a validated data set in the second memory, each word or group of words being separately cryptographically protected.
• Feature 34: Device according to feature 33, which is designed
  • that it reads the words or groups of words from the second memory, and
  • that it validates the words or groups of words read using a security code stored in the non-volatile memory and
  • that it processes the read and validated words or groups of words in the processor.
• Feature 35: Device according to feature 34,
  • wherein the integrated circuit comprises a hash calculator, and
  • wherein the processor and the hash engine are arranged so that
  • that a) for each word or group of words, calculate a hash function depending on a security code stored in the non-volatile memory and store the hash in association with the word or group in the second memory,
  • b) retrieving a stored word or group from the second memory, recalculating a hash function for the retrieved word or group using the security code and comparing the recalculated hash with the stored hash, and
  • (c) only allow the data processing system to process the retrieved word or group if the newly calculated and stored hashes are in a certain relationship to each other.
• Feature 36: The apparatus of feature 35, wherein the hash calculator is a circuit in the integrated circuit.
• Feature 37 The device of any one of features 23 to 36, wherein the non-volatile memory of the integrated circuit is a one-time programmable memory.
• Feature 38 Apparatus according to any one of features 23 to 37, wherein the or each data set stored in the first memory is cryptographically protected by a corresponding digital signature.
• Feature 39: Device according to one of features 23 to 38, wherein the or each data set stored in the first memory is cryptographically protected by a corresponding digital signature with the aid of at least one random number of the quantum random number generator.
• Feature 40: Device according to feature 38 or 39, wherein a security code is stored in the non-volatile memory of the integrated circuit, which the device has generated at least partially by means of at least one random number of the quantum random number generator (28).
• Feature 41: Apparatus according to any one of features 38 to 39, wherein the apparatus is arranged to validate a digital signature of the data set by reference to or by reference to the security code stored in the non-volatile memory of the integrated circuit.
• Feature 42: A data processing device,
  • wherein the data processing device comprises an integrated circuit and
  • wherein the integrated circuit comprises a processor and
  • wherein the integrated circuit comprises a non-volatile memory and
  • wherein the non-volatile memory stores at least one security code and
  • wherein the integrated circuit comprises a hash calculator and
  • wherein the integrated circuit has an interface at the boundary of the integrated circuit and
  • wherein the integrated circuit comprises a quantum random number generator according to one of features 1 to 9 and
  • wherein the integrated circuit and the quantum random number generator are manufactured in a semiconductor crystal and
  • wherein the semiconductor crystal has a surface (56) and
  • wherein the semiconductor crystal has a semiconducting material beneath its surface (56) and
  • wherein the surface (56) of the semiconductor crystal has a metallization stack and
  • wherein the metallization stack comprises a typically structured and optically transparent and electrically insulating layer (44) and
  • wherein at least a part of said typically structured, transparent and electrically insulating layer (44) of the surface (46) forms the optical waveguide (44) and
  • wherein the first SPAD diode (54) radiates photons (57) from the semiconducting material of the semiconductor substrate into this optical waveguide (44) and
  • wherein the at least one optical waveguide (44) transports such photons (58) to the second SPAD diode 55 and
  • wherein the optical waveguide (44) irradiates the second SPAD diode (55) such that the light (59) from within the optical waveguide (44) penetrates back into the semiconducting material of the semiconductor substrate from the surface (56) and there strikes device parts of the second SPAD diode (55) and
  • wherein the first SPAD diode (54) and the second SPAD diode (55) and the optical waveguide (44) are part of the quantum random number generator (28).
• Feature 43: Data processing device according to claim 42, wherein the processor and/or another device part of the data processing device encrypts or decrypts data with the aid of at least one random number of the quantum random number generator.
• Feature 44: Data processing equipment according to feature 42 or 43,
  • wherein the data processing device has a memory and
  • wherein the memory is for storing data when used by the processor and;
  • wherein the memory is coupled to the processor to receive words from the processor and to provide words to the processor.
• Feature 45: Data processing device according to one of features 42 to 44,
  • where the memory is external to the integrated circuit and
  • wherein the memory is coupled to the processor via the interface at the boundary of the integrated circuit for receiving words from the processor and providing words to the processor.
• Feature 46 Data processing device according to one of claims 42 to 45,
  • where the processor and the hash computer are arranged so that they
    • - a) calculate for each word a hash function depending on a security code stored in the non-volatile memory and store the hash in association with the word,
    • - b) retrieving stored words from the memory, recalculating a hash function for each retrieved word using the security code and comparing the recalculated hash value with the stored hash value, and
    • - c) to allow the processing of the retrieved word by the data processing system only if the newly calculated and stored hashes have a predetermined relationship.
• Feature 47: A device comprising:
  • an integrated circuit containing a data processing means and a non-volatile storage means storing at least one security code;
  • a first means for storing data, the data being cryptographically protected in a first format by at least one authentication code; and
  • a quantum random number generator (28) according to one of features 1 to 9 as part of the integrated circuit,
  • wherein the quantum random number generator comprises a photon source (54) and a photon detector (55) which are or can be coupled to one another, in particular via an optical waveguide (44) which is manufactured in particular outside the semiconductor substrate of the integrated circuit on the surface of the integrated circuit, and
  • wherein the device uses at least one random number of the quantum random number generator (28) for encrypting or decrypting a date or the authentication code at least temporarily.
• Feature 48 A device according to feature 47,
  • wherein the device comprises a second device, in particular outside the integrated circuit, for storing data and
  • the device comprising means for transferring data from the first memory via the integrated circuit to the second memory so that the processor can access it from the second memory, and
  • the device comprising means for validating the data read from the first memory during transmission using a security code stored in the non-volatile memory and
  • the device comprising means for applying cryptographic protection comprising at least one authentication code to the validated data in a second format using a security code stored in the non-volatile memory when the data is validated, and
  • wherein the apparatus comprises means for storing the protected data in the second memory in the second format.
• Feature 49: Device, in particular according to one of features 23 to 48,
  • wherein the device comprises a quantum random number generator (28) according to one of features 1 to 9 and
  • wherein the quantum random number generator comprises the following device parts:
    • a photon source (54)
    • a photon detector (55),
    • wherein the photon detector (55) is optically coupled to the photon source (55), an optional optical waveguide (44) for this optical coupling,
    • an optional amplifier (404) and/or filter,
    • an analog-to-digital converter (403),
    • an optional comparator (404.2),
    • a time-to-pseudo-random number converter (404.3),
    • an entropy extraction device (404.4) which converts output values of the time-to-pseudo-random number converter (403) into first and second values and generates quantum random bits 411 therefrom.
• Feature 50: Device according to feature 49, wherein the device comprises a watchdog (404.5) which monitors device parts of the quantum random number generator (28).
• Feature 51: Device according to one of features 49 to 50, wherein the device comprises a voltage monitor (413) which detects and monitors analog values of analog signals of the quantum random number generator (28) and/or for the operation of the quantum random number generator (28).
• Feature 52: Device according to one of features 49 to 51, wherein the device comprises a further pseudorandom number generator (404.6), in particular in the form of a linear feedback shift register (404.6).
• Feature 53: Device according to one of features 49 to 52, wherein the device comprises a signal multiplexer (404.7) which, in the event of an error, switches from the signal of the output (411) of the entropy extraction device to a signal of a replacement random number generator or a replacement pseudorandom number generator (404.6).
• Feature 54: Device according to one of features 49 to 53, wherein the starting value of the additional pseudorandom number generator 404.6 in the event of an error depends on previously correctly generated quantum random bits 411 of the quantum random number generator (28).
• Feature 55: Method for generating a random bit
  • Generating a pulse sequence with random intervals by means of a photon source (54), in particular a silicon LED (54) and/or in particular a first SPAD diode (54), and a photon detector (55), in particular a second SPAD diode (55),
  • Generating (501) a first value in the form of a first pseudorandom number depending on the time interval between a first pulse and a second pulse which is different from the first pulse;
  • Generating (501) a second value in the form of a second pseudorandom number depending on the time interval between a third pulse, which is different from the first pulse, and a fourth pulse, which is different from the first pulse and the second pulse and the third pulse.
  • Comparing (502) the first value with the second value and
  • Outputting (503) a first logical value as a quantum random bit (411) if the first value is greater than the second value, and
  • Outputting (503) a second logical value, different from the first logical value, as the random bit if the first value is less than the second value.
• Feature 56: Method (3700) for generating a quantum random number QZ (418) with m quantum random bits (411) with the steps;
  • Generation (3710) of a random single photon stream 57, 58, 59, 44 from single photons by means of one or more photon sources, in particular one or more silicon LEDs (54) and/or one or more first SPAD diodes (54);
  • Transmission (3720) of the random single photon stream (57, 58, 59, 44), in particular by means of an optical waveguide 44 different from the semiconductor substrate (49, 48) and/or the semiconductor substrate or by direct transmission, to one or more photon detectors (55), in particular one or more second SPAD diodes (55);
  • Converting (3730) the random single photon stream (57, 58, 59, 44) into a detection signal by means of the one or more photon detectors (55);
  • conditioning (3740) the detection signal into a conditioned detection signal;
  • Determining (3760) a first pseudorandom number as a function of a first time interval between a first pulse and a second pulse of a first pair of two successive pulses of the processed detection signal produced by coupling the emissions of the photon source (54) and the photon detector (55) and
  • Determining (3765) a second pseudorandom number as a function of a second time interval between a third pulse and a fourth pulse of a second pair of two successive pulses of the conditioned detection signal produced by coupling the emissions of the photon source (54) and the photon detector (55);
  • Determining (3770) the bit value of a quantum random bit (411) by comparing the value of the first pseudorandom number and the value of the second pseudorandom number;
  • If the number (3780) n of the random bits determined is less than the desired number m of the random bits of the quantum random number QZ (418) to be generated, repeat the above steps (3710 to 3770) and terminate the process for generating a quantum random number if the number (3780) n of the random bits determined is greater than or equal to the desired number m of the random bits of the quantum random number (418) QZ to be generated.

Advantage

The monolithically integrable quantum random number generator 28 presented here is particularly robust against external attacks. Even in the event of a successful attack on the entropy source 401, the quantum random numbers 411 are not influenced in such a way that the attacker can break an encryption without considerable additional effort. The secure microcontroller presented here therefore has an improved entropy of its random number generator. As a result, the encryption of this secure microcontroller is post quantum secure, in contrast to the state of the art. The advantages are not limited to this, however.

List of characters

• 1 zeigt ein schematisches Blockdiagramm eines Datenverarbeitungsgeräts in Kombination mit einem kontrollierten System;
• 2 zeigt ein schematisches Blockdiagramm einer Schaltung zum Deaktivieren einer Testschnittstelle der Vorrichtung von 1;
• 3 zeigt ein Diagramm, das die Überprüfung digitaler Signaturen veranschaulicht;
• 4 zeigt ein Flussdiagramm, das die Verwendung von HASH-Funktionen beim Speichern und Abrufen von Daten aus einem DRAM der Vorrichtung von 1 veranschaulicht.
• 5 zeigt eine vorschlagsgemäße SPAD-Diode im Querschnitt.
• 6 zeigt die Kombination zweier vorschlagsgemäßer SPAD-Dioden im Querschnitt.
• 7 zeigt die Kombination zweier vorschlagsgemäßer SPAD-Dioden im Querschnitt, wobei nun mehrere Isolationslagen den Lichtwellenleiter 44 ausbilden.
• 8 zeigt die Einbindung der SPAD-Dioden und des Lichtwellenleiters in eine Auswerte- und Betriebsschaltung
• 9 entspricht der 8, die nun um Überwachungsschaltkreise ergänzt ist.
• 10 zeigt ein typisches Ausgangssignal der zweiten SPAD-Diode.
• 11 zeigt ein beispielhaftes Oszillogramm des Spannungssignals 404 der Entropie Quelle 401.
• 12 zeigt den schematischen Ablauf einer Server-Client-Kommunikation unter Nutzung eines vorschlaggemäßen Quantenzufallszahlengenerators.
• 13 zeigt den schematischen Ablauf der Funktionen KeyExchangeServer() und KeyExchangeClient().
• 14 zeigt schematischen Ablauf der Funktion setPrimes().
• 15 zeigt den schematischen Ablauf der Funktion setE() 3400.
• 16 zeigt den schematischen Ablauf der Funktion findD().
• 17 zeigt den schematischen Ablauf einer sicheren Übertragung von quantenbasierten Zufallszahlen zwischen einem ersten Prozessor 10-1 des Rechners, insbesondere in Form einer vorschlagsgemäßen integrierten Schaltung 2, eines Servers 3600 und einem ersten Prozessor 10-1 des Rechners, insbesondere in Form einer weiteren vorschlagsgemäßen integrierten Schaltung 2, eines Client 3610.
• 18 zeigt schematisch das vorschlagsgemäße Verfahren 3700 zur Erzeugung einer Quantenzufallszahl.
• 19 zeigt einen weiteren beispielhaften Vorschlag für einen einstückigen, monolithisch integrierten Schaltkreis 2.
• 20 zeigt eine Vorrichtung ähnlich der Vorrichtung der 8 und 9.
• 21 zeigt ein Beispiel für einen Zeit-zu-Pseudozufallszahl-Wandler 404.3.
• 22 zeigt ein Diagramm, dass die Erfassung der Pulse (2201, 2202, 2203, 2204) auf dem Spannungssignal 405 der Entropie Quelle 401 darstellt.
• 23 zeigt einen beispielhaften Spannungswandler 91 zur Versorgung der Entropiequelle 411 mit einer ausreichenden Betriebsspannung der Versorgungsspannungsleitung V_ENT der Entropiequelle 411 gegenüber der Bezugspotenzialleitung GND auf dem Bezugspotenzial.

The above objects and the advantages described below will be highlighted in the description of a preferred embodiment of the invention, presented as a non-limiting example with reference to the accompanying drawings, in which:

• 1 shows a schematic block diagram of a data processing device in combination with a controlled system;
• 2 shows a schematic block diagram of a circuit for deactivating a test interface of the device of 1 ;
• 3 shows a diagram illustrating the verification of digital signatures;
• 4 shows a flowchart illustrating the use of HASH functions in storing and retrieving data from a DRAM of the device of 1 illustrated.
• 5 shows a proposed SPAD diode in cross section.
• 6 shows the combination of two proposed SPAD diodes in cross section.
• 7 shows the combination of two proposed SPAD diodes in cross section, whereby several insulation layers now form the optical waveguide 44.
• 8th shows the integration of the SPAD diodes and the optical fiber into an evaluation and operating circuit
• 9 equals to 8th , which is now supplemented by monitoring circuits.
• 10 shows a typical output signal of the second SPAD diode.
• 11 shows an example oscillogram of the voltage signal 404 of the entropy source 401.
• 12 shows the schematic flow of a server-client communication using a proposed quantum random number generator.
• 13 shows the schematic flow of the functions KeyExchangeServer() and KeyExchangeClient().
• 14 shows schematic flow of the function setPrimes().
• 15 shows the schematic flow of the function setE() 3400.
• 16 shows the schematic flow of the findD() function.
• 17 shows the schematic sequence of a secure transmission of quantum-based random numbers between a first processor 10-1 of the computer, in particular in the form of a proposed integrated circuit 2, a server 3600 and a first processor 10-1 of the computer, in particular in the form of another proposed integrated circuit 2, a client 3610.
• 18 shows schematically the proposed method 3700 for generating a quantum random number.
• 19 shows another exemplary proposal for a one-piece, monolithic integrated circuit 2.
• 20 shows a device similar to the device of the 8th and 9 .
• 21 shows an example of a time-to-pseudorandom number converter 404.3.
• 22 shows a diagram that represents the detection of the pulses (2201, 2202, 2203, 2204) on the voltage signal 405 of the entropy source 401.
• 23 shows an exemplary voltage converter 91 for supplying the entropy source 411 with a sufficient operating voltage of the supply voltage line V _ENT of the entropy source 411 relative to the reference potential line GND at the reference potential.

Description of the characters

The figures show, by way of example and in simplified form, essential parts of the proposed devices and methods. For purposes of illustration, specific examples constructed in accordance with the teachings of this disclosure will now be described with reference to the accompanying drawings in which:

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

In this example, the data processing device is a computer in the form of a monolithic, micro-integrated circuit 2, for example the microcontroller, for controlling a controlled system 26.

The following description first describes the configuration of an exemplary microcontroller as an example of a monolithic microintegrated circuit 2 with a proposed quantum random number generator 28 and the exemplary contents of its various memories as it would be used after manufacture.

The computer in the form of the monolithic, micro-integrated circuit 2, for example the microcontroller, is connected to a controlled system 26 via a connection 3. The controlled system can be, for example, a backup tape drive. In a backup tape drive, it is important that the integrity of the backed up data is maintained. It is therefore important that the integrity of the data and programs used by the computer in the form of the monolithic, micro-integrated circuit 2, for example the microcontroller, is maintained.

Figure 1

The computer in the form of the monolithic, micro-integrated circuit 2, for example the microcontroller, comprises in the example of the 1 for example, the monolithic integrated circuit 2 of an exemplary microcontroller, which comprises, for example, a control device 4, a non-volatile memory 6 and a random access memory 8, hereinafter also referred to as RAM (Random Access Memory). The non-volatile memory 6 can comprise any suitable type, e.g. a flash memory and other types. In this example, it is a read-only memory, e.g. an EEPROM. The microcontroller here is only an exemplary embodiment of a one-piece and monolithic integrated circuit 2 with a monolithic integrated quantum random number generator 28. Other microelectronic integrated circuits 2 are expressly included in the technical teaching of the document presented here. When this document refers to an "integrated circuit 2 of a microcontroller" or an "integrated circuit 2 of the microcontroller", the technically knowledgeable person automatically reads other microelectronic integrated circuits and devices here. These microelectronic integrated circuits and devices, within the meaning of the document presented here, expressly also include MEMS (micro-electro-mechanical system), MOEMS (also: MOMS) (micro-optical-electro-mechanical system), optical MEMS, optical microsystems, BioMEMS (stands for the application of MEMS to e.g. cell biology or its neighbouring areas), micromachines, MEFS (micro-electro-fluidic systems), NEMS (nano-electro-mechanical system), pMEMS (piezo-electric micro-electro-mechanical resonators), RF-MEMS (radio-frequency MEMS).

The document presented here therefore sees the term "microcontroller" used here only as an example. The person skilled in the art immediately reads the use of a quantum random number generator 28 with a time-to-pseudo-random number converter 404.3, as proposed here, in a monolithic co-integration with conventional micro-integrated circuits when reference is made to "integrated circuit 2 of the microcontroller", and expressly does not limit the technical teaching of this document to the co-integration of the proposed quantum random number generator 28 with a microcontroller.

• - Mikrokontroller, Mikroprozessoren, Speicher, DRAMs, SRAMs, RAMs, flüchtige Speicher, OTP-Speicher, EEPROMs, Flash-Speicher, MRAMs, FRAM" Bus-Transceiver, Sensor-Auswerteschaltkreise, Motortreiber-Schaltkreise, Steuerschaltkreise für eine automobile Steuerschaltungen, Grafik-Controller, Kommunikationsschaltkreise, Auswerteschaltkreise für einen biometrischen Sensoren, Auswerteschaltkreise für Eingabegeräte, Steuerschaltungen, Chip-Karten-Schaltkreise, Schaltkreise für Mobiltelefone oder eines Smart-Phones, Schaltkreise für Server. Schaltkreise für PCs, Schaltkreise für Laptops, Schaltkreise für Zugangs- und/oder Zugriffskontrollsysteme, Schaltkreise für die kodierte Aufzeichnung von Betriebsparametern, Schaltkreise elektronischer Sicherungen, Funksystemschaltkreise, Kommunikationsschaltkreise, Schaltkreise von Verschlüsselungs- und/oder Entschlüsselungssystemen, Schaltkreise für Individualisierungs- und Identifikationszwecke und/oder Identifikationssysteme und/oder Identifikationssysteme, Schaltkreise von Spielvorrichtungen, Schalkreise von Simulationssysteme, Schaltkreise von Rechnersystemen, Schaltkreise von Rausch und/oder Signalquellen, Schaltkreise von Modulationssystemen und/oder -vorrichtungen, Schaltkreise mit einer Vorrichtung zur Erzeugung und/oder Nutzung von Spreizkodes. Diese vorstehende Liste ist sicherlich unvollständig.

Such other conventional integrated circuits 2 may include, for example:

• - Microcontrollers, microprocessors, memories, DRAMs, SRAMs, RAMs, volatile memories, OTP memories, EEPROMs, flash memories, MRAMs, FRAM" bus transceivers, sensor evaluation circuits, motor driver circuits, control circuits for automotive control circuits, graphics controllers, communication circuits, evaluation circuits for biometric sensors, evaluation circuits for input devices, control circuits, chip card circuits, circuits for mobile phones or smart phones, circuits for servers, circuits for PCs, circuits for laptops, circuits for access and/or access control systems, circuits for coded recording of operating parameters, electronic security circuits, radio system circuits, communication circuits, encryption and/or decryption system circuits, individualisation and identification circuits and/or identification systems, gaming device circuits, simulation system circuits, computer system circuits, noise and/or signal source circuits, modulation system and/or device circuits, circuits with a device for generating and/or using spreading codes. The above list is certainly not exhaustive.

The random access memory 8 may be any suitable memory, such as an SRAM, but in this case it is a DRAM. The non-volatile memory 6 and the random access memory 8 are located in the example of 1 outside the control device 4. A further non-volatile memory 30 can optionally be provided within the micro-integrated circuit outside the control device 4 and connected to it via an internal interface 301.

The micro-integrated circuit 2 with the exemplary control device 4 is preferably a monolithic integrated circuit, which comprises, for example, the following: one or more processors 10-1, 10-2; a tightly coupled memory 14, which can be, for example, an SRAM; a non-volatile boot ROM 16, which contains a preferably non-changeable code; a hashing engine 18, for example, present; one or more one-time programmable memories (OTP) 20 and 22; a JTAG test interface 12; an interface 32; internal interfaces 63, 81 and 301, which are coupled to the memories 6, 8 and 30; a quantum random number generator 28, which the document presented here also refers to as QRNG (English abbreviation for Quantum Random Number Generator); and hardwired test disabling circuitry 24. OTP memories 20 and 22 may be separate memories or portions of memory within example integrated circuit 2. In this example, they are portions of a single memory. Test disabling circuitry 24 is preferably located between test port 12, which in this example is a JTAG port, and processor(s) 10. Preferably, disabling circuitry 24 is responsive to data in OTP memory portion 22. Optional hashing engine 18 uses data (one or more keys) in OTP memory portion 20. OTP memory portion 20 preferably stores critical security parameters (CSPs) including a secret key and at least one public key. Additional keys may be stored in OTP memory portion 20. In one embodiment of the proposal of this example application of a quantum random number generator 28, the secret key is preferably unique for each instance of the exemplary microintegrated circuit 2 proposed here.

The processor(s) 10 preferably executes instructions only from the tightly coupled memory 14 and from the DRAM 8 in the example presented here of the 1 The boundary of the controller 4 is a cryptographic virtual boundary and the data and program execution within this boundary are considered secure in this first proposal for the application of a proposed quantum random number generator 28, as explained below. The EEPROM 6 and the DRAM 8 (and the memory 30, if present) are outside the cryptographic boundary and without security measures the contents of these memories would not be secure in the sense of the document presented here. The interfaces 12, 63, 301, 32 and 81 are located at the physical and cryptographic boundary of the control device 4 within the micro-integrated circuit 2. The document presented here thus discloses a micro-integrated circuit 2 having internal interfaces 63, 301, 32 and 81 at a cryptographic boundary between a control device 4 and other parts (8, 30, 6) of the integrated microelectronic circuit 2 that are classified as non-secure or less secure. The essential purpose of these internal interfaces 63, 301, 32 and 81 is thus the secure shielding of an internal control device 4 within the micro-integrated microelectronic circuit 2.

The contents of the DRAM 8 and the EEPROM 6 are preferably cryptographically protected by authentication codes. In this example, the authentication codes used in the DRAM 8 are preferably of a different type than the authentication codes used in the EEPROM 6. In this example, the contents of the EEPROM 6 are protected against undetected malicious modification at least by the use of digital signatures. The format of the data in the EEPROM 6 is also preferably different from that in the DRAM 8.

For example, the EEPROM 6 preferably stores the firmware arranged in one or more data sets 61, each with a digital signature 62. The digital signatures used in this example of the proposal use public and private keys. Therefore, the details The digital signatures are not described further, since they are known to the person skilled in the art. When a processor (10-1, 10-2) reads a data set from the EEPROM 6, the processor 10 checks its digital signature. If the digital signature is valid, the data set is processed by the processor(s) 10 using computer-implemented methods of the firmware. The processor(s) 10 therefore preferably only executes validly signed firmware. For signing, the processors 10 preferably use keys and authentication codes that depend on quantum random numbers 418 of one or more quantum random number generators 28.

As in 1 , in one example, the boot ROM 16 contains code that the processor 10 uses to read a loader program S2 from the EEPROM 6 to read further records from the EEPROM 6. Logic in the processor 10 loads a program counter (not shown) in the processor 10 with the starting address 15 of the boot ROM 16. The processor 10 then executes the code in the boot ROM 15. This boot ROM 15 code can read a computer-implemented loader program from the EEPROM 6. The boot code in the boot ROM 15 is considered secure because it is within the cryptographic boundary 4. The loader program is protected by a digital signature that the processor 10 verifies when executing the boot ROM code S4 in the boot ROM 15 against the public key stored in the first OTP memory 20. Subsequent records are read using the loader program S6. The loading program in the EEPROM 6 and the subsequent data records are each provided with a digital signature and have one or more public keys embedded. When executing the loading code of the loading program in the EEPROM 6 in step S8, the processor 10 checks the signature of the data record newly read from the EEPROM 6 using a public key that is embedded in a data record that was previously loaded or stored in the OTP memory 20.

A record read from the EEPROM 6 may contain too much firmware code/data for the small, tightly coupled memory TCM 14 of the controller 4 within the microelectronic circuit 2 to store. The TCM 14 preferably stores firmware code/data that is immediately required by the processor(s) 10. The remainder of the firmware record is transferred to the DRAM 8. Since the DRAM 8 lies outside the cryptographic boundary 4, the codes/data stored there are cryptographically protected by authentication codes that the processor 10 has preferably generated using quantum random numbers from the quantum random number generator 28.

Figure 3

As in 3 As shown, the processor 10 reads the data as a data record from the EEPROM 6 and writes it as words into the DRAM 8 or reads these words again from this DRAM 8. In this example, when the processor 10 reads a data record from the EEPROM in step S20, the processor 10 validates it as in 4 and the associated description. At least a portion of the data of the set is stored by the processor 10 in the TCM 14 in step S21. The remaining data of the set is processed by the processor 10, for example as follows, and stored in the DRAM 8. The processor(s) 10 cooperates with the optional hash engine 18 to calculate a hash value for each word of the remaining data, for example in step S22, and to store the hash value in the DRAM 8 at a location associated with the stored word in step S24. The word size is chosen according to system constraints. It may be as small as one byte. In practice, it may be 32 bits. When the processor 10 reads a word from the DRAM 8 in step S26, the processor 10 and the hash engine 18 preferably recalculate the hash value and compare the recalculated hash value with the corresponding hash value stored in the DRAM 8 in step S30.

If the hash values have a predetermined relationship, which is checked in step S34, e.g. are equal, the processor 10 processes the read data in a step S38. If the hash values do not have the predetermined relationship, the processor 10 interrupts the processing in step S36 and/or the processor 10 generates an error message and/or the processor 10 ignores the data/code.

Storing words in the DRAM 8 with corresponding authentication codes, which are preferably based on quantum random numbers from the quantum random number generator 28, facilitates random access to the words by the processor(s) 10.

The hash function can be any suitable hash function. An example is the well-known HMAC function. In this example, the HASH function uses the secret key stored in the OTP memory 20. It could also use another key stored in the OTP memory. Preferably, the secret key is based on a quantum random number of the quantum random number generator 28. An example of the hash value is HMAC (address | | data | | secret key), where the character string “| |” here stands for the concatenation. Taking into account the number of bytes that the DRAM 8 can store, the HASH value preferably comprises at least enough bits to avoid or at least reduce duplication of HASH values in the DRAM 8. The number of bits of the HASH value is preferably at least 96 bits and can also be significantly larger. The industry standard is 160 bits, which reduces the probability of duplication of HASH values to a sufficiently low level.

By providing the cryptographic boundary 4 and protecting the data stored in the DRAM 8 and EEPROM 6, the integrated circuit 2, in particular that of the microcontroller, is protected against unauthorized access to the programs and data used by the processor(s) 10 of the computer in normal operation. This is of particular importance in the automotive field to prevent plagiarism and unauthorized spare parts, which usually require knowledge of the firmware of the illegally copied spare parts. The JTAG test interface 12 could, however, allow access to the processor(s) 10 in a test mode with known EMULATE and TRACE routines and still allow illegal program modifications. The JTAG test port 12 is required for testing at least during the manufacturing process of the integrated circuit 2, for example that of a microcontroller, and can be used for fault diagnosis after manufacturing. Such an analysis capability of an automotive integrated circuit 2, for example an automotive microcontroller, is an indispensable prerequisite for meeting the quality requirements of T16491.

In order to prevent unauthorized and in particular illegal use of the JTAG interface 12, the OTP memory 22 can, for example, comprise at least one security bit which, together with the blocking circuit 24, blocks the JTAG interface 12.

In an example, the OTP memory 22 contains only one bit. The OTP memory 22 allows a bit to be changed from one state, e.g. "0", to the opposite state "1" only once. For example, during manufacture of the integrated circuit 2, e.g. the microcontroller, the bit is "0", which enables testing. In a final testing step, the manufacturer of the exemplary integrated circuit 2, e.g. the microcontroller, sets the bit to "1" before releasing the integrated circuit 2, e.g. the microcontroller, for delivery and use. The JTAG connector 12 typically has a serial input and a serial output (see 2 ). The deactivation circuit, which is part of the circuit of the control device 4 within the integrated circuit 2, for example the microcontroller, preferably comprises a gate 241, which is for example located between the serial output of the JTAG interface 10 and the processor(s) 10, and a gate 242, which is located between the serial input of the JTAG interface 10 and the processor(s) 10. The security bit "1" in the OTP memory 22 deactivates the gates 241 and 242. Since the security bit cannot be changed, the test port is then secured against use after the manufacture and delivery of the integrated circuit 2, for example the microcontroller.

In another example, the OTP memory 22 has a two-bit security code, which is initially "00". This allows a check during manufacture, after which the code is set to "01", i.e. one of the two bits is set to "1". This code "01" locks the gates 241 and 242. If an error occurs, the integrated circuit 2, for example of the microcontroller, is returned to its manufacturer, who sets the other bit to "1", resulting in the code "11", which allows a check via the terminal 12. Such a check is preferably destructive, since it does not allow a reset to the original value. Access to the OTP memory 22 to change the security code can be made by a suitable access code, preferably generated by means of a quantum random number generator 28, which is provided with a digital signature that can be verified by a quantum random number-based key stored in the OTP memory 20. The key may, for example, be the standard public key stored in the memory 20. This allows the security code to be changed to "11", which enables testing via the JTAG interface 12. The original integrated circuit 2, for example the microcontroller, is preferably retained by the manufacturer and preferably destroyed and the user receives a new integrated circuit 2, for example a microcontroller.

In another example, the security code may consist of three or more bits that change when the signed access code is used. When manufactured, the code is “000” and when released to a user, it is “001”. If an error occurs, the manufacturer changes the code to “011” to provide a testing. After testing, the code is changed to "111", thereby securing the JTAG interface 12 against use and allowing the integrated circuit 2, for example of the microcontroller, to be returned to the user. Only a signed access code provided with a digital signature verified by a key in the OTP memory 20 can be used to change the code stored in the OTP memory 22.

Security codes of two or more bits provide an audit trail for testing (or any unauthorized testing attempts) after manufacturing.

Additional interface and additional EEPROM

As in 1 As shown, the control device 4 of the integrated circuit 2, for example the microcontroller, can optionally have at least one further interface 32 in addition to the connections 3 and 12. This further interface 32 can be, for example, an Ethernet connection or a Fibre Channel connection or an automotive data bus connection for data buses such as CAN, LIN, DSI3 or PSI5. A Fibre Channel connection in the sense of the document presented here is a data connection that uses an optical fiber or another waveguide for electromagnetic radiation.

The integrated circuit 2, for example the microcontroller, can additionally have a further non-volatile memory 30 outside the control device 4 of the integrated circuit 2, for example a microcontroller, which stores data that is cryptographically protected by a security parameter stored in the OTP memory 20. The further non-volatile memory 30 is coupled to the control device 4 via the internal interface 301 of the integrated circuit 2, for example the microcontroller.

The further non-volatile memory 30 can be an EEPROM, for example. The further memory 30 can store further critical security parameters outside the control device 4. The further parameters are preferably encrypted and provided with digital signatures to make them secure. The further parameters are preferably encrypted with the secret key that is only valid for the control device 4 and is stored in the OTP memory 20. Preferably, the secret key is based on a quantum random number from a quantum random number generator 28. The digital signatures of the further parameters are created using the unique secret key stored in the OTP memory 20. This secret key is used to decrypt the further security parameters and to verify the digital signatures read from the further memory 30.

The additional non-volatile memory 30 may contain other encrypted and/or digitally signed data.

The additional security parameters outside the control device 4 of the integrated circuit 2, for example the microcontroller, can be used to secure the data and codes transmitted via the interface(s) 32.

Manufacturing of the integrated circuit 2, for example the microcontroller.

During manufacture of the integrated circuit 2, e.g. the microcontroller, the boot code is preferably hard-coded in the boot ROM 16; the loader and other codes/data are stored in the EEPROM 6 with digital signatures based on the public and private keys, preferably generated using quantum random numbers of a quantum random number generator 28; and preferably at least one public key is generated using a quantum random number of a quantum random number generator and stored in the OTP memory 20.

The secret key is preferably only stored in the OTP 20 when the security code, which is preferably based on a quantum random number of a quantum random number generator 28, is set in the OTP 22 and the test connection of the exemplary JTAG interface 12 has been blocked. The control device 4 of the integrated circuit 2, for example the microcontroller, contains the necessary quantum random number generator QRNG 28 in the example presented here. The firmware stored in the tightly coupled memory 14 or in the DRAM 8 reads one or more quantum random numbers of e.g. 256 bits from the quantum random number generator 28 and stores them in the OTP 20 as a secret key without this data leaving the control device 4, preferably within the integrated circuit 2, for example the microcontroller. This preferably only happens after the deactivation of the Test connection 12 to prevent access to the secret key even for persons who have access to the manufacturing process. Preferably, the logic gates of the integrated circuit 2, for example the microcontroller, or at least those of the control device 4 of the integrated circuit 2, for example the microcontroller, are designed in such a way that the current peaks that occur when logical states within the circuits of the logic gates change do not allow any conclusions to be drawn about the processes and/or the data and/or the quantum random numbers and/or the circuit states of the device. This avoids so-called side channels. For this purpose, the proposed device can comprise current sources, complementary switching, complementary dummy circuits, energy reserves (e.g. capacities), etc.

The hash function of the hashing engine 18 may be any suitable hash function and is not limited to the example of HMAC described above.

The on-chip quantum random number generator 28 QRNG could be omitted from the integrated circuit 2, for example the microcontroller, and instead an off-chip quantum random number generator QRNG could be used to generate the secret key during the manufacturing process. However, an on-chip quantum random number generator QRNG is significantly more secure.

The firmware stored in the EEPROM 6 is preferably cryptographically protected, in this example by digital signatures. During production, the firmware is first compiled. It is then digitally signed with a secret private key of a private-public key system. Preferably, the secret private key of the private-public key system is based on a quantum random number of a quantum random number generator 28. The public key is preferably stored in the OTP memory 20 so that the signature can be verified. The signed firmware is stored in the EEPROM 6. The digital signatures can be created by transmitting the compiled firmware to a secure signature generator during the production process. The secure signature generator can be the integrated circuit 2, for example of the microcontroller, namely the control device 4 in cooperation with the quantum random number generator 28 itself. The signed firmware can be downloaded into the EEPROM 6 via a communication connection, e.g. the Internet, if the signing is done externally. However, the processor 10 can remove the signature of the firmware before storing it in the EEPROM 6 and replace it with its own quantum random number-based signature based on a quantum random number from its quantum random number generator 28, which then makes it impossible for anyone to read the firmware without exception.

Instead of an EEPROM, the non-volatile memory 6 can be any other suitable memory, for example a FLASH memory.

The additional non-volatile memory 30 may, for example, be a serial EEPROM memory.

The one-time programmable memory OTP 22, which contains the security code, can be replaced with another re-programmable, non-volatile memory and the security code can be changed using signed firmware. However, a memory 22 that can only be programmed once is more secure because its programming is irreversible.

The DRAM 8 can be further protected by making access to the DRAM 8 physically very difficult and detectable in the event of an attempt. For example, the connections between the DRAM 8 and the control device 4 can be buried in layers of the metallization stack of the integrated circuit 2, for example the microcontroller, or protected in another way against physical scanning (e.g. by e-beam). Preferably, the device parts of the control device 4 also comprise such scanning protection. In particular, it is advantageous if the quantum random number generator 28 has such scanning protection, for example in the form of a metal layer 53, 142 lying at a predefined potential.

The entire integrated circuit 2, for example of the microcontroller, can be provided with such scanning protection, for example in the form of a metal layer 53, 142 lying at a predefined potential. The entire integrated circuit 2, for example of the microcontroller, can also be housed in a tamper-proof housing with tamper-proof seals.

The secure integrated circuit 2, for example of the microcontroller, preferably has at least one photon source 54 or a silicon LED 54 or a first SPAD diode 54 as a photon source for photons of the quantum random number generator 28. The secure integrated circuit 2, for example of the microcontroller, preferably has at least one photon detector 55 or a second SPAD diode 55. An optical system preferably optically couples the at least one photon source 54 or the silicon LED 54 or the first SPAD diode 54 to the photon detector 55 or the second SPAD diode 55 by means of these photons. The optical system can comprise an optical waveguide 44. The quantum random number generator 28 is preferably a quantum process-based generator for true random numbers (QRNG) 28. The quantum process-based generator for true random numbers (QRNG) 28 preferably comprises a photon source 54 or a silicon LED 54 or a first SPAD diode 54 as a light source for an optical quantum signal and a photon detector 55 or a second SPAD diode 55 as a photodetector for this optical quantum signal. Furthermore, the quantum process-based generator for true random numbers (QRNG) 28 preferably comprises at least the processing circuit and optionally the optical fiber 44. The optical fiber 44, which may be present, preferably optically couples the photon source 54 or the silicon LED 54 or the first SPAD diode 54 to the photon detector 55 or a second SPAD diode 55. An operating circuit supplies the photon source 54 or the silicon LED 54 or the first SPAD diode 54 with electrical energy in such a way that the photon source 54 or the silicon LED 54 or the first SPAD diode 54 emit light. The emission of light requires that the operating voltage provides a sufficient electrical bias voltage for the photon source 54 or the silicon LED 54 or the first SPAD diode 54. A processing circuit (402, 403, 404) detects the signal from the photon detector 55 or the second SPAD diode 55 and forms the quantum random number 418 from it. The processing circuit then preferably makes the quantum random number 418 thus formed available to one or more of the one or more processors 10 via a data bus 419.

The semiconductor crystal of the integrated circuit 2, for example of the microcontroller, preferably has a surface 56. The semiconductor crystal typically has a semiconducting material below its surface 56. In particular when using conventional semiconductor circuit manufacturing processes, such as CMOS processes, bipolar processes, BiCMOS processes and BCD processes, the surface 56 of the semiconductor crystal typically has a metallization stack as structured metal layers and electrical insulation layers. The structured metal layers typically form the electrically conductive conductor tracks, which are electrically separated from one another by the insulation layers. The metallization stack thus has a typically structured and optically transparent and electrically insulating layer 44. At least part of this typically structured, transparent and electrically insulating layer 44 of the surface 56 preferably forms the optical waveguide 44.

The examples presented here of 6 and 7 use a first SPAD diode 54 as a photon source 54. The first SPAD diode 54 radiates in the examples of 6 and 7 for example, from the semiconducting material of the semiconductor substrate 49 into this optical waveguide 44. This means that the first SPAD diode 54 generally radiates perpendicular to the surface 56 essentially upwards and not sideways into the semiconductor substrate 49 of the semiconductor crystal 49. The material of the semiconductor crystal 49 has a high attenuation for this light. Nevertheless, the emission of the photons 57 of the first SPAD diode 54 in the optical waveguide 44 is not directed. In particular, the emission via the substrate 48, 49 is very attenuated, since visible light has a very high absorption. This arrangement enables the device to couple more photons of the first SPAD diode 54 directly to the second SPAD diode 55, which is shown here in the examples of the 6 and 7 serves as a photon detector 54. The optical waveguide 44 transports in the examples of 6 and 7 these photons 57, 58, 59 of the first SPAD diode 54 in the optical waveguide 44 are transmitted to the second SPAD diode 55 with practically no loss compared to other prior art solutions. The optical waveguide 44 irradiates in the examples of 6 and 7 with these photons 57, 58, 59 of the first SPAD diode 54, the second SPAD diode 55 in such a way that the light 59 penetrates from within the optical waveguide 44 back into the semiconducting material of the semiconductor substrate 49 from the surface 56 and there strikes device parts of the second SPAD diode 55. The second SPAD diode 55 then generates a reception signal depending on the irradiation with these photons 59.

Typically, at least one operating circuit in the examples of 6 and 7 the at least one first SPAD diode 54 at least temporarily with electrical energy. The at least one first SPAD diode 54 then feeds photons 57 into the 6 and 7 The optical waveguide 44 then transports these photons 57, 58, 59 further. The photons 57, 58, 59 shown in the examples of 6 and 7 The optical waveguide 44 provided then radiates the transported photons 58 as essentially vertically moving photons 59 into the second SPAD diode 55. Since this transport of the photons from the first SPAD diode 54 to the second SPAD Diode 55 loses significantly fewer photons than in other prior art designs that use the highly absorbent semiconductor substrate 49, 49 due to the low attenuation in the optical waveguide 44, the quantum efficiency is massively higher. This increases the bit rate of the quantum random bits 411 with which the device can generate quantum random numbers 418. Therefore, in the design presented here, a pair of a single first SPAD diode 54 and a single second SPAD diode 55 is sufficient. Other prior art devices typically use multiple SPAD diodes.

In a further development of the proposed secure integrated circuit 2, for example of the microcontroller, at least one data interface of the one or more data interfaces 64 is a wired automotive data bus interface 64. In this case, the wired automotive data bus interface 64 can be, for example, a CAN data bus interface or a CAN-FD data bus interface or a Flexray data bus interface or a PSI5 data bus interface or a DSI3 data bus interface or a LIN data bus interface or an Ethernet data bus interface or an SPI data bus interface or a MELIBUS data bus interface.

In a further development of the proposed secure integrated circuit 2, for example the microcontroller, at least one data interface 64 of the one or more data interfaces 64 is a wireless data bus interface. The wireless data bus interface 64 can be, for example, a WLAN interface or a Bluetooth interface.

In a further development of the proposed secure integrated circuit 2, for example the microcontroller, at least one data interface 64 of the one or more data interfaces 64 is a wired data bus interface 64. The wireless data bus interface 64 can be, for example, a KNX data bus interface or an EIB data bus interface or a DALI data bus interface or a PROFIBUS data bus interface.

Although the proposed device has been described by way of example with reference to a control device 4 and the integrated circuit 2, for example of the microcontroller, it is not limited to a control device 4 or the integrated circuit 2, for example of the microcontroller. The proposed device can also be applied to other types of integrated circuit processors and other integrated circuits. A microprocessor is only a particularly favorable, because complex, example of a proposed exemplary integrated circuit 2.

The embodiments of the proposed device store data inside and possibly also outside the integrated circuit 2, for example the microcontroller. The embodiments of the proposal ensure that the data to be processed, including the executable code, cannot be changed by unauthorized persons who access the data stored outside the integrated circuit 2, for example the microcontroller, or, if such access occurs, ensure that this access and/or such an attempted access does not go unnoticed and that the data and/or program codes and/or keys and/or authentication data etc. cannot be changed unnoticed. Security is ensured by security data, and the security data itself is secure because it is stored within the integrated circuit 2, for example the microcontroller, in a protected area 4 and protected from unauthorized access.

The description presented herein is not intended to be exhaustive and does not limit this disclosure to the examples shown. Other variations to the disclosed examples can be understood and practiced by those of ordinary skill in the art from the drawings, the disclosure and the claims. The indefinite articles "a" or "an" and their inflections do not exclude a plurality, while the mention of a certain number of elements does not exclude the possibility of more or fewer elements being present. A single unit may perform the functions of several elements mentioned in the disclosure, and conversely, several elements may perform the function of a unit. Numerous alternatives, equivalents, variations and combinations are possible without departing from the scope of the present disclosure.

Unless otherwise stated, all features of the present invention can be freely combined with one another. This applies to the entire document presented here. The features described in the description of the figures can also be freely combined with the other features as features of the invention, unless otherwise stated. A restriction of individual features of the It is expressly not intended to limit the combination of embodiments with other features of the embodiments. In addition, physical features of the device can be reformulated and used as process features, and process features can be reformulated as physical features of the device. Such a reformulation is therefore automatically disclosed.

In the foregoing detailed description, reference is made to the accompanying drawings. The examples in the description and drawings should be considered as illustrative and are not to be considered as limiting the specific example or element described. Multiple examples may be derived from the foregoing description and/or drawings and/or the claims by modifying, combining or varying certain elements. In addition, examples or elements not described verbatim may be derived from the description and/or drawings by a person skilled in the art.

Figure 6

The secure integrated circuit 2, for example the microcontroller, has in the example of 6 for example, at least one first SPAD diode 54 and at least one second SPAD diode 55 and at least one optical waveguide 44. The quantum random number generator 28 is preferably a quantum process-based generator for true random numbers (QRNG) 28. The quantum process-based generator for true random numbers (QRNG) 28 comprises in the example of 6 a first SPAD diode 54 as a light source for an optical quantum signal and a second SPAD diode 55 as a photodetector for the optical quantum signal. Furthermore, the quantum process-based true random number generator (QRNG) 28 in the example of 6 at least the processing circuit and the optical waveguide 44. Preferably, the optical waveguide 44 in the example of 6 the at least one first SPAD diode 54 with the at least one second SPAD diode 55 optically. An operating circuit supplies in the example of the 6 the first SPAD diode 54 with electrical energy in such a way that the first SPAD diode 54 emits light 57. The emission of light 57 requires in the example of the 6 that the operating voltage provides a sufficient electrical bias voltage of the first SPAD diode 54 (404.1). A processing circuit (402, 403, 404) detects in the example of the 6 the signal of the second SPAD diode 55 (404.3) and forms the quantum random number 418 therefrom. The processing circuit then preferably makes the quantum random number 418 thus formed available to one or more of the one or more processors 10 via a data bus 419.

Preferably, the semiconductor crystal 49 of the control device 4 of the integrated circuit 2, for example of the microcontroller, has a surface 56. Typically, the semiconductor crystal 49 has a semiconducting material below its surface 56. In particular when using conventional semiconductor circuit manufacturing processes, such as CMOS processes, bipolar processes, BiCMOS processes and BCD processes, the surface 56 of the semiconductor crystal 49 typically has a metallization stack as structured metal layers and electrical insulation layers. The structured metal layers typically form the electrically conductive conductor tracks, which are electrically separated from one another by the insulation layers. The metallization stack thus has a typically structured and optically transparent and electrically insulating layer 44. At least part of this typically structured, transparent and electrically insulating layer 44 of the surface 56 preferably forms the optical waveguide 44.

In the example of 6 the first SPAD diode 54 radiates light 57 from the semiconducting material of the semiconductor substrate 49 into this optical waveguide 44. That is, in the example of the 6 In contrast to other devices from the prior art, the first SPAD diode 54 radiates perpendicular to the surface 56 essentially upwards and not sideways into the semiconductor substrate 49 of the semiconductor crystal, which has a high attenuation. Nevertheless, the radiation of the photons 57 of the first SPAD diode 54 is not directed in the optical waveguide 44. In particular, the radiation via the substrate 48, 49 is very attenuated, since visible light has a very high absorption. This enables the device of the 6 compared to prior art devices, more photons of the first SPAD diode 54 are coupled directly to the second SPAD diode 55. The optical waveguide 44 transports these photons 57, 58, 59 of the first SPAD diode 54 in the example of 6 in the optical waveguide 44 compared to other devices from the prior art practically loss-free to the second SPAD diode 55. The optical waveguide 44 irradiates with these photons 57, 58, 59 of the first SPAD diode 54 in the example of 6 the second SPAD diode 55 in such a way that the light 59 from within the optical waveguide 44 is again reflected into the semiconducting material of the semiconductor substrate 49 from the surface 56. and hits parts of the second SPAD diode 55. The second SPAD diode 55 then generates in the example of the 6 depending on the irradiation with these photons 59 a received signal.

Typically, at least one operating circuit in the example of 6 the at least one first SPAD diode 54 at least temporarily with electrical energy. The at least one first SPAD diode 54 then feeds in the example of the 6 When supplied with sufficient electrical energy, photons 57 enter the at least one optical waveguide 44. The optical waveguide 44 transports in the example of the 6 these photons 57, 58, 59 then further. The at least one optical waveguide 44 then radiates in the example of 6 the transported photons 58 enter the second SPAD diode 55 as essentially vertically moving photons 59. Since this transport of photons from the first SPAD diode 54 to the second SPAD diode 55 in the example of 6 Because the optical waveguide 44 loses significantly fewer photons than in other prior art designs that use the highly absorbing semiconductor substrate 48, 49, the quantum efficiency is massively higher. This increases the efficiency of a device according to the example of the 6 the quantum random bit rate with which the device can generate quantum random numbers. Therefore, in the construction presented here, the 6 typically already a pair of a single first SPAD diode 54 and a single second SPAD diode 55. Prior art devices typically use multiple SPAD diodes.

Figure 7

7 essentially corresponds to the 6 . In contrast to 6 the semiconductor crystal 48 and the epitaxial layer 49 are now covered with a first optically transparent insulating layer, for example an oxide layer 143. The vias 140 are in the example of the 7 filled with electrically conductive metal. The metallization level 1 with the electrical lines of the first wiring level 141 contact in the example of 7 these vias 140. On this first insulation layer 142 and the first metallization layer with the first wiring level 141, in the example of the 7 a second optically transparent insulation layer 144, preferably also in the form of an oxide layer, is applied. This can also be achieved by vias which are in the 7 are not shown, so that lines of the first metallization level are connected to lines of the second metallization level in the example of 7 The dashed boundary surface 145 between the first optically transparent insulation layer 143 and the second optically transparent insulation layer 144 is in the example of the 7 is also substantially optically transparent and preferably does not reflect and/or absorb the light of the first SPAD diode 55. The first optically transparent insulation layer 143 and the second optically transparent insulation layer 144 form in the example of the 7 essentially the optical waveguide in the area of the first SPAD diode 54 and the second SPAD diode 55. In the optical path between the first SPAD diode 54 and the second SPAD diode 55 are in the example of the 7 preferably no vias 140 and no metal lines 141, so that the light of the first SPAD diode 54 in the example of 7 can reach the second SPAD diode 55 without hindrance. A metal cover 142 prevents in the example of the 7 the exit of photons upwards and preferably reflects them back into the optical waveguide 44 in the example of 7 The vias 140 and the metal lines of the first metallization level 141 prevent in a similar way in the example of the 7 that light from the optical waveguide 44 is lost horizontally in the metallization stack.

Figure 8

8th shows schematically the simplified block diagram of a quantum-based random number generator (quantum random number generator 28) as proposed in this document.

A preferred common system clock 2106 preferably clocks the digital circuits of the exemplary in the 8th The quantum random number generator 28 of the 8th is preferably part of the control device 4 and thus of the integrated circuit 2, for example the microcontroller. The structure of the quantum random number generator 28 includes an entropy source 401, in the example of the 8th a broadband 40 dB high frequency amplifier 402 or the like and an analog-digital converter 403, which may also be just an inverter or the like. In experiments, an analog-to-digital converter 403 with a resolution of 14 bits and a sampling rate of 125 MS/s and with an evaluation device 404 was successfully used.

The entropy source 401 of the quantum random number generator 28 comprises in the example the 8th an array 54 of single photon avalanche diodes (SPAD) 54 as photon sources 54 and an array 55 of single photon avalanche diodes (SPAD) 55 as photon detectors 55. It can also be a single common array. The voltage converters 91 of the integrated circuit 2, for example of the microcontroller, supply the first SPADs 54 of the array 54 of single photon avalanche diodes (SPAD) 54 of the quantum random number generator 28, which serve as photon sources 54, and the second SPADs 55 of the array 55 of single photon avalanche diodes (SPAD) 55 of the quantum random number generator 28, which serve as photon detectors 55, preferably with such an operating voltage that they are preferably in the so-called Geiger mode. The operating voltage of these SPAD diodes 54, 55 is then above the breakdown voltage. The SPAD diodes 54, 55 are then preferably connected in reverse direction. In addition, a quenching resistor 401.4 is preferably connected in series for each SPAD diode 54, 55. The quenching resistor 401.4 prevents thermal destruction of the respective SPAD diode 54, 55 in the event of a charge carrier avalanche. The respective quenching resistor 401.4 of the 8th serves here at the same time as a shunt resistor for the detection of the electrical diode current through the SPAD diodes 54, 55. The current signal of the second single photon avalanche diodes 55 of the array 55 of single photon avalanche diodes (SPAD) is measured via a shunt resistor 401.4 for these second SPAD diodes 55. A shunt resistor 401.4 corresponding to the example of the 8th The series resistor for limiting the current through the respective SPAD diodes forms the shunt resistor 401.4. The shunt resistor 401.4 can, however, be inserted into the supply line of the respective SPAD diode 54, 55 independently of the quenching resistor 401.4. An exemplary common array of SPAD diodes includes in the example of the 8th for example, four active first SPAD diodes 54 and twelve passive second SPAD diodes 55. The example four active first SPAD diodes 54 and twelve passive second SPAD diodes 55 are preferably coupled via an optical waveguide (optical waveguide 44). The active first SPAD diodes 54 emit spontaneously and randomly individual light pulses 57. They correspond to the first SPAD diode 54 of the 6 and 7 . The active first SPAD diodes 54 are preferably located inside the array of first and second SPAD diodes 54 and 55. The proposed device supplies the active first SPAD diodes 54 with an increased supply voltage by means of its voltage converters. For this purpose, the proposed device preferably uses particularly voltage-resistant DMOS transistors in these voltage converters. It is therefore particularly advantageous if the one-piece, micro-integrated quantum random number generator 28 is manufactured using a BCD semiconductor technology, which typically allows the manufacture of CMOS circuits, SPADs and DMOS transistors at the same time in a cost-effective and chip-area-effective manner. The proposed device therefore operates the active, first SPAD diodes 54 in the example of the 8th preferably well above the breakdown voltage of the first SPAD diodes 54. This operation at an increased supply voltage of the first SPAD diodes 54 increases the dark count rate of these first SPAD diodes 54, which leads to a higher number of spontaneously emitted photons 57. The optical waveguide 44 directs some photons 58 of the emitted photons 57 to the passive, second SPAD diodes 55 in the example of the 8th The optical waveguide 44 corresponds to the optical waveguide 44 of the 6 and 7 . The passive, second SPAD diodes 55 correspond to the second SPAD diode 55 of the 6 and 7 . One or more voltage converters of the proposed device supply the passive, second SPAD diodes 55 in the example of 8th with an increased supply voltage. For this purpose, the proposed device preferably uses particularly voltage-resistant DMOS transistors in these voltage converters. It is therefore particularly advantageous if the one-piece, micro-integrated quantum random number generator 28 is manufactured using a BCD semiconductor technology, which typically allows the manufacture of CMOS circuits, SPADs and DMOS transistors at the same time in a cost-effective and chip-area-effective manner. The proposed device operates the passive, second SPAD diodes 55 just above the breakdown voltage. The passive, second SPAD diodes 55 are preferably arranged as a ring around the active, first SPAD diodes 54 in the example of the 8th Other arrangements are conceivable. In particular, it is conceivable to replace the first SPAD diodes 54 with other silicon LEDs and to use an arrangement of such other silicon LEDs and second SPAD diodes 55 close to each other <<<<<, whereby the light transmission then takes place directly through the semiconductor substrate 49 as an optical waveguide 44 with an extremely short light transmission path of only a few µm. The passive, second SPAD diodes 55 detect in the example of the 8th at least a portion of the photons 59 arriving via the optical waveguide 44. The passive, second SPAD diodes 55 generate a current flow via a shunt resistor associated with the second SPAD diodes 55 depending on the incoming photons 59. The entropy source 401 comprises in the example of the 8th preferably the shunt resistors, the operating device of the SPAD diodes, the SPAD diodes 54 and 55 and the optical waveguide 44. A voltage signal 405 of the entropy source 401 preferably connects the entropy source 401 to a preferred, exemplary, broadband 40 dB high frequency amplifier 402. In other embodiments of the proposal, this 40 dB high frequency amplifier 402 is not required. In this respect, the 40 dB high frequency amplifier 402 is optional. Preferably, the voltage signal corresponds to the voltage drop across the quenching Resistor 401.4, which in the example of the figure functions as a shunt resistor 401.4. It is conceivable to supply the first SPAD diodes 54 and the second SPAD diodes 55 via a common quenching resistor 401.4, which then also functions as a common shunt resistor. The proposed, exemplary high-frequency amplifier 402 preferably has, by way of example, a bandwidth of 30 to 4000 MHz and preferably a 1 dB compression point of 20 dBm. The voltage swing of the voltage signal 405 of the entropy source 401 was in the sub-millivolt range in tests in connection with the elaboration of the technical teaching of the document presented here. The exemplary proposed high-frequency amplifier 402, for example, amplifies the voltage swing of this voltage signal 405 of the entropy source 401 to, for example, 50 to 150 mV.

An amplifier output signal 406 of the high-frequency amplifier 402 connects, for example, the exemplary high-frequency amplifier 402 to an exemplary evaluation device 404, which essentially comprises sub-devices of the control device 4. The evaluation device 404 of the 8th is only one of many different implementation possibilities of the technical teaching presented in this document. The evaluation device 404 is preferably part of the integrated circuit 2, for example the microcontroller. Preferably, the integrated circuit 2, for example the microcontroller, comprises one or more processors 10-1, 10-2. The evaluation circuit 404 has in the examples of 8th and 9 via an exemplary 14-bit analog-to-digital converter (ADC) 403 with an exemplary sampling rate of 125 mega-samples/s and an exemplary bandwidth of 50 MHz. During development, it has been shown that smaller bit widths and lower sampling rates are possible. If necessary, analog preprocessing before digitization by the analog-to-digital converter 403 using pulse broadening circuits 2022 is expedient. The amplified voltage signal of the exemplary high-frequency amplifier 402 is the amplifier output signal 406 of the high-frequency amplifier 402. The analog-to-digital converter 403 samples the amplifier output signal 406 of the high-frequency amplifier 402 at a sampling rate of the analog-to-digital converter 403. The sampling rate preferably depends on the system clock 2106. As a rule, the sampling rate of the analog-to-digital converter 403 is equal to the frequency of the system clock 2106. The analog-to-digital converter 403 digitally transmits the determined sampling values of the amplifier output signal 406 of the high-frequency amplifier 402 with a bus width of, for example, 14 bits to the evaluation device 404. A proposal is also described below which works without a high-frequency amplifier 402 and which provides an analog-to-digital converter 403 with a bit width of 1.

The simplified block diagram of the 8th The device shown includes, by way of example, a comparator 404.2, a time-to-pseudo-random number converter (TPRC) 404.3, an entropy extraction device 404.4 and a finite state machine 404.8.

The comparator 404.2 compares in the example of 8th the exemplary digital 14-bit value 407 of the analog-to-digital converter 403 with a constant 404.1, which represents a threshold value, and generates a two-cycle 1-bit output pulse on its output signal 409 of the comparator 404.2 if the output value of the analog-to-digital converter 403 is greater than the constant 404.1. In the case of a device without a high-frequency amplifier 402 and with an analog-to-digital converter 403 with a bit width of 1, the comparator 404.2 and the constant 404.1 are omitted and the analog-to-digital converter 403 immediately generates the output signal 409 of the comparator, since the analog-to-digital converter 403 then also fulfills the function of the comparator 404.2. The disadvantages of such a design include its lower flexibility and the increased demands on design and production. The output signal 409 of the comparator 404.2 connects the comparator 404.2 to the time-to-pseudo-random number converter 404.3 (TPRC). The time-to-pseudo-random number converter 404.3 (TPRC) preferably comprises, for example, a linearly-coupled 32-bit shift register that counts up with the system clock 2106 of the integrated circuit 2, for example the microcontroller. The oscillator 30 and the clock system of the control device 4 typically provide this clock. The bit width of this linearly-coupled shift register can vary depending on the application. This bit width can preferably be set via a register of the control device 4 of the integrated circuit 2, for example the microcontroller. Preferably, the feedback polynomial of the linearly fed back shift register of the time-to-pseudo-random number converter 404.3 (TPRC) can be set via a register of the control device 4 of the integrated circuit 2, for example the microcontroller. The system clock 2106 can have a frequency of 125 MHz, for example. A pulse on the 1-bit output signal of the comparator 404.2 preferably causes the time-to-pseudo-random number converter 404.3 (TPRC) to output the current shift register value of the linearly fed back shift register of the time-to-pseudo-random number converter 404.3 (TPRC) as a pseudo-random number at the output 410 of the time-to-pseudo-random number converter 404.3 (TPRC). The pseudo-random number dorandom numbers typically change with the clock period of the system clock 2106, which results in a time resolution with regard to the pulses on the 1-bit output signal of the comparator 404.2. With an exemplary 125 MHz system clock 2106, this results in a time resolution of 1/(125 MHz)=8 ns. The output 410 of the time-to-pseudo-random number converter 404.3 (TPRC) passes the exemplary 32-bit shift register value, also called raw data, of the time-to-pseudo-random number converter 404.3 (TPRC) to the entropy extraction 404.4 downstream in the signal path. The entropy extraction 404.4 converts the random raw data RD of the time-to-pseudo-random number converter 404.3 (TPRC) on the signal of the output 410 of the time-to-pseudo-random number converter 404.3 (TPRC) into a 1-bit random number 411 RN. The raw data on the signal of the output 410 of the time-to-pseudo-random number converter 404.3 (TPRC) typically represents the last shift register value at which the output signal 409 of the comparator 404.2 showed a pulse. The output 411 of the entropy extraction 404.4 is connected to the input of the finite state machine FSM 404.8.

The finite state machine 404.8 typically has the task of receiving data in the form of a serial stream of quantum random bits 411 from the entropy extraction 404.4, converting the serial stream of random data bits into random data words and storing these in the RAM block 404.9 of the evaluation device 404, which is typically the volatile memory. The finite state machine 404.8 preferably communicates with the processor 404.11 (10-1, 10-2) via an internal data bus 419. After a successful write operation, the finite state machine 404.8 sets a finish flag 404.10. The processor 404.11 can preferably write and/or read the finish flag 404.10 via the internal data bus 419. The finish flag 404.10 can be part of the RAM 404.9 or a register of the processor 404.11. The processor 404.11 preferably controls and monitors the finite state machine 404.8 via the internal data bus 419. The finish flag 404.10 is preferably not set at system start. The processor 404.11 can then access the RAM block 414.9 and read the random number from the RAM 404.9, for example using a C program that is started on the embedded processor 404.11, for example a dual-core Arm Cortex-A9 MPCore. The processor 404.11 is preferably identical to the first processor 10-1 of the 1 The processor 404.11 can be, for example, a dual-core Arm Cortex-A9 MPCore. The processor 404.11 can also carry out some of the functions of the sub-devices of the evaluation device 404 by means of a suitable program and thus replace these device parts if necessary.

Preferably, the processor 404.11 controls a watchdog 404.5. In the sense of the document presented here, the watchdog 404.5 is not only a watchdog timer, which comprises a timer that is clocked with the system clock of the quantum random number generator 28 or the system clock 2106 of the processor 404.11 and that must be reset to a start value by the processor 404.11 at regular intervals in order to avoid interrupting the program execution of the processor 404.11 when a watchdog counter reading threshold is reached and/or crossed by the counter reading of the timer of the watchdog 405.5. The watchdog 405.5 also carries out further monitoring tasks within the quantum random number generator 28. For example, the watchdog 404.5 preferably monitors the entropy of the quantum random bits 411. In particular, the watchdog 404.5 preferably ensures that the quantum random bits 411 preferably do not have more than q consecutive random bits of the same logical value. If this is the case, the watchdog 404.5 preferably inserts other bits instead of the quantum random bits 411 into this serial bit data stream from the entropy extraction 404.5 to the finite state machine 407.8. For this purpose, see the following 9 more. In this case, the watchdog 404.5 preferably adds random bits from another true random number generator and/or another quantum random number generator and/or pseudorandom bits from a pseudorandom number generator whose starting value is determined by valid random bits from a quantum random number generator (QRNG) or a true random number generator (TRNG). Since the time-to-pseudorandom number converter 404.3 (TPRC) already ensures by design that this case should not occur, the watchdog 404.5 preferably issues an error message to the processor 404.11 in such a case. The watchdog 404.5 is preferably also a watchdog for the first processor 10-1 at the same time. In addition, the watchdog 404.5 in the sense of the document presented here monitors other variables, such as the agreement of voltage values within the quantum random number generator 28 and/or within the device by means of one or more analog-to-digital converters and/or by means of one or more voltage monitoring devices such as voltage monitors 413, etc.

Figure 9

9 shows the extended exemplary evaluation device 404, which now includes monitoring of the random number 411 RN and has an additional backup system for the case of errors in order to ensure the security of the application circuit even in the event of a failure of the quantum random number generator. by means of an emergency procedure. For a better overview, the components processor 404.11 RAM 404.9 and finish flag 404.10 are omitted. The reader should identify these device parts or functions in the 9 still be considered as present. However, the expert can easily establish the connection to the finite state machine 404.8 from the 8th in the 9 and then comes to the disclosed technical teaching. The watchdog 404.5, an optional additional linear feedback shift register 404.6 as backup pseudorandom number generator PRNG and a signal multiplexer 404.7 extend the device of the 8th for the device of 9 .

The output 411 of the entropy extraction 404.4 is now connected to the watchdog 404.5 and the signal multiplexer 404.7 as an example. The watchdog 404.5 monitors the quantum random number RN at the output 411 of the entropy extraction 404.4. The watchdog 404.5 detects at least three defined error cases as proposed. For this purpose, the watchdog 404.5 passes valid quantum random bits 411 to the optional additional linear feedback shift register 404.6, for example, while generating a seed value S 412. The watchdog 404.5 preferably prevents the use of these valid quantum random bits by the finite state machine 404.8. If an error occurs, the watchdog 404.5 sets error bits in an unmarked error register ER of the processor 404.11. Which error bit the watchdog 404.5 sets in the error register of the processor 404.11 preferably depends on the respective error case that the watchdog 404.5 detects. In addition, the watchdog 404.5 is connected to the processor 404.11 via one or more, preferably digital, input/output signal lines 414 in the example of the 9 connected to a voltage monitor 413. Preferably, the watchdog circuit 404.5 monitors the voltage values determined by the voltage monitor 413. It has proven useful if the voltage monitor 413 not only determines and monitors the voltages in the quantum random number generator 28, but also other voltages within the respective application circuit. The voltage monitor 413 can be the aforementioned analog-to-digital converter.

The voltage monitor 413 monitors in the example of 9 preferably the operating voltages of the entropy source 401 and/or other voltages that voltage converters generate within the application circuit. If, for example, one of the operating voltages of a photon source 54 and/or a silicon LED 54 and/or a first SPAD diode 54 and/or a photon detector 55 and/or a second SPAD diode 55 is too low, i.e. the voltage value is below a lower operating voltage threshold for these components, or too high, i.e. the voltage value is above an upper operating voltage threshold for these components, the voltage monitor 413 detects this voltage deviation and reports it to the watchdog 404.5 and/or the processor 10-1, 404.11. The processor 404.11 can preferably read the values of the voltage monitor 413 via the internal data bus 419 of the control device 4 of the integrated circuit 2, for example the microcontroller. In the event of such a voltage deviation, the voltage monitor 413 signals such a deviation to the watchdog 404.5 or directly to the processor 404.11. In the event of a signal to the watchdog 404.5, the watchdog 404.5 can, for example, generate an interrupt signal 420 for the processor 404.11. The watchdog 404.5 can, for example, trigger such an interrupt 420 of the microcontroller 404.11 or another sub-device of an application system if the supply voltage of the entropy source 401 or the high-frequency amplifier 402 or another device part of the quantum random number generator QRNG 28 and/or the integrated circuit 2, for example the microcontroller, and/or the application device is faulty. If the watchdog 404.5 has detected an error in the quantum random number generator 28, it preferably causes the quantum random number generator 28 to switch to an emergency running state. For this purpose, the watchdog 404.5 preferably sets the selection signal 416 of a signal multiplexer 404.7, so that the signal multiplexer 404.7 applies the pseudorandom number PRN of the optional additional linear feedback shift register 404.6 in the form of a stream of pseudorandom bits via a pseudorandom signal line 417 to the input of the finite state machine 404.8 instead of the output 411 of the entropy extraction 404.4 as a replacement for the at least potentially erroneous random number RN of the output 411 of the entropy extraction 404.4.

The optional additional linear feedback shift register 404.6 is in the example of the 9 connected to the output Seed S 412 of the watchdog 404.5. In the event of an error, the watchdog 404.5 activates the optional, additional, linear feedback shift register 404.6. The optional, additional, linear feedback shift register 404.6 then generates pseudorandom numbers PRN as a pseudorandom number generator PRNG. The seed S 412 preferably has the last quantum random bits that are still valid. The watchdog 404.5 preferably applies these last valid quantum random bits 411 to the input of the optional, additional, linear feedback shift register 404.6. The seed S thus serves as a random PQC safe starting value for the generator polynomial of the feedback of the optional, additional linear feedback shift register 404.6 for the generation of the pseudorandom number PRN and its signaling via the Pseudorandom signal line 417. The generator polynomial and the degree of the generator polynomial are preferably freely selectable.

The signal of the output 411 of the entropy extraction 404.4 with the 1 bit random number RN of the entropy extraction 404.4 or the signal of the pseudorandom signal line 417 with the pseudorandom number PRN of the linear feedback shift register 404.6 are connected to the inputs of the signal multiplexer 404.7. The signal multiplexer 404.7 forwards one of the two inputs to the finite state machine 404.8 depending on the value of the selection signal 416 SEL. It is of course conceivable to use a multiplexer with more than two inputs and a more complex control signal if the application requires it. The number of inputs of the signal multiplexer 404.7 is therefore typically greater than or equal to two.

Here too, the finite state machine 404.8 has the task of receiving the random data RN or the pseudorandom number PRN at the output of the signal multiplexer 404.7 and writing it into the RAM block 404.9, 15 of the evaluation device 404 within the control device 4. If the writing process is successful, the finite state machine 404.8 sets the finish flag 404.10 again. The processor 404.11 can then access the RAM block 404.9, for example using a C program that preferably runs on the embedded processor 404.11, and read out the random number and use it, for example, for encryption.

Preferably, time-to-pseudo-random number converter 404.3 records the time between two pulses on the output signal 409 of comparator 404.2 as a time value. If a time value at the output 410 of time-to-pseudo-random number converter 404.3 is less than a minimum value, it is a value that lies within the dead time of the second SPAD diodes 55. When such a value occurs, evaluation device 404 preferably discards the generated pseudo-random numbers and preferably increases the error counter by the first error step size, which can also be negative. In this case, entropy extraction 404.4 waits for the next random number to be determined by time-to-pseudo-random number converter 404.3. Once the random bit has been extracted in this way, quantum random number generator 28 starts the process from the beginning.

If the error counter crosses or reaches the error counter threshold, an error may be present, for example, in which the time-to-pseudorandom number converter 404.3, for example, delivers constant numerical values due to an error.

This device is thus able to detect a failure of the voltage supply 5 of the entropy source 401 or other parts of the device (e.g. 4, 28). The processor 404.11 can also use the analog-to-digital converter 403 to record voltages and currents in the quantum random number generator 28 and/or within the control device 4 of the integrated circuit of a microcontroller and/or within the integrated circuit 2, for example the microcontroller, for test purposes and compare the values thus determined with expected value ranges in which these values must lie. The processor 404.11 can also record digital values within the quantum random number generator 28 and/or within the control device 4 of the integrated circuit of a microcontroller and/or within the integrated circuit 2, for example the microcontroller. For example, the processor 404.11 can set the constant Const 404.1 so low for test purposes that the noise floor essentially controls the time-to-pseudo-random number converter 404.3. To this end, the processor 404.11 preferably sets an operating state of the time-to-pseudo-random number converter 404.3 in which the time-to-pseudo-random number converter 404.3 restarts with the last seed value after generating a pseudo-random number. The values of the time-to-pseudo-random number converter 404.3 should then satisfy an expected statistic within a tolerance band. If this is not the case, an error is present. The processor 404.11 can create this statistic and, if necessary, conclude that this error has occurred if the statistical values determined do not lie within an expected value interval.

The watchdog 404.5 can monitor the entropy of the quantum random bits 411 supplied. If the mean entropy of the quantum random bits 411 deviates from the expected random mean value of 50% by significantly more than a permitted entropy deviation value over an entropy measurement period, the watchdog 404.5 preferably concludes that there is an error in the quantum random number generator 28 and preferably increments the error counter by the said error counter step size. The watchdog 404.5 then preferably stops the use of these quantum random bits of the output 411 of the entropy extraction 404.4 in order to prevent the device from sending plain text via the data bus. Plain text means in the sense of the document presented here that the data sent and/or stored is in a form that allows a third party to directly and/or by applying statistical or other methods. can provide unauthorized access to the content of a data message and/or stored data and/or program code. It is conceivable that a virtual permanent one or a virtual permanent zero is generated randomly even in functioning sub-devices. Randomness also includes the permanent zero and the permanent one. It is therefore sensible if the maximum length of a bit sequence without changing the logical state at the output 411 of the entropy extraction 404.4 is limited to a value programmable by the processor 404.11 by the watchdog 404.5.

• • Störung von Versorgungsspannungen
• • Fehlerhafte Signalerzeugung der Photonenquellen 54 und/oder der Silizium-LEDs 54 und/oder der ersten SPAD-Dioden 54,
• • Fehlerhafte Signalerzeugung der Photonendetektoren 55 und/oder der zweiten SPAD-Dioden 55,
• • Störung des optionalen Lichtwellenleiters 44,
• • Störung der Ankoppelung der Photonenquellen 54 und/oder der Silizium-LEDs 54 und/oder der ersten SPAD-Dioden 54 an den Lichtwellenleiter 44,
• • Störung der Ankoppelung der Photonendetektoren 55 und/oder der zweiten SPAD-Dioden 55 an den Lichtwellenleiter 44,
• • Schaltungsausfälle im Digitalteil 404 des Quantenzufallszahlengenerators 28,
• • Fehlerhafte Entropie der gelieferten Quantenzufallsbits 411.

Essentially, the quantum random number generator 28 described above can thus detect the following errors and compensate for them by an emergency run using an optional, additional pseudorandom number generator 404.6, for example using an optional, additional, linearly fed-back shift register 4104.6, with a lower security level:

• • Disturbance of supply voltages
• • Faulty signal generation of the photon sources 54 and/or the silicon LEDs 54 and/or the first SPAD diodes 54,
• • Faulty signal generation of the photon detectors 55 and/or the second SPAD diodes 55,
• • Malfunction of the optional fiber optic cable 44,
• • Disturbance of the coupling of the photon sources 54 and/or the silicon LEDs 54 and/or the first SPAD diodes 54 to the optical waveguide 44,
• • Disturbance of the coupling of the photon detectors 55 and/or the second SPAD diodes 55 to the optical waveguide 44,
• • Circuit failures in the digital part 404 of the quantum random number generator 28,
• • Incorrect entropy of the supplied quantum random bits 411.

It is conceivable to use a second complete quantum random number generator 28 instead of the optional, additional linear feedback shift register 404.6 or the optional, additional pseudorandom number generator 404.6, the output 411 of which, the entropy extraction 404.4 of which is then used by the multiplexer 404.7 instead of the signal of the optional, additional pseudorandom signal line 417 for the emergency operation of the quantum random number generator 28. In the event that the output of the optional, additional pseudorandom number generator 404.6 depends on one or more real quantum random bits 411 as seed 412, it is again a quantum random number as long as the number of inserted bits is limited. The watchdog 405.5 preferably determines the number q of the permitted, maximum consecutive quantum random bits 411 using a quantum random number. If this quantum random number, which the watchdog 404.5 uses to determine q, only contains quantum random bits 411 with a single logical value, there is a possibility that an error has occurred. The number q should not be maximum in order to avoid sending or storing plain text. Instead, the watchdog 404.5 should choose a very small number q, preferably a minimum.

Figure 10

10 shows the flow chart 500 of the entropy extraction method, which, for example, carries out the entropy extraction 404.4. The method provides for, firstly, in a first step 501, two values of the output 410 of the time-to-pseudo-random number converter 404.3 to be determined and stored in a shift register of the entropy extraction 404.4. If two values are stored in the shift register of the entropy extraction 404.4, the entropy extraction 404.4 compares these two values in a second step 502. The two values in the shift register of the entropy extraction 404.4 therefore include a first value and a second value, both of which the time-to-pseudo-random number converter 404.3 has determined by means of two different pseudo-random number determinations depending on the respective time period between two signal pulses of the output signal 409 of the comparator 404.2. In a third step 503, the entropy extraction 404.4 evaluates the two values. If the first value is smaller than the second value and the difference between value 1 and value 2 is greater than a minimum difference ε, the entropy extraction 404.4 sets the value of its output 411 to a first logical value. If the first value is greater than the second value and the difference between the first value and the second value is greater than the minimum difference ε, the entropy extraction 404.4 sets its output to a second logical value that is different from the first logical value. If the difference between the first value and the second value is smaller than the minimum difference ε, the entropy extraction discards the first value and the second value. In such a case, the entropy extraction preferably causes the watchdog 404.5 to set an error counter. to increase a first error counter step size. The first error counter step size can be negative. Conversely, the entropy extraction 404.4 can decrease the error counter of the watchdog 404.5 by a second error counter step size if the difference between the first value and the second value is greater than the minimum difference ε. The second error counter step size can be equal to the first error counter step size. Typically, the signs of the first error counter step size and the second error counter step size are the same. Preferably, the processor 404.11 can set the error counter step sizes and the start value of the error counter and an error counter threshold value. If the count of the error counter crosses the error counter threshold value, the watchdog 404.5 signals the presence of a critical error state to the processor 404.11, preferably by means of an interrupt 420 or another signaling. The processor 404.11 then typically starts a self-test program to test the various parts of the quantum random number generator 28. For this purpose, the processor 404.11 can preferably, for example, put the analog-to-digital converter 403 into a state in which the processor 404.11 can write test values to an output register of the analog-to-digital converter 403, which the subsequent signal chain then processes like real sample values. Since the test values are known in advance, the processor 404.11 can observe and evaluate the correct reaction of the rest of the system, for example the incrementing of the error counter in the watchdog 404.5. The microcontroller 404.11 can therefore preferably monitor as many memory nodes as possible of the evaluation circuit 404 or the control device 4 and read their logical state.

Figure 11

11 shows an example oscillogram of the voltage signal 404 of the entropy source 401. As can easily be seen, first spikes 601 with a first height and second spikes 602 with a second height occur. The scatter of the first height of the first spikes 601 and the scatter of the second height of the second spikes 602 are so small that a clear separation of these events 601, 602 is possible by means of an example cutting level 603 via the selection of the constant 404.1. The cutting level 603 corresponds to the value that the processor location 404.11 sets using the constant 404.1, which is preferably implemented as a register of the processor 404.11.

Figure 12

12 shows the schematic sequence of a server-client communication using a proposed quantum random number generator. A first device, such as the one in the 1 , as a server via a data bus with a second device, such as the 1 , communicate in encrypted form as a client. In a first example, both the first device and the second device should each comprise a quantum random number generator 28, which the respective first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) uses for encryption. Preferably, the quantum random number generator 28 corresponds in whole or in part to a construction according to one of the 5 to 9 . The quantum random number generators of the first device and the second device most preferably each comprise a quantum random number generator 28, which in each case has at least one photon source 54 or a silicon LED 54 or a first SPAD diode 54 and in each case, for example, an optical waveguide 44, for example in the form of the oxide stack 44 on the semiconductor surface of the semiconductor substrate 49 and preferably at least one photon detector 55 or a second SPAD diode 55 as a receiver. This increases the data rate of the generated quantum random bits 411 and enables the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the respective device to generate and exchange the keys very quickly. The respective first processors 10-1 of the respective computers (here the exemplary micro-integrated circuit 2) of the respective devices encrypt their mutual communication preferably using an RSA encryption method. The exemplary RSA encryption method is for example from RL Rivest, A. Shamir, and L. Adleman, “A Method for Obtaining Digital Signatures and Public-Key Cryptosystems” Communications of the ACM, February 1978, Vol. 21, No. 2, pages 120 to 126 known. The prime numbers that the respective first processor 10-1 of the respective computer (here the respective exemplary micro-integrated circuit 2) of the respective device preferably uses to generate the public and private keys are preferably randomly generated by the quantum random number generator 28 QRNG. The communication of the computer (here the exemplary micro-integrated circuit 2) of the server with the respective first processor 10-1 of the respective computer (here the exemplary micro-integrated circuit 2) of the client preferably comprises, firstly, the process “Server Process”, which is started on the respective first processor 10-1 of the respective computer (here the exemplary micro-integrated circuit 2) of the server, i.e. the first device, and, secondly, the process “Client Process”, which is started on the respective first processor 10-1 of the respective computer (here the exemplary micro-integrated circuit 2) of the client, i.e. the second device. The respective first processor 10-1 of the respective computer (here the exemplary micro-integrated circuit 2) of the client typically communicates with the respective first processor 10-1 of the respective computer (here the exemplary micro-integrated circuit 2) of the server via so-called sockets. These are communication points which the respective operating system of the respective computer (here the exemplary micro-integrated circuit 2) provides. Preferably, the functions required to establish communication come, for example, from the standard C library socket.h. The following explains the communication according to 12 : At the beginning, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server generates a socket descriptor in step 3000. A socket descriptor in the sense of the document presented here is an integer-like file handle that is generated, for example, by the standard C library function socket() of the socket.h library. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server can use this socket descriptor in later function calls that use sockets.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server preferably binds the socket descriptor to a port and an IP address in step 3010. Binding in the sense of this document means that the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server uses the standard C function bind() from the standard C library socket.h to logically link the port and the IP address to the socket descriptor generated in step 3000. In the sense of this document, a port is a part of the network address that enables the assignment of data packets between server and client programs. In the sense of this document, an IP address is a network address that makes a participant in a network uniquely identifiable.

In the next step 3020, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server goes into a passive waiting state 3020 and waits for connection requests from a first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of a client. In the sense of the document presented here, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server preferably calls the standard C function listen() of the socker.h library for this purpose. The function indicates that the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server is ready, that the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) can accept connection requests from clients. The first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) creates a queue for incoming connection requests from the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client in one of the memories of the computer (here of the exemplary micro-integrated circuit 2) or the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) or another device part of the computer (here of the exemplary micro-integrated circuit 2). If the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server detects a connection request from a first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of a client, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server accepts this connection request from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client.

The first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the server then establishes a connection to the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client in a following step 3030. The first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the server detects a connection request from the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client by the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the server leaving the listen() function. The first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the server accepts the connection request preferably by calling the standard C function accept() of the socket.h standard C library. The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server preferably extracts the first connection request from the queue of open connection requests for the server and then uses it to establish the connection to the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client. If successful, the accept() function returns a socket descriptor of the client to the first processor 10-1 of the computer (here the example micro-integrated circuit 2). A socket descriptor in the sense of this document is an integer similar to a file handle of the standard C library socket.h. This then creates the connection between the first processor 10-1 and the first processor 10-1 of the computer (here the example micro-integrated circuit 2). processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server and the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client.

If such a connection exists, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server preferably starts a function keyExchangeServer() in a subsequent step 3040. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server then executes this function keyExchange() in this step 3040 in order to send the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client its public key. However, this function keyExchangeServer() is not a standard C function. In this function, in this step 3040, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server generates quantum random numbers using a quantum random number generator 28 QRNG. The quantum random number preferably has a bit width of n. Here, n is a positive integer including zero. These random numbers of the quantum random number generator 28 of the computer (here the exemplary micro-integrated circuit 2) of the server serve in the example presented in this document as indices for a look-up table of the first 2n prime numbers. This look-up table is preferably located in one of the memories of the computer (here the exemplary micro-integrated circuit 2) or in a memory of sub-devices of the computer (here the exemplary micro-integrated circuit 2) of the server. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server then reads the prime number corresponding to this index of the quantum random number of the quantum random number generator 28 of the computer (here the exemplary micro-integrated circuit 2) from the memory of the computer (here the exemplary micro-integrated circuit 2) of the server. Using these prime numbers, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) server generates both a public and a private key according to the aforementioned RSA encryption method.

The first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) then transmits a public key to the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client via the data interface 64 of the computer (here of the exemplary micro-integrated circuit 2) of the server and the data bus 95 and the data interface 64 of the computer (here of the exemplary micro-integrated circuit 2).

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server then waits for a message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client via the data interface 64 of the computer (here the exemplary micro-integrated circuit 2) of the client and the data bus 65 and the data interface 64 of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server. Preferably, this message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client includes a public key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client. Thus, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client typically transmits the private key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client via the data interface 64 of the computer (here the exemplary micro-integrated circuit 2) of the client and the data bus 95 and the data interface 64 of the computer (here the exemplary micro-integrated circuit 2) of the server to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server. If the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server has received the public key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server stores this public key in a memory of the computer (here the exemplary micro-integrated circuit 2) of the server.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server then sends, for example, its public key via its data bus interface 64 and the data bus 65 and the data bus interface 64 of the computer (here the exemplary micro-integrated circuit 2) of the client to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client.

Thus, the server is typically used for the exchange of encrypted data between the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client and the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server.

After the keys have been exchanged, the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server preferably executes the function recv() 3050 and waits for an encrypted message from the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client. If the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server receives a message, the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server preferably initially stores this encrypted message in a temporary buffer of the computer (here the example micro-integrated circuit 2) of the server. In the sense of the present document, the function recv() is preferably a standard C function of the standard C library socket.h. The recv() function typically reads incoming data from a socket descriptor, in this case the socket descriptor of the first processor 10-1 of the client's computer (here, the exemplary micro-integrated circuit 2) from step 3030 of the method. The recv() function, which the first processor 10-1 of the server's computer (here, the exemplary micro-integrated circuit 2) typically executes, typically stores the received data in the temporary cache of the server's computer (here, the exemplary micro-integrated circuit 2).

If the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server has received an encrypted message in this way, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) server preferably executes the function Decrypt() 3060 in a further step 3060. This function Decrypt() is not a standard C function. In this step 3060, the function Decrypt() decrypts the message of the server's private key from step 3040, which is temporarily stored in the memory of the computer (here the exemplary micro-integrated circuit 2), in accordance with the RSA method. As a result, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server decrypts the received encrypted message from the client using the private key from step 3040 temporarily stored in the memory of the computer (here the exemplary micro-integrated circuit 2) according to the RSA method. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server preferably stores the then decrypted message in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) of the server.

If the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server does not receive a message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client within a predetermined period of time, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server jumps to the step now described. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server checks whether a message should be sent to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client. Typically, such a message is stored in a memory of the computer (here the exemplary micro-integrated circuit 2) of the server for sending in such a case. If necessary, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server can also collect or receive such a message from another memory or system before sending it. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server then preferably stores such a message temporarily in a buffer of the computer (here the exemplary micro-integrated circuit 2) of the server. If such a message to be sent is waiting to be sent in a memory or buffer of the computer (here the exemplary micro-integrated circuit 2) of the server, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server preferably executes the Encrypt() function in a further step 3070. In this step 3070, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server encrypts its own message using the client's public key from 3040 in accordance with the RSA method. This Encrypt() function is not a standard C function. The server stores its now encrypted message in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) of the server.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server now executes the function send() in a step 3080. In the step 3080, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server sends its encrypted message stored in the buffer of the computer (here the exemplary micro-integrated circuit 2) to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client via the data bus interface 64 of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server and via the data bus 65 and via the data interface 64 of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2). In the sense of this document, the send() function is a standard C function of the standard C library socket.h. The send() function sends data via a socket descriptor, in this case the client's socket descriptor from step 3030. The typical cycle is terminated when the transmission ends.

Thereafter, the encrypted communication for the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server starts again at step 3040.

If the communication is terminated by the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server or the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client, the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server executes the function close() 3090. The close() function is a standard C function of the standard C library socket.h. By executing the close() function, the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server closes the open connection to a socket, here the socket of the client, and thus terminates the communication.

In an analogous manner, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client executes a client process.

At the beginning of the "client process", the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client creates a socket descriptor in a step 3100. A socket descriptor in the sense of this document is again an integer similar to a file handle, for example the standard C library function socket() of the socket.h library, which the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client can use in later function calls that use sockets. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client makes a connection request to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server using the port and the IP address that were specified in step 3010.

To do this, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client preferably executes the standard C function connect() of the standard C library socket.h. This function establishes a connection between the server socket from step 3010 and the client socket from step 3100.

If the connection was accepted by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server in accordance with step 3030, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client executes the function KeyExchangeClient() in a step 3120. This function is not a standard C function. By executing this function, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client generates one or more QRNG quantum random numbers using the quantum random number generator 28. This quantum random number has a bit width n. Here, n is a positive integer including zero. These random numbers of the quantum random number generator 28 of the computer (here the exemplary micro-integrated circuit 2) of the client preferably serve as indices for a look-up table of the first 2 ⁿ prime numbers. Using these prime numbers or other prime numbers, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client generates both a public and a private key according to RSA encryption (ANGANG). The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client stores its public key generated in this way and its private key generated in this way preferably in a memory of the computer (here the exemplary micro-integrated circuit 2) of the client. Then the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client sends its public key to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server via the data interface 64 of the computer (here the exemplary micro-integrated circuit 2) of the client and via the data bus 65 and via the data interface 54 of the computer (here the exemplary micro-integrated circuit 2) of the server. Then the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client responds to a message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server. This message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server typically contains the public key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client then executes the Encrypt() function 3130. By executing the Encrypt() function in step 3130, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client encrypts its own message using the public key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server from step 3040 using the RSA method. This function is not a standard C function. The client saves the encrypted message in a temporary buffer.

The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client now executes the send() function in step 3140 and sends its encrypted message to the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server. In the sense of this document, the send() function is a standard C function of the standard C library socket.h. By executing the send() function, the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client sends data via a socket descriptor, in this case the client's socket descriptor from 3100.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client then executes the function recv() 3150. In the process, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client waits in step 3150 for an encrypted message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server. If the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client receives a message, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client stores this received and typically encrypted message in a temporary buffer. In the sense of the present document, the function recv() is preferably a standard C function of the standard C library socket.h. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client reads incoming data from a socket descriptor, in this case from the socket descriptor of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client from step 3100, by executing the function recv(). The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client preferably stores the read data in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) of the client.

If the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client has received an encrypted message in this way, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client preferably executes the function Decrypt() in a step 3160. This function DeCrypt() is not a standard C function. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client decrypts an encrypted message of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server received by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client by executing the function Decrypt() using the private key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client from step 3120 using the RSA method. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client then stores the message decrypted in this way in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) of the client.

Thereafter, the communication between the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server and the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client starts again at step 3120.

If the communication is initiated by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client or the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server is terminated, the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client executes the close() function in step 3170. The close() function is a standard C function of the standard C library socket.h. Because the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client executes the close() function, the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client closes the open connection to a socket and thus terminates the communication with the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the server.

Figure 13

13 shows the schematic flow of the functions KeyExchangeServer() and KeyExchangeClient().

When starting the KeyExchangeServer() function, the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server first calls the setPrimes() function in step 3200. This KeyExchangeServer() function is not a standard C function. The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server uses the KeyExchangeServer() function to generate two different prime numbers p and q, the product n=p*q and the Euler phi function phi = (p-1)(q-1) in step 3200.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server then calls the setE() function in step 3210. This setE() function in step 3210 is not a standard C function. When the setE() function is called in step 3210, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server generates a number e that is coprime to phi, where the number phi is the number from step 3200. Coprime in the sense of this document means that there is no natural number other than the number one that divides the number e and phi at the same time.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server then executes the findD() function in step 3220. This findD() function is not a standard C function. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server uses the findD() function to calculate the multiplicative inverse of e, so that (e*d)mod phi = 1.

Now the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server calls the function recv() in step 3230. The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server now waits for an incoming message from the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client, which should typically include the client's public key. In the sense of this document, the function recv() is a standard C function of the standard C library socket.h. By calling the function recv(), the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server reads the incoming data from a socket descriptor, in this case the socket descriptor of the client. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server preferably stores the read data in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2).

Now the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server calls the send() function in step 3240. In this step 3240, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server sends its public key (d,n) from steps 3200 and 3220 to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client. In the sense of this document, the send() function is a standard C function of the standard C library socket.h. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server uses the send() function to send data via a socket descriptor, in this case the client's socket descriptor from step 3030.

Subsequently, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server leaves the function KeyExchangeServer() in step 3245.

When starting the KeyExchangeClient() function, the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client first calls the setPrimes() function in step 3250. This function is not a standard C function. The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client uses the KexExchangeClient() function to generate the prime number p and the prime number q that is different from q. The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client uses the KexExchangeClient() function to generate the product n=p*q. The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client uses the KexExchangeClient() function to generate the Euler Phi function phi = (p-1)(q-1).

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client then calls the function setE() in step 3260. This function is not a standard C function. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client uses the function setE() to generate an integer e that is coprime to the number phi from step 3250. Coprime in the sense of this document means that there is no natural number other than the number one that simultaneously divides the number e and the phi without a remainder.

The first processor 10-1 of the client's computer (here the example micro-integrated circuit 2) then calls the function findD() 3270. This function is not a standard C function. The first processor 10-1 of the client's computer (here the example micro-integrated circuit 2) uses the function findD() to calculate the multiplicative inverse of the number e, so that (e*d)mod phi = 1.

Now the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client calls the send() function 3280 and sends its public key (d,n) from steps 3250 and 3270 to the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server. In the sense of this document, the send() function is a standard C function of the standard C library socket.h. The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client uses the send() function to send data via a socket descriptor, in this case the client's socket descriptor from step 3100.

Now the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client calls the function recv() in step 3290. The first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the client now waits for an incoming message from the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server with the public key of the first processor 10-1 of the computer (here the example micro-integrated circuit 2) of the server. In the sense of this document, the function recv() is a standard C function of the standard C library socket.h. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client reads incoming data from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server from a socket descriptor, in this case from the socket descriptor of the client from step 3100, using the recv() function and stores the data in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) of the client.

Subsequently, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client leaves the function KeyExchangeClient() in step 3295.

Figure 14

14 shows schematic flow of the function setPrimes().

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client and the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server each call this function at the given time. If one of these first processors 10-1 calls the setPrimes() function, the calling processor 10-1, in the case of the present document the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server or the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client, generates a quantum random number using a quantum random number generator QRNG 28 in step 3300. This quantum random number has a bit width n. Here, n is a positive integer including zero. These quantum random numbers serve in the technical teaching of the document presented here as Indices for a look-up table of the first 2 ⁿ prime numbers. The calling first processor 10-1 stores the prime number indexed by the quantum random number as variable p.

The calling first processor 10-1 then generates another quantum random number in step 3310 with the preferred bit width n using the quantum random number generator 28 QRNG. These quantum random numbers preferably serve the calling first processor 10-1 again as indices for a look-up table of the first 2 ⁿ prime numbers. The calling first processor 10-1 stores the prime number, which is indexed by the random number, as a variable q in a buffer of the computer (here the exemplary micro-integrated circuit 2), of which the first processor 10-1 is preferably a part.

Now the calling first processor 10-1 checks in step 3320 whether the logical statement q ==p is true. If this statement is true, step 3310 is repeated.

The calling processor 10-1 then calculates the product n = p * q in step 3330.

Then the calling processor 10-1 calculates the Euler phi function phi = (q-1) * (p-1) in step 3340.

The calling processor 10-1 then exits the setPrimes() function in step 3350.

Figure 15

The 15 shows the schematic sequence of the setE() function 3400. When calling the setE() function in step 3400, the caller, in the case of the present document the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server or the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client, generates a random number e for which it is coprime to the number phi. Coprime in the sense of the present document means that there is no natural number other than the number one that divides the number e and phi at the same time. The calling processor 10-1 can generate the number e both by a random number from the quantum random number generator 28 QRNG and by a pseudo-random number generator PRNG and by iterating up an integer number starting with 2. However, generation by means of the quantum random number generator 28 QRNG is preferred.

Then, the calling processor 10-1 checks in step 3410 whether the logical statement gcd(e,phi) != 1 is satisfied.

If the logical statement is fulfilled, the calling processor 10-1 repeats step 3400.

If the logical statement is not fulfilled, the calling processor 10-1 exits the setE() function and returns the current value of e to the calling processor 10-1. The gcd(a,b) function is not a standard C function. The calling processor 10-1 uses this gcd(a,b) function to calculate the greatest common divisor of the parameters a, b and returns the result to the calling processor 10-1.

Figure 16

16 shows the schematic flow of the findD() function. When the calling processor 10-1 calls the findD() function in step 3500, the calling processor 10-1 initializes a variable d with 0 in step 3500.

In the subsequent step 3510, the calling processor 10-1 adds the number 1 to the number d.

Now, in step 3520, the calling processor 10-1 checks whether the logical statement (e*d) (mod phi) == 1 is true. If the logical statement (e*d) (mod phi) == 1 is not true, the calling processor repeats the steps from step 3510.

If the logical statement (e*d) (mod phi) == 1 is fulfilled, the calling processor 10-1 exits the function findD() in step 3530 and the calling processor 10-1 returns the current value of d to the calling processor 10-1, in the case of the present document the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server or the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client.

Figure 17

17 shows the schematic sequence of a secure transmission of quantum-based random numbers between a first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of a server 3600 and a first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of a client 3610.

In the case of the present document, the server 3600 is a first processor 10-1 of a computer (here the exemplary micro-integrated circuit 2), wherein the computer (here the exemplary micro-integrated circuit 2) of this server 3600 has a quantum random number generator 28 QRNG. In the case of the present document, the client 3610 is another first processor 10-1 of a computer 2, wherein this computer (here the exemplary micro-integrated circuit 2) of the client 3610 should NOT have a quantum random number generator 28 QRNG.

At the beginning, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 generates quantum random numbers QZ1. The quantum random numbers QZ1 serve the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 as a basis for generating a private and a public key of the server 3600 according to an asymmetric encryption method.

The asymmetric encryption method can, for example, be the RSA method.

In a step 3620, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 sends the public key of the server 3600 via a non-tap-proof channel to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 then generates a pseudo-random number PZ or a random number generated in another way. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 stores the pseudo-random number PZ or the random number generated in another way in a memory of the computer (here the exemplary micro-integrated circuit 2) of the client 3610. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 generates a first private key of the client 3610 and a first public key of the client 3610 using this pseudo-random number PZ or this random number generated in another way.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 encrypts the first public key of the client 3610 using the public key of the server 3600.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 then sends the encrypted first public key of the client 3610 to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 now decrypts this message with its first private key. As a result, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 now has the first public key of the client 3610 without this being known to third parties.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 then generates a further, second quantum random number QZ2 using the quantum random number generator 28. The bit width of this second quantum random number is preferably equal to the bit width of the random number PZ of the client 3610.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 now encrypts the second quantum random number QZ2 with the first public key of the client 3610. For example, the first public key of the client 3610 can be the client's. In this case, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 can encrypt the second quantum random number QZ2, for example by bitwise XORing the second quantum random number QZ2 with PZ to form an encrypted second quantum random number QZ2'. The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 then preferably sends the encrypted second quantum random number QZ2' to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 in a step 3640.

The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 decrypts the encrypted second quantum random number QZ2' using its first private key to form the second quantum random number QZ2. If the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) has determined the second encrypted quantum random number QZ2' by bitwise XORing the random number PZ with the second quantum random number QZ2, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 can decrypt the encrypted second quantum random number QZ2' with the random number PZ known to it, for example by bitwise XORing the encrypted second quantum random number QZ2' with the random number PZ known to it to form the second quantum random number QZ2.

Preferably, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 uses the second quantum random number QZ2 that it now has as a basis for generating a second private key and a second public key according to an asymmetric encryption method. The asymmetric encryption method can be, for example, the RSA method (APPENDIX). The first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client 3610 now sends its second public key to the server 3600 via the non-tap-proof channel. In doing so, it preferably encrypts this second public key of the client 3610 with the public key of the server 3600. The server 3600 decrypts the encrypted second public key of the client 3610 and then uses this second public key of the client to encrypt further messages to the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the client 3610. Preferably, the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the server 3600 generates and sends after a predetermined time or after sending a predetermined amount of data to the processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) of the Clients 3610 generate a new public key based on a new quantum random number from its quantum random number generator 28 QRNG encrypted with the second public key of the client 3610. Preferably, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 and the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client then carry out the previously described process again so that the keys change permanently. This also makes it impossible for a quantum computer to break the keys.

This means that after exchanging these keys, communication can be carried out based on the selected asymmetric encryption method.

Figure 18

18 shows schematically the proposed method 3700 for generating a quantum random number.

The method 3700 begins with the generation 3710 of a random single photon stream (57, 58, 59, 44) by means of one or more photon sources 54 or one or more silicon LEDs 54 or one or more first SPAD diodes (54), which are preferably manufactured in one piece in a semiconductor material 49.

The method 3700 continues with the transmission 3720 of the random single photon stream (57, 58, 59, 44), for example by means of an optical waveguide 44 different from the semiconductor substrate (49, 48) or by means of the semiconductor substrate 49 as an optical waveguide or by means of direct irradiation to one or more photon detectors 55 or one or more second SPAD diodes 55.

This is followed in the method 3700 by the conversion 3730 of the random single photon stream (57, 58, 59, 44) into a detection signal in the form of a voltage signal 405 of the entropy source 401, which preferably comprises the photon sources 54 or the silicon LEDs 54 or the first SPAD diodes 54 and the optical system for optical coupling and the photon detectors 55 or the second SPAD diodes 55. The optical system can comprise a direct optical coupling of these components and/or comprise an optical waveguide 44.

Then, in the method 3700, the processing 3740, in particular amplifying and/or filtering and/or analog-to-digital converting, of the detection signal into a processed detection signal, in particular a digital 14-bit value 407 of the analog-to-digital converter 403 or a 1-bit analog-to-digital converter, follows.

Then, in the method 3700, the pulses of the conditioned detection signal generated by coupling the emissions of a photon source 54 or a silicon LED 54 or a first SPAD diode 54 on the one hand and a photon detector 55 or a second SPAD diode 55 on the other hand are optionally separated 3750 from the pulses of the conditioned detection signal generated by spontaneous emission by comparing the conditioned detection signal with a threshold value, in particular in a comparator 404.2 and generating a corresponding output signal 409, in particular of the comparator 404.2. If necessary, the analog-to-digital converter 403 can generate the output signal 409 directly if it is a 1-bit analog-to-digital converter 403. In this respect, this step 3750 is optional and is therefore only shown in dashed lines.

This is followed by the determination 3760 of a first pseudorandom number as a function of a first time interval between the first pulse and the second pulse of a first pair of two successive pulses of the conditioned detection signal, which pulses are generated by optical coupling of the emissions of a photon source 54 or a silicon LED 54 or a first SPAD diode 54 on the one hand and a photon detector 55 or a second SPAD diode 55 on the other hand, as the first value of the output 410 of the time-to-pseudorandom number converter 404.3.

This is followed by the determination 3765 of the second first pseudorandom number as a function of a second time interval between the third pulse and the fourth pulse of a second pair of two successive pulses of the conditioned detection signal, which pulses are generated by optical coupling of the emissions of a photon source 54 or a silicon LED 54 or a first SPAD diode 54 on the one hand and a photon detector 55 or a second SPAD diode 55 on the other hand, as the second value of the output 410 of the time-to-pseudorandom number converter 404.3.

On this basis, the bit value of a quantum random bit 411 is then determined 3670 by comparing the value of the first pseudorandom number and the value of the second pseudorandom number.

In a final check 3680, the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) and/or a finite state machine 404.8 check whether the number n of random bits determined is still smaller than the desired number m of random bits of the desired quantum random number. If this is not the case, the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) and/or finite state machine 404.8 repeat the above steps 3710 to 3770. Otherwise, the processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) or the finite state machine 404.8 terminate the process for generating a quantum random number. If necessary, the finite state machine 404.8 makes the quantum random number available to the processor 10-1 and preferably signals this availability to the processor 10-1, for example by an interrupt via an interrupt signal 420 or by setting a flag.

Preferably, the processor 10-1 and/or the finite state machine 404.8 control this process of generating a quantum random number.

Figure 19

19 shows another exemplary proposal for a one-piece, monolithic integrated circuit 2, for example a microcontroller.

The exemplary one-piece, monolithic integrated circuit 2, for example the microcontroller, comprises one or more processors 10-1, 10-2; a bus arbiter 82; an internal data bus 419; a read-only memory ROM 19; a volatile random access memory RAM 8; a first non-volatile, multi-programmable memory NVM 6; a second non-volatile, multi-programmable memory NVM 30; a first non-volatile, only once programmable memory OTP I 20; a second non-volatile, only once programmable memory OTP II 22; a test controller 12, in particular a JTAG test controller; a circuit (block) 24 for deactivating tests; one or more data bus interfaces 64; a tightly coupled memory TCM 14; an interface 32 to a system controlled by the integrated circuit 2, for example by the microcontroller; a quantum random number generator 28; a reset circuit 83; an analog input processing 84, an analog-to-digital converter 85; a digital signal processing 86; one or more digital-to-analog converters 87; an analog output processor 88; one or more voltage converters 91;

The one voltage converter 91 or the multiple voltage converters 91 generate the necessary internal operating voltages of the integrated circuit 2, for example the microcontroller, from the external supply voltages. Since the entropy source 401 in particular generally requires a higher operating voltage than the supply voltages provided externally, at least one of the voltage converters 91 preferably comprises a charge pump or the like. Typically, such voltage converters 91 here comprise DMOS transistors.

An analog input processor 84 acquires one or more external analog signals 89 and prepares them for analog-to-digital conversion. For example, the analog input processor 84 may include one or more amplifiers, filters, analog adders, analog multipliers, logarithmizers, exponentiators, voltage sources, current sources, and/or other analog circuits for adapting, enhancing, or modifying the external analog signals 89.

An analog-to-digital converter 85 can then convert the external analog signals 89 thus processed into a data stream of digital samples of the external analog signals 89, for example with a sampling frequency that typically depends on the system clock 2106.

A digital signal processor 86 can then convert the digitized and processed external analog signals 89 into digital output signals using circuits that carry out circuit-implemented methods and/or computer-implemented methods. The digital signal processor 86 can also generate new digital output signals. The digital signal processor 86 typically works with the system clock 2106. When generating these two output signal groups, the digital signal processor 86 can use quantum random numbers from the quantum random number generator 28. If the digital signal processor 86 is to generate a modulated excitation signal for a sensor, for example, and is to evaluate a response signal from this sensor as an external analog signal 89 after processing and digitization, it is useful in some applications, for example, if the digital signal processor 86 uses such a quantum random number as a spreading code for generating the excitation signal of the sensor and then searches for and detects this spreading code in the external analog signal 89, for example using a synchronous demodulator.

The digital-to-analog converter(s) 87 converts the digital output signals of the digital signal processing 86 to internal analog output signals.

The analog output processing 88 processes the analog internal output signals into analog output signals 90. For example, the analog output processing 88 can include filters, amplifiers and power amplifiers.

The rest circuit 83 brings the integrated circuit 2, for example the microcontroller, into a predefined state. Such a reset can occur, for example, when the operating voltage is switched on or when the operating voltage drops or when one of the processors 10-1, 10-2 requests such a rest from the reset circuit 83, for example via the data bus 419 or a SW rest signaling line, or when a means for monitoring the correct functioning of the quantum random generator 28 (watchdog 404.5, voltage monitor 2013) detects an error from a predefined set of errors. This enables the system to be restarted.

The quantum random number generator 28 preferably has the features presented here. Most preferably, the quantum random number generator 28 comprises a time-to-pseudo random number generator 404.3.

Preferably, the quantum random number generator 28 comprises means for monitoring the correct functioning of the quantum random number generator 28. Such means can be, for example, a voltage monitor 413 and/or a watchdog 404.5. These means typically generate an interrupt signal 420 in the event of an error and/or a suspected attack.

Other circuit parts of the integrated circuit 2, for example the microcontroller, can also trigger interrupts using additional interrupt lines. An interrupt logic in the processors controls the behavior of the processors 10-1, 10-2.

Preferably, the processors 10-1, 10-2 execute computer-implemented methods, the program code of which they retrieve from memories of the device during execution and execute. In one or more of these computer-implemented methods, the processors 10-1, 10-2 use quantum random numbers of the quantum random number generator 28. If the means of the quantum random number generator 28 for monitoring the correct functioning of the quantum random number generator 28, for example by means of the interrupt line 420, signal an error in the quantum random number generator 28, the processors 10-1, 10-2 preferably execute other computer-implemented replacement methods instead of these computer-implemented methods or modify parameters of these computer-implemented methods or preferably no longer execute these computer-implemented methods at all, at least as long as the error exists.

The circuit (block) 24 for deactivating tests, also referred to here as the deactivation circuit, is preferably able to control and prevent or allow access by meta-customers of the customers of the semiconductor manufacturer and the customers of the semiconductor manufacturer and the analysis department of the semiconductor manufacturer of the integrated circuit 2, for example the microcontroller, to circuit parts and contents of memories of the integrated circuit 2, for example the microcontroller. Typically, the deactivation circuit 24 can, for example, allow or prevent the activation of predetermined test modes. This can include, for example, the activation of scan paths and access to memory contents.

Preferably, the processor 10-1, 10-2 can only influence some of the accesses by reconfiguring the deactivation circuit 24. Thus, certain circuit and memory areas are not accessible for access after processor activation by a processor 10-1, 10-2. These circuit and memory areas are thus protected against processor activation of the access. It can be provided that no processor activation at all is possible by a processor 10-1, 10-2.

Preferably, the test interface (JTAG interface) 12 can only influence some of the accesses by reconfiguring the deactivation circuit 24. Thus, certain circuit and memory areas are not accessible for access after test controller activation by the test interface (JTAG interface) 12. These circuit and memory areas are thus protected against test controller activation of the access. It can be provided that no test controller activation at all is possible through the test interface (JTAG interface) 12.

Access can be activated, for example, by writing access codes into the second non-volatile, once-programmable memory OTP II 22.

The contents of the first, non-volatile and only once programmable memory OTP 120 can, for example, include critical system parameters (CSPs).

The contents of the second, non-volatile and only once programmable memory OTP II 22 can include, for example, access codes.

The first volatile, multi-programmable memory NVM 6 can comprise an EEPROM and/or a flash memory or the like. The memory content of the first volatile, multi-programmable memory NVM 6 can comprise, for example, data records 61 and signatures 61.

The volatile random access memory RAM 8 may comprise an SRAM and/or a DRAM or the like.

The second processor 10-2 is to be used in the 19 be optional.

The bus arbiter 82 regulates the access of the device parts of the exemplary one-piece, monolithic integrated circuit 2, for example the microcontroller, want to gain active write access to the internal data bus 419. In the case of 19 These are the two processors 10-1, 10-2.

The above description is not exhaustive and does not limit this disclosure to the examples shown. Other variations to the disclosed examples can be understood and practiced by those of ordinary skill in the art from the drawings, the disclosure and the claims. The indefinite articles "a" or "an" and their inflections do not exclude a plurality, while the mention of a certain number of elements does not exclude the possibility of more or fewer elements being present. A single unit may perform the functions of several elements mentioned in the disclosure and, conversely, several elements may perform the function of a unit. Numerous alternatives, equivalents, variations and combinations are possible without departing from the scope of the present disclosure.

Unless otherwise stated, all features of the present invention can be freely combined with one another. This applies to the entire document presented here. The features described in the description of the figures can also be freely combined with the other features as features of the invention, unless otherwise stated. A restriction of individual features of the exemplary embodiments to the combination with other features of the exemplary embodiments is expressly not intended. In addition, material features of the device can be reformulated and used as process features, and process features can be reformulated as material features of the device. Such a reformulation is therefore automatically disclosed.

In the foregoing detailed description, reference is made to the accompanying drawings. The examples in the description and drawings should be considered as illustrative and are not to be considered as limiting the specific example or element described. Multiple examples may be derived from the foregoing description and/or drawings and/or the claims by modifying, combining or varying certain elements. In addition, examples or elements not described verbatim may be derived from the description and/or drawings by a person skilled in the art.

Figure 20

20 shows a device similar to the device of the 8th and 9 . In contrast to the 8th and 9 The quantum random number generator comprises 28 in the 20 no high frequency amplifier 402 and no analog-digital converter (ADC) 403 with 14 bit width and no comparator 404.1 and no constant 404.1. The device of the 20 is suitable for forming a quantum random number generator 28 in which the photon source 54 and the photon detector 55 are electrically connected in series. In this case, the stimulated emissions can no longer be distinguished from the dark count.

One problem is that the pulses on the voltage signal 405 of the entropy source 401 are usually shorter than the frequency of the system clock 2106. This means that a direct sampling of the voltage signal 405 of the entropy source 401 with a sampling frequency equal to the frequency of the system clock 2106 no longer satisfies the Nyquist condition. Therefore, the exemplary 1-bit analog-digital converter (ADC) 403 is followed by a pulse extension circuit 2023 which extends a pulse on the voltage signal 405 of the entropy source 401 to a time length greater than one clock period of the system clock 2106 and preferably ends the generated pulse synchronously with the system clock 2106, so that the pulse on the voltage signal 405 of the entropy source 401 can be reliably synchronized by a subsequent flip-flop. The processor 10-1, 10-2 generated in this way can preferably access the registers of the watchdog 404.5, the memory RAM 404.9 or the FIFO 404.9 and the finish flag 404.10 via the internal data bus 419 and read them and, as far as permitted or possible, write them. The finish flag 404.10 preferably signals to the processor 10-1, 10-2 via an interrupt line (not shown) that a new quantum random number is available in the RAM/FIFO 404.9. Reading the contents of the RAM/FIFO preferably clears this finish flag 404.10 again. In order to save energy, it is sensible to switch off device parts of the quantum random number generator 28 when the finish flag 404.10 is set. Preferably, the processor 10-1, 10-2 can access device parts of the quantum random number generator 28 via the data bus 419 and switch certain parts of the quantum random number generator 28 on and off by setting or clearing flags in the registers of these device parts. These device parts can be, for example: the voltage monitor 419, a voltage converter 91 of the quantum random number generator 28, in particular a charge pump for supplying the entropy source 401, the ADC 403, the pulse extension circuit 2023, the time-to-pseudo-random number converter (TPRC) 404.3, the entropy extraction 404.4, the finite state machine 404.8. The watchdog 404.5 preferably evaluates these register bits and checks whether an enable register inside it has a permissible authentication code for these activations or deactivations. The finite state machine 404.8 preferably also evaluates these flags and preferably only allows the generation of quantum random numbers 418 when all parts of the quantum random number generator 28 are working.

The synchronized voltage signal 415 can then be processed as described above. With regard to the remaining device parts, the document presented here refers to the preceding descriptions.

Figure 21

21 shows an example of a time-to-pseudo-random number converter 404.3. The crucial idea here is to use a pseudo-random number generator 404.3 in the quantum random number generator 28 instead of a digital counter as in the prior art, which generates the first and second values for the entropy extraction 404.4. The document presented here refers here to 18 regarding the corresponding process. The advantage is that even if a disturbance is successfully introduced into the synchronized voltage signal 415, the randomness of the quantum random bit 411 is only marginally disturbed, since the attacker would also have to know the feedback polynomial. However, this is also randomly selected as proposed. The same applies to the seed value of the pseudorandom number generator, which the attacker would also have to determine. Another advantage of a pseudorandom number generator instead of a counter is the smaller area required by the feedback logic of a simple primitive feedback polynomial compared to a binary counter. If the linearly feedback shift register of the pseudorandom number generator is long enough, each cycle between two pulses of the voltage signal 405 of the entropy source 401 is typically assigned a unique pseudorandom number. Preferably, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) starts the generation of a pseudo-random number by the shift register of the time-to-pseudo-random number converter 404.3 (TPRC) with a first pulse on the voltage signal 405 of the entropy source 401 and ends the generation of the pseudo-random number with a subsequent second pulse on the voltage signal 405 of the entropy source 401.

In order to make tapping even more difficult, it is useful if, for example, the quantum random number generator 28 changes the feedback polynomial of the linearly feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 (TPRC) after the complete determination of a number m of random quantum bits 411 as a function of one or more previously determined random quantum bits 411.

The following simple primitive feedback polynomials are known from the literature, for example: No . XNOR from No . XNOR from No . XNOR from No . XNOR from 3 3.2 45 45,44,42,41 87 87.74 129 129,124 4 4.3 46 46,45,26,25 88 88,87,17,16 130 130,127 5 5.3 47 47.42 89 89.51 131 131,130,84,83 6 6.5 48 48,47,21,20 90 90,89,72,71 132 132,103 7 7.6 49 49.40 91 91,90,8,7 133 133,132,82,81 8th 8,6,5,4 50 50,49,24,23 92 92,91,80,79 134 134.77 9 9.5 51 51,50,36,35 93 93.91 135 135,124 10 10.7 52 52.49 94 94.73 136 136,135,11,10 11 11.9 53 53,52,38,37 95 95.84 137 137,116 12 12,6,4,1 54 54,53,18,17 96 96,94,49,47 138 138,137,131,130 13 13,4,3,1 55 55.31 97 97.91 139 139,136,134,131 14 14,5,3,1 56 56,55,35,34 98 98.87 140 140,111 15 15.14 57 57.50 99 99,97,54,52 141 141,140,110,109 16 16,15,13,4 58 58.39 100 100.63 142 142,121 17 17.14 59 59,58,38,37 101 101,100,95,94 143 143,142,123,122 18 18.11 60 60.59 102 102,101,36,35 144 144,143,75,74 19 19,6,2,1 61 61,60,46,45 103 103.94 145 145.93 20 20.17 62 62,61,6,5 104 104,103,94,93 146 146,145,87,86 21 21.19 63 63.62 105 105.89 147 147,146,110,109 22 22,21 64 64,63,61,60 106 106.91 148 148,121 23 23.18 65 65.47 107 107,105,44,42 149 149,148,40,39 24 24,23,22,17 66 66,65,57,56 108 108.77 150 150.97 25 25.22 67 67,66,58,57 109 109,108,103,102 151 151,148 26 26,6,2,1 68 68.59 110 110,109,98,97 152 152,151,87,86 27 27,5,2,1 69 69,67,42,40 111 111,101 153 153,152 28 28.25 70 70,69,55,54 112 112,110,69,67 154 154,152,27,25 29 29.27 71 71.65 113 113,104 155 155,154,124,123 30 30,6,4,1 72 72,66,25,19 114 114,113,33,32 156 156,155,41,40 31 31.28 73 73.48 115 115,114,101,100 157 157,156,131,130 32 32,22,2,1 74 74,73,59,58 116 116,115,46,45 158 158,157,132,131 33 33.20 75 75,74,65,64 117 117,115,99,97 159 159,128 34 34,27,2,1 76 76,75,41,40 118 118.85 160 160,159,142,141 35 35.33 77 77,76,47,46 119 119,111 161 161,143 36 36.25 78 78,77,59,58 120 120,113,9,2 162 162,161,75,74 37 37,5,4,3,2,1 79 79.70 121 121,103 163 163,162,104,103 38 38,6,5,1 80 80,79,43,42 122 122,121,63,62 164 164,163,151,150 39 39.35 81 81.77 123 123,121 165 165,164,135,134 40 40,38,21,19 82 82,79,47,44 124 124.87 166 166,165,128,127 41 41.38 83 83,82,38,37 125 125,124,18,17 167 167,161 42 42,41,20,19 84 84.71 126 126,125,90,89 168 168,166,153,151 43 43,42,38,37 85 85,84,58,57 127 127,126 44 44,43,18,17 86 86,85,74,73 128 128,126,101 ,99

As can easily be seen, the number of XNOR operations is very limited, which makes the linear feedback shift registers very fast. The longest chain listed has a length of 2 ¹⁶⁸ -1 clock cycles with a shift register length of n=168 shift register bits. At a GHz=10 ⁹ Hz, a period lasts 2 ¹⁵⁹ seconds, or in other words about 2 ¹⁵³ minutes, or in other words about 2 ¹⁴⁷ hours, or in other words about 2 ¹⁴² days, or in other words (very roughly) about 2 ¹³¹ years. It obviously takes too long to solve the problem in a finite time with a normal computer. This, in combination with a permanent quantum random number key change, makes it almost impossible for an attacker to break the corresponding barrier.

In order to prevent the protection of the quantum random number generator 28 from being broken, it is also useful if, for example, the quantum random number generator 28 changes the shift register length n of the linear feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 (TPRC) after the complete determination of a number k of random quantum bits 411 depending on one or more previously determined random bits. For this purpose, it is useful if the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or a processor (10-1, 10-2) rewrites the value of the feedback polynomial selection register 2112 for this purpose. The value stored in the feedback polynomial selection register 2112 preferably controls the feedback multiplexer 2102 of the time-to-pseudo-random number converter 404.3 (TPRC). Thus, the value stored in the feedback polynomial selection register 2112 preferably selects which feedback polynomial of the m feedback polynomial circuits RKN ₁ to RKN _m determines the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC). Preferably, by means of a line 2022 for preventing the use of a quantum random bit 411 by the finite state machine 404.8, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or one of the processors (10-1, 10-2) or another device prevents the forwarding of a generated quantum random bit 411 by the finite state machine 404.8 when this random bit 411 is used for the feedback polynomial selection register 2112. This prevents double use and thus increases security. Instead, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or the processor (10-1, 10-2) or the other device preferably uses this random bit 411 to generate a random data word for storage in the feedback polynomial selection register 2112. This has the advantage that the feedback polynomial of the m feedback polynomial circuits RKN ₁ to RKN _m selected by the feedback polynomial selection register 2112 is completely random. This means that it is no longer possible for an attacker to feed in a deterministic bit data stream instead of the data bit stream of the quantum random bits 411, even if an attack on the entropy source 401 is successful.

• • bei Erreichen einer vorbestimmten Anzahl erfolgreich erzeugter Quantenzufallsbits 411 und/oder
• • bei Erreichen einer vorbestimmten Anzahl erfolgreich erzeugter Zufallsdatenworte 418 und/oder
• • bei Änderung des Werts des Rückkoppelpolynom-Auswahlregisters 2112 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) und damit des ausgewählten Rückkoppelpolynoms der m Rückkoppelpolynome RKN₁ bis RKN_m des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC).

In order to further harden the proposed micro-integrated quantum random number generator 28, it is also useful if, for example, the quantum random number generator 28 changes the start value (seed value) of the linear feedback shift register of the pseudorandom number generator of the time-to-pseudorandom number converter 404.3 (TPRC) after the complete determination of a number p of random quantum bits 411 depending on one or more previously determined random bits. For this purpose, it is useful if the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or a processor (10-1, 10-2) rewrites the value of a seed reload register in the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) with random bits for this purpose. The bit width of a seed reload register in the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably corresponds to the number n of the shift register bits SB ₁ to SB _n of the time-to-pseudo-random number converter 404.3 (TPRC). The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably counts the number of successfully generated quantum random bits 411. For this purpose, the finite state machine 404.8 preferably signals the generation of a valid random bit to the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC). Instead of counting the valid quantum random bits 411, it is also possible to count the successfully generated random data words 418 in the finite state machine 404.8. The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferentially loads the new seed value of a seed reload register in the shift beregistercontroller 2103 in one or more of the following events in the shift register bits SB ₁ to SB _n of the time-to-pseudo-random number converter 404.3 (TPRC)

• • upon reaching a predetermined number of successfully generated quantum random bits 411 and/or
• • upon reaching a predetermined number of successfully generated random data words 418 and/or
• • when changing the value of the feedback polynomial selection register 2112 of the time-to-pseudo-random number converter 404.3 (TPRC) and thus of the selected feedback polynomial of the m feedback polynomials RKN ₁ to RKN _m of the time-to-pseudo-random number converter 404.3 (TPRC).

This reliably prevents any kind of predictability.

Preferably, the circuit parts of the quantum random number generator 28 are covered with a metal layer 142, 53 in order to ward off any influence by temperature or electromagnetic radiation or electrostatic fields or magnetic fields. Preferably, the metal layer also comprises a soft magnetic layer to ward off attempts at attack using magnetic fields.

Preferably, by means of a line 2022 for preventing the use of a quantum random bit 411 by the finite state machine 404.8, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or one of the processors (10-1, 10-2) or another device prevents the forwarding of a generated quantum random bit 411 by the finite state machine 404.8 when this random bit 411 is used for the seed reload register in the shift register controller 2103 in the time-to-pseudo-random number converter 404.3 (TPRC). This prevents double use and thus increases security. Instead, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or the processor (10-1, 10-2) or the other device preferably uses this random bit 411 to generate a random data word for storage in the seed reload register in the shift register controller 2103. This has the advantage that the seed value of the linear feedback shift register of the n shift register bits SB ₁ to SB _n selected by the seed reload register in the shift register controller 2103 is completely random. Since a linear feedback shift register has two cycles when using simple primitive feedback polynomials, one of which only includes a shift register value, this one-cycle shift register value must be prevented. If the random reload value of the seed reload register in the shift register controller 2103 corresponds to the one-cycle seed value of the linear feedback shift register with the current feedback polynomial or the next feedback polynomial provided, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) or one of the processors (10-1, 10-2) or another device generates a new random reload value in the seed reload register of the shift register controller 2103.

Preferably, the m feedback polynomials RKN ₁ to RKN _m are selected such that the one-cycle seed values are equal. This reduces the effort for detecting the one-cycle shift register value, since this no longer depends on the selected feedback polynomial of the feedback polynomials RKN ₁ to RKN _m . In any case, it is recommended that the time-to-pseudorandom number converter 404.3 (TPRC) includes a detection circuit 2113 for detecting an illegal value of the state vector of the n shift register bits SB ₁ to SB _n when linear feedback shift registers are used. If the state vector of the n shift register bits SB ₁ to SB _n is in such an illegal state, the detector 2113 preferably signals this illegal state to the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or one of the processors (10-1, 10-2) or another device. The detector 2113 or the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) or the processor (10-1, 10-2) or the other device then resets the value of the state value of the state vector of the n shift register bits SB ₁ to SB _n to a predetermined value and/or the value of the seed reload register in the shift register controller 2103. These reload values are preferably different from the one-cycle shift register value. This preferably also occurs when the watchdog 404.5 and/or the voltage monitor 413 detect a fault or a suspected or possible attack. The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably counts the number of these faults. Preferably, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) reduces this counter value again depending on the number of random quantum bits 411 and/or random data words 418 successfully generated, in particular since the last disturbance. If this number and/or the event density of such events exceeds a certain predetermined temporal density and/or a certain numerical value, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) signals a defect in the quantum random number generator, preferably to the watchdog 404.5 and/or a processor (10-1, 10-2). 28 or a successful attack on the quantum random number generator 28. Typically, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) then signals the finite state machine 404.8 that no more random numbers may be generated. Preferably, a processor (10-1, 10-2) must then reactivate the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) by means of a predetermined reactivation code word. The processor (10-1, 10-2) then writes this reactivation code word via the internal data bus 419 of the quantum random number generator 28 into a special reactivation register of the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC), which reactivates the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) and the quantum random number generator 28 and preferably resets all error counters. The number of possible reactivations is preferably limited. If the maximum number of reactivations is exceeded, the quantum random number generator 28 can preferably no longer be reactivated. The counter for the reactivations of the quantum random number generator 28 can preferably be reset by means of a special reset command before this maximum value is reached. Preferably, the shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) of the quantum random number generator 28 or another device of the quantum random number generator 28 issues a warning before reaching this blocking limit.

When the quantum random number generator 28 is started, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) first ensures that the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) first determines a new seed value based on quantum random numbers 411 and a new value of the feedback polynomial selection register 2112 based on quantum random numbers from quantum random bits 411 by means of a predetermined seed value and a predetermined value of the feedback polynomial selection register 2112. Only when the seed value and the value of the feedback polynomial selection register 2112 are based on quantum random numbers is the initialization phase of the quantum random number generator 28 completed and the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) signals the finite state machine 404.8 that it may use and pass on the quantum random bits 411 and the quantum random data words 418 (quantum random numbers). The finite state machine 404.8 preferably signals this fact to one or more processors (10-1, 10-2). This has the advantage that the device only generates quantum random numbers 418 generated with full protection.

By using a time-to-pseudorandom number generator 404.3 (TPRC), it is no longer possible for an attacker to feed in a deterministic bit data stream instead of the data bit stream of the quantum random bits 411, even if an attack on the entropy source 401 is actually successful for whatever reason.

In order to prevent this, it is also useful if, for example, the quantum random number generator 28 changes this number m after the complete determination of a number m of quantum random bits 411 depending on one or more previously determined random bits.

Preferably, the finite state machine 404.8 of the quantum random number generator 28 does not output these already used quantum random bits 411 and does not use them for generating quantum random data words 418.

The logic extraction method also includes three borderline cases, which are described below.

Typically, the time-to-pseudo-random number generator 404.3 (TPRC) uses the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC) as the value of the output 410 of the time-to-pseudo-random number converter 404.3 (TPRC). If necessary, a buffer amplifier can be provided which detects the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC) and outputs it as the value of the output 410 of the time-to-pseudo-random number converter 404.3 (TPRC).

The entropy extraction 404.4 now compares two different pseudorandom numbers generated by the time-to-pseudorandom number converter 404.3 (TPRC) from the output 410 of the time-to-pseudorandom number converter 404.3, a first pseudorandom number 410.1 and a second pseudorandom number 410.2.

If the first pseudorandom number 410.1 and the second pseudorandom number 410.2 are equal, the entropy extraction 404.4 rejects one of the two pseudorandom numbers, the first pseudorandom number 410.1 or the second quantum random number 410.2, and replaces it with a new pseudorandom number 410.3 of the time-to-pseudorandom number converter 404.3 (TPRC). The entropy extraction 404.4 preferably uses a counter to count the events in which the two pseudorandom numbers, the first pseudorandom number 410.1 and the second pseudorandom number 410.2, are the same, and increases the counter by a first counter step with each such event. The entropy extraction 404.4 preferably also uses this counter to count the events in which the two pseudorandom numbers, the first pseudorandom number 410.1 and the second pseudorandom number 410.2, are not the same, and decreases the counter by a second counter step with each such event, preferably not falling below the value 0. Preferably, the second counter step size is smaller in magnitude than the first counter step size of the counter in the entropy extraction 404.4. If the value of this counter exceeds a predetermined value, the control device of the entropy extraction 404.4 assumes a defect in the time-to-pseudo-random number converter 404.3 (TPRC). Preferably, the control device of the entropy extraction 404.4 then signals a processor (10-1, 10-2) a defect in the quantum random number generator 28 or a successful attack on the quantum random number generator 28. Preferably, the entropy extraction 404.4 then no longer signals the finite state machine that a quantum random bit 411 has been successfully generated, so that the finite state machine 404.8 can no longer report successful quantum random number generation to a processor (10-1, 10-2) and no longer generates quantum random numbers 418.

If the first pseudorandom number 410.1 is smaller than the second pseudorandom number 410.2, the entropy extraction 404.4 generates a quantum random bit of a first logical value, for example a logical '1', and signals the successful generation to the finite state machine 404.8.

If the first pseudorandom number 410.1 is greater than the second pseudorandom number 410.2, the entropy extraction 404.4 generates a quantum random bit of a second logical value, for example a logical '0', which is different from the first logical value, and signals the successful generation to the finite state machine 404.8.

The finite state machine converts the successfully generated quantum random bits 411 into quantum random data words 418, each of which represents a quantum random number, and makes these available to the processors (10-1, 10-2) via a RAM or a FIFO 404.9 via the internal data bus 419. The finite state machine 404.8 preferably signals the provision of one or more quantum random numbers to one or more processors (10-1, 10-2).

One problem may be a jitter of the system clock 2106. By using a time-to-pseudo-random number generator 404.3 (TPRC), a monofrequency or otherwise systematic disturbance of the system clock 2106 is spread in the spectrum with a random spreading code, making detection difficult, if not impossible, for an attacker.

This further complicates the vulnerability of the quantum random number generator 28.

By using quantum random numbers from quantum random bits 411 for the seed value of the linear feedback shift register of the time-to-pseudo-random number converter and a quantum random number for the selection of the simple primitive feedback polynomial, the behavior of the time-to-pseudo-random number converter 404.2 (TPRC) itself is at a random level of a quantum random number. By regularly changing these values, it is made even more difficult for an attacker to influence the generated quantum random numbers.

Therefore, the proposed quantum random number generator 28 achieves all of the above-mentioned goals.

In particular, the proposal achieves the objective of providing a one-piece, micro-integrated quantum random number generator 28 that makes it possible to guarantee a high level of entropy so that it at least passes the statistical tests defined by NIST.

It is a further object of the proposal to provide a one-piece, micro-integrated quantum random number generator 28 which makes it possible to achieve a high bit rate when generating random sequences of quantum random bits 411 and/or quantum random data words 418.

It is also the object of the proposal to provide a one-piece, micro-integrated quantum random number generator 28 which, compared to the quantum random number generators of the state of the art, nik has a more compact, robust and less complex and, above all, micro-integrated and CMOS compatible structure, which allows for one-piece manufacturing and co-integration into conventional systems such as memories (such as DRAMS, SRAMS, flash memories and the like) or processors (microprocessors and/or microcontrollers and/or SoCs via a processor on the IC).

Here too, the proposal achieves the goal of providing a quantum random number generator 28 with a high degree of security against any attempt to manipulate its internal components. In particular, the use of a time-to-pseudo random number generator 1004.3 (TRNG) prevents the evaluation of successful attacks on the entropy source 401. Furthermore, the many tests enable a reliable detection of an attack on the quantum random number generator 28 and thus prevent the use of manipulated numbers as supposedly secure quantum random numbers.

Finally, the proposal also achieves the objective of providing a quantum random number generator 28 which is more economical than the generators of the known state of the art, in particular due to the ability to be co-integrated into CMOS circuits.

Figure 22

This in 22 The diagram shown represents the detection of the pulses (2201, 2202, 2203, 2204) on the voltage signal 405 of the entropy source 401. The entropy source 401 preferably comprises the one or more photon sources 54 or the one or more silicon LEDs 54 or the one or more SPAD diodes 54 and the light transmission path 44 between them. The entropy source 401 is preferably manufactured in or on the semiconductor substrate 49 and is thus preferably part of the micro-integrated circuit of the quantum random number generator 28. The output signal 405 of the entropy source 401 is typically the said voltage signal 405 of the entropy source 401. The voltage signal 405 of the entropy source 401 is preferably the signal of one or more photon detectors 55 or one or more second SPAD diodes 55 of the entropy source 401.

The voltage signal 405 shows exemplary pulses 2201, 2202, 2203, 2104 for random events of the voltage signal 405. These can be spontaneous voltage pulses of the photon detector 55 or the second SPAD diode 55 of the entropy source 401, which are not related to the activity of the photon source 54 or the silicon LED 54 or the first SPAD diode 54 of the entropy source 401. However, the pulses 2201, 2202, 2203, 2204 of the photon detector 55 or the second SPAD diode 55 of the entropy source 401 can also be based on stimulated emission, which causes the detection of a photon of the one or more photon sources 54 or the one or more silicon LEDs 54 or the one or more SPAD diodes 54 by the photon detector 55 or by the second SPAD diode 55 of the entropy source 401.

The time interval is random. However, after the reception of a photon by the photon detector 55 or by the second SPAD diode 55 of the entropy source 401, a dead time occurs during which the photon detector 55 or the second SPAD diode 55 of the entropy source 401 is no longer able to receive. If the magnitude of the voltage signal 405 of the entropy source 401 exceeds a threshold value 2105, an analog-to-digital converter (ADC, 403), here an exemplary one-bit analog-to-digital converter 403, generates

Pulse extension circuit, which is preferably part of the integral microelectronic circuit, generates a pulse with a minimum length of n clock cycles of a system clock 2106 of the quantum random number generator 28, which is preferably one of the system clock cycles of the integral microintegrated circuit, on a synchronized voltage signal 415.

In the example of 22 For example, the pulse extension circuit 2023 is designed in such a way that it goes to a first logic level for at least three subsequent clock cycles of the system clock 2106 and then falls back to the second logic level until the next event, here for example with the falling edge of the third clock pulse. Instead of three clock pulses, a to n clock pulses can be used, where a whole positive number is greater than 0.

In the example of 22 the falling edges of the pulses 2211, 2212, 2213, 2214 of the synchronized voltage signal 415 represent the synchronized signals of the entropy source 401.

With a falling edge of a first pulse 2211 of the synchronized voltage signal 415, the time-to-pseudorandom number converter (TPRC) resets a pseudorandom number generator, for example, to a predefined seed value. For example, the pseudorandom number generator of the time-to-pseudorandom number converter (TPRC) can be a feedback shift register that shifts its values by one place to the left or right depending on the design with each clock pulse of the system clock 2106 and feeds the feedback value of the feedback polynomial back into the bit that becomes free.

It is important that, starting with the starting value of the pseudorandom number generator (seed value), each clock pulse of the system clock 2106 is bijectively assigned exactly one pseudorandom number of the pseudorandom number generator from the falling edge. This means that the value of the pseudorandom number must be able to be used to determine the temporal position of the relevant clock pulse of the system clock 2106 after the falling edge of the synchronized voltage signal 415.

With the next falling edge of the second pulse 2212 synchronized voltage signal 415, a first pseudorandom number register takes over the last status of the pseudorandom number generator and the time-to-pseudorandom number converter (TPRC) preferably resets the pseudorandom number generator to the predefined seed value.

With the next falling edge of the third pulse 2213 synchronized voltage signal 415, a second pseudorandom number register takes over the last status of the pseudorandom number generator and the time-to-pseudorandom number converter (TPRC) preferably resets the pseudorandom number generator to the predefined seed value. The entropy extraction 401 compares the value in the first pseudorandom number register with the value in the second pseudorandom number register. If the first value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate a random bit with a first logical level. If the second value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate a random bit with a second logical level that is different from the first level.

With the next falling edge of the fourth pulse 2214 of the synchronized voltage signal 415, the first pseudorandom number register takes over the previous value of a second pseudorandom number register and the second pseudorandom number register instead takes over the last status of the pseudorandom number generator and the time-to-pseudorandom number converter (TPRC) preferably resets the pseudorandom number generator to the predefined seed value. The entropy extraction 401 then compares the value in the first pseudorandom number register with the value in the second pseudorandom number register. If the first value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate another new and here second quantum random bit 411 with a first logic level. If the second value in the first pseudorandom number register is greater than the second value in the second pseudorandom number register, the entropy extraction 404.4 can, for example, generate another new and here second quantum random bit 411 with a second logic level that is different from the first level.

In this way, the quantum random number generator 28 can continue this process of quantum random bit generation and thus generate a continuous stream of quantum random bits 411, albeit with phase noise.

Figure 23

23 shows an exemplary voltage converter 91 for supplying the entropy source 411 with a sufficient operating voltage of the supply voltage line V _ENT of the entropy source 411 compared to the reference potential line GND at the reference potential. The voltage converter 91 corresponds to that of the 20 . In this respect, the 23 an excerpt from the 20 , with only the most essential parts shown for clarity.

The voltage converter 91 of the 23 is only one example of several possible voltage converter designs. The voltage converter is only intended as an example to explain the possible use of DMOS transistors in a proposed quantum random number generator 28 or an integrated circuit 2, for example a microcontroller, with such a quantum random number generator 28.

The voltage converter 91 of the 23 includes a first half bridge. In the example of the 23 the reference potential line GND and the positive supply voltage line VDD supply the voltage converter to supply the entropy source 411 with a sufficient operating voltage of the supply voltage line V _ENT of the entropy source 411 relative to the reference potential line GND at the reference potential with electrical energy.

The first half bridge of the exemplary voltage converter 91 is in the example of 23 between the reference potential line GND and the positive supply voltage line VDD.

The first half bridge of the exemplary voltage converter 91 of the 23 includes the high-side transistor 2301 of the first half-bridge of the charge pump for the entropy source 411 and the low-side transistor 2302 of the first half-bridge of the charge pump for the entropy source 411.

The second high-side transistor 2303 of the charge pump for the entropy source 411 is electrically connected to the positive supply voltage line VDD.

The control device 2330 of the voltage converter 91 controls the high-side transistor 2301 of the first half-bridge via the control contact (gate) 2311 of the high-side transistor 2301 of the first half-bridge.

The control device 2330 of the voltage converter 91 controls the low-side transistor 2302 of the first half-bridge via the control contact (gate) 2312 of the low-side transistor 2302 of the first half-bridge.

The control contact (gate) 2311 of the second high-side transistor 2303 is electrically connected to the output node 2321 of the charge pump. As a result, the high-side transistor 2303 of the second half-bridge forms a MOS diode that becomes conductive when the potential of the output node 2321 of the charge pump falls below the positive potential of the positive supply voltage line VDD minus the threshold voltage of the second high-side transistor 2303. The second high-side transistor 2303 then charges the first energy storage device, here a first capacitor 2306.

The first capacitor 2306 is in the example of the 23 with its second terminal of the first capacitor 2306 electrically connected to the output node 2321 of the charge pump. The first capacitor 2306 is in the example of the 23 with its first terminal of the first capacitor 2306 electrically connected to the output node 2320 of the first half-bridge of the charge pump.

The control device 2330 of the voltage converter 91 initially blocks the high-side transistor 2301 of the first half-bridge and the low-side transistor 2302 of the first half-bridge.

A transfer transistor 2305 of the charge pump for the entropy source 411 is in the example of 23 between the output node 2321 of the charge pump and the positive supply voltage line V _EXT of the entropy source 411. In the example of the 23 the transfer transistor 2305 of the charge pump for the entropy source 411 is connected as a MOS diode. As a result, the transfer transistor 2305 forms a MOS diode that becomes conductive when the potential of the output node 2321 of the charge pump falls below the positive potential of the positive supply voltage line V _EXT of the entropy source 411 minus the threshold voltage of the transfer transistor 2305. The transfer transistor 2305 then charges the second energy storage device, here a second capacitor 2307.

The second capacitor 2307 is in the example of the 23 with its second terminal of the second capacitor 2307 electrically connected to the positive supply voltage line V _EXT of the entropy source 411. The second capacitor 2307 is in the example of the 23 with its first terminal of the second capacitor 2307 electrically connected to the reference potential line GND.

Preferably, the control device 2330 of the voltage converter 91 switches the low-side transistor 2302 of the first half-bridge on for a short time in an initialization phase.

This connects the first terminal of the first capacitor 2306 to the reference potential line GND. If the first capacitor 2306 is not charged or is charged with a reverse polarity, the second high-side transistor 2303 then charges the first capacitor 2306 to the voltage between the positive supply voltage terminal VDD and the reference potential line GND minus the threshold voltage of the second high-side transistor 2303.

In a subsequent step, the control device 2330 of the voltage converter 91 blocks the low-side transistor 2302 of the first half-bridge. This ends the charging process of the first capacitor 2306.

In a subsequent step, the control device 2330 of the voltage converter 91 switches the high-side transistor 2301 of the first half-bridge into conduction. This shifts the output potential of the output 2321 of the charge pump to a potential with a voltage that corresponds to twice the voltage between the positive supply voltage line VDD and the reference potential line GND minus the threshold voltage of the second high-side transistor 2303. The potential of the output 2321 of the charge pump is thus above the potential of the positive supply voltage line V _EXT of the entropy source 411 if the second capacitor 2307 is not charged or is only insufficiently charged or has the wrong polarity. If the voltage difference between the potential of the output 2321 of the charge pump and the potential of the supply voltage line V _EXT of the entropy source 411 is greater than the threshold voltage of the transfer transistor 2305, the transfer transistor 2305 switches on and connects the output 2321 of the charge pump to the supply voltage line V _EXT of the entropy source 411. As a result, charge passes from the first capacitor 2306 to the second capacitor 2307, which increases the potential of the supply voltage line V _EXT of the entropy source 411 until the voltage drops across the first capacitor 2306 and the second capacitor 2307 have equalized.

The control device 2330 of the voltage converter 91 repeats these steps until no more charge transfer takes place.

If necessary, the processor 10-1 or the voltage monitor 413 can determine this state of no longer occurring charge transfer, for example by means of an analog-to-digital converter or a comparator, and then interrupt the charging process, for example by signaling the control device 2330 of the voltage converter 91, until they determine that the potential of the supply voltage line V _EXT of the entropy source 411 falls below a minimum potential. If this is the case, the processor 10-1 or the voltage monitor 413 preferably restart the charge pump of the voltage converter 91 by means of another signaling to the control device 2330 of the voltage converter 91 and keep it in operation until no significant charge transfer takes place again.

If the processor 10-1 or the voltage monitor 413 does not detect this state of essentially no longer occurring charge transfer within a predefined period of time after the charge transfer has been restarted, then a defect or a malfunction or an attack is probably present. Preferably, the processor 10-1 and/or the voltage monitor 413 signal this error. For example, the voltage monitor 413 can signal such an error to the watchdog 404.5 via a signal line 414.

The voltage converter 91 and the second capacitor 2307 can thus supply the entropy source 411 with a sufficient operating voltage on the supply voltage line V _EXT of the entropy source 411.

The first capacitor 2306 and/or the second capacitor 2307 can be manufactured externally of the integrated circuit 2, for example the microcontroller, and connected via terminals of the housing of the integrated circuit 2, for example the microcontroller. This enables very high capacitance values for the first capacitor 2306 and/or the second capacitor 2307 in a cost-effective manner.

However, it is advantageous if the first capacitor 2306 and/or the second capacitor 2307 are silicon capacitors. In one embodiment, when the first capacitor 2306 and/or the second capacitor 2307 are integrated into the integrated circuit 2, for example into the microcontroller, the first capacitor 2306 and/or the second capacitor 2307 can each be an interconnection of trench capacitors that are manufactured in the semiconductor substrate 49 of the quantum random number generator 28. In a further additional or alternative embodiment, the first capacitor 2306 and/or the second capacitor 2307 can, when integrating the first capacitor 2306 and/or the second capacitor 2307 into the integrated circuit 2, for example into the microcontroller, each comprise, for example, an interconnection of MIM capacitors that are manufactured in the metallization stack on the semiconductor substrate 49 of the quantum random number generator 28. MIM stands for metal-insulator-metal. Preferably, an insulation layer of the metallization stack comprises a high-K material, such as hafnium oxide.

Of course, it is also conceivable to provide, for example, gate capacitances of additional transistors as device components of the first capacitor 2306 and/or the second capacitor 2307.

In the example of 23 During operation, an increased voltage is then present, at least temporarily, between gate 2313 and substrate of the second high-side transistor 2303 and between gate 2315 and substrate of the transfer transistor 2305. These transistors must therefore be particularly voltage-resistant. The second high-side transistor 2303 and/or the transfer transistor 2305 are therefore preferably each designed as a DMOS transistor. It is therefore advantageous to manufacture the integrated circuit 2, for example the microcontroller, or the monolithically integrated quantum random number generator 28 using BCD technology.

Figure 24

24 shows an example of a rough layout of an imaginary integrated circuit 2, for example a microcontroller, with a proposed quantum random generator 28 in top view.

The integrated circuit 2, for example a microcontroller, has an inner region 2405 of the integrated circuit 2 in which the essential subcircuits of the integrated circuit 2, for example the microcontroller, are located. Typically, this inner region 2405 of the integrated circuit 2, for example the microcontroller, is surrounded by a wiring region 2404 in which supply voltage lines, data bus lines and other lines are typically routed.

The wiring area 2404 and the inner area 2405 of the integrated circuit 2, for example the microcontroller, are surrounded by the pad frame 2403, which includes the connection pads (connection areas) 2402 for the electrical bond connections or other electrical connection connections.

The document presented here now proposes to use the quantum random number generator 28, as used for example in the 20 shown by way of example is to be placed entirely or at least in substantial parts in the pad frame 2403, since the gaps between the connection pads 2402 are often not filled with electronic circuit parts, but nevertheless have to be processed during production and therefore cause unnecessary costs. This placement of the quantum random number generator 28 entirely or at least in substantial parts in the pad frame 2403 therefore significantly reduces the additional costs for such a quantum random number generator 28. The document presented here proposes, very preferably, to place at least the entropy source 401 in the pad frame between two connection pads 2402. The document presented here preferably also proposes to place the analog-to-digital converter 403 in the pad frame between two connection pads 2402. The document presented here preferably also proposes to place the voltage converter 91 for the energy supply of the entropy source 401 in the pad frame between two connection pads 2402. The document presented here preferably also proposes to place the pulse extension circuit 2023 also in the pad frame between two connection pads 2402. The document presented here preferably also proposes to place other analog parts of the quantum random number generator 28 (eg the amplifier 402) also in the pad frame between two connection pads 2402.

List of reference symbols

2

integrierte Schaltkreis eines Mikrocontrollers;

3

Anschluss;

4

Steuervorrichtung. Bevorzugt handelt es sich bei der Steuervorrichtung 4 um einen mikroelektronischen Schaltkreis;

6

nichtflüchtigen Speicher, EEPROM, externer Speicher;

8

Random Access Memory, externer Speicher;

10-1

erster Prozessor 10-1;

10-2

zweiter Prozessor 10-2;

11

Verkettung 11;

12

JATG-Test-Controller 12 mit Testanschluss (TDI, TDO, TCK, TM);

14

eng gekoppelter Speicher TCM 14;

15

Startadresse 15 des Boot ROMs 16;

16

nicht flüchtiges Boot-ROM 16;

18

Hashing-Engine 18;

20

erster One-Time-Programmable-Speicher (OTP) (einmalig programmierbarer Speicher);

22

zweiter One-Time-Programmable-Speicher (OTP) (einmalig programmierbarer Speicher);

24

Schaltung 24 zur Deaktivierung von Tests, Deaktivierungsschaltung;

26

kontrolliertes System 26 (z.B. gesteuerte Anlage, Regelstrecke);

28

Quantenzufallszahlengenerator 28;

30

weiterer nicht flüchtiger Speicher 30, externer Speicher;

32

Schnittstelle 32czu einem kontrollierten System 26;

40

Beispielhafte SPAD-Diode 40 für den Einsatz als Sensorelement eines Einzelphotonendetektors;

41

Isolation, beispielsweise Shallow-Trench-Isolation STI 41 der beispielhaften SPAD-Diode 40 oder LOCOS-Isolation;

42

Anodenkontakt 42 der beispielhaften SPAD-Diode 40;

43

Kathodenkontakt 43 der beispielhaften SPAD-Diode 40. Der Kathodenkontakt 43 der beispielhaften SPAD-Diode 40 ist bevorzugt aus Indium-Zinn-Oxid (ITO) oder einem anderen transparenten und elektrisch leitendem Material gefertigt;

44

Lichtwellenleiter 44 für den Transport der Photonen der ersten SPAD-Diode 54 zur zweiten SPAD-Diode 55. Der Lichtwellenleiter 44 ist aus einem Abdeckoxid 44 oder optisch transparente Isolierschicht 44 der beispielhaften SPAD-Diode 40 gefertigt;

45

hoch dotiertes erstes Anschlussgebiet 45 eines ersten Leitungstyps, auch als n+ S/D Implantation bezeichnet. In einer CMOS-Technologie mit einem p-dotiertem Wafer-Material kann es sich beispielsweise um ein n+-dotiertes Gebiet im halbleitenden Substratmaterial der SPAD-Diode 40 handeln;

46

erste dotierte Wanne 46 eines zweiten Leitungstyps. In einer CMOS-Technologie mit einem p-dotiertem Wafer-Material kann es sich beispielsweise um ein p- --dotiertes Gebiet im halbleitenden Substratmaterial der SPAD-Diode 40 handeln;

47

zweite dotierte Wanne 47 eines zweiten Leitungstyps. In einer CMOS-Technologie mit einem p-dotiertem Wafer-Material kann es sich beispielsweise um ein p--dotiertes Gebiet im halbleitenden Substratmaterial der SPAD-Diode 40 handeln;

48

epitaktische Schicht 48 eines zweiten Leitungstyps. In einer CMOS-Technologie mit einem p-dotiertem Wafer-Material kann es sich beispielsweise um eine p-dotierte epitaktische Schicht im halbleitenden Substratmaterial der SPAD-Diode 40 handeln;

49

Basismaterial 49 und/oder Halbleitersubstrat 49 des beispielhaften halbleitenden einkristallinen Wafers bzw. Wafer-Stückes, der bevorzugt einen zweiten Leitungstyp aufweist. In einer CMOS-Technologie mit einem p-dotiertem Wafer-Material handelt es sich beispielsweise um einen p-dotierten einkristallinen Halbleiter-Wafer bzw. ein einen p-dotiertes einkristallines Halbleiter-Wafer-Stück (Die);

50

zweite dotierte Wanne eines zweiten Leitungstyps unterhalb des Anodenkontakts. In einer CMOS-Technologie mit einem p-dotiertem Wafer-Material kann es sich beispielsweise um ein p--dotiertes Gebiet im halbleitenden Substratmaterial der SPAD-Diode 40 handeln;

51

hoch dotiertes zweites Anschlussgebiet eines zweiten Leitungstyps, auch als p+ S/D Implantation bezeichnet. In einer CMOS-Technologie mit einem p-dotiertem Wafer-Material kann es sich beispielsweise um ein p+-dotiertes Gebiet im halbleitenden Substratmaterial der SPAD-Diode 40 handeln;

52

Isolation, beispielsweise ein Oxid oder dergleichen;

53

Metallabdeckung des Lichtwellenleiters 44;

54

Erste SPAD-Diode. Die erste SPAD-Diode 55 dient zumindest zeitweise als Lichtquelle für die Bestrahlung der zweiten SPAD-Diode 45 mit Photonen der ersten SPAD-Diode 54;

55

Zweite SPAD-Diode 55. Die zweite SPAD-Diode 55 dient beispielsweise zumindest zeitweise als Fotodetektor für das Licht der ersten SPAD-Diode 54.

56

Oberfläche 56 des Wafers im Sinne der hier vorgelegten Schrift;

57

vertikal nach oben in senkrechter Richtung zur Oberfläche 56 emittiertes Licht 57 der ersten SPAD-Diode 54;

58

horizontal im Lichtwellenleiter 44 transportiertes Licht 58, das ein Teil des vertikal von der ersten SPAD-Diode 54 in den Lichtwellenleiter 44 eingestrahlten Lichts 57 ist;

59

vertikal nach unten in senkrechter Richtung zur Oberfläche 56 aus dem Lichtwellenleiter 44 in die zweite SPAD-Diode 55 eingestrahltes Licht 59 der ersten SPAD-Diode 54, das von der ersten SPAD-Diode 54 als senkrechtes Licht 57 in den Lichtwellenleiter 44 hinein emittiert wurde und dann vom Lichtwellenleiter 44 horizontal zur zweiten SPAD-Diode 55 transportiert wurde;

61

Datensätze;

62

digitale Signatur;

63

Schnittstelle;

64

Datenbusschnittstelle;

65

externer Datenbus. Der externe Datenbus kann im Sinne der hier vorgelegten Schrift eine drahtgebundene Datenverbindung oder eine drahtlose Datenverbindung sein;

81

Schnittstelle 81;

82

Bus-Arbiter 82;

83

Reset-Schaltung 83;

84

analoge Eingangsverarbeitung 84;

85

Analog-zu-Digital-Wandler 85;

86

digitale Signalverarbeitung 86;

87

Digital-zu-Analog-Wandler 87

88

analoge Ausgangsverarbeitung 88;

89

ein oder mehrere externe analoge Signale 89;

90

analoge Ausgangssignale 90;

91

Spannungswandler 91;

92

Taktgenerator 92. Der Taktgenerator 92 erzeugt vorzugsweise den Systemtakt 2106. Vorzugsweise überwacht der Watchdog 404.5 den Systemtakt 2106 auf zu niedrige oder zu hohe Geschwindigkeit und auf Clock-Jitter. Sofern der Systemtakt 2106 des Taktgenerators 92 einen Clock-Jitter zeigt, meldet der Watchdog 404.5 einen Fehler an den Prozessor 10-1 über den Datenbus 419 oder über die Interrupt-Leitung 420;

140

Kontakt;

141

Metall 1 Leitungen;

142

Metall 2 Leitungen / Metall 2 Deckel;

241

Gatter

242

Gatter

301

Schnittstelle

401

Entropie-Quelle 401;

402

Hochfrequenzverstärker 402;

403

Analog-Digital-Converter (ADC) 403;

404

Auswerteschaltung 404;

404.1

Konstante 404.1;

404.2

Komparator 404.2;

404.3

Zeit-zu-Pseudozufallszahlen-Wandler 404.3 (TPRC);

404.4

Entropie-Extraktions-Vorrichtung 404.4;

404.5

Watchdog 404.5;

404.6

optionales, weiteres, linear rückgekoppeltes Schieberegister. Die Rückkopplung ist bevorzugt ein einfach primitives Polynom, um Pseudozufallsbittfolgen zu erzeugen;

404.7

Signal-Multiplexer;

404.8

Finite State Machine (endlichen Automaten);

404.9

RAM oder FIFO;

404.10

Finish Flag;

404.11

Prozessor 10-1, 10-2;

405

Spannungssignal der Entropie Quelle 401;

406

Verstärkerausgangssignal 406 des Hochfrequenzverstärkers 402;

407

Ausgangssignal 407 des Analog-zu-Digital-Wandlers 403. des digitaler Bit Wert 407 des Analog-zu-Digital-Wandlers 403. Andere Bitbreiten als 1 Bit sind denkbar;

408

Signal der Konstanten 404.1;

409

Ausgangssignal 409 des Komparators 404.2;

410

Ausgang 410 des Zeit-zu-Pseudozufallszahlen-Wandler 404.3 (TPRC);

411

Ausgang der Entropie Extraktion 404.4;

412

Seed S;

413

Spannungsmonitor;

414

Signalleitungen;

415

einsynchronisiertes Spannungssignal 415. Das einsynchronisierte Spannungssignal 415 erzeugt die Pulsverlängerungsschaltung 2023 (MF) aus dem Ausgangsignal 407 des Analog-zu-Digital-Wandlers 403 in Abhängigkeit vom Systemtakt 2106;

416

Selektionssignal;

417

Pseudozufallssignalleitung;

418

Quantenzufallsdatenwörter;

419

interner Datenbus 419 des Quantenzufallszahlengenerators 28. Bevorzugt handelt es sich um den internen Datenbus der Steuervorrichtung 4;

420

Interrupt Signal 420 des Watchdogs 404.5 des Quantenzufallszahlengenerators 28 bzw. der Steuervorrichtung 4;

500

Flussdiagramm 500 des Entropie Extraktionsverfahrens;

501

erster Schritt 501 mit Ermittlung des ersten Werts des Ausgangs 410 des Zeit-zu-Pseudozufallszahlen-Wandlers 404.3 und des zweiten Werts des Ausgangs 410 des Zeit-zu- Pseudozufallszahlen -Wandlers 404.3 und Speicherung in einem Schieberegister der Entropie Extraktion 404.4;

502

zweiter Schritt des Vergleichens des ersten Werts mit dem zweiten Wert;

503

dritter Schritt der Bewertung des ersten Werts und des zweiten Werts und der Erzeugung des Quantenzufallsbits 411;

601

erste Spikes;

602

zweite Spikes;

603

Schneidepegel;

Bezugszeichen von 1001 bis 2999

2021

überwachte interne Spannungen 2021;

2022

Leitung 2022 zur Verhinderung der Nutzung eines Quantenzufallsbits 411 durch die Finite State Maschine (endlicher Automat) 404.8;

2023

Pulsverlängerungsschaltung 2023, typischerweise in Form eines Monoflops MF. Das Monoflop MF verlängert einen Puls auf der Leitung des digitalen Bit Wert 407 des Analog-zu-Digital-Wandlers 403 auf eine Zeitliche Länge von mindestens einer Taktperiode des Systemtakts 2106;

2101

Schieberegisterbus 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC);

2102

Rückkoppelmultiplexer 2102 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC);

2103

Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC). Der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) stellt beispielsweise auf Veranlassung eines Prozessors (10-1, 10-2) über den internen Datenbus 419 mittels eines Parallel zur seriell Schieberegistermodus-Umschaltleitung 2107 die n Schieberegisterbits (SB₁ bis SB_n) vom seriellen Schieberegisterbetriebsmodus auf den parallelen Schieberegisterbetriebsmodus um, sodass die Schieberegisterbits (SB₁ bis SB_n) des Schieberegisters den aktuellen logischen Wert des TPRG-Datenbus 2110 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als Startwert (Seed) des linear rückgekoppelten Schieberegisters verwenden. Der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) aktiviert beispielsweise auf Veranlassung eines Prozessors (10-1, 10-2) über den internen Datenbus 419 mittels einer mittels eines Parallel zur seriell Schieberegistermodus-Umschaltleitung 2107 die n Schieberegisterbits (SB₁ bis SB_n) vom seriellen Schieberegisterbetriebsmodus auf den seriellen Schieberegisterbetriebsmodus um, sodass das erste Schieberegisterbit SB₁ der n Schieberegisterbits (SB₁ bis SB_n) den aktuellen logischen Wert der Schieberegisternachladewertleitung 2104 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) mit dem nächsten Takt des Systemtakts 2106 übernimmt und die anderen Schieberegisterbits SB_j der Schieberegisterbits (SB₁ bis SB_n) des Schieberegisters den jeweiligen logischen Wert ihres Vorgänger-Schieberegisterbits SB_(j-1) mit dem nächsten Takt des Systemtakts 2106 übernehmen. Einer oder mehrere Prozessoren (10-1, 10-2) können über den internen Datenbus 419 ein oder mehrere Register des Schieberegistercontrollers 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) schreiben und/oder lesen. Bevorzugt können die Prozessoren (10-1, 10-2) über den internen Datenbus 419 ein oder mehrere Register des Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) beschreiben und so den logischen Wert des TPRG-Datenbusses 2110 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) bestimmen, den das Schieberegister als nächsten Seed-Wert benutzt. Diese Funktion kann ggf. durch einen Zugriffscode im OPT II Speicher 22 mittels der Deaktivierungsschaltung 24 blockiert sein. Vorzugsweise erzeugt jedoch der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) aus dem Datenstrom der Quantenzufallsbits 411 in einem speziellen internen Register des Schieberegistercontrollers 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) den logischen Wert des TPRG-Datenbusses 2110 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), den das Schieberegister als nächsten Seed-Wert benutzt. Dies hat den Vorteil, dass das Verhalten der Schaltung dann von einem Quantenprozess abhängt und damit nicht vorhersagbar ist. Sofern die Detektionsschaltung 2113 einen illegalen Wert des Zustandsvektors der n Schieberegisterbits SB₁ bis SB_n detektiert, meldet sie dieses an den Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), der daraufhin Maßnahmen ergreift. Eine solche typische Maßnahme ist das Rücksetzen des Zustandsvektors der n Schieberegisterbits SB₁ bis SB_n auf einen vorbestimmten Wert, beispielsweise den Seed-Wert des aktuellen Werts des TPRG-Datenbusses 2110 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) oder einen anderen vordefinierten Wert. Der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) aktiviert oder deaktiviert vorzugsweise über den Schieberegisterbitaktivierungsbus 2109 die Datenübernahme der n Schieberegisterbits (SB₁ bis SB_n) bei der nächsten Taktflanke der verwendeten Taktflankenrichtung typischerweise bitselektiv. Vorzugsweise erzeugt jedoch der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) aus dem Datenstrom der Quantenzufallsbits 411 in einem speziellen internen Register des Schieberegistercontrollers 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) den logischen Nachladewert des Rückkoppelpolynom-Auswahlregisters 2112 und lädt diesen Nachladewert in das Rückkoppelpolynom-Auswahlregisters 2112. Mittels einer Leitung 2022 zur Verhinderung der Nutzung eines Quantenzufallsbits 411 durch die Finite State Maschine (endlicher Automat) 404.8 verhindert der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) vorzugsweise, dass Finite State Maschine (endlicher Automat) 404.8 solche Quantenbits 411 nutzt, die der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) bereits benutzt hat;

2104

Schieberegisternachladewertleitung 2104 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), die den nächsten seriellen Nachladewert für das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) bei Auswahl eines Rückkoppelnetzwerks der m Rückkoppelnetzwerke (RKN₁ bis RKN_m) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) durch den Rückkoppelmultiplexer 2102 und bei Einstellung des seriellen Schiebemodus durch den Schieberegister-Controller 2103 als n auswählt, das mit dem nächsten Takt des Systemtakts 2106 in das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) geladen wird;

2105

Schwellwert 2105;

2106

Systemtakt 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28;

2107

Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, die die n Schieberegisterbits (SB₁ bis SB_n) vom seriellen Schieberegisterbetriebsmodus auf den parallelen Schieberegisterbetriebsmodus in Abhängigkeit von ihrem logischen Wert umstellen kann;

2109

Schieberegisterbitaktivierungsbus 2109 mit typischerweise n Schieberegisterbitaktivierungsleitungen der jeweils zugehörigen n Schieberegisterbits (SB₁ bis SB_n) zur jeweiligen, vorzugsweise bitselektiven Aktivierung der Datenübernahme der n Schieberegisterbits (SB₁ bis SB_n) bei der nächsten Taktflanke der verwendeten Taktflankenrichtung, wobei die jeweilige Datenquelle der Datenübernahme durch das jeweilige Schieberegisterbit der jeweils zugehörigen n Schieberegisterbits (SB₁ bis SB_n) durch eine oder mehrere Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitungen 2107 des Schieberegistercontrollers 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) festgelegt wird;

2110

TPRG-Datenbus 2110 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), der typischer weise je Schieberegisterbit der Schieberegisterbits (SB1 bis SB_n) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) jeweils bevorzugt eine Datenleitung umfasst, deren logischer Inhalt ein Bit des TPRG-Datenbusses 2110 darstellt. Diese Bits des TPRG-Datenbus 2110 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) bilden typischerweise den Startwert (Seed) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), den der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) auf Befehl eines Prozessors (10-1, 10-2) über den internen Datenbus 1901 in die Schieberegisterzellen der Schieberegisterbits (SB1 bis SB_n) lädt;

2111

Steuerregister 2111 des Rückkoppelmultiplexers 2102 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC). Vorzugsweise lädt der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) das Steuerregister 2111 des Rückkoppelmultiplexers 2102 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) und wählt dadurch das Rückkoppelpolynom durch Auswahl des aktuellen Rückkoppelnetzwerkes der Rückkoppelnetzwerke (RKN₁ bis RKN_m) aus. Vorzugsweise ändert der Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) den Wert des Steuerregisters 2111 des Rückkoppelmultiplexers 2102 nur dann, wenn ein Quantenzufallsbit 411 erfolgreich erzeugt wurde oder wenn Schieberegistercontroller 2103 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) mindestens einen Startpuls für den

2112

Rückkoppelpolynom-Auswahlregister 2112;

2113

Detektionsschaltung 2113 zur Detektion eines illegalen Werts des Zustandsvektors der n Schieberegisterbits SB₁ bis SB_n;

2201

erster beispielhafter Puls 2201 der Entropie Quelle 401 auf dem Spannungssignal 405 der Entropie Quelle 401;

2202

zweiter beispielhafter Puls 2202 der Entropie Quelle 401 auf dem Spannungssignal 405 der Entropie Quelle 401;

2203

dritter beispielhafter Puls 2203 der Entropie Quelle 401 auf dem Spannungssignal 405 der Entropie Quelle 401;

2204

vierter beispielhafter Puls 2204 der Entropie Quelle 401 auf dem Spannungssignal 405 der Entropie Quelle 401;

2211

erster beispielhafter Puls des einsynchronisierten Spannungssignals 415, der aus dem ersten beispielhaften Puls 2201 der Entropie Quelle 401 erzeugt wurde;

2212

zweiter beispielhafter Puls des einsynchronisierten Spannungssignals 415, der aus dem zweiten beispielhaften Puls 2202 der Entropie Quelle 401 erzeugt wurde;

2213

dritter beispielhafter Puls des einsynchronisierten Spannungssignals 415, der aus dem dritten beispielhaften Puls 2203 der Entropie Quelle 401 erzeugt wurde;

2214

vierter beispielhafter Puls des einsynchronisierten Spannungssignals 415, der aus dem vierten beispielhaften Puls 2204 der Entropie Quelle 401 erzeugt wurde;

2301

High-Side-Transistor 2301 der ersten Halbbrücke der Ladungspumpe für die Entropiequelle 411;

2302

Low-Side-Transistor 2302 der ersten Halbbrücke der Ladungspumpe für die Entropiequelle 411;

2303

zweiter High-Side-Transistor 2303 der zweiten Halbbrücke der Ladungspumpe für die Entropiequelle 411. In dem Beispiel der 23 ist der zweite High-Side-Transistor 2301 der Ladungspumpe für die Entropiequelle 411 als MOS-Diode verschaltet;

2305

Transfer-Transistor 2305 der Ladungspumpe für die Entropiequelle 411. In dem Beispiel der 23 ist der Transfer-Transistor 2305 der Ladungspumpe für die Entropiequelle 411 als MOS-Diode verschaltet;

2306

erster Energiespeicher, hier in dem Beispiel der 23 ein erster Kondensator 2306;

2307

zweiter Energiespeicher, hier in dem Beispiel der 23 ein zweiter Kondensator 2307;

2311

Steuerkontakt (Gate) 2311 des High-Side-Transistors 2301 der ersten Halbbrücke der Ladungspumpe für die Entropiequelle 411;

2312

Steuerkontakt (Gate) 2311 des Low-Side-Transistors 2302 der ersten Halbbrücke der Ladungspumpe für die Entropiequelle 411;

2313

Steuerkontakt (Gate) 2311 des zweiten High-Side-Transistors 2303 der Ladungspumpe für die Entropiequelle 411;

2320

Ausgangsknoten 2320 der ersten Halbbrücke der Ladungspumpe für die Entropiequelle 411;

2321

Ausgangsknoten 2321 der Ladungspumpe für die Entropiequelle 411;

2330

Steuervorrichtung 2330 des Spannungswandlers 91 zur Versorgung der Entropiequelle 411 mit einer ausreichenden Betriebsspannung der Versorgungsspannungsleitung V_ENT der Entropiequelle 411 gegenüber der Bezugspotenzialleitung GND auf dem Bezugspotenzial.

2401

beispielhaftes imaginäres Halbleiter-Die 2401 des integrierten Schaltkreises 2, beispielsweise des Mikrocontrollers, zur Erläuterung der optimalen Platzierung eines Quantenzufallszahlengenerators in einem beispielhaften Layout eines mikrointegrierten Schaltkreises 2;

2402

Anschluss-Pads (Anschlussfläche) einer Leitung des mikrointegrierten Schaltkreises 2;

2403

Pad-Rahmen des mikrointegrierten Schaltkreises 2;

2404

Verdrahtungsbereich des mikrointegrierten Schaltkreises 2;

2405

innerer Bereich des mikrointegrierten Schaltkreises 2;

Bezugszeichen von 3000 bis 3999

3000

Erzeugung eines Socket-Descriptors;

3010

Binden des Socket-Descriptors an einen Port und eine IP-Adresse;

3020

passiver Wartezustand und Warten auf Verbindungsanfragen einer integrierten Schaltung 2, beispielsweise eines Mikrocontrollers, eines Clients;

3030

Herstellen einer Verbindung vom ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers zum ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers;

3040

Erzeugen einer Quantenzufallszahl 411 und Erzeugung eines öffentlichen und eines privaten Schlüssels mittels eines RSA-Verfahrens durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers mittels eines Quantenzufallszahlengenerators 28 QRNG und eines RSA-Verfahrens.

3050

Warten auf eine verschlüsselte Nachricht des ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) Clients durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers;

3060

Entschlüsseln der Nachricht des mittels des in einem Speicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) zwischengespeicherten privaten Schlüssels aus dem Schritt 3040 gemäß des RSA-Verfahrens

3070

Verschlüsselung der Nachricht des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers mittels des öffentlichen Schlüssels des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients aus Schritt 3040 gemäß des RSA-Verfahrens durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers;

3080

Senden der im Zwischenspeicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers gespeicherten, verschlüsselten Nachricht an den erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Client über die Datenbusschnittstelle 64 des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers und über den Datenbus 65 und über die Datenschnittstelle 64 des ersten Prozessors 10-1 des Rechners durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers;

3090

Ausführen der Funktion close() und Schließen der offenen Verbindung zu einem Socket, hier dem Socket des Clients, und Beenden der Kommunikation mit dem Client durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers;

3100

Erzeugen eines Socket-Descriptors durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients und stellen einer Verbindungsanfrage an den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers unter Benutzung des Ports und der IP-Adresse, welche in dem Schritt 3010 festgelegt wurden, durch den Der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3110

Herstellen einer Verbindung zwischen dem Server-Socket aus dem Schritt 3010 und dem Client-Socket aus dem Schritt 3100;

3120

Erzeugen einer Quantenzufallszahl basierend auf Quantenzufallsbits 411 und Erzeugung eines öffentlichen und eines privaten Schlüssels mittels eines RSA-Verfahrens durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients mittels eines Quantenzufallszahlengenerators 28 QRNG und eines RSA-Verfahrens.

3130

Verschlüsseln der eigenen Nachricht des Clients mittels des öffentlichen Schlüssels des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers aus Schritt 3040 mittels des RSA-Verfahrens durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3140

Senden der verschlüsselten Nachricht des Clients an den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3150

Warten auf eine verschlüsselte Nachricht des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients und Empfangen einer Nachricht des ersten Prozessors 10-1 des Servers den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients und Speichern der so empfangenen und typischerweise verschlüsselten Nachricht des ersten Prozessors 10-1 des Servers in einem temporären Zwischenspeicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients und Lesen der ankommende Daten des ersten Prozessors 10-1 des Servers durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients mittels Ausführen der Funktion recv() von einem Socket-Discriptor, in diesem Fall von dem Socket-Descriptor des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients aus dem Schritt 3100 und speichern die gelesenen Daten vorzugsweise in einen temporären Zwischenspeicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3160

Entschlüsseln einer durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients empfangenen, verschlüsselten Nachricht des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients mittels der Ausführung der Funktion Decrypt() durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients unter Verwendung des privaten Schlüssels des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients aus dem Schritt 3120 mittels des RSA-Verfahrens und anschließendes Speichern der so entschlüsselten Nachricht in einen temporären Zwischenspeicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3170

Schließen der offenen Verbindung zu dem Socket durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients und Beenden der Kommunikation mit dem erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3200

Erzeugung zweier verschiedener Primzahlen p und q und des Produkts n=p*q und des Ergebnisses der Eulerschen Phi-Funktion phi = (p-1)(q-1) durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers mittels der Funktion KeyExchangeServer();

3210

Erzeugung einer zu phi teilerfremden Zahl e mittels Aufruf der Funktion setE() durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers, wobei die Zahl phi diejenige aus dem Schritt 3200 ist und wobei teilerfremd in Sinne des vorliegenden Dokuments bedeutet, dass es keine natürliche Zahl außer der Zahl eins gibt, die gleichzeitig die Zahl e und die Zahl phi gleichzeitig ganzzahlig teilt;

3220

Berechnung des multiplikativen Inversen zur Zahl e mittels des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers unter Verwendung der Funktion findD(), sodass gilt (e*d)mod phi = 1;

3230

Warten auf eine eintreffende Nachricht des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients, die typischerweise den öffentlichen Schlüssel des Clients umfassen sollte, durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers und Lesen der ankommenden Daten von einem Socket-Discriptor, in diesem Fall der Socket-Descriptor des Client durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers und Speichern die gelesenen Daten vorzugsweise in einen temporären Zwischenspeicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers;

3240

Versenden des öffentlichen Schlüssel (d,n) des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers aus den Schritten 3200 und 3220 durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers an den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients über einen Socket-Descriptor, in diesem Fall der Socket-Descriptor des Clients aus dem Schritt 3030;

3245

Verlassen der Funktion KeyExchangeServer() durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers;

3250

Erzeugen der Primzahl p und Erzeugen der von q verschiedenen Primzahl q und Erzeugen des Produkts n=p*q und Erzeugen der Eulerschen Phi-Funktion phi = (p-1)(q-1) jeweils durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients mittels der Fuktion KexExchangeClient();

3260

Erzeugen eine zur Zahl phi aus dem Schritt 3250 teilerfremden ganzen Zahl e durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients mittels der Funktion setE(), wobei teilerfremd in Sinne des vorliegenden Dokuments bedeutet, dass es keine natürliche Zahl außer der Zahl eins gibt, die gleichzeitig die Zahl e und die phi restfrei teilt;

3270

Berechnen des multiplikativen Inversen zur Zahl e durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients mittels der Funktion findD(), sodass gilt (e*d)mod phi = 1;

3280

Versenden der öffentlichen Schlüssels (d,n) des ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients aus den Schritten 3250 und 3270 an den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients, wobei der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients mittels der Funktion send() Daten über einen Socket-Descriptor, in diesem Fall der Socket-Descriptor des Clients aus Schritt 3100, sendet;

3290

Warten auf eine eintreffende Nachricht des ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers mit dem öffentlichen Schlüssel des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients und lesen ankommender Daten des ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers von einem Socket-Discriptor, in diesem Fall von dem Socket-Descriptor des Clients aus Schritt 3100, durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients mittels der Funktion recv() und speichern dieser Daten in einen temporären Zwischenspeicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3295

Verlassen der Funktion KeyExchangeClient() durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3300

Erzeugen einer Zufallszahl mittels eines Quantenzufallszahlengenerators 28 QRNG durch den aufrufenden ersten Prozessor 10-1 und Ermitteln einer Primzahl in Abhängigkeit von dieser Zufallszahl durch den aufrufenden ersten Prozessor 10-1 und Abspeichern dieser Primzahl als Variable p in dem Speicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2), dessen Teil der aufrufende erste Prozessor 10-1 ist;

3110

Erzeugen einer zweiten Zufallszahl mittels eines Quantenzufallszahlengenerators 28 QRNG durch den aufrufenden ersten Prozessor 10-1 und Ermitteln einer Primzahl in Abhängigkeit von dieser Zufallszahl durch den aufrufenden ersten Prozessor 10-1 und Abspeichern dieser Primzahl als Variable q in dem Speicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2), dessen Teil der aufrufende erste Prozessor 10-1 ist;

3320

Überprüfung, ob die logische Aussage q==p gilt, durch den aufrufenden ersten Prozessor 10-1 und Wiederholen der Schritte ab dem Schritt 3310 durch den aufrufenden Prozessor 10-1, wenn diese Aussage gilt;

3330

Berechnen des Produkts n= p * q durch den aufrufenden Prozessort 10-1;

3340

Berechnen der Euler'schen Phi-Funktion phi = (q-1) * (p-1) durch den aufrufenden Prozessort 10-1;

3350

Verlassen der Funktion setPrimes() durch den aufrufenden Prozessor 10-1;

3400

Ablauf der Funktion SetE(), Beim Aufrufen der Funktion setE() im Schritt 3400 generiert der Aufrufende, in Fall des vorliegenden Dokuments der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers oder der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients, eine zufällige Zahl e für die gilt, dass sie teilerfremd zur Zahl phi ist. Teilerfremd in Sinne des vorliegenden Dokuments bedeutet, dass es keine natürliche Zahl außer der Zahl eins gibt, die gleichzeitig die Zahl e und die phi teilt. Der aufrufende Prozessor 10-1 kann die Zahl e sowohl durch eine Zufallszahl des Quantenzufallszahlengenerators 28 QRNG als auch durch einen Pseudozufallszahlengenerator PRNG als auch durch Hochiterieren einer Integer-Zahl beginnend mit 2 erzeugen. Die Erzeugung mittels des Quanten-Zufallszahlen-Generators 18 QRNG ist aber bevorzugt;

3410

Überprüfen, ob die logische Aussage gcd(e,phi) != 1 erfüllt ist, durch den aufrufenden Prozessor 10-1 und wiederholen des Schritts 3400 durch den aufrufenden Prozessor 10-1, wenn die logische Aussage erfüllt ist. Der aufrufende Prozessor 10-1 berechnet mittels dieser Funktion gcd(a,b) den größten gemeinsamen Teiler der Übergabeparameter a, b und gibt das Ergebnis an den aufrufenden Prozessor 10-1 zurück;

3420

Verlassen der Funktion setE() und Rückgabe des aktuelle Werts von e als Rückgabewert an den aufrufenden Prozessor 10-1 durch den aufrufenden Prozessor 10-1, wenn die logische Aussage gcd(e,phi) != 1 nicht erfüllt ist;

3500

Initialisieren einer Variablen d mit 0 durch den aufrufenden Prozessor 10-1, hier der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients oder der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers;

3510

Addieren der Zahl 1 zu der Zahl d durch den aufrufenden Prozessor 10-1;

3520

Überprüfen, ob die logische Aussage (e*d) (mod phi) == 1 erfüllt ist, durch den aufrufenden Prozessor 10-1 und Wiederholen der Schritte ab Schritt 3510, wenn die logische Aussage (e*d) (mod phi) == 1 nicht erfüllt ist;

3530

Verlassen der Funktion findD() durch den aufrufenden Prozessor 10-1, wenn die logische Aussage (e*d) (mod phi) == 1 erfüllt ist, und Rückgeben des aktuellen Werts von d als Rückgabewert an den aufrufenden Prozessor 10-1, in Fall des vorliegenden Dokuments den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers oder der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients;

3600

Server;

3610

Client;

3620

Versenden des auf einer ersten Quantenzufallszahl des Quantenzufallszahlgenerators 28 QRNG des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600 basierenden öffentlichen Schlüssels des Servers 3600 über einen nicht abhörsicheren Kanal an den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600;

3630

Erzeugen einer Pseudozufallszahl PZ oder einer anders erzeugten Zufallszahl durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 und Speichern der Pseudozufallszahl PZ bzw. der anders erzeugten Zufallszahl in einem Speicher des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 und Erzeugen eines ersten privaten Schlüssels des Clients 3610 und eines ersten öffentlichen Schlüssels des Clients 3610 unter Benutzung dieser Pseudozufallszahl PZ bzw. dieser anders erzeugten Zufallszahl durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 und Verschlüsselung dieses ersten öffentlichen Schlüssel des Clients 3610 mittels des öffentlichen Schlüssels des Servers 3600 durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 und Versenden des verschlüsselten ersten öffentlichen Schlüssel des Clients 3610 an den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600 durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610;

3640

Entschlüsseln der Nachricht des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 mit dem ersten privaten Schlüssel des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610, sodass der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600 über den ersten öffentlichen Schlüssel des Clients 3610 verfügt, ohne dass dieser Dritten bekannt sein kann, und Erzeugen einer weiteren, zweiten Quantenzufallszahl QZ2 durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600 mittels des Quantenzufallszahlengenerators 28 QRNG, wobei die Bitbreite dieser zweiten Quantenzufallszahl ist bevorzugt gleich der Bitbreite, der Zufallszahl PZ des Clients 3610 ist, und Verschlüsseln der zweite Quantenzufallszahl QZ2 mit dem ersten öffentlichen Schlüssel des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 zu einer verschlüsselten zweiten Quantenzufallszahl QZ2' durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600, wobei beispielsweise der erste öffentliche Schlüssel des Clients 3610 die Zufallszahl PZ des Clients sein kann und wobei in dem Fall der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600 die zweite Quantenzufallszahl QZ2 beispielsweise durch bitweise XOR-Verknüpfung der zweiten Quantenzufallszahl QZ2 mit PZ zu einer verschlüsselten zweiten Quantenzufallszahl QZ2' verschlüsseln kann, und Versendung der verschlüsselten zweite Quantenzufallszahl QZ2' an den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Client 3610 durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600.

3650

Entschlüsselung der verschlüsselten zweiten Quantenzufallszahl QZ2' unter Benutzung des ersten privaten Schlüssels des ersten Prozessors 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600 zur zweiten Quantenzufallszahl QZ2 durch den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Client 3610. Hat der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) die zweite verschlüsselte Quantenzufallszahl QZ2' durch bitweise XOR-Verknüpfung der Zufallszahl PZ mit der zweiten Quantenzufallszahl QZ2 ermittelt, so kann der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 beispielsweise durch bitweise XOR-Verknüpfung der verschlüsselten zweiten Quantenzufallszahl QZ2' mit der ihm bekannten Zufallszahl PZ zur zweiten Quantenzufallszahl QZ2 entschlüsseln. Bevorzugt nutzt der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 die ihm nun vorliegende zweite Quantenzufallszahl QZ2 als Grundlage für die Erzeugung eines zweiten privaten und eines zweiten öffentlichen Schlüssels gemäß einem asymmetrischen Verschlüsselungsverfahren. Bei dem asymmetrischen Verschlüsselungsverfahren kann es sich zum Beispiel um das RSA-Verfahren (ANHANG) handeln. Der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 verschickt nun seinen zweiten öffentlichen Schlüssel über den nicht abhörsicheren Kanal an den Server 3600. Hierbei verschlüsselt er bevorzugt diesen zweiten öffentlichen Schlüssel des Clients 3610 mit dem öffentlichen Schlüssel des Servers 3600. Der Server 3600 entschlüsselt den verschlüsselten zweiten öffentlichen Schlüssel des Clients 3610 und verwendet dann diesen zweiten öffentlichen Schlüssel des Clients für die Verschlüsselung weiterer Nachrichten an den ersten Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Client 3610. Bevorzugt erzeugt und sendet der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600 nach einer vorbestimmten Zeit oder einer nach dem Versenden einer vorbestimmten Datenmenge an den Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients 3610 einen neuen öffentlichen Schlüssel auf Basis einer neuen Quantenzufallszahl seines Quantenzufallszahlengenerators 28 QRNG verschlüsselt mit dem zweiten öffentlichen Schlüssel des Clients 3610. Bevorzugt führen dann der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Servers 3600 und der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) des Clients das zuvor beschriebene Verfahren erneut durch, sodass die Schlüssel permanent wechseln. Dies macht es auch einem Quantencomputer unmöglich, die Schlüssel zu brechen;

3700

Verfahren zur Erzeugung einer Quantenzufallszahl QZ 418 mit m Quantenzufallsbits 411;

3710

Erzeugung eines zufälligen Einzelphotonenstroms (57, 58, 59, 44) mittels einer oder mehrerer Photonenquellen 54 und/oder einer oder mehrerer Silizium-LEDs 54 und/oder einer oder mehrerer erster SPAD-Dioden (54), wobei bevorzugt die Photonenquellen 54 und/oder die Silizium-LEDs 54 und/oder die ersten SPAD-Dioden (54) einstückig in einem gemeinsamen Halbleitersubstrat 49 gefertigt sind;

3720

Übertragung des zufälligen Einzelphotonenstroms (57, 58, 59, 44) mittels des Halbleitersubstrats (49, 48) und/oder mittels eines vom Halbleitersubstrat (49, 48) verschiedenen Lichtwellenleiters 44 und/oder direkt zwischen den Bauelementen an einen oder mehrere Photonendetektoren 55 und/oder eine oder mehrere zweite SPAD-Dioden (55);

3730

Wandlung des zufälligen Einzelphotonenstroms (57, 58, 59, 44) in ein Detektionssignal in Form eines Spannungssignal 405 der Entropie Quelle 401, die bevorzugt Photonenquellen 54 und/oder einer oder mehrerer Silizium-LEDs 54 und/oder einer oder mehrerer erster SPAD-Dioden (54) und die Mittel zur Lichtübertragung, wie das Halbleitersubstrat (49, 48) und/oder den Lichtwellenleiter 44, und die Photonendetektoren 55 und/oder die die zweiten SPAD-Dioden 55 umfasst;

3740

Aufbereiten, insbesondere Verstärken und/oder Filtern und/oder Analog-zu-Digital-Wandeln, des Detektionssignals in ein aufbereitetes Detektionssignal, insbesondere einen digitalen 14 Bit-Wert 407 des Analog-zu-Digital-Wandlers 403 bzw. eines 1-Bit-Analog-zu-Digitalwandlers 403;

3750

optionales Abtrennen der durch optische Kopplungen der Emissionen einer Photonenquelle 54 und/oder einer Silizium-LED 54 und/oder einer ersten SPAD-Diode 54 einerseits und einem Photonendetektor 55 und/oder einer zweiten SPAD-Diode 55 andererseits entstandenen Pulse des aufbereiteten Detektionssignals von den durch spontane Emission entstandenen Pulsen des aufbereiteten Detektionssignals durch Vergleich des aufbereiteten Detektionssignals mit einem Schwellwert, insbesondere in einem Komparator 404.2 und Erzeugung eines entsprechenden Ausgangssignals 409, insbesondere des Komparators 404.2. Ggf. kann der Analog-zu-Digital-Wandler 403 das Ausgangssignal 409 direkt erzeugen, wenn es sich um einen 1-Bit Analog-zu-Digitalwandler 403 handelt. Insofern ist dieser Schritt 3750 optional und ist daher nur gestrichelt eingezeichnet;

3760

Ermittlung 3760 einer ersten Pseudozufallszahl in Abhängigkeit von einem ersten zeitlichen Abstand zwischen dem ersten Puls und dem zweiten Puls eines ersten Paares aus zwei aufeinander folgenden, durch optische Kopplungen der Emissionen einer Photonenquelle 54 bzw. einer Silizium-LED 54 bzw. einer ersten SPAD-Diode 54 einerseits und eines Photonendetektors 55 bzw. einer zweiten SPAD-Diode 55 andererseits entstandenen Pulse des aufbereiteten Detektionssignals, als ersten Werts des Ausgangs 410 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3;

3765

Ermittlung 3760 einer zweiten Pseudozufallszahl in Abhängigkeit von einem zweiten zeitlichen Abstand zwischen dem dritten Puls und dem vierten Puls eines ersten Paares aus zwei aufeinander folgenden, durch optische Kopplungen der Emissionen einer Photonenquelle 54 bzw. einer Silizium-LED 54 bzw. einer ersten SPAD-Diode 54 einerseits und eines Photonendetektors 55 bzw. einer zweiten SPAD-Diode 55 andererseits entstandenen Pulse des aufbereiteten Detektionssignals, als ersten Werts des Ausgangs 410 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3. Dabei kann der dritte Puls mit dem zweiten Puls (siehe Schritt 3760) identisch sein.;

3670

Ermittlung des Bit-Werts eines Quantenzufallsbits 411 durch Vergleich des Werts der ersten Pseudozufallszahl und des Werts der zweiten Pseudozufallszahl;

3680

Überprüfung 3680. In der Überprüfung 3680 überprüfen der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) und/oder eine Finite-State-Machine 404.8, ob die Anzahl n der ermittelten Quantenzufallsbits 411 noch kleiner als die gewünschte Zahl m der Zufallsbits der gewünschten Quantenzufallszahl 418 ist. Sofern dies nicht der Fall ist wiederholen der erste Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) und/oder Finite-State-Machine 404.8 die vorstehenden Schritte 3710 bis 3770. Ansonsten beenden der Prozessor 10-1 des Rechners (hier des beispielhaften mikrointegrierten Schaltkreises 2) bzw. die Finite-State-Machine 404.8 den Prozess zur Erzeugung einer Quantenzufallszahl. Ggf. stellt die Finite-State-Machine 404.8 die Quantenzufallszahl dem Prozessor 10-1 zur Verfügung und signalisiert vorzugsweise dem Prozessor 10-1 diese Verfügbarkeit, beispielsweise durch einen Interrupt oder durch das Setzen eines Flags.

Nicht numerische Bezugszeichen

GND

Bezugspotenzialleitung GND auf Bezugspotenzial;

S2

Lesen eines Ladeprogramms aus dem EEPROM 6;

S4

Überprüfung der digitalen Signatur des mittels des Boot-ROM-Codes anhand des im ersten OTP 20 gespeicherten öffentlichen Schlüssels;

S6

Lesen nachfolgender Datensätze mit Hilfe des Ladeprogramms

S8

prüfen der Signatur des neu aus dem EEPROM 6 gelesenen Datensatzes anhand eines öffentlichen Schlüssels, der in einem zuvor geladenen oder im OTP-I-Speicher 20 gespeicherten Datensatz eingebettet ist, durch den Ladecode;

S20

Lesen eines Datensatzes aus dem EEPROM 6;

S21

Speichern zumindest eines Teils der Daten des Satzes im TCM 14;

S22

Berechnen eines Hash-Werts für jedes Wort der verbleibenden Daten;

S24

Speichern des berechneten Hash-Werts im DRAM 8 an einer mit dem gespeicherten Wort verbundenen Stelle mittels einer Zusammenarbeit des Prozessors 10-1 bzw. der Prozessoren 10-1, 10-2 einerseits mit der Hash-Engine 18 andererseits;

S26

Neuberechnung des Hash-Werts, wenn ein Wort aus dem DRAM 8 gelesen wird, durch den Prozessor 10-1, 10-2 und die Hash-Engine 18;

S30

Vergleich des neu berechneten Hash-Werts mit dem entsprechenden im DRAM 8 gespeicherten Hash-Wert, mittels des Prozessors 10-1, 10-2 und der Hash-Engine 18;

S34

Überprüfen, ob die Hash-Werte eine vorbestimmte Beziehung haben, z. B. gleich sind;

S36

Unterbrechen der Verarbeitung und/oder Erzeugen einer Fehlermeldung und/oder Ignorieren von Daten/ Code, wenn sie nicht die vorgegebene Beziehung aufweisen;

S38

Verarbeitung der gelesenen Daten mittels des Prozessors bzw. der Prozessoren 10-1, 10-2, wenn die Hash-Werte eine vorbestimmte Beziehung haben, z. B. gleich sind;

RKN1

erstes Rückkoppelnetzwerk RKN₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), das typischerweise aus dem logischen Datenwort, das auf dem Schieberegisterbus 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) vorhanden ist, den logischen Rückkoppelwert erzeugt, den das erste Schieberegisterbit SB₁ 1. bei Auswahl des ersten Rückkoppelnetzwerks RKN₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) durch den Rückkoppelmultiplexer 2102 und 2. bei Einstellung des seriellen Schiebemodus durch den Schieberegister-Controller 2103 über Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 eine Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 und 3. bei Aktivierung der Schieberegisterbitaktivierungsleitung des ersten Schieberegisterbits SB₁ des Schieberegisterbitaktivierungsbusses 2109 zur Aktivierung der Datenübernahme des ersten Schieberegisterbits SB₁ bei der nächsten Taktflanke des verwendeten Taktflankenrichtungssignals als nächsten seriellen Nachladewert für das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) auswählt. Das erste Schieberegisterbit SB₁ lädt dann mit dem nächsten Takt des Systemtakts 2106 diesen nächsten seriellen Nachladewert in das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC). Bevorzugt ist das erste Rückkoppelnetzwerk RKN, des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) von den andern Rückkoppelnetzwerken des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) verschieden. Bevorzugt realisiert das erste Rückkoppelnetzwerk RKN, des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) eine logische Verknüpfung des logischen Inhalts des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) zu dem logischen Wert des Schieberegisternachladewertleitung 2104 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), der unter den obigen Bedingungen der nächste Nachladewert ist. Bevorzugt realisiert die logische Verknüpfung des ersten Rückkoppelnetzwerks RKN₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein einfach primitives Polynom;

RKN2

zweites Rückkoppelnetzwerk RKN₂ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), das typischerweise aus dem logischen Datenwort, das auf dem Schieberegisterbus 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) vorhanden ist, den logischen Rückkoppelwert erzeugt, den das erste Schieberegisterbit SB₁ 1. bei Auswahl des zweiten Rückkoppelnetzwerks RKN₂ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) durch den Rückkoppelmultiplexer 2102 und 2. bei Einstellung des seriellen Schiebemodus durch den Schieberegister-Controller 2103 über Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 eine Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 und 3. bei Aktivierung der Schieberegisterbitaktivierungsleitung des ersten Schieberegisterbits SB₁ des Schieberegisterbitaktivierungsbusses 2109 zur Aktivierung der Datenübernahme des ersten Schieberegisterbits SB₁ bei der nächsten Taktflanke des verwendeten Taktflankenrichtungssignals als nächsten seriellen Nachladewert für das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) auswählt. Das erste Schieberegisterbit SB₁ lädt dann mit dem nächsten Takt des Systemtakts 2106 diesen nächsten seriellen Nachladewert in das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC). Bevorzugt ist das zweite Rückkoppelnetzwerk RKN₂ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) von den andern Rückkoppelnetzwerken des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) verschieden. Bevorzugt realisiert das zweite Rückkoppelnetzwerk RKN₂ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) eine logische Verknüpfung des logischen Inhalts des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) zu dem logischen Wert des Schieberegisternachladewertleitung 2104 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), der unter den obigen Bedingungen der nächste Nachladewert ist. Bevorzugt realisiert die logische Verknüpfung des zweiten Rückkoppelnetzwerks RKN₂ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein einfach primitives Polynom, das von den einfachprimitiven Polynomen der logischen Verknüpfungen der anderen Rückkoppelnetzwerke des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) vorzugsweise verschieden ist;

RKN3

drittes Rückkoppelnetzwerk RKN₃ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), das typischerweise aus dem logischen Datenwort, das auf dem Schieberegisterbus 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) vorhanden ist, den logischen Rückkoppelwert erzeugt, den das erste Schieberegisterbit SB₁ 1. bei Auswahl des dritte Rückkoppelnetzwerks RKN₃ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) durch den Rückkoppelmultiplexer 2102 und 2. bei Einstellung des seriellen Schiebemodus durch den Schieberegister-Controller 2103 über Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 eine Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 und 3. bei Aktivierung der Schieberegisterbitaktivierungsleitung des ersten Schieberegisterbits SB₁ des Schieberegisterbitaktivierungsbusses 2109 zur Aktivierung der Datenübernahme des ersten Schieberegisterbits SB₁ bei der nächsten Taktflanke des verwendeten Taktflankenrichtungssignals als nächsten seriellen Nachladewert für das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) auswählt. Das erste Schieberegisterbit SB₁ lädt dann mit dem nächsten Takt des Systemtakts 2106 diesen nächsten seriellen Nachladewert in das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC). Bevorzugt ist das dritte Rückkoppelnetzwerk RKN₃ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) von den andern Rückkoppelnetzwerken des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) verschieden. Bevorzugt realisiert das dritte Rückkoppelnetzwerk RKN₃ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) eine logische Verknüpfung des logischen Inhalts des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) zu dem logischen Wert des Schieberegisternachladewertleitung 2104 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), der unter den obigen Bedingungen der nächste Nachladewert ist. Bevorzugt realisiert die logische Verknüpfung des dritten Rückkoppelnetzwerks RKN₃ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein einfach primitives Polynom, das von den einfachprimitiven Polynomen der logischen Verknüpfungen der anderen Rückkoppelnetzwerke des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) vorzugsweise verschieden ist;

RKNm

m-tes Rückkoppelnetzwerk RKN, des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), das typischerweise aus dem logischen Datenwort, das auf dem Schieberegisterbus 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) vorhanden ist, den logischen Rückkoppelwert erzeugt, den das erste Schieberegisterbit SB₁ 1. bei Auswahl des m-te Rückkoppelnetzwerks RKN_m des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) durch den Rückkoppelmultiplexer 2102 und 2. bei Einstellung des seriellen Schiebemodus durch den Schieberegister-Controller 2103 über Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 eine Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 und 3. bei Aktivierung der Schieberegisterbitaktivierungsleitung des ersten Schieberegisterbits SB₁ des Schieberegisterbitaktivierungsbusses 2109 zur Aktivierung der Datenübernahme des ersten Schieberegisterbits SB₁ bei der nächsten Taktflanke des verwendeten Taktflankenrichtungssignals als nächsten seriellen Nachladewert für das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) auswählt. Das erste Schieberegisterbit SB₁ lädt dann mit dem nächsten Takt des Systemtakts 2106 diesen nächsten seriellen Nachladewert in das erste Schieberegisterbit SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC). Bevorzugt ist das m-te Rückkoppelnetzwerk RKN_m des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) von den andern Rückkoppelnetzwerken des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) verschieden. Bevorzugt realisiert das m-te Rückkoppelnetzwerk RKN_m des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) eine logische Verknüpfung des logischen Inhalts des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) zu dem logischen Wert des Schieberegisternachladewertleitung 2104 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC), der unter den obigen Bedingungen der nächste Nachladewert ist. Bevorzugt realisiert die logische Verknüpfung des m-ten Rückkoppelnetzwerks RKN, des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein einfach primitives Polynom, das von den einfachprimitiven Polynomen der logischen Verknüpfungen der anderen Rückkoppelnetzwerke des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) vorzugsweise verschieden ist;

SB1

erste Schieberegisterzelle mit dem ersten Schieberegisterbit SB₁. Das erste Schieberegisterbit SB₁ speist bevorzugt seinen logischen Inhalt in die erste Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das erste Schieberegisterbit SB₁ beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert der Schieberegisternachladewertleitung 2104 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des ersten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist.

SB2

zweite Schieberegisterzelle mit dem zweiten Schieberegisterbit SB₂. Das zweite Schieberegisterbit SB₂ speist seinen logischen Inhalt in die zweite Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das zweite Schieberegisterbit SB₂ beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des ersten Schieberegisterbits SB₁ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des zweiten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB3

dritte Schieberegisterzelle mit dem dritten Schieberegisterbit SB₃. Das dritte Schieberegisterbit SB₃ speist seinen logischen Inhalt in die dritte Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das dritte Schieberegisterbit SB₃ beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des zweiten Schieberegisterbits SB₂ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des dritten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB4

vierte Schieberegisterzelle mit dem vierten Schieberegisterbit SB₄. Das vierte Schieberegisterbit SB₄ speist seinen logischen Inhalt in die vierte Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das vierte Schieberegisterbit SB₄ beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des dritten Schieberegisterbits SB₃ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des vierten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SBs

fünfte Schieberegisterzelle mit dem fünften Schieberegisterbit SBs. Das fünfte Schieberegisterbit SB₅ speist seinen logischen Inhalt in die fünfte Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das fünfte Schieberegisterbit SBs beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des vierten Schieberegisterbits SB₄ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des fünften Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB6

sechste Schieberegisterzelle mit dem sechsten Schieberegisterbit SB₆. Das sechste Schieberegisterbit SB₆ speist seinen logischen Inhalt in die sechste Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das sechste Schieberegisterbit SB₆ beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des fünften Schieberegisterbits SB₅ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des sechsten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB7

siebte Schieberegisterzelle mit dem siebten Schieberegisterbit SB₇. Das siebte Schieberegisterbit SB₇ speist seinen logischen Inhalt in die siebte Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das siebte Schieberegisterbit SB₇ beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des sechsten Schieberegisterbits SB₆ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des siebten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB8

achte Schieberegisterzelle mit dem achten Schieberegisterbit SB₈. Das achte Schieberegisterbit SB₈ speist seinen logischen Inhalt in die achte Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das achte Schieberegisterbit SB₈ beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des siebten Schieberegisterbits SB₇ des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des achten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB(n-6)

(n-6)-te Schieberegisterzelle mit dem (n-6)-ten Schieberegisterbit SB_(n-6). Das (n-6)-te Schieberegisterbit SB_(n-6) speist seinen logischen Inhalt in die (n-6)-te Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das (n-6)-te Schieberegisterbit SB_(n-6) beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-7)-ten Schieberegisterbits SB_(n-7) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-6)-ten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB(n-6)

(n-5)-te Schieberegisterzelle mit dem (n-5)-ten Schieberegisterbit SB_(n-5). Das (n-5)-te Schieberegisterbit SB_(n-6) speist seinen logischen Inhalt in die (n-5)-te Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das (n-5)-te Schieberegisterbit SB_(n-6) beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-6)-ten Schieberegisterbits SB_(n-7) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-5)-ten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB(n-4)

(n-4)-te Schieberegisterzelle mit dem (n-4)-ten Schieberegisterbit SB_(n-4). Das (n-4)-te Schieberegisterbit SB_(n-4) speist seinen logischen Inhalt in die (n-4)-te Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das (n-4)-te Schieberegisterbit SB_(n-6) beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-5)-ten Schieberegisterbits SB_(n-7) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-4)-ten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB(n-3)

(n-3)-te Schieberegisterzelle mit dem (n-3)-ten Schieberegisterbit SB_(n-3). Das (n-3)-te Schieberegisterbit SB_(n-3) speist seinen logischen Inhalt in die (n-3)-te Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das (n-3)-te Schieberegisterbit SB_(n-6) beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-4)-ten Schieberegisterbits SB_(n-7) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-3)-ten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB(n-2)

(n-2)-te Schieberegisterzelle mit dem (n-2)-ten Schieberegisterbit SB_(n-2). Das (n-2)-te Schieberegisterbit SB_(n-2) speist seinen logischen Inhalt in die (n-2)-te Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das (n-2)-te Schieberegisterbit SB_(n-6) beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-3)-ten Schieberegisterbits SB_(n-7) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-2)-ten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SB(n-1)

(n-1)-te Schieberegisterzelle mit dem (n-1)-ten Schieberegisterbit SB_(n-1). Das (n-1)-te Schieberegisterbit SB_(n-1) speist seinen logischen Inhalt in die (n-1)-te Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das (n-1)-te Schieberegisterbit SB_(n-6) beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-2)-ten Schieberegisterbits SB_(n-7) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-1)-ten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

SBn

n-te Schieberegisterzelle mit dem n-ten Schieberegisterbit SB_n. Das n-te Schieberegisterbit SB_n speist seinen logischen Inhalt in die n-te Schieberegisterbusleitung des Schieberegisterbusses 2101 des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) ein. In Abhängigkeit vom logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107 lädt bevorzugt das n-te Schieberegisterbit SB_(n-6) beispielsweise a) bei einem ersten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem seriellen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des (n-1)-ten Schieberegisterbits SB_(n-7) des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) als ihren nächsten logischen Wert nach und b) bei einem zweiten logischen Wert der Parallel-zu-Seriell-Schieberegistermodus-Umschaltleitung 2107, dem parallelen Schieberegisterbetriebsmodus, beispielsweise mit der nächsten steigenden Taktflanke des Systemtakts 2106 des Quantenzufallszahlengenerators 28 und des Zeit-zu-Pseudozufallszahl-Wandlers 404.3 (TPRC) des Quantenzufallszahlengenerators 28 den logischen Wert des n-ten Bits des TPRG-Datenbusses 2110 als ihren nächsten logischen Wert nach, wenn gleichzeitig die erste Schieberegisterbitaktivierungsleitung des Schieberegisterbitaktivierungsbusses 2109 aktiv (z.B. high) ist;

VDD

positive Versorgungsspannungsleitung VDD auf einem positiven elektrischen Potenzial gegenüber dem Bezugspotenzial der Bezugspotenzialleitung GND;

VENT

positive Versorgungsspannungsleitung V_EXT der Entropiequelle 411;

Numerical reference symbols Reference symbols from 0 to 1000

2

integrated circuit of a microcontroller;

3

Connection;

4

Control device. Preferably, the control device 4 is a microelectronic circuit;

6

non-volatile memory, EEPROM, external memory;

8th

Random Access Memory, external memory;

10-1

first processor 10-1;

10-2

second processor 10-2;

11

Concatenation 11;

12

JATG test controller 12 with test connection (TDI, TDO, TCK, TM);

14

tightly coupled memory TCM 14;

15

Starting address 15 of boot ROM 16;

16

non-volatile boot ROM 16;

18

Hashing engine 18;

20

first one-time programmable memory (OTP);

22

second one-time programmable memory (OTP);

24

Test disabling circuit 24, disabling circuit;

26

controlled system 26 (e.g. controlled plant, controlled system);

28

Quantum random number generator 28;

30

additional non-volatile memory 30, external memory;

32

Interface 32c to a controlled system 26;

40

Example SPAD diode 40 for use as a sensor element of a single photon detector;

41

Isolation, for example shallow trench isolation STI 41 of the exemplary SPAD diode 40 or LOCOS isolation;

42

Anode contact 42 of the exemplary SPAD diode 40;

43

Cathode contact 43 of the exemplary SPAD diode 40. The cathode contact 43 of the exemplary SPAD diode 40 is preferably made of indium tin oxide (ITO) or another transparent and electrically conductive material;

44

Optical waveguide 44 for transporting the photons from the first SPAD diode 54 to the second SPAD diode 55. The optical waveguide 44 is made from a covering oxide 44 or optically transparent insulating layer 44 of the exemplary SPAD diode 40;

45

highly doped first connection region 45 of a first conduction type, also referred to as n+ S/D implantation. In a CMOS technology with a p-doped wafer material, this can be, for example, an n+-doped region in the semiconducting substrate material of the SPAD diode 40;

46

first doped well 46 of a second conduction type. In a CMOS technology with a p-doped wafer material, this can be, for example, a p-doped region in the semiconducting substrate material of the SPAD diode 40;

47

second doped well 47 of a second conduction type. In a CMOS technology with a p-doped wafer material, this can be, for example, a p-doped region in the semiconducting substrate material of the SPAD diode 40;

48

epitaxial layer 48 of a second conduction type. In a CMOS technology with a p-doped wafer material, this can be, for example, a p-doped epitaxial layer in the semiconducting substrate material of the SPAD diode 40;

49

Base material 49 and/or semiconductor substrate 49 of the exemplary semiconducting single-crystal wafer or wafer piece, which preferably has a second conduction type. In a CMOS technology with a p-doped wafer material, this is, for example, a p-doped single-crystal semiconductor wafer or a p-doped single-crystal semiconductor wafer piece (die);

50

second doped well of a second conduction type below the anode contact. In a CMOS technology with a p-doped wafer material, this can be, for example, a p-doped region in the semiconducting substrate material of the SPAD diode 40;

51

highly doped second connection region of a second conduction type, also referred to as p+ S/D implantation. In a CMOS technology with a p-doped wafer material, this can be, for example, a p+-doped region in the semiconducting substrate material of the SPAD diode 40;

52

Insulation, for example an oxide or the like;

53

Metal cover of the optical fiber 44;

54

First SPAD diode. The first SPAD diode 55 serves at least temporarily as a light source for irradiating the second SPAD diode 45 with photons from the first SPAD diode 54;

55

Second SPAD diode 55. The second SPAD diode 55 serves, for example, at least temporarily as a photodetector for the light from the first SPAD diode 54.

56

Surface 56 of the wafer as defined in the document presented here;

57

light 57 of the first SPAD diode 54 emitted vertically upwards in a direction perpendicular to the surface 56;

58

light 58 transported horizontally in the optical waveguide 44, which is a part of the light 57 radiated vertically by the first SPAD diode 54 into the optical waveguide 44;

59

light 59 of the first SPAD diode 54 radiated vertically downwards in a direction perpendicular to the surface 56 from the optical waveguide 44 into the second SPAD diode 55, which was emitted by the first SPAD diode 54 as perpendicular light 57 into the optical waveguide 44 and then transported horizontally by the optical waveguide 44 to the second SPAD diode 55;

61

data records;

62

digital signature;

63

Interface;

64

data bus interface;

65

external data bus. The external data bus can be a wired data connection or a wireless data connection in the sense of the document presented here;

81

Interface 81;

82

Bus arbiter 82;

83

Reset circuit 83;

84

analog input processing 84;

85

Analog-to-digital converter 85;

86

digital signal processing 86;

87

Digital-to-analog converter 87

88

analog output processing 88;

89

one or more external analog signals 89;

90

analog output signals 90;

91

Voltage converter 91;

92

Clock generator 92. The clock generator 92 preferably generates the system clock 2106. Preferably, the watchdog 404.5 monitors the system clock 2106 for too low or too high speed and for clock jitter. If the system clock 2106 of the clock generator 92 shows a clock jitter, the watchdog 404.5 reports an error to the processor 10-1 via the data bus 419 or via the interrupt line 420;

140

Contact;

141

Metal 1 wires;

142

Metal 2 wires / metal 2 covers;

241

gate

242

gate

301

interface

401

Entropy Source 401;

402

High frequency amplifier 402;

403

Analog-to-digital converter (ADC) 403;

404

Evaluation circuit 404;

404.1

Constant 404.1;

404.2

Comparator 404.2;

404.3

Time-to-Pseudo-Random Number Converter 404.3 (TPRC);

404.4

Entropy Extraction Device 404.4;

404.5

Watchdog 404.5;

404.6

optional, additional, linear feedback shift register. The feedback is preferably a simple primitive polynomial to generate pseudorandom bit sequences;

404.7

signal multiplexer;

404.8

Finite State Machine;

404.9

RAM or FIFO;

404.10

finish flag;

404.11

Processor 10-1, 10-2;

405

Voltage signal of entropy source 401;

406

Amplifier output signal 406 of the high frequency amplifier 402;

407

Output signal 407 of the analog-to-digital converter 403. of the digital bit value 407 of the analog-to-digital converter 403. Bit widths other than 1 bit are conceivable;

408

Signal of constant 404.1;

409

Output signal 409 of comparator 404.2;

410

Output 410 of the time-to-pseudo-random number converter 404.3 (TPRC);

411

Entropy extraction output 404.4;

412

Seed S;

413

voltage monitor;

414

signal lines;

415

synchronized voltage signal 415. The synchronized voltage signal 415 generates the pulse extension circuit 2023 (MF) from the output signal 407 of the analog-to-digital converter 403 in dependence on the system clock 2106;

416

selection signal;

417

pseudorandom signal line;

418

quantum random data words;

419

internal data bus 419 of the quantum random number generator 28. Preferably, this is the internal data bus of the control device 4;

420

Interrupt signal 420 of the watchdog 404.5 of the quantum random number generator 28 or the control device 4;

500

Flowchart 500 of the entropy extraction process;

501

first step 501 with determination of the first value of the output 410 of the time-to-pseudo-random number converter 404.3 and the second value of the output 410 of the time-to-pseudo-random number converter 404.3 and storage in a shift register of the entropy extraction 404.4;

502

second step of comparing the first value with the second value;

503

third step of evaluating the first value and the second value and generating the quantum random bit 411;

601

first spikes;

602

second spikes;

603

cutting level;

Reference numbers from 1001 to 2999

2021

monitored internal tensions 2021;

2022

Line 2022 for preventing the use of a quantum random bit 411 by the finite state machine 404.8;

2023

Pulse extension circuit 2023, typically in the form of a monoflop MF. The monoflop MF extends a pulse on the line of the digital bit value 407 of the analog-to-digital converter 403 to a temporal length of at least one clock period of the system clock 2106;

2101

Shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC);

2102

Feedback multiplexer 2102 of the time-to-pseudorandom number converter 404.3 (TPRC);

2103

Shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC). The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) switches the n shift register bits (SB ₁ to SB _n ) from the serial shift register operating mode to the parallel shift register operating mode via the internal data bus 419 by means of a parallel to serial shift register mode switching line 2107, for example at the instigation of a processor (10-1, 10-2), so that the shift register bits (SB ₁ to SB _n ) of the shift register use the current logic value of the TPRG data bus 2110 of the time-to-pseudo-random number converter 404.3 (TPRC) as the starting value (seed) of the linear feedback shift register. The shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) activates, for example, at the instigation of a processor (10-1, 10-2) via the internal data bus 419 by means of a parallel to serial shift register mode switching line 2107, the n shift register bits (SB ₁ to SB _n ) from the serial shift register operating mode to the serial shift register operating mode, so that the first shift register bit SB ₁ of the n shift register bits (SB ₁ to SB _n ) takes over the current logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC) with the next clock of the system clock 2106 and the other shift register bits SB _j of the shift register bits (SB ₁ to SB _n ) of the shift register take over the respective logical value of their Previous shift register bits SB _(j-1) are taken over with the next clock of the system clock 2106. One or more processors (10-1, 10-2) can write and/or read one or more registers of the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) via the internal data bus 419. Preferably, the processors (10-1, 10-2) can write one or more registers of the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) via the internal data bus 419 and thus determine the logical value of the TPRG data bus 2110 of the time-to-pseudo-random number converter 404.3 (TPRC) that the shift register uses as the next seed value. This function can be blocked by an access code in the OPT II memory 22 by means of the deactivation circuit 24. Preferably, however, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) generates the logical value of the TPRG data bus 2110 of the time-to-pseudo-random number converter 404.3 (TPRC) from the data stream of the quantum random bits 411 in a special internal register of the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC), which the shift register uses as the next seed value. This has the advantage that the behavior of the circuit then depends on a quantum process and is therefore unpredictable. If the detection circuit 2113 detects an illegal value of the state vector of the n shift register bits SB ₁ to SB _n , it reports this to the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC), which then takes action. One such typical action is resetting the state vector of the n shift register bits SB ₁ to SB _n to a predetermined value, for example the seed value of the current value of the TPRG data bus 2110 of the time-to-pseudo-random number converter 404.3 (TPRC) or another predefined value. The shift register controller 2103 of the time-to-pseudorandom number converter 404.3 (TPRC) activates or deactivates, preferably via the shift register bit activation bus 2109, the data transfer of the n shift register bits (SB ₁ to SB _n ) at the next clock edge of the clock edge direction used, typically bit-selectively. Preferably, however, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) generates the logical reload value of the feedback polynomial selection register 2112 from the data stream of the quantum random bits 411 in a special internal register of the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) and loads this reload value into the feedback polynomial selection register 2112. By means of a line 2022 for preventing the use of a quantum random bit 411 by the finite state machine 404.8, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) preferably prevents the finite state machine 404.8 from using those quantum bits 411 that the Shift register controller 2103 of time-to-pseudorandom number converter 404.3 (TPRC) has already been used;

2104

Shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC), which selects the next serial reload value for the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) when one of the m feedback networks (RKN ₁ to RKN _m ) of the time-to-pseudo-random number converter 404.3 (TPRC) is selected by the feedback multiplexer 2102 and when the serial shift mode is set by the shift register controller 2103 as n, which is loaded into the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) with the next clock of the system clock 2106;

2105

Threshold 2105;

2106

System clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28;

2107

Parallel-to-serial shift register mode switching line 2107 which can switch the n shift register bits (SB ₁ to SB _n ) from the serial shift register operation mode to the parallel shift register operation mode depending on their logic value;

2109

Shift register bit activation bus 2109 with typically n shift register bit activation lines of the respectively associated n shift register bits (SB ₁ to SB _n ) for the respective, preferably bit-selective activation of the data transfer of the n shift register bits (SB ₁ to SB _n ) at the next clock edge of the clock edge direction used, wherein the respective data source of the data transfer is determined by the respective shift register bit of the respectively associated n shift register bits (SB ₁ to SB _n ) by one or more parallel-to-serial shift register mode switching lines 2107 of the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC);

2110

TPRG data bus 2110 of the time-to-pseudo-random number converter 404.3 (TPRC), which typically comprises one data line for each shift register bit of the shift register bits (SB1 to SB _n ) of the time-to-pseudo-random number converter 404.3 (TPRC), the logical content of which represents one bit of the TPRG data bus 2110. These bits of the TPRG data bus 2110 of the time-to-pseudo-random number converter 404.3 (TPRC) typically form the starting value (seed) of the time-to-pseudo-random number converter 404.3 (TPRC), which the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) loads into the shift register cells of the shift register bits (SB1 to SB _n ) via the internal data bus 1901 at the command of a processor (10-1, 10-2);

2111

Control register 2111 of the feedback multiplexer 2102 of the time-to-pseudo-random number converter 404.3 (TPRC). Preferably, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) loads the control register 2111 of the feedback multiplexer 2102 of the time-to-pseudo-random number converter 404.3 (TPRC) and thereby selects the feedback polynomial by selecting the current feedback network of the feedback networks (RKN ₁ to RKN _m ). Preferably, the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) changes the value of the control register 2111 of the feedback multiplexer 2102 only when a quantum random bit 411 has been successfully generated or when the shift register controller 2103 of the time-to-pseudo-random number converter 404.3 (TPRC) has generated at least one start pulse for the

2112

Feedback polynomial selection register 2112;

2113

Detection circuit 2113 for detecting an illegal value of the state vector of the n shift register bits SB ₁ to SB _n ;

2201

first exemplary pulse 2201 of the entropy source 401 on the voltage signal 405 of the entropy source 401;

2202

second exemplary pulse 2202 of the entropy source 401 on the voltage signal 405 of the entropy source 401;

2203

third exemplary pulse 2203 of the entropy source 401 on the voltage signal 405 of the entropy source 401;

2204

fourth exemplary pulse 2204 of the entropy source 401 on the voltage signal 405 of the entropy source 401;

2211

first exemplary pulse of the synchronized voltage signal 415 generated from the first exemplary pulse 2201 of the entropy source 401;

2212

second exemplary pulse of the synchronized voltage signal 415 generated from the second exemplary pulse 2202 of the entropy source 401;

2213

third exemplary pulse of the synchronized voltage signal 415 generated from the third exemplary pulse 2203 of the entropy source 401;

2214

fourth exemplary pulse of the synchronized voltage signal 415 generated from the fourth exemplary pulse 2204 of the entropy source 401;

2301

High-side transistor 2301 of the first half-bridge of the charge pump for the entropy source 411;

2302

Low-side transistor 2302 of the first half-bridge of the charge pump for the entropy source 411;

2303

second high-side transistor 2303 of the second half-bridge of the charge pump for the entropy source 411. In the example of 23 the second high-side transistor 2301 of the charge pump for the entropy source 411 is connected as a MOS diode;

2305

Transfer transistor 2305 of the charge pump for the entropy source 411. In the example of 23 the transfer transistor 2305 of the charge pump for the entropy source 411 is connected as a MOS diode;

2306

first energy storage, here in the example of 23 a first capacitor 2306;

2307

second energy storage, here in the example of the 23 a second capacitor 2307;

2311

Control contact (gate) 2311 of the high-side transistor 2301 of the first half-bridge of the charge pump for the entropy source 411;

2312

Control contact (gate) 2311 of the low-side transistor 2302 of the first half-bridge of the charge pump for the entropy source 411;

2313

Control contact (gate) 2311 of the second high-side transistor 2303 of the charge pump for the entropy source 411;

2320

Output node 2320 of the first half bridge of the charge pump for the entropy source 411;

2321

Output node 2321 of the charge pump for the entropy source 411;

2330

Control device 2330 of the voltage converter 91 for supplying the entropy source 411 with a sufficient operating voltage of the supply voltage line V _ENT of the entropy source 411 relative to the reference potential line GND at the reference potential.

2401

exemplary imaginary semiconductor die 2401 of the integrated circuit 2, for example the microcontroller, for explaining the optimal placement of a quantum random number generator in an exemplary layout of a microintegrated circuit 2;

2402

Connection pads (connection area) of a line of the micro-integrated circuit 2;

2403

Pad frame of the micro-integrated circuit 2;

2404

Wiring area of the micro-integrated circuit 2;

2405

inner area of the microintegrated circuit 2;

Reference numbers from 3000 to 3999

3000

Creating a socket descriptor;

3010

Binding the socket descriptor to a port and IP address;

3020

passive wait state and waiting for connection requests from an integrated circuit 2, for example a microcontroller, a client;

3030

Establishing a connection from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client through the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server;

3040

Generating a quantum random number 411 and generating a public and a private key using an RSA method by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server using a quantum random number generator 28 QRNG and an RSA method.

3050

Waiting for an encrypted message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server;

3060

Decrypting the message of the private key from step 3040 stored in a memory of the computer (here the exemplary micro-integrated circuit 2) according to the RSA method

3070

Encryption of the message of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server by means of the public key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client from step 3040 according to the RSA method by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server;

3080

Sending the encrypted message stored in the buffer of the computer (here the exemplary micro-integrated circuit 2) of the server to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client via the data bus interface 64 of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server and via the data bus 65 and via the data interface 64 of the first processor 10-1 of the computer by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server;

3090

Executing the function close() and closing the open connection to a socket, here the client's socket, and terminating communication with the client by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server;

3100

Generating a socket descriptor by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client and making a connection request to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server using the port and the IP address which were determined in step 3010 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client;

3110

Establishing a connection between the server socket from step 3010 and the client socket from step 3100;

3120

Generating a quantum random number based on quantum random bits 411 and generating a public and a private key using an RSA method by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client using a quantum random number generator 28 QRNG and an RSA method.

3130

Encrypting the client's own message using the public key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server from step 3040 using the RSA method by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client;

3140

Sending the encrypted message of the client to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client;

3150

Waiting for an encrypted message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client and receiving a message from the first processor 10-1 of the server by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client and storing the thus received and typically encrypted message from the first processor 10-1 of the server in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client and reading the incoming data from the first processor 10-1 of the server by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client by executing the function recv() from a socket descriptor, in this case from the socket descriptor of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client from step 3100 and store the read data preferably in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) of the client by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client;

3160

Decrypting an encrypted message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server received by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client by executing the function Decrypt() by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client using the private key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client from step 3120 by means of the RSA method and then storing the message decrypted in this way in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) of the client by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client. exemplary micro-integrated circuit 2) of the client;

3170

Closing the open connection to the socket by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client and terminating the communication with the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client;

3200

Generation of two different prime numbers p and q and the product n=p*q and the result of Euler's phi function phi = (p-1)(q-1) by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server by means of the function KeyExchangeServer();

3210

Generation of a number e that is coprime to phi by calling the function setE() by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server, where the number phi is the one from step 3200 and where coprime in the sense of the present document means that there is no natural number other than the number one that simultaneously divides the number e and the number phi by integers;

3220

Calculating the multiplicative inverse of the number e using the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server using the function findD(), such that (e*d)mod phi = 1;

3230

Waiting for an incoming message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client, which should typically include the client's public key, by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server and reading the incoming data from a socket descriptor, in this case the client's socket descriptor, by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server and storing the read data preferably in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server;

3240

Sending the public key (d,n) of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server from steps 3200 and 3220 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client via a socket descriptor, in this case the socket descriptor of the client from step 3030;

3245

Exiting the KeyExchangeServer() function by the first processor 10-1 of the computer (here the exemplary microintegrated circuit 2) of the server;

3250

Generating the prime number p and generating the prime number q different from q and generating the product n=p*q and generating the Euler phi function phi = (p-1)(q-1), each by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client by means of the function KexExchangeClient();

3260

Generating an integer e that is relatively prime to the number phi from step 3250 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client using the function setE(), where relatively prime in the sense of the present document means that there is no natural number other than the number one that simultaneously divides the number e and the phi without a remainder;

3270

Calculating the multiplicative inverse of the number e by the first processor 10-1 of the computer (here the exemplary microintegrated circuit 2) of the client using the function findD(), such that (e*d)mod phi = 1;

3280

Sending the public key (d,n) of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client from steps 3250 and 3270 to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client, wherein the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client sends data via a socket descriptor, in this case the socket descriptor of the client from step 3100, using the send() function;

3290

Waiting for an incoming message from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server with the public key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client and reading incoming data from the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server from a socket descriptor, in this case from the socket descriptor of the client from step 3100, by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client using the recv() function and storing this data in a temporary buffer of the computer (here the exemplary micro-integrated circuit 2) of the client by the first processor 10-1 of the Computer (here the example micro-integrated circuit 2) of the client;

3295

Exiting the KeyExchangeClient() function by the first processor 10-1 of the computer (here the exemplary microintegrated circuit 2) of the client;

3300

Generating a random number by means of a quantum random number generator 28 QRNG by the calling first processor 10-1 and determining a prime number as a function of this random number by the calling first processor 10-1 and storing this prime number as a variable p in the memory of the computer (here the exemplary microintegrated circuit 2), of which the calling first processor 10-1 is a part;

3110

Generating a second random number by means of a quantum random number generator 28 QRNG by the calling first processor 10-1 and determining a prime number as a function of this random number by the calling first processor 10-1 and storing this prime number as a variable q in the memory of the computer (here the exemplary micro-integrated circuit 2), of which the calling first processor 10-1 is a part;

3320

Checking whether the logical statement q==p holds by the calling first processor 10-1 and repeating the steps from step 3310 by the calling processor 10-1 if this statement holds;

3330

Calculating the product n= p * q by the calling processor location 10-1;

3340

Calculating Euler's phi function phi = (q-1) * (p-1) by the calling processor location 10-1;

3350

Exit of the function setPrimes() by the calling processor 10-1;

3400

Sequence of the SetE() function, When the setE() function is called in step 3400, the caller, in the case of the present document the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server or the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client, generates a random number e for which it is coprime to the number phi. Coprime in the sense of the present document means that there is no natural number other than the number one that divides the number e and phi at the same time. The calling processor 10-1 can generate the number e both by a random number from the quantum random number generator 28 QRNG and by a pseudo-random number generator PRNG and by iterating up an integer number starting with 2. However, generation by means of the quantum random number generator 18 QRNG is preferred;

3410

Checking whether the logical statement gcd(e,phi) != 1 is satisfied by the calling processor 10-1 and repeating step 3400 by the calling processor 10-1 if the logical statement is satisfied. The calling processor 10-1 calculates the greatest common divisor of the transfer parameters a, b using this function gcd(a,b) and returns the result to the calling processor 10-1;

3420

Exiting the function setE() and returning the current value of e as a return value to the calling processor 10-1 by the calling processor 10-1 if the logical statement gcd(e,phi) != 1 is not satisfied;

3500

Initializing a variable d with 0 by the calling processor 10-1, here the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client or the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server;

3510

Adding the number 1 to the number d by the calling processor 10-1;

3520

Checking whether the logical statement (e*d) (mod phi) == 1 is satisfied by the calling processor 10-1 and repeating the steps from step 3510 if the logical statement (e*d) (mod phi) == 1 is not satisfied;

3530

Exiting the function findD() by the calling processor 10-1 when the logical statement (e*d) (mod phi) == 1 is satisfied and returning the current value of d as a return value to the calling processor 10-1, in the case of the present document the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server or the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client;

3600

Server;

3610

Clients;

3620

Sending the public key of the server 3600, which is based on a first quantum random number of the quantum random number generator 28 QRNG of the computer (here the exemplary micro-integrated circuit 2) of the server 3600, via a non-tap-proof channel to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600;

3630

Generating a pseudorandom number PZ or a random number generated in another way by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 and storing the pseudorandom number PZ or the random number generated in another way in a memory of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 and generating a first private key of the client 3610 and a first public key of the client 3610 using this pseudorandom number PZ or this random number generated in another way by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 and encrypting this first public key of the client 3610 using the public key of the server 3600 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 and sending the encrypted first public key of the client 3610 to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610;

3640

Decrypting the message of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 with the first private key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610, so that the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 has the first public key of the client 3610 without this being known to third parties, and generating a further, second quantum random number QZ2 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 by means of the quantum random number generator 28 QRNG, wherein the bit width of this second quantum random number is preferably equal to the bit width of the random number PZ of the client 3610, and Encrypting the second quantum random number QZ2 with the first public key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 to form an encrypted second quantum random number QZ2' by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600, wherein, for example, the first public key of the client 3610 can be the random number PZ of the client and wherein in this case the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 can encrypt the second quantum random number QZ2, for example by bitwise XORing the second quantum random number QZ2 with PZ to form an encrypted second quantum random number QZ2', and sending the encrypted second quantum random number QZ2' to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600.

3650

Decryption of the encrypted second quantum random number QZ2' using the first private key of the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 to the second quantum random number QZ2 by the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610. If the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) has determined the second encrypted quantum random number QZ2' by bitwise XORing the random number PZ with the second quantum random number QZ2, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 can, for example, by bitwise XORing the encrypted second quantum random number QZ2' with the random number PZ known to it. to decrypt the second quantum random number QZ2. Preferably, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 uses the second quantum random number QZ2 that it now has as the basis for generating a second private key and a second public key according to an asymmetric encryption method. The asymmetric encryption method can be, for example, the RSA method (APPENDIX). The first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610 now sends its second public key to the server 3600 via the non-tap-proof channel. In doing so, it preferably encrypts this second public key of the client 3610 with the public key of the server 3600. The server 3600 decrypts the encrypted second public key of the client 3610 and then uses this second public key of the client to encrypt further messages to the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client 3610. Preferably, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 generates and sends after a predetermined time or after sending a predetermined amount of data to the processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the Clients 3610 generate a new public key based on a new quantum random number from their quantum random number generator 28 QRNG encrypted with the second public key of the client 3610. Preferably, the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the server 3600 and the first processor 10-1 of the computer (here the exemplary micro-integrated circuit 2) of the client then carry out the previously described method again so that the keys change permanently. This also makes it impossible for a quantum computer to break the keys;

3700

Method for generating a quantum random number QZ 418 with m quantum random bits 411;

3710

Generation of a random single photon stream (57, 58, 59, 44) by means of one or more photon sources 54 and/or one or more silicon LEDs 54 and/or one or more first SPAD diodes (54), wherein preferably the photon sources 54 and/or the silicon LEDs 54 and/or the first SPAD diodes (54) are manufactured in one piece in a common semiconductor substrate 49;

3720

Transmission of the random single photon stream (57, 58, 59, 44) by means of the semiconductor substrate (49, 48) and/or by means of an optical waveguide 44 different from the semiconductor substrate (49, 48) and/or directly between the components to one or more photon detectors 55 and/or one or more second SPAD diodes (55);

3730

Conversion of the random single photon stream (57, 58, 59, 44) into a detection signal in the form of a voltage signal 405 of the entropy source 401, which preferably comprises photon sources 54 and/or one or more silicon LEDs 54 and/or one or more first SPAD diodes (54) and the means for light transmission, such as the semiconductor substrate (49, 48) and/or the optical waveguide 44, and the photon detectors 55 and/or the second SPAD diodes 55;

3740

Processing, in particular amplifying and/or filtering and/or analog-to-digital converting, the detection signal into a processed detection signal, in particular a digital 14-bit value 407 of the analog-to-digital converter 403 or a 1-bit analog-to-digital converter 403;

3750

optionally separating the pulses of the conditioned detection signal generated by optical coupling of the emissions of a photon source 54 and/or a silicon LED 54 and/or a first SPAD diode 54 on the one hand and a photon detector 55 and/or a second SPAD diode 55 on the other hand from the pulses of the conditioned detection signal generated by spontaneous emission by comparing the conditioned detection signal with a threshold value, in particular in a comparator 404.2 and generating a corresponding output signal 409, in particular of the comparator 404.2. If necessary, the analog-to-digital converter 403 can generate the output signal 409 directly if it is a 1-bit analog-to-digital converter 403. In this respect, this step 3750 is optional and is therefore only shown in dashed lines;

3760

Determination 3760 of a first pseudorandom number as a function of a first time interval between the first pulse and the second pulse of a first pair of two successive pulses of the processed detection signal, which pulses are generated by optical coupling of the emissions of a photon source 54 or a silicon LED 54 or a first SPAD diode 54 on the one hand and a photon detector 55 or a second SPAD diode 55 on the other hand, as the first value of the output 410 of the time-to-pseudorandom number converter 404.3;

3765

Determination 3760 of a second pseudorandom number as a function of a second time interval between the third pulse and the fourth pulse of a first pair of two successive pulses of the processed detection signal, which pulses are generated by optical coupling of the emissions of a photon source 54 or a silicon LED 54 or a first SPAD diode 54 on the one hand and a photon detector 55 or a second SPAD diode 55 on the other hand, as the first value of the output 410 of the time-to-pseudorandom number converter 404.3. The third pulse can be identical to the second pulse (see step 3760).;

3670

Determining the bit value of a quantum random bit 411 by comparing the value of the first pseudorandom number and the value of the second pseudorandom number;

3680

Check 3680. In the check 3680, the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) and/or a finite state machine 404.8 check whether the number n of the determined quantum random bits 411 is still smaller than the desired number m of the random bits of the desired quantum random number 418. If this is not the case, the first processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) and/or finite state machine 404.8 repeat the above steps 3710 to 3770. Otherwise, the processor 10-1 of the computer (here of the exemplary micro-integrated circuit 2) or the finite state machine 404.8 terminate the process for generating a quantum random number. If necessary, the finite state machine 404.8 makes the quantum random number available to the processor 10-1 and preferably signals this availability to the processor 10-1, for example by means of an interrupt or by setting a flag.

Non-numeric reference symbols

GND

Reference potential line GND to reference potential;

S2

Reading a loading program from the EEPROM 6;

S4

Verifying the digital signature of the boot ROM code using the public key stored in the first OTP 20;

S6

Reading subsequent data records using the loader program

S8

checking the signature of the data record newly read from the EEPROM 6 using a public key embedded in a data record previously loaded or stored in the OTP-I memory 20, by the loading code;

S20

Reading a data record from the EEPROM 6;

S21

Storing at least part of the data of the set in the TCM 14;

S22

Calculating a hash value for each word of the remaining data;

S24

Storing the calculated hash value in the DRAM 8 at a location associated with the stored word by means of cooperation between the processor 10-1 or the processors 10-1, 10-2 on the one hand and the hash engine 18 on the other hand;

S26

Recalculating the hash value when a word is read from the DRAM 8 by the processor 10-1, 10-2 and the hash engine 18;

S30

Comparing the newly calculated hash value with the corresponding hash value stored in the DRAM 8, by means of the processor 10-1, 10-2 and the hash engine 18;

S34

Check whether the hash values have a predetermined relationship, e.g. are equal;

S36

Interrupting processing and/or generating an error message and/or ignoring data/code if it does not have the specified relationship;

S38

Processing the read data by the processor or processors 10-1, 10-2 if the hash values have a predetermined relationship, e.g. are equal;

RKN1

first feedback network RKN ₁ of the time-to-pseudo-random number converter 404.3 (TPRC), which typically generates the logical feedback value from the logical data word present on the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC), which the first shift register bit SB ₁ 1. when the first feedback network RKN ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) is selected by the feedback multiplexer 2102 and 2. when the serial shift mode is set by the shift register controller 2103 via parallel-to-serial shift register mode switching line 2107 a parallel-to-serial shift register mode switching line 2107 and 3. when the shift register bit activation line of the first shift register bit SB ₁ of the Shift register bit activation bus 2109 for activating the data transfer of the first shift register bit SB ₁ at the next clock edge of the clock edge direction signal used as the next serial reload value for the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC). The first shift register bit SB ₁ then loads this next serial reload value into the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) with the next clock of the system clock 2106. The first feedback network RKN of the time-to-pseudo-random number converter 404.3 (TPRC) is preferably different from the other feedback networks of the time-to-pseudo-random number converter 404.3 (TPRC). Preferably, the first feedback network RKN of the time-to-pseudo-random number converter 404.3 (TPRC) implements a logical connection of the logical content of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC) to the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC), which is the next reload value under the above conditions. Preferably, the logical connection of the first feedback network RKN ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) implements a simple primitive polynomial;

RKN2

second feedback network RKN ₂ of the time-to-pseudo-random number converter 404.3 (TPRC), which typically generates the logical feedback value from the logical data word present on the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC), which the first shift register bit SB ₁ 1. when the second feedback network RKN ₂ of the time-to-pseudo-random number converter 404.3 (TPRC) is selected by the feedback multiplexer 2102 and 2. when the serial shift mode is set by the shift register controller 2103 via parallel-to-serial shift register mode switching line 2107 a parallel-to-serial shift register mode switching line 2107 and 3. when the shift register bit activation line of the first shift register bit SB ₁ of the Shift register bit activation bus 2109 for activating the data transfer of the first shift register bit SB ₁ at the next clock edge of the clock edge direction signal used as the next serial reload value for the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC). The first shift register bit SB ₁ then loads this next serial reload value into the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) with the next clock of the system clock 2106. Preferably, the second feedback network RKN ₂ of the time-to-pseudo-random number converter 404.3 (TPRC) is different from the other feedback networks of the time-to-pseudo-random number converter 404.3 (TPRC). Preferably, the second feedback network RKN ₂ of the time-to-pseudo-random number converter 404.3 (TPRC) implements a logical connection of the logical content of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC) to the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC), which is the next reload value under the above conditions. Preferably, the logical connection of the second feedback network RKN ₂ of the time-to-pseudo-random number converter 404.3 (TPRC) implements a simple primitive polynomial, which is preferably different from the simple primitive polynomials of the logical connections of the other feedback networks of the time-to-pseudo-random number converter 404.3 (TPRC);

RKN3

third feedback network RKN ₃ of the time-to-pseudo-random number converter 404.3 (TPRC), which typically generates the logical feedback value from the logical data word present on the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC), which the first shift register bit SB ₁ 1. when the third feedback network RKN ₃ of the time-to-pseudo-random number converter 404.3 (TPRC) is selected by the feedback multiplexer 2102 and 2. when the serial shift mode is set by the shift register controller 2103 via parallel-to-serial shift register mode switching line 2107 a parallel-to-serial shift register mode switching line 2107 and 3. when the shift register bit activation line of the first shift register bit SB ₁ of the Shift register bit activation bus 2109 for activating the data transfer of the first shift register bit SB ₁ at the next clock edge of the clock edge direction signal used as the next serial reload value for the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC). The first shift register bit SB ₁ then loads this next serial reload value into the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) with the next clock of the system clock 2106. The third feedback network RKN ₃ of the time-to-pseudo-random number converter 404.3 (TPRC) is preferably different from the other feedback networks of the time-to-pseudo-random number converter 404.3 (TPRC). Preferably, the third feedback network RKN ₃ of the time-to-pseudo-random number converter 404.3 (TPRC) implements a logical connection of the logical content of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC) to the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC), which is the next reload value under the above conditions. Preferably, the logical connection of the third feedback network RKN ₃ of the time-to-pseudo-random number converter 404.3 (TPRC) implements a simple primitive polynomial, which is preferably different from the simple primitive polynomials of the logical connections of the other feedback networks of the time-to-pseudo-random number converter 404.3 (TPRC);

RKNm

m-th feedback network RKN, of the time-to-pseudo-random number converter 404.3 (TPRC), which typically generates the logical feedback value from the logical data word present on the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC), which the first shift register bit SB ₁ 1. upon selection of the m-th feedback network RKN _m of the time-to-pseudo-random number converter 404.3 (TPRC) by the feedback multiplexer 2102 and 2. upon setting of the serial shift mode by the shift register controller 2103 via parallel-to-serial shift register mode switching line 2107 a parallel-to-serial shift register mode switching line 2107 and 3. upon activation of the shift register bit activation line of the first shift register bit SB ₁ of the Shift register bit activation bus 2109 for activating the data transfer of the first shift register bit SB ₁ at the next clock edge of the clock edge direction signal used as the next serial reload value for the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC). The first shift register bit SB ₁ then loads this next serial reload value into the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) with the next clock of the system clock 2106. Preferably, the m-th feedback network RKN _m of the time-to-pseudo-random number converter 404.3 (TPRC) is different from the other feedback networks of the time-to-pseudo-random number converter 404.3 (TPRC). Preferably, the m-th feedback network RKN _m of the time-to-pseudo-random number converter 404.3 (TPRC) implements a logical connection of the logical content of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC) to the logical value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC), which is the next reload value under the above conditions. Preferably, the logical connection of the m-th feedback network RKN of the time-to-pseudo-random number converter 404.3 (TPRC) implements a simple primitive polynomial, which is preferably different from the simple primitive polynomials of the logical connections of the other feedback networks of the time-to-pseudo-random number converter 404.3 (TPRC);

SB1

first shift register cell with the first shift register bit SB ₁ . The first shift register bit SB ₁ preferably feeds its logical content into the first shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the first shift register bit SB ₁ preferably reloads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the shift register reload value line 2104 of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the first bit of the TPRG data bus 2110 as their next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (e.g. high).

SB2

second shift register cell with the second shift register bit SB ₂ . The second shift register bit SB ₂ feeds its logical content into the second shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the second shift register bit SB ₂ preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the first shift register bit SB ₁ of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the second bit of the TPRG data bus 2110 as its next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (e.g. high);

SB3

third shift register cell with the third shift register bit SB ₃ . The third shift register bit SB ₃ feeds its logical content into the third shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the third shift register bit SB ₃ preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the second shift register bit SB ₂ of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the third bit of the TPRG data bus 2110 as its next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (e.g. high);

SB4

fourth shift register cell with the fourth shift register bit SB ₄ . The fourth shift register bit SB ₄ feeds its logical content into the fourth shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the fourth shift register bit SB ₄ preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the third shift register bit SB ₃ of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the fourth bit of the TPRG data bus 2110 as its next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (e.g. high);

SBs

fifth shift register cell with the fifth shift register bit SBs. The fifth shift register bit SB ₅ feeds its logical content into the fifth shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the fifth shift register bit SBs preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the fourth shift register bit SB ₄ of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the fifth bit of the TPRG data bus 2110 as its next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (e.g. high);

SB6

sixth shift register cell with the sixth shift register bit SB ₆ . The sixth shift register bit SB ₆ feeds its logical content into the sixth shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logical value of the parallel-to-serial shift register mode switching line 2107, the sixth shift register bit SB ₆ preferably loads, for example a) at a first logical value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logical value of the fifth shift register bit SB ₅ of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logical value and b) at a second logical value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logical value of the sixth bit of the TPRG data bus 2110 as its next logical value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (eg high);

SB7

seventh shift register cell with the seventh shift register bit SB ₇ . The seventh shift register bit SB ₇ feeds its logical content into the seventh shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the seventh shift register bit SB ₇ preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the sixth shift register bit SB ₆ of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the seventh bit of the TPRG data bus 2110 as their next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (e.g. high);

SB8

eighth shift register cell with the eighth shift register bit SB ₈ . The eighth shift register bit SB ₈ feeds its logical content into the eighth shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logical value of the parallel-to-serial shift register mode switching line 2107, the eighth shift register bit SB ₈ preferably loads, for example a) at a first logical value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logical value of the seventh shift register bit SB ₇ of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logical value and b) at a second logical value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logical value of the eighth bit of the TPRG data bus 2110 as its next logical value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (eg high);

SB(n-6)

(n-6)-th shift register cell with the (n-6)-th shift register bit SB _(n-6) . The (n-6)-th shift register bit SB _(n-6) feeds its logical content into the (n-6)-th shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the (n-6)th shift register bit SB _(n-6) preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-7)th shift register bit SB _(n-7) of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel Shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-6)-th bit of the TPRG data bus 2110 as their next logic value if at the same time the first shift register bit enable line of the shift register bit enable bus 2109 is active (eg high);

SB(n-6)

(n-5)th shift register cell with the (n-5)th shift register bit SB _(n-5) . The (n-5)th shift register bit SB _(n-6) feeds its logical content into the (n-5)th shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the (n-5)th shift register bit SB _(n-6) preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-6)th shift register bit SB _(n-7) of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel Shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-5)th bit of the TPRG data bus 2110 as their next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (eg high);

SB(n-4)

(n-4)th shift register cell with the (n-4)th shift register bit SB _(n-4) . The (n-4)th shift register bit SB _(n-4) feeds its logical content into the (n-4)th shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the (n-4)th shift register bit SB _(n-6) preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-5)th shift register bit SB _(n-7) of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel Shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-4)th bit of the TPRG data bus 2110 as their next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (eg high);

SB(n-3)

(n-3)th shift register cell with the (n-3)th shift register bit SB _(n-3) . The (n-3)th shift register bit SB _(n-3) feeds its logical content into the (n-3)th shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the (n-3)th shift register bit SB _(n-6) preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-4)th shift register bit SB _(n-7) of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel Shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-3)th bit of the TPRG data bus 2110 as its next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (eg high);

SB(n-2)

(n-2)-th shift register cell with the (n-2)-th shift register bit SB _(n-2) . The (n-2)-th shift register bit SB _(n-2) feeds its logical content into the (n-2)-th shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the (n-2)th shift register bit SB _(n-6) preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-3)th shift register bit SB _(n-7) of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel Shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-2)-th bit of the TPRG data bus 2110 as their next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (eg high);

SB(n-1)

(n-1)-th shift register cell with the (n-1)-th shift register bit SB _(n-1) . The (n-1)th shift register bit SB _(n-1) feeds its logical content into the (n-1)th shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logical value of the parallel-to-serial shift register mode switching line 2107, the (n-1)th shift register bit SB _(n-6) preferably loads, for example a) at a first logical value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logical value of the (n-2)th shift register bit SB _(n-7) of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logical value and b) at a second logical value of the parallel-to-serial shift register mode switching line 2107, the parallel shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28 the logical value of the (n-1)th bit of the TPRG data bus 2110 as its next logical value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (e.g. high);

SBn

n-th shift register cell with the n-th shift register bit SB _n . The n-th shift register bit SB _n feeds its logical content into the n-th shift register bus line of the shift register bus 2101 of the time-to-pseudo-random number converter 404.3 (TPRC). Depending on the logic value of the parallel-to-serial shift register mode switching line 2107, the n-th shift register bit SB _(n-6) preferably loads, for example, a) at a first logic value of the parallel-to-serial shift register mode switching line 2107, the serial shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the (n-1)-th shift register bit SB _(n-7) of the time-to-pseudo-random number converter 404.3 (TPRC) as its next logic value and b) at a second logic value of the parallel-to-serial shift register mode switching line 2107, the parallel Shift register operating mode, for example with the next rising clock edge of the system clock 2106 of the quantum random number generator 28 and the time-to-pseudo-random number converter 404.3 (TPRC) of the quantum random number generator 28, the logic value of the n-th bit of the TPRG data bus 2110 as their next logic value if at the same time the first shift register bit activation line of the shift register bit activation bus 2109 is active (eg high);

VDD

positive supply voltage line VDD at a positive electrical potential with respect to the reference potential of the reference potential line GND;

VENTS

positive supply voltage line V _EXT of the entropy source 411;

Relevant writings

• R. L. Rivest, A. Shamir, and L. Adleman, “A Method for Obtaining Digital Signatures and Public-Key Cryptosystems” Communications of the ACM, February 1978, Vol. 21, No. 2, pages 120 to 126

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions.

Cited patent literature

• EN 1020221255743 [0001]
• EP 3529694 B1 [0007, 0050]
• WO 2023072956 A1 [0007]
• WO 2016016741 A1 [0019]

Cited non-patent literature

• R. L. Rivest, A. Shamir, and L. Adleman, “A Method for Obtaining Digital Signatures and Public-Key Cryptosystems” Communications of the ACM, February 1978, Vol. 21, No. 2, pages 120 to 126 [0229, 0407]

Claims (13)

Quantum process-based generator (28) for true random numbers (411, 418) (English: Quantum Random Number Generator: QRNG), - wherein the quantum process-based generator (28) for true random numbers (411, 418) (has an entropy source (401) and - wherein the quantum process-based generator (28) for true random numbers (411, 418) evaluates a signal (405) of the entropy source (401) by means of a time-to-pseudo-random number converter (TPRC) (404.3) and generates one or more random bits (411). Quantum process-based generator (28) for true random numbers (411, 418) according to Claim 1 , - wherein the quantum process-based generator (28) for true random numbers (411, 418) generates one or more random numbers (418) from several random bits (411) and makes them available or uses them. Quantum process-based generator (28) for true random numbers (411, 418) according to Claim 1 or 2 , - wherein the behavior of the P of a time-to-pseudorandom number converter (TPRG) (404.3) depends on one or more quantum random bits (411) and/or one or more quantum random numbers (418). Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 3 , - wherein the quantum process-based generator (28) for true random numbers (411, 418) comprises a watchdog (404.5) which monitors the correct functioning of the quantum process-based generator (28) for true random numbers (411, 418). Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 4 , - wherein the quantum process-based generator (28) for true random numbers (411, 418) comprises a watchdog (404.5) which monitors the correct functioning of the quantum process-based generator (28) for true random numbers (411, 418) by measuring the randomness of the generated quantum random bits (411) in the form of a measured value and comparing it with a tolerance interval or a threshold value and concluding that there is an error in the event of a deviation. Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 5 , - wherein the quantum process-based generator (28) for true random numbers (411, 418) comprises a watchdog (404.5) which monitors the correct functioning of a time-to-pseudo-random number converter (TPRC) (404.3) and detects and/or signals an error in the event of deviations from an expected behavior. Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 6 , - wherein the integrated circuit (2) is manufactured using a BCD technology. Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 7 , - wherein the quantum process-based generator (28) for true random numbers (411, 418) is manufactured in one piece as part of an integrated circuit (2). Quantum process-based generator (28) for true random numbers (411, 418) according to Claim 7 and Claim 8 , - wherein the integrated circuit (2) comprises a voltage converter (91) for supplying the entropy source (401) of the quantum process-based generator (28) for true random numbers (411, 418) and - wherein the voltage converter (91) comprises one or more DMOS transistors. Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 9 , - wherein the quantum process-based generator (28) for true random numbers (411, 418) is manufactured in one piece as part of an integrated circuit (2) and - wherein the integrated circuit (2) is one of the following circuits or comprises one of the following circuits circuits includes: - a microcontroller, - a microprocessor, - a memory, - a DRAM, - an SRAM, - a RAM, - a volatile memory, - an OTP memory, - an EEPROM, - a flash memory, - an MRAM, - an FRAM, - a sensor evaluation circuit, - a control circuit for an automotive control circuit, - a graphics controller, - an evaluation circuit for a biometric sensor or an input device, - a control circuit, - a chip card circuit, - an electronic circuit of a mobile phone or a smart phone, - a circuit of an access control system, - a circuit with a coded recording of operating parameters, - a circuit of an access control system, - a circuit of a security system for electronic security, - a radio system circuit, - a communication circuit, - a circuit of an encryption and/or decryption system, - a circuit of an individualization system, - a circuit of a gaming device, - a circuit of a simulation system, - a circuit of a computer system, - a circuit of a noise source, - a circuit with a device for generating and/or using a spreading code. Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 10 , - wherein the quantum process-based generator (28) for true random numbers (411, 418) is manufactured in one piece as part of an integrated circuit (2), and - wherein the integrated circuit (2) has internal interfaces (63, 301, 32 and 81) as special circuits at a cryptographic boundary between a control device (4) and other parts (8, 30, 6) of the integrated microelectronic circuit (2) which are classified as not secure or less secure, and - wherein the quantum process-based generator (28) for true random numbers (411, 418) is arranged within the cryptographic boundary between a control device (4) and other parts (8, 30, 6) of the integrated microelectronic circuit (2). Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 11 , - wherein the entropy source (401) comprises a photon source (54) and - wherein the entropy source (401) comprises a photon detector (55) and - wherein the photon source (54) emits photons as a quantum signal when supplied with electrical energy and - wherein the photon source (54) is optically coupled to the photon detector (55) and - wherein the photon detector (55) at least partially receives the quantum signal of the photon source (54) and generates the output signal (405) of the entropy source (401) or a precursor signal thereof. Quantum process-based generator (28) for true random numbers (411, 418) according to one of the Claims 1 until 12 , wherein the quantum process-based generator (28) is completely or partially arranged in the pad frame (2403) between connection pads (2402) of an integrated circuit (2) on the die (2401) of this integrated circuit circuit (2) and wherein at least the entropy source (401) is placed in the pad frame (2403) between connection pads (2402) of an integrated circuit (2) on the die (2401) of this integrated circuit (2).

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