DE102023112387A1 - STORAGE DEVICE AND METHOD FOR OPERATING THE STORAGE DEVICE - Google Patents

Abstract

The present technology relates to a memory device and a method of operating the memory device. The memory device includes a memory block that includes a plurality of memory cells corresponding to a plurality of word line groups, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a voltage generation circuit configured to provide one of to apply an operating voltage increasing from a first operating voltage to a second operating voltage to the plurality of word line groups during the erase operation, and control logic configured to control the source line driver and the voltage generating circuit to perform an interrupt operation to stop the erase operation.

Description

BACKGROUND

1. Technical area

The present disclosure relates to an electronic device, and more particularly to a memory device and a method of operating the memory device.

2. State of the art

In particular, among semiconductor devices, a memory device is essentially divided into a volatile memory device and a nonvolatile memory device.

A writing speed and reading speed of the non-volatile memory devices are relatively slow, but the non-volatile memory devices maintain the memory data even when the power supply is interrupted. Therefore, the non-volatile memory devices are used to store data that is maintained regardless of whether power is supplied. The non-volatile memory devices include read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM). , an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like . Flash memory is divided into a NOR type and a NAND type.

The flash memory has the advantage of a RAM that can freely program and erase data and the advantage of a ROM that can retain stored data even when a power supply is interrupted. Flash memory is widely used as a storage medium for portable electronic devices such as digital cameras, PDAs (Personal Digital Assistant) and MP3 players.

SUMMARY

According to an embodiment of the present disclosure, a memory device may include a memory block that includes a plurality of memory cells corresponding to a plurality of word line groups, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a voltage generation circuit, configured to apply an operating voltage increasing from a first operating voltage to a second operating voltage to the plurality of word line groups during the erase operation, and control logic configured to control the source line driver and the voltage generating circuit to perform an interrupt operation to stop or stop. Stopping the erase operation in response to an interrupt command, and configured to determine the number of remaining erase pulses of the erase operation and a rise time at which the operating voltage rises from the first operating voltage to the second operating voltage based on the number of times the interrupt operation is performed is performed to set for each of the plurality of word line groups.

According to an embodiment of the present disclosure, a method of operating a memory device may include performing an erase operation on a memory block that includes a plurality of memory cells corresponding to a plurality of word line groups, performing an interrupt operation to stop the erase operation in response to an interrupt command received during the erase operation, setting the number of remaining erase pulses based on the number of times the interrupt operation is performed during the erase operation, setting a rise timing of an operating voltage applied to the word lines of the selected memory block for each of the plurality of word line groups during the erase operation based on the number of times the interrupt operation is performed and a setting ratio of each of the plurality of word line groups, and performing a resume operation to resume the stopped erase operation, performing an erase pulse application loop as many times as the number of remaining erase pulses during the resume operation, and increasing the operating voltage applied to the word lines from a first operating voltage to a second operating voltage at the set rise time of the operating voltage.

According to an embodiment of the present disclosure, a memory device may include a memory block that includes a plurality of memory cells corresponding to a plurality of word line groups, a source line driver configured to apply an erase voltage to an erase voltage during an erase operation source line of the memory block, a voltage generating circuit that is configured to apply an operating voltage increasing from a first operating voltage to a second operating voltage to the plurality of word line groups during the erase operation, and a control logic that is configured to control the source line driver and the voltage generating circuit to perform an interrupt operation to stop the erase operation in response to an interrupt command, and is configured to set the number of remaining erase pulses of the erase operation for each of the plurality of word line groups based on a timing at which the interrupt operation is performed.

According to an embodiment of the present disclosure, a method of operating a memory device may include performing an erase operation on a memory block that includes a plurality of memory cells corresponding to a plurality of word line groups, performing an interrupt operation to stop the erase operation in response to an interrupt command, received during the erase operation, setting the number of remaining erase pulses based on a timing at which the interrupt operation performed during the erase operation is performed, and performing a resume operation to resume the stopped erase operation and performing an erase pulse application loop so many times like the set number of remaining deletion pulses.

According to an embodiment of the present disclosure, a memory device may include a memory block that includes a plurality of memory cells corresponding to a plurality of word line groups, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a voltage generation circuit, configured to apply an operating voltage increasing from a first operating voltage to a second operating voltage to the plurality of word line groups during the erase operation, and control logic configured to control the source line driver and the voltage generating circuit to perform an interrupt operation to stop the erase operation in response to an interrupt command, and is configured to determine a rise timing at which the operating voltage rises from the first operating voltage to the second operating voltage for each of the plurality of word line groups based on a timing at which the interrupt operation is performed, or the To set the number of times the interrupt operation is performed.

According to an embodiment of the present disclosure, a method of operating a memory device may include performing an erase operation on a memory block that includes a plurality of memory cells corresponding to a plurality of word line groups, performing an interrupt operation to stop the erase operation in response to an interrupt command, received during the erase operation, setting the number of remaining erase pulses based on the number of times the interrupt operation is performed during the erase operation, setting a rise timing of an operating voltage applied to word lines of the selected memory block for each of the plurality of word line groups during the erase operation based on the time at which the interrupt operation is performed or the number of times the interrupt operation is performed, and performing a resume operation to resume the stopped erase operation, performing an erase pulse application loop as many times as the number of remaining erase pulses during the resume operation, and increasing the operating voltage applied to the word lines from a first operating voltage to a second operating voltage at the set operating voltage rise time.

BRIEF DESCRIPTION OF DRAWINGS

• 1 shows a diagram illustrating a storage system according to an embodiment of the present disclosure.
• 2 shows a diagram illustrating a storage device 1 represents.
• 3 shows a diagram showing a memory block of 2 represents.
• 4 shows a diagram illustrating an embodiment of a three-dimensional memory block.
• 5 shows a flowchart illustrating a method for operating a storage device according to a first embodiment of the present disclosure.
• 6 Fig. 11 shows a waveform diagram of operating voltages illustrating an operation of the memory device according to the first embodiment of the present disclosure.
• 7 shows a flowchart illustrating a method of operating a storage device according to a second embodiment of the present disclosure.
• 8th Fig. 12 is a diagram illustrating an erasure characteristic and a subtraction number setting ratio according to an operation period of the memory device according to the second embodiment of the present disclosure.
• 9 Fig. 11 shows a waveform diagram of operating voltages illustrating an operation of the memory device according to the second embodiment of the present disclosure.
• 10 shows a flowchart illustrating a method of operating a storage device according to a third embodiment of the present disclosure.
• 11 Fig. 12 shows a waveform diagram of operating voltages illustrating a method of operating the memory device according to the third embodiment of the present disclosure.
• 12 shows a diagram illustrating another embodiment of the storage system incorporating the in 2 storage device shown includes.
• 13 shows a diagram illustrating another embodiment of the storage system incorporating the in 2 storage device shown includes.
• 14 shows a diagram illustrating another embodiment of the storage system incorporating the in 2 storage device shown includes.
• 15 shows a diagram illustrating another embodiment of the storage system incorporating the in 2 storage device shown includes.

DETAILED DESCRIPTION

Specific structural or functional descriptions of embodiments in accordance with the concept disclosed in the present specification or application are presented only to describe the embodiments in accordance with the concept of the present disclosure. The embodiments according to the concept of the present disclosure may be embodied in various forms and should not be construed as being limited to the embodiments described in the present specification or application.

Below, the present disclosure will be described in detail by describing a preferred embodiment of the present disclosure with reference to the accompanying drawings. Below, an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

An embodiment of the present disclosure provides a memory device and a method of operating the memory device capable of improving a threshold voltage distribution of memory cells during an erase operation of a memory device.

In one embodiment, a threshold voltage distribution of memory cells may be improved during an erase operation of a memory device.

1 shows a diagram illustrating a storage system according to an embodiment of the present disclosure.

With reference to 1 The storage system 1000 may include a storage device 1100 in which data is stored and a storage controller 1200 that controls the storage device 1100 under the control of a host 2000.

The host 2000 may communicate with the storage system 1000 using an interface protocol such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). or get in touch. Furthermore, the interface protocols between the host 2000 and the storage system 1000 are not limited to the examples described above and may be any of other interface protocols such as Universal Serial Bus (USB), a Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE)).

The storage controller 1200 may control an overall operation of the storage system 1000 and may control data exchange between the host 2000 and the storage device 1100. For example, storage controller 1200 may program, read, or delete data by controlling storage device 1100 according to a request from host 2000. According to one embodiment, the memory device 1100 may include a double data rate synchronous dynamic random access memory (DDR SDRAM). fourth generation Low Power Double Data Rate4 (LPDDR4), Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (Rambus Dynamic Random Access Memory - RDRAM) or flash memory.

The memory device 1100 may perform a program, read, or erase operation under the control of the memory controller 1200.

2 shows a diagram showing the storage device of 1 represents.

With reference to 2 The storage device 1100 may include the memory cell array 100 in which data is stored. The memory device 1100 may include peripheral circuits 200 configured to perform a program operation to store data in the memory cell array 100, a read operation to output the stored data, and an erase operation to delete the stored data. The memory device 1100 may include control logic 300 that controls the peripheral circuits 200 according to the control of the memory controller 1200 1 controls. The control logic 300 can be implemented as hardware, software or as a combination of hardware and software. For example, control logic 300 may be a control logic circuit that operates according to an algorithm and/or a processor that executes control logic code.

The memory cell array 100 may include a plurality of memory blocks MB1 to MBk; Include 110 (k is a positive integer). Local lines LL and bit lines BL1 to BLn (n is a positive integer) can be connected to each of the memory blocks MB1 to MBk; 110 be connected. The local lines LL may include, for example, a first selection line, a second selection line, and a plurality of word lines disposed between the first and second selection lines. In addition, the local lines LL may include dummy lines arranged between the first selection line and the word lines and between the second selection line and the word lines. The first selection line can be a source selection line and the second selection line can be a drain selection line. The local lines LL can include, for example, the word lines, the drain and source select lines and the source lines SL. For example, the local lines LL can also include the dummy lines. For example, the local lines LL can also include pipe lines. The local lines LL can each be connected to the memory blocks MB1 to MBk; 110 may be connected, and the bit lines BL1 to BLn may be shared with the memory blocks MB1 to MBk; 110 be connected. The memory blocks MB1 to MBk; 110 can be implemented in a two- or three-dimensional structure. For example, the memory cells in the memory block 110 of the two-dimensional structure may be arranged in a direction parallel to a substrate. For example, the memory cells in the memory block 110 of the three-dimensional structure may be stacked in a direction perpendicular to the substrate.

The peripheral circuits 200 may be configured to perform the program, read and erase operations of the selected memory block 110 under the control of the control logic 300. The peripheral circuits 200 may include, for example, a voltage generation circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input/output circuit 250, a pass/fail determiner (pass/fail check circuit) 260, and a source line driver 270 .

The voltage generating circuit 210 can generate various operating voltages Vop used in the program, read and erase operations in response to an operation signal OP_CMD. For example, the voltage generating circuit 210 may generate a program voltage, verification voltages, pass voltages, a turn-on voltage, a read voltage, first and second word line voltages, and the like under the control of the control logic 300.

The row decoder 220 may transmit the operating voltages Vop to the local lines LL connected to the selected memory block 110 in response to decoder control signals AD_signals. The line decoder 220 may be implemented such that it is included in the voltage generation circuit 210.

The page buffer group 230 may include a plurality of page buffers PB1 to PBn; 231, which are connected to the bit lines BL1 to BLn. The page buffers PB1 to PBn; 231 can operate in response to page buffer control signals PBSIGNALS. For example, the page buffers PB1 to PBn; 231 store data received via the bit lines BL1 to BLn or sample or detect a voltage or a current of the bit lines BL1 to BLn during a read or test operation.

The column decoder 240 can CADD data between the in response to a column address Input/output circuit 250 and page buffer group 230. For example, the column decoder 240 may exchange data with the page buffers 231 via data lines DL or may exchange data with the input/output circuit 250 via column lines CL.

The input/output circuit 250 may have a command CMD and an address ADD received from the memory controller 1200 1 are received, transmitted to the control logic 300 or can exchange the data DATA with the column decoder 240.

During the read operation or the test operation, the pass/fail determiner 260 may generate a reference current in response to a valid bit VRY_BIT<#>, compare a sample voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current, and generate a pass signal PASS or output a fail signal FAIL.

The source line driver 270 may be connected to the memory cell included in the memory cell array 100 via a source line SL, and may control a voltage applied to the source line SL. For example, the source line driver 270 may electrically connect the source line and a ground node during the program, read, or test operation. In addition, the source line driver 270 may apply the erase voltage to the source line SL during the erase operation. The source line driver 270 may receive a source line control signal CTRL_SL from the control logic 300 and may connect the ground node to the source line or apply the erase voltage to the source line based on the source line control signal CTRL_SL.

The control logic 300 may output the operation signal OP_CMD, the row decoder control signals AD_signals, the page buffer control signals PBSIGNALS, and the allowable bit VRY_BIT<#> in response to the CMD command and the address ADD, and control the peripheral circuits 200. In addition, the control logic 300 may determine whether the test operation passed or failed in response to the pass signal PASS or the fail signal FAIL.

If during the erase operation of the storage device 1100, an interrupt command is received from the storage controller 1200 1 is received, control logic 300 may perform an interrupt operation to stop a delete operation in progress. Thereafter, the control logic 300 may perform a resume operation to resume the stopped erase operation by issuing a resume command from the memory controller 1200 1 receives.

During the resume operation, the control logic 300 may adjust the number of remaining erase pulses of the erase operation and set a rise timing of a word line operating voltage applied to the word lines based on the number of interrupt operations performed during the current erase operation. For example, control logic 300 may adjust the number of erase pulses remaining by subtracting the number corresponding to the number of interrupt operations from the number of erase pulse application loops that are not performed during the current erase operation. For example, the control logic 300 may calculate a shortened period based on the number of interrupt operations and a setting ratio and reset the initial set rise timing of the word line operating voltage by advancing the rise timing by the calculated shortened period. The shortened period may be equal to or shorter than a period corresponding to the number of subtractions. The control logic 300 may control the peripheral circuits 200 to perform the erase operation according to the set number of remaining erase pulses and the rise timing.

The control logic 300 may adjust the number of remaining erase pulses of the erase operation based on a timing of the suspend operation performed immediately before the resume operation. For example, the control logic 300 may determine, from a plurality of periods of the erase operation, a period in which the interrupt operation is performed, calculate the number of subtractions based on a setting ratio corresponding to the particular period and the number of interrupt operations, and calculate the calculated number of subtractions from the Subtract number of erase pulse application loops not performed to adjust number of erase pulses remaining. The number of subtractions may be equal to or less than the number of interrupt operations. For example, the erase operation may include a plurality of periods, and the plurality of periods may have different erase characteristics. For example, a sub-period of the plurality of periods may have a flat erase characteristic in which data is erased in a state in which the threshold voltage is higher than a target threshold voltage. If the interrupt operation is performed in the period corresponding to the flat erase characteristic, the control logic 300 may further set the number of interrupt operations with a relatively high adjustment ratio and calculate the number of subtractions less than the number of interrupt operations to adjust the number of remaining erase pulses . The control logic 300 may control the peripheral circuits 200 to perform the erase operation according to the set number of remaining erase pulses.

During the resume operation, the control logic 300 may adjust the initial set rise timing of the word line operating voltage based on the number of interrupt operations performed during the current erase operation or the timing at which the interrupt operation is performed. For example, based on the number of interrupt operations, it may be determined whether the current erase operation has a deep erase characteristic in which the data is erased in a state in which the threshold voltage of the memory cells is lower than the target threshold voltage, or has the shallow erase characteristic in which the data is erased in a state in which the threshold voltage of the memory cells is higher than the target threshold voltage, and the initially set rise timing of the word line operating voltage may be advanced or delayed according to the determined erasure characteristic to reset the rise timing. In addition, the period in which the interrupt operation is performed among the plurality of periods of the erase operation can be determined, and the initially set rise timing of the word line operating voltage can be advanced or delayed according to the erase characteristic corresponding to the specific period to reset the rise timing . The control logic 300 may control the peripheral circuits 200 to perform the erase operation according to the reset rise timing of the word line operating voltage.

3 shows a diagram showing the memory block of 2 represents.

With reference to 3 The memory block 110 may be connected to a plurality of word lines arranged in parallel with each other between the first select line and the second select line. The first selection line can be the source selection line SSL and the second selection line can be the drain selection line DSL. More specifically, the memory block 110 may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may each be connected to the strings ST, and the source line SL may be commonly connected to the strings ST. Since the strings ST may be made identical to each other, a string ST connected to the first bit line BL1 will be specifically described as an example.

The string ST may include a source select transistor SST, a plurality of memory cells MC1 to MC16 and a drain select transistor DST connected in series between the source line SL and the first bit line BL1. A string ST may include at least one or more of the source select transistors SST and drain select transistors DST, and may include more than the number of memory cells MC1 to MC16 shown in the figure.

A source of the source selection transistor SST may be connected to the source line SL and a drain of the drain selection transistor DST may be connected to the first bit line BL1. The memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST. Gates of the source select transistors SST included in the various strings ST may be connected to the source select line SSL, gates of the drain select transistors DST may be connected to the drain select line DSL, and gates of the memory cells MC1 to MC16 may be connected to the plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line may be referred to as a physical page PPG among the memory cells included in different strings ST. Therefore, the memory block 11 may include the physical pages PPG of the number of word lines WL1 to WL16.

The plurality of word lines WL1 to WL16 can be divided into a plurality of word line groups GR1 and GR2. For example, among the plurality of memory cells MC1 to MC16 included in the memory block 110, word lines connected to memory cells whose erase speed is relatively high during the erase operation may be defined as a first word line group GR1, and word lines connected to Memory cells connected whose erasing speed is relatively slow can be defined as a second word line group GR2. For example, the word lines WL1 to WL8 connected to the memory cells MC1 to MC8 adjacent to the source select transistor SST may be defined as the first word line group GR1, and the word lines WL9 to WL16 connected to the memory cells MC9 to MC16 adjacent connected to the drain select transistor DST can be defined as the second word line group GR2.

At least one dummy memory cell DMC1 may be arranged between the source select transistor SST and the memory cell MC1, and at least one dummy memory cell DMC2 may be arranged between the drain select transistor DST and the memory cell MC16. Each of the dummy memory cell DMC1 and the dummy memory cell DMC2 may be included in the same word line group as the memory cells adjacent thereto. For example, the dummy memory cell DMC1 may be included in the first word line group GR1 and the dummy memory cell DMC2 may be included in the second word line group GR2.

Furthermore, dummy memory cells (not shown) may be arranged between memory cells (e.g. MC8 and MC9) arranged in a central area of the plurality of memory cells MC1 to MC16, and the dummy memory cells may be arranged in a word line group of adjacent ones Memory cells may be included.

A memory cell can store one bit of data. This is commonly referred to as a single-level cell (SLC). In this case, a physical page can store PPG data of a logical page data (LPG). Logical page data (LPG) may include data bits of the number of cells included in a physical page PPG. In addition, a memory cell can store data with two or more bits. This is commonly referred to as a multi-level cell (MLC). In this case, a physical page PPG can store data from two or more logical pages (LPG).

4 shows a diagram illustrating an embodiment of a three-dimensional memory block.

With reference to 4 The memory cell array 100 may include a plurality of memory blocks MB1 to MBk; 110 include. Each of the memory blocks 110 may include a plurality of strings ST11 to STln and ST21 to ST2n. Each of the plurality of strings ST11 to STln and ST21 to ST2n may extend along a vertical direction (Z direction). In the memory block 110, n strings can be arranged in a row (X direction). In 4 There are two strings arranged in a column direction (Y direction), but this is only for ease of description, and there may be three or more strings arranged in the column direction (Y direction).

Each of the plurality of strings ST11 to STln and ST21 to ST2n may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

The source select transistor SST of each string may be connected between the source select line SL and the memory cells MC1 to MCn. The source select transistors of the strings arranged in the same row can be connected to the same source select line. The source selection transistors of the strings ST11 to STln arranged in the first row may be connected to a first source selection line SSL1. The source selection transistors of the strings ST21 to ST2n arranged in the second row may be connected to a second source selection line SSL2. As another embodiment, the source select transistors of the strings ST11 to STln and ST21 to ST2n may be connected together to a source select line.

The first to nth memory cells MC1 to MCn of each string may be connected in series between the source select transistor SST and the drain select transistor DST. Gates of the first to nth memory cells MC1 to MCn may be connected to the first to nth word lines WL1 to WLn, respectively. The first to nth word lines WL1 to WLn may be divided into a plurality of word line groups GR1 and GR2. For example, among the plurality of memory cells MC1 to MCn included in the memory block MB1, word lines connected to memory cells whose erase speed is relatively high during the erase operation may be defined as a first word line group GR1, and word lines connected to Memory cells connected whose erasing speed is relatively slow can be defined as a second word line group GR2. For example, word lines WL1 to WLm connected to memory cells MC1 to MCm adjacent to the source select transistor SST may be defined as the first word line group GR1, and word lines WLm+1 to WLm connected to memory cells MCm+1 to MCn adjacent to the drain Selection transistor DST connected can be defined as second word line group GR2.

As an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. When the dummy memory cell is provided, a voltage or a current of an ent speaking strings can be stably controlled or regulated.

The drain select transistor DST of each string may be connected between the bit line and the memory cells MC1 to MCn. The drain select transistor DST of the strings arranged in the row direction may be connected to the drain select line extending in the row direction. The drain selection transistors DST of the strings ST11 to STln of the first row can be connected to a first drain selection line DSL1. The drain selection transistors DST of the strings ST21 to ST2n of the second row can be connected to a second drain selection line DSL2.

The plurality of memory blocks MB1 to MBk; 110, which with reference to 4 are described, can share the source line SL.

5 shows a flowchart illustrating a method for operating a storage device according to a first embodiment of the present disclosure.

6 Fig. 11 shows a waveform diagram of operating voltages illustrating an operation of the memory device according to the first embodiment of the present disclosure.

The method of operating the memory device according to the first embodiment of the present disclosure will be explained with reference to 2 until 6 described as follows.

In step S510, the delete operation is performed. The storage device 1100 receives the CMD command corresponding to the erase operation, and the control logic 300 controls the peripheral circuits 200 to perform the erase operation.

For example, during the erase operation, the source line driver 270 applies an erase voltage Vera to the source line SL connected to the selected memory block (e.g., MB1). The erase voltage Vera may rise to a target level during a rising period, and then the erase voltage Vera of the target level may be applied to the source line SL during erase pulse application periods tERAPLS1 and tERAPLS2. The erase pulse application operation periods tERAPLS1 and tERAPLS2 may include a first erase pulse application operation period tERAPLS1, which includes a first erase pulse application loop <0>, and a second erase pulse application operation period tERAPLS2, which includes remaining erase pulse application loops <1:K>.

The voltage generating circuit 210 generates the operating voltage Vop to be applied to the word lines of the selected memory block MB1. The operating voltage Vop may include a first operating voltage Vop1 and a second operating voltage Vop2, and a potential of the second operating voltage Vop2 is higher than that of the first operating voltage Vop1. The first operating voltage Vop1 can have a higher potential than an earth or ground voltage.

The row decoder 220 applies the operating voltage Vop generated by the voltage generating circuit 210 to the word lines of the selected memory block MB1. For example, the row decoder 220 may apply the first operating voltage Vop1 to a set erase pulse application loop from the plurality of erase pulse application loops 0 to K sequentially performed in the erase pulse application operating periods tERAPLS1 and tERAPLS2 and the second operating voltage Vop2 to the word lines from a next erase pulse application loop. A timing at which the operating voltage Vop is changed from the first operating voltage Vop1 to the second operating voltage Vop2 can be defined as a rising timing of the word line operating voltage. During the erasing operation, the memory cells are erased by the erasing voltage Vera applied to the source line SL and the first operating voltage Vop1 or the second operating voltage Vop2 applied to the word lines, and an erasing speed in a period in which the first operating voltage Vop1 is applied is faster than an erasing speed in a period in which the second operating voltage Vop2 is applied.

In step S520, the interrupt operation is performed during the erase operation. The storage device 1100 may receive the CMD command corresponding to the erase operation during the interrupt operation, and the control logic 300 stops the erase operation in response to the CMD command. Thereafter, the storage device 1100 may perform other general operations.

In step S530, control logic 300 sets the number of remaining erase pulses based on the number of interrupt operations performed during the erase operation currently being performed.

For example, control logic 300 may adjust the number of erase pulses remaining by subtracting the number of times the interrupt operation is performed from the number of erase pulse application loops cannot be performed due to the interrupt operation in the current delete operation.

For example, if the number of times the interrupt operation is performed is four, the control logic 300 may adjust the number of remaining erase pulses by subtracting four from the number of unperformed erase pulse application loops.

In step S540, the control logic 300 sets the rising timing of the word line operating voltage based on the number of times the interrupt operation is performed and the setting ratio.

For example, the control logic 300 may calculate the shortened period based on the number of interrupt operations and the setting ratio, and reset the initial set rise timing of the word line operating voltage by advancing the rise timing by the calculated shortened period. The shortened period may be equal to or shorter than the period corresponding to the number of erase pulse application loops subtracted in step S530 described above.

For example, if the number of times the interrupt operation is performed is four and the setting ratio is 1:1, the control logic 300 may define the shortened period as a period of four times the erase pulse application loops according to the subtracted number of erase pulse application loops (four times) and adjust the setting ratio.

For example, if the number of times the interrupt operation is performed is four and the setting ratio is 2:1, the control logic 300 may define the shortened period as a period of twice the erase pulse application loops according to the subtracted number of erase pulse application loops (four times) and adjust the setting ratio.

For example, if the number of times the interrupt operation is performed is four and the setting ratio is 4:1, the control logic 300 may define the shortened period as a period of once the erase pulse application loop according to the subtracted number of erase pulse application loops (four times) and adjust the setting ratio.

The above-described operation for setting the rise timing of the word line operating voltage can be performed for each of the plurality of word line groups GR1 and GR2. For example, a setting ratio of the word line group GR1 and a setting ratio of the word line group GR2 may be the same or different from each other.

With reference to 6 , when the initial set rising timing of the word line operating voltage of the first word line group GR1 is an erase pulse application loop <4>, the number of times the interrupt operation is performed is four, and the setting ratio is 1:1, the first operating voltage Vopl applied to the first Word line group GR1 is applied to the second operating voltage Vop2 in an erase pulse application loop <0> by a shortened period equal to the number of times the interrupt operation is performed. That is, the rise timing of the word line operating voltage can be advanced by the shortened period corresponding to the number of times the interrupt operation is performed by the erase pulse application loop <4>, which is the initially set rise timing of the word line operating voltage, and can be applied to the erase pulse Application loop <0> can be reset. An erasing speed of the memory cells connected to the second word line group GR2 may be slower than an erasing speed of the memory cells connected to the first word line group GR1. Accordingly, the initially set rising timing of the word line operating voltage of the memory cells connected to the second word line group GR2 can be set to be later than the initially set rising timing of the word line operating voltage of the memory cells connected to the first word line group GR1. When the initial set rising timing of the word line operating voltage of the second word line group GR2 is an erase pulse application loop <9>, the number of times the interrupt operation is performed is four, and the setting ratio is 1:1, the first operating voltage Vopl applied to the second word line group GR2 is applied to the second operating voltage Vop2 in an erase pulse application loop <5> by the shortened period equal to the number of times the interrupt operation is performed. That is, the rise timing of the word line operating voltage can be advanced by the shortened period of time corresponding to the number of times the interrupt operation is performed by the erase pulse application loop <9>, which is the initially set rise timing of the word line operating voltage, and can be applied to the erase pulse Application loop <5> can be reset. If the number of times the interrupt operation is performed is increased, a time for applying sequentially applied erase pulses can be shortened, so that the flat erasure characteristic of the memory cells can occur.

When the initial set rising timing of the word line operating voltage of the first word line group GR1 is the erase pulse application loop <4>, the number of times the interrupt operation is performed is 4, and the setting ratio is 2:1, the shortened period is considered a period of twice that Erase pulse application loops are calculated according to the number of times the interrupt operation is performed and the setting ratio. The first operating voltage Vop1 applied to the first word line group GR1 can be changed into the second operating voltage Vop2 in an erase pulse application loop <2> by the calculated shortened period. That is, the rising timing of the word line operating voltage can be advanced by the calculated shortened period from the erase pulse application loop <4>, which is the initially set rising timing of the word line operating voltage, and can be reset to the erase pulse application loop <2>. When the initial set rising point of the word line operating voltage of the second word line group GR2 is the erase pulse application loop <9>, the number of times the interrupt operation is performed is 4, and the setting ratio is 2:1, the shortened period is considered a period of twice that Erase pulse application loops are calculated according to the number of times the interrupt operation is performed and the setting ratio. The first operating voltage Vop1 applied to the second word line group GR2 can be changed into the second operating voltage Vop2 in an erase pulse application loop <7> by the calculated shortened period. That is, the rise timing of the word line operating voltage can be advanced by the calculated shortened period from the erase pulse application loop <9>, which is the initially set rise timing of the word line operating voltage, and can be reset to the erase pulse application loop <7>.

As described above, the erasing speed of the memory cells can be adjusted by adjusting the rise timing of the word line operating voltage by setting the adjustment ratio to be high.

In step S550, the resume operation is performed to resume the stopped erase operation. During the resume operation, the stopped erase operation is resumed according to the number of remaining erase pulses set in the previous step S530 and the set rise timing of the word line operating voltage reset in step S540.

For example, the control logic 300 controls the source line driver 270 to sequentially proceed from the stopped erase pulse application loop and sequentially perform erase pulse application loops corresponding to the set number of remaining erase pulses.

In addition, the control logic 300 controls the voltage generation circuit 210 and the row decoder 220 to increase the first operating voltage Vopl applied to the first and second word line groups GR1 and GR2 to the second operating voltage Vop2 and the second operating voltage Vop2 at the reset rise timing of the Apply word line operating voltage.

According to the above-described first embodiment of the present disclosure, the rising timing of the operating voltage applied to the word lines can be controlled based on the number of interrupt operations and the setting ratio. That is, a time for which the first operating voltage Vop1 is applied can be increased by controlling the shortened period of the rise timing of the operating voltage applied to the word lines to be as large as the number of times the interrupt operation is performed. is relatively short. Accordingly, in one embodiment, the flat erase characteristic in which data is erased in a state where the threshold voltage is higher than a target threshold voltage can be improved.

7 shows a flowchart illustrating a method of operating a storage device according to a second embodiment of the present disclosure.

8th Fig. 12 is a diagram illustrating an erasure characteristic and an adjustment ratio of the subtraction number according to an operation period of the memory device according to the second embodiment of the present disclosure.

9 Fig. 11 shows a waveform diagram of operating voltages illustrating an operation of the memory device according to the second embodiment of the present disclosure.

The operation of the memory device according to the second embodiment of the present Revelation is made with reference to the 2 until 4 and 7 until 9 described as follows.

In step S710, the delete operation is performed. The storage device 1100 receives the CMD command corresponding to the erase operation, and the control logic 300 controls the peripheral circuits 200 to perform the erase operation.

For example, during the erase operation, the source line driver 270 applies an erase voltage Vera to the source line SL connected to the selected memory block (e.g., MB1). The erase voltage Vera may gradually increase to a target level during a rising period, and then the erase voltage Vera of the target level may be applied to the source line SL during the erase pulse application operation periods tERAPLS1 and tERAPLS2. The erase pulse application operation periods tERAPLS1 and tERAPLS2 may include a first erase pulse application operation period tERAPLS1, which includes a first erase pulse application loop <0>, and a second erase pulse application operation period tERAPLS2, which includes remaining erase pulse application loops <1:K>.

The voltage generating circuit 210 generates the operating voltage Vop to be applied to the word lines of the selected memory block MB1. The operating voltage Vop may include a first operating voltage Vop1 and a second operating voltage Vop2, and a potential of the second operating voltage Vop2 is higher than that of the first operating voltage Vop1. The first operating voltage Vop1 can have a higher potential than that of the ground voltage.

The row decoder 220 applies the operating voltage Vop generated by the voltage generating circuit 210 to the word lines of the selected memory block MB1. For example, the row decoder 220 may apply the first operating voltage Vop1 to a set erase pulse application loop from the plurality of erase pulse application loops 0 to K sequentially performed in the erase pulse application operating periods tERAPLS1 and tERAPLS2 and the second operating voltage Vop2 to the word lines from a next erase pulse application loop. A timing at which the operating voltage Vop is changed from the first operating voltage Vop1 to the second operating voltage Vop2 can be defined as a rising timing of the word line operating voltage. During the erasing operation, the memory cells are erased by the erasing voltage Vera applied to the source line SL and the first operating voltage Vop1 or the second operating voltage Vop2 applied to the word lines, and an erasing speed in a period in which the first operating voltage Vop1 is applied is faster than an erasing speed in a period in which the second operating voltage Vop2 is applied.

In step S720, the interrupt operation is performed during the erase operation. The storage device 1100 may receive the CMD command corresponding to the erase operation during the erase operation, and the control logic 300 stops the erase operation in response to the CMD command. Thereafter, the storage device 1100 may perform other general operations.

In step S730, the timing of the interrupt operation is determined.

With reference to 9 The erase operation may include a first period to a sixth period. The first period may be an initial period of the rise timing when the erase voltage increases, and the second period may be an end period of the rise period. The third period may be a time at which an initial erase pulse application loop of the plurality of erase pulse application loops is performed, that is, the first erase pulse application operation period tERAPLS1, and the fourth to sixth periods may be initial, intermediate or final periods of the second erase pulse -Application operation period tERAPLS2.

With reference to 8th The extinction characteristics of each period may differ from each other. The first period is the initial period of the rise period in which the erase voltage Vera rises and the erase operation is substantially not performed. Accordingly, the memory cells can have a normal erase characteristic even if the interrupt operation is repeatedly performed in the first period. The second period is a period in which the erase voltage Vera rises to a level next to the target level. The second period is a period in which the number of remaining erase pulses is not subtracted even if the interrupt operation is repeatedly performed because the erase pulse application loop is not performed. Accordingly, the memory cells can have a deep erase characteristic Deep ERS when the interrupt operation is repeatedly performed in the second period. When the interrupt operation is performed in the third period, the memory cells may have a shallow erase characteristic Shallow ERS. This is because if the interrupt operation and the resume operation are repeated in the initial erase pulse application loop <0> is performed, the erase pulse application operation is repeated briefly and thus the erase efficiency is reduced. As a result, the memory cells can have the shallow erase characteristic Shallow ERS. In each of the fourth to sixth periods, the memory cells may have the deep erase characteristic Deep ERS, a normal erase characteristic normal, and the shallow erase characteristic Shallow ERS. In the case of the fourth period, the number of erase pulse application loops subtracted based on the number of interrupt operations may be similar to that of the third period, but the first erase pulse application operation period tERAPLS1 may be repeatedly performed, and thus the memory cells have the depth Deep ERS extinguishing characteristic. In the case of the sixth period, when the interrupt operation is performed less than a predetermined number of times (eg, 60 times), the memory cells may have the shallow erase characteristic Shallow ERS. The word "predetermined" as used herein in reference to a parameter, such as a predetermined number of times, means that a value for the parameter is determined before the parameter is used in a process or algorithm. In some embodiments, the value for the parameter is determined before the process or algorithm begins. In other embodiments, the value for the parameter is determined during the process or algorithm, but before the parameter is used in the process or algorithm.

In step S740, the number of remaining erase pulses is set based on the specific timing at which the interrupt operation is performed.

For example, the control logic 300 calculates the number of subtractions based on the number of times the interrupt operation is performed and the setting ratio of the subtraction number corresponding to the time the interrupt operation is performed. In addition, the control logic 300 may adjust the number of remaining erase pulses by subtracting the calculated number of subtractions (x) from the number of unperformed erase pulse application loops.

Accordingly, a total number of erase pulse application loops (K) of the second erase pulse application operation period tERAPLS2 may be subtracted from the calculated number of subtractions (x), and the erase operation may be completed in a final erase pulse application loop (K-x).

With reference to 8th a plurality of periods of the erasing operation have different erasing characteristics, and in the third period and the sixth period corresponding to the flat erasing characteristic among the plurality of periods, the setting ratio of the subtraction number is set higher than that of the remaining periods. Accordingly, when the interrupt operation is performed in the third period and the sixth period corresponding to the flat erase characteristic, a number of subtractions smaller than the number of times the interrupt operation is performed can be calculated.

For example, if the interrupt operation is performed in the second, fourth, and fifth periods and the number of interrupt operations performed during the erase operation is 60, the control logic 300 may adjust the number of remaining erase pulses by subtracting 60 from the number of unperformed erase pulse application loops . On the other hand, if the interrupt operation is performed in the third period and the number of interrupt operations performed during the erase operation is 60, the control logic 300 may adjust the number of remaining erase pulses by taking the number of subtractions as 15 times on the basis the number of times the interruption operation is performed (60 times) and the setting ratio of the subtraction number (4:1), and the calculated number of subtractions (15 times) is subtracted from the number of erase pulse application loops not performed. Furthermore, when the interrupt operation is performed within the second erase pulse application operation period tERAPLS2 and the number of interrupt operations performed during the erase operation is less than 60, for example, interrupt operations are performed 20 times, the control logic 300 may control the number of remaining Erase pulses by calculating the number of subtractions as 5 times based on the number of times the interruption operation is performed (20 times) and the setting ratio of the subtraction number (4:1), and subtracting the calculated number of subtractions (5 times) from that Set the number of deletion pulse application loops not performed.

That is, when the interrupt operation is performed in the period corresponding to the flat erase characteristic, the number of remaining erase pulses can be adjusted by calculating the number of subtractions such that that it is less than the number of interrupt operations.

In step S750, the resume operation is performed to resume the stopped erase operation. During the resume operation, the stopped erase operation is resumed according to the number of remaining erase pulses set in the previous step S740 and the initially set rise timing of the word line operating voltage.

For example, the control logic 300 controls the source line driver 270 to sequentially proceed from the stopped erase pulse application loop and sequentially perform erase pulse application loops corresponding to the set number of remaining erase pulses.

In addition, the control logic 300 controls the voltage generation circuit 210 and the row decoder 220 to increase the first operating voltage Vop1 applied to the first and second word line groups GR1 and GR2 to the second operating voltage Vop2 and the second operating voltage Vop2 at the set rising time of the word line operating voltage to create.

According to the above-described second embodiment of the present disclosure, the number of remaining erase pulses can be set based on the number of interrupt operations, the timing at which the interrupt operation is performed, and the corresponding setting ratio of the subtraction number. That is, in one embodiment, when the interrupt operation is performed in the flat erase characteristic period, the number of remaining erase pulses may be adjusted by subtracting the number of interrupt operations smaller than the number of interrupt operations from the number not performed Erase pulse application loops is subtracted, thereby improving a threshold voltage distribution.

The above-described second embodiment of the present disclosure can be carried out in parallel with the above-described first embodiment of the present disclosure. That is, the stopped erase operation can be performed by controlling the rise timing of the operating voltage applied to the word lines based on the number of interrupt operations and the setting ratio as in the first embodiment, and the number of remaining erase pulses based on the number of interrupt operations. the timing at which the interruption operation is performed and the corresponding setting ratio of the subtraction number is set as in the second embodiment.

10 shows a flowchart illustrating a method of operating a storage device according to a third embodiment of the present disclosure.

11 Fig. 12 shows a waveform diagram of operating voltages illustrating a method of operating the memory device according to the third embodiment of the present disclosure.

The third embodiment of the present disclosure is explained with reference to 1 until 4 , 8th , 10 and 11 described as follows.

In step S1010, the delete operation is performed. The storage device 1100 receives the CMD command corresponding to the erase operation, and the control logic 300 controls the peripheral circuits 200 to perform the erase operation.

For example, during the erase operation, the source line driver 270 applies an erase voltage Vera to the source line SL connected to the selected memory block (e.g., MB1). The erase voltage Vera may gradually increase to a target level during a rising period, and then the erase voltage Vera of the target level may be applied to the source line SL during erase pulse application operation periods tERAPLS1 and tERAPLS2. The erase pulse application operation periods tERAPLS1 and tERAPLS2 may include a first erase pulse application operation period tERAPLS1, which includes a first erase pulse application loop <0>, and a second erase pulse application operation period tERAPLS2, which includes the remaining erase pulse application loops <1:K>.

The voltage generating circuit 210 generates the operating voltage Vop to be applied to the word lines of the selected memory block MB1. The operating voltage Vop may include a first operating voltage Vop1 and a second operating voltage Vop2, and a potential of the second operating voltage Vop2 is higher than that of the first operating voltage Vop1. The first operating voltage Vop1 may have a potential that is higher than that of a ground voltage.

The row decoder 220 applies the operating voltage Vop generated by the voltage generating circuit 210 to the word lines of the selected memory block MB1. For example, the row decoder 220 may apply the first operating voltage Vop1 to a set erase pulse application loop from the plurality of erase pulse application loops 0 to K that are sequentially performed in the erase pulse application operating periods tERAPLS1 and tERAPLS2 and the second operating voltage Vop2 to the word lines from a next erase pulse application loop. A timing at which the operating voltage Vop is changed from the first operating voltage Vop1 to the second operating voltage Vop2 can be defined as a rising timing of the word line operating voltage. During the erasing operation, the memory cells are erased by the erasing voltage Vera applied to the source line SL and the first operating voltage Vop1 or the second operating voltage Vop2 applied to the word lines, and an erasing speed in a period in which the first operating voltage Vop1 is applied is faster than an erasing speed in a period in which the second operating voltage Vop2 is applied.

In step S1020, the interrupt operation is performed during the erase operation. The storage device 1100 may receive the CMD command corresponding to the interrupt operation during the erase operation, and the control logic 300 stops the erase operation in response to the CMD command. Thereafter, the storage device 1100 may perform other general operations.

In step S1030, the timing of the interrupt operation or the number of interrupts is determined.

For example, control logic 300 determines the timing of the immediately previous interrupt operation. For example, as in 8th shown, the period in which the interrupt operation is performed is determined among the first to sixth periods. Additionally, the control logic 300 may count the number of times the interrupt operation performed during the current erase operation is performed.

The control logic 300 may adjust the number of erase pulses remaining by subtracting the number of times the interrupt operation is performed from the number of erase pulse application loops that are not performed due to the interrupt operation in the current erase operation.

If the number of times the interrupt operation is performed is 4, the control logic 300 may adjust the number of remaining erase pulses by subtracting four from the number of unperformed erase pulse application loops.

In step S1040, the offset value of the rise timing of each word line group is set based on the specific timing of the interrupt operation or the number of interrupts.

For example, the control logic 300 may determine the erase characteristics of the memory cells corresponding to each of the word line groups GR1 and GR2 based on the particular timing of the interrupt operation or the number of interrupts. For example, when it is determined that the memory cells corresponding to the first word line group GR1 have the flat erase characteristic based on the timing of the interrupt operation or the number of interrupts, the offset value of the first word line group GR1 may be set to a positive value (for example, + 5) can be set. If the offset value is a positive value, the rise timing of the word line group can be delayed by the number of clear pulse application loops corresponding to the offset value. For example, when it is determined that the memory cells corresponding to the second word line group GR2 have the deep erase characteristic based on the timing of the interrupt operation or the number of interrupts, the offset value of the second word line group GR2 can be set to a negative value (for example -2). When the offset value is the negative value, the rise timing of the word line group can be advanced by the number of erase pulse application loops corresponding to the offset value.

In step S1050, the resume operation is performed to resume the stopped erase operation.

The control logic 300 resets the rise timing of each word line group based on the offset value and proceeds according to the number of remaining erase pulses set in the previous step S1030 and the reset rise timing of the word line operating voltage.

For example, the control logic 300 controls the source line driver 270 to sequentially continue from the stopped erase pulse application loop and erase pulse application loops one after the other, which correspond to the set number of remaining deletion pulses.

In addition, the control logic 300 controls the voltage generation circuit 210 and the row decoder 220 to increase the first operating voltage Vop1 applied to the first and second word line groups GR1 and GR2 to the second operating voltage Vop2 and the second operating voltage Vop2 at the reset rising timing of the Apply word line operating voltage.

According to the above-described third embodiment of the present disclosure, the rising timing of the operating voltage applied to the word lines can be controlled based on the timing of the interrupt operation and the number of interrupt operations. That is, based on the timing of the interrupt operation and the number of interrupt operations, the rising timing of the operating voltage can be set to be delayed in the word line group corresponding to the memory cells in which the flat erase characteristic is likely to occur and the rising timing of the operating voltage can be set to advance in the word line group corresponding to the memory cells in which the deep erase characteristic is likely to occur. Accordingly, in one embodiment, the threshold voltage distribution of the memory cells can be improved.

The third embodiment described above can be carried out in parallel with the second embodiment described above. That is, the stopped erase operation can be performed by setting the number of remaining erase pulses based on the number of interrupt operations, the timing at which the interrupt operation is performed and the subtraction number setting ratio corresponding thereto, as in the second embodiment and the Rise timing of the operating voltage applied to the word lines is controlled based on the timing of the interrupt operation or the number of interrupt operations as in the third embodiment.

12 shows a diagram illustrating another embodiment of the storage system incorporating the in 2 storage device shown includes.

With reference to 12 The storage system 30000 can be implemented as a cell phone, smartphone, tablet PC, personal digital assistant (PDA) or as a wireless communication device. The storage system 30000 may include the storage device 1100 and the storage controller 1200 capable of controlling the operation of the storage device 1100. The memory controller 1200 may control a data access operation, for example, a program operation, an erase operation, or a read operation, of the storage device 1100 under the control of a processor 3100.

Data programmed into the memory device 1100 may be output via a display 3200 under the control of the memory controller 1200.

A radio transceiver 3300 can transmit or send and receive a radio signal via an antenna ANT. For example, the radio transceiver 3300 can convert a radio signal received via the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and transmit the processed signal to the memory controller 1200 or the display 3200. The memory controller 1200 may program the signal processed by the processor 3100 into the memory device 1100. In addition, the radio transceiver 3300 can convert a signal output from the processor 3100 into a radio signal and output the converted radio signal to an external device via the antenna ANT. An input device 3400 may be a device capable of inputting a control signal for controlling the operation of the processor 3100 or the data to be processed by the processor 3100. The input device 3400 may be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard. The processor 3100 may control an operation of the display 3200 such that data output from the storage device 1200, data output from the radio transceiver 3300, or data output from the input device 3400 are output via the display 3200.

According to one embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100 and may also be implemented as a chip separate from the processor 3100.

13 shows a diagram illustrating another embodiment of the storage system incorporating the in 2 storage device shown includes.

With reference to 13 The storage system 40000 can be used as a personal computer (PC), tablet PC, net book, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

The storage system 40000 may include the storage device 1100 and the storage controller 1200 capable of controlling a data processing operation of the storage device 1100.

A processor 4100 may output data stored in the storage device 1100 via a display 4300 according to data entered via an input device 4200. The input device 4200 can be implemented, for example, as a pointing device such as a touchpad or a computer mouse, a keypad or a keyboard.

The processor 4100 may control overall operation of the storage system 40000 and control the operation of the storage controller 1200. According to one embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or may be implemented as a chip separate from the processor 4100.

14 shows a diagram illustrating another embodiment of the storage system incorporating the in 2 storage device shown includes.

With reference to 14 The storage system 50000 may be implemented as an image processing device, for example a digital camera, a portable telephone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet PC equipped with a digital camera.

The storage system 50000 includes the storage device 1100 and the storage controller 1200 capable of controlling a data processing operation, such as a program operation, an erase operation, or a read operation, of the storage device 1100.

An image sensor 5200 of the storage system 50000 can convert an optical image into digital signals. The converted digital signals can be transmitted to a processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signals can be output via a display 5300 or stored in the storage device 1100 via the memory controller 1200. In addition, data stored in the storage device 1100 may be output via the display 5300 under the control of the processor 5100 or the memory controller 1200.

According to one embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 5100 or may be implemented as a chip separate from the processor 5100.

15 shows a diagram illustrating another embodiment of the storage system incorporating the in 2 storage device shown includes.

With reference to 15 The storage system 70000 can be implemented as a memory card or smart card. The storage system 70000 may include the storage device 1100, the storage controller 1200, and a card interface 7100.

The storage controller 1200 can control data exchange between the storage device 1100 and the card interface 7100. According to one embodiment, the card interface 7100 may be, but is not limited to, a Secure Digital (SD) card interface or a MultiMedia Card (MMC) interface.

The card interface 7100 may enable data exchange between a host 60000 and the storage controller 1200 according to a host 60000 protocol. According to one embodiment, the card interface 7100 may support a Universal Serial Bus (USB) protocol and an Interchip (IC) USB protocol. Here, the card interface may refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

When the storage system 70000 is connected to a host interface 6200 of the host 60000, such as a personal computer, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box, The host interface 6200 may perform data communication with the storage device 1100 via the card interface 7100 and the storage controller 1200 under the control of a microprocessor 6100.

Claims (30)

A memory device comprising: a memory block comprising a plurality of memory cells corresponding to a plurality of word line groups; a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation gene; a voltage generating circuit configured to apply an operating voltage increasing from a first operating voltage to a second operating voltage to the plurality of word line groups during the erase operation; and control logic configured to control the source line driver and the voltage generating circuit to perform an interrupt operation to stop the erase operation in response to an interrupt command, and configured to determine the number of remaining erase pulses of the erase operation and a rise timing at which the Operating voltage increases from the first operating voltage to the second operating voltage based on the number of times the interrupt operation is performed for each of the plurality of word line groups. Storage device after Claim 1 , wherein the control logic controls the source line driver and the voltage generation circuit to perform a resume operation for resuming the stopped erase operation after the interrupt operation. Storage device after Claim 2 , wherein the control logic sets the number of remaining erase pulses of the erase operation based on the number of times the interrupt operation is performed during the erase operation and controls the voltage generation circuit to perform an erase pulse application loop as many times as the number of remaining erase pulses during the resume operation . Storage device after Claim 3 , wherein the control logic sets the number of remaining erase pulses by subtracting the number corresponding to the number of interrupt operations from the number of erase pulse application loops that are not performed during the erase operation. Storage device after Claim 4 , wherein the control logic calculates a shortened period of each of the plurality of word line groups based on the number of interrupt operations and a setting ratio corresponding to each of the plurality of word line groups, and resets the rise timing of each of the plurality of word line groups by changing the initially set rise timing of the word line operating voltage advanced by the shortened period calculated for each of the plurality of word line groups. Storage device after Claim 5 , where the shortened period is equal to or shorter than a period corresponding to the number of interrupt operations. Method for operating a storage device, the method comprising: performing an erase operation on a memory block comprising a plurality of memory cells corresponding to a plurality of word line groups; performing an interrupt operation to stop the erase operation in response to an interrupt command received during the erase operation; setting a number of remaining erase pulses based on the number of times the interrupt operation is performed during the erase operation; setting a rise timing of an operating voltage applied to the word lines of the selected memory block for each of the plurality of word line groups during the erase operation based on the number of times the interrupt operation is performed and a setting ratio of each of the plurality of word line groups; and performing a resume operation to resume the stopped erase operation, performing an erase pulse application loop as many times as the number of remaining erase pulses during the resume operation, and increasing the operating voltage applied to the word lines from a first operating voltage to a second operating voltage at the set operating voltage rise time. Procedure according to Claim 7 wherein adjusting the number of remaining erase pulses comprises adjusting the number of remaining erase pulses by subtracting the number corresponding to the number of interrupt operations from the number of erase pulse application loops that are not performed due to the interrupt operation during the erase operation. Procedure according to Claim 8 wherein adjusting the rise timing of the operating voltage comprises: calculating a shortened period corresponding to each of the plurality of word line groups based on the number of interrupt operations and the adjustment ratio of each of the plurality of word line groups; and resetting the initially set rise timing of the word line operating voltage by the calculated shortened period of each of the plurality of word line groups. Procedure according to Claim 9 , where the shortened period is equal to or shorter than a period corresponding to the number of interrupt operations. Storage device comprising: a memory block including a plurality of memory cells corresponding to a plurality of word line groups; a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation; a voltage generating circuit configured to apply an operating voltage increasing from a first operating voltage to a second operating voltage to the plurality of word line groups during the erase operation; and a control logic configured to control the source line driver and the voltage generating circuit to perform an interrupt operation to stop the erase operation in response to an interrupt command, and configured to generate a number of remaining erase pulses of the erase operation for each of the plurality of word line groups on the Based on a time at which the interrupt operation is performed. Storage device after Claim 11 , wherein the control logic controls the source line driver and the voltage generation circuit to perform a resume operation for resuming the stopped erase operation after the interrupt operation. Storage device after Claim 12 , wherein the control logic controls the voltage generation circuit to perform an erase pulse application loop as many times as the number of remaining erase pulses during the resume operation. Storage device after Claim 11 , wherein the erasing operation includes a plurality of periods, and a sub-period among the plurality of periods is a period corresponding to a flat erasing characteristic. Storage device after Claim 14 , where if the time at which the interrupt operation is performed corresponds to the subperiod, the control logic calculates a number of subtractions using a setting ratio corresponding to the subperiod and the number of times the interrupt operation is performed. Storage device after Claim 15 , wherein the control logic sets the number of remaining erase pulses by subtracting the calculated number of subtractions from the number of erase pulse application loops that are not performed due to the interrupt operation during the erase operation. Storage device after Claim 15 , where the number of subtractions is equal to or less than the number of times the break operation is performed. Method for operating a storage device, the method comprising: performing an erase operation on a memory block comprising a plurality of memory cells corresponding to a plurality of word line groups; performing an interrupt operation to stop the erase operation in response to an interrupt command received during the erase operation; setting a number of remaining erase pulses based on a timing at which the interrupt operation performed during the erase operation is performed; and Performing a resume operation to resume the stopped erase operation and performing an erase pulse application loop as many times as the set number of remaining erase pulses. Procedure according to Claim 18 , wherein the erasing operation includes a plurality of periods, and a sub-period among the plurality of periods is a period corresponding to a flat erasing characteristic. Procedure according to Claim 19 , wherein adjusting the number of remaining erase pulses comprises: calculating a number of subtractions using an adjustment ratio corresponding to the subperiod and the number of times the interrupt operation is performed if the time at which the interrupt operation is performed corresponds to the subperiod; and adjusting the number of remaining erase pulses by subtracting the calculated number of subtractions from the number of erase pulse application loops not performed due to the interrupt operation during the erase operation. Procedure according to Claim 20 , where the number of subtractions is equal to or less than the number of times the break operation is performed. A memory device comprising: a memory block comprising a plurality of memory cells corresponding to a plurality of word line groups; a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation; a voltage generating circuit configured to apply an operating voltage increasing from a first operating voltage to a second operating voltage to the plurality of word line groups during the erase operation; and control logic configured to control the source line driver and the voltage generating circuit to perform an interrupt operation to stop the erase operation in response to an interrupt command, and configured to determine a rise timing at which the operating voltage is increased from the first operating voltage to the second Operating voltage for each of the plurality of word line groups increases based on at least one of a time at which the interrupt operation is performed and the number of times the interrupt operation is performed. Storage device after Claim 22 , wherein the control logic controls the source line driver and the voltage generation circuit to perform a resume operation for resuming the stopped erase operation after the interrupt operation. Storage device after Claim 23 , wherein the control logic sets a number of remaining erase pulses of the erase operation based on the number of times the interrupt operation is performed during the erase operation, and controls the voltage generating circuit to execute an erase pulse application loop as many times as the number of remaining erase pulses during the resume operation to carry out. Storage device after Claim 24 , wherein the control logic sets the number of remaining erase pulses by subtracting a number equal to the number of interrupt operations from a number of erase pulse application loops that are not performed during the erase operation. Storage device after Claim 25 , wherein the control logic determines an erasing characteristic of each of the plurality of word line groups based on the timing at which the erasing operation is performed or the number of times the erasing operation is performed, and an offset value of each of the plurality of word line groups according to the determined erasing characteristic sets. Storage device after Claim 26 , where the control logic resets an initially set rise time by advancing or delaying the rise time according to the offset value. Method for operating a storage device, the method comprising: performing an erase operation on a memory block comprising a plurality of memory cells corresponding to a plurality of word line groups; performing an interrupt operation to stop the erase operation in response to an interrupt command received during the erase operation; setting a number of remaining erase pulses based on the number of times the interrupt operation is performed during the erase operation; setting a rise timing of an operating voltage applied to word lines of the selected memory block for each of the plurality of word line groups during the erase operation based on at least one of the timing at which the interrupt operation is performed and the number of times the interrupt operation is performed; and performing a resume operation to resume the stopped erase operation, performing an erase pulse application loop as many times as the number of remaining erase pulses during the resume operation, and increasing the operating voltage applied to the word lines from a first operating voltage to a second operating voltage at the set operating voltage rise time. Procedure according to Claim 28 wherein adjusting the number of remaining erase pulses comprises adjusting the number of remaining erase pulses by subtracting a number corresponding to the number of interrupt operations from the number of erase pulse application loops not performed due to the interrupt operation during the erase operation. Procedure according to Claim 29 , wherein adjusting the rising timing of the operating voltage comprises: determining an erasing characteristic of each of the plurality of word line groups based on at least one of the timing at which the erasing operation is performed, and the Number of times the delete operation is performed; setting an offset value of each of the plurality of word line groups based on the determined erasure characteristic; and resetting the initially set rise timing of the operating voltage by advancing or delaying the rise timing according to the offset value.

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