DE102022214193A1 - Method and device for operating an error counter in a technical system - Google Patents

Abstract

The invention relates to a method for operating an error memory in a technical system, with the following steps:- Regularly carrying out (S1) a check to detect an error event;- Incrementing (S2) an error event counter (FE) and an error count counter (FA) in an error memory (24) when the error event is detected;- Decrementing (S5) the error event counter (FE) if it is not equal to 0 and the check has not resulted in an error event, wherein the error memory (24) corresponds to a data unit with several bits that can be processed jointly by a processor of the technical system (1), so that a number of bits are assigned to each of the counters, wherein the incrementing of the error event counter (FE) and the error count counter (FA) is carried out by adding a value to the value of the error memory (24), which value results from the values of the low-order bit positions of the error event counter (FE) and the error count counter (FA);- When a error event threshold (S) by the error event counter (FE), performing error handling;- performing (S4) a diagnosis using the value of the error count counter (FA).

Description

Technical area

The invention relates to technical systems with diagnostic devices for detecting errors, and in particular to methods for signaling error handling.

Technical background

Technical systems usually have diagnostic functions that are used to implement various safety mechanisms. Control units in which the diagnostic functions are implemented can implement question/answer communication as a safety mechanism, such as that which exists between a control unit and an external watchdog. The external watchdog ensures the transition to a safe state of the technical system if an error is detected in the control unit.

In real systems, internal and external influences and disturbances can lead to the detection of an error. To prevent an error from being detected incorrectly (false positive), error handling is not started immediately when a specific error event is detected for the first time, but only after the occurrence of a certain number of consecutive error events has been detected. An error event counter is usually implemented for this purpose. The error event counter is operated by incrementing it when error events are detected in corresponding consecutive checks, and by decrementing it if it has a value other than 0 and a check has not revealed an error. The error event counter is therefore incremented when an error event is detected and decremented if the error event counter is not zero and a check has not revealed an error.

Disclosure of the invention

According to the invention, a method for operating an error event counter according to claim 1 and a device with an error event counter according to the independent claim are provided.

Further embodiments are specified in the dependent claims.

• - Regelmäßiges Durchführen einer Überprüfung zum Erkennen eines Fehlerereignisses;
• - Inkrementieren eines Fehlerereigniszählers und eines Fehleranzahlzählers in einem Fehlerspeicher bei Erkennen des Fehlerereignisses;
• - Dekrementieren des Fehlerereigniszählers, wenn dieser ungleich 0 ist und die Überprüfung kein Fehlerereignis ergeben hat, wobei der Fehlerspeicher einer durch einen Prozessor gemeinsam verarbeitbaren Dateneinheit, insbesondere in einem Byte, einem Wort oder einem Doppelwort, entspricht, so dass jedem der Zähler eine Anzahl von Bits zugeordnet sind, wobei das Inkrementieren des Fehlerereigniszählers und des Fehleranzahlzählers durchgeführt wird, indem zu dem Wert des Fehlerspeichers ein Wert addiert wird, der sich aus den Wertigkeiten der niederwertigen Bitpositionen des Fehlerereigniszählers und des Fehleranzahlzählers ergeben;
• - Bei Erreichen eines Fehlerereignisschwellenwerts durch den Fehlerereigniszähler, Durchführen einer Fehlerbehandlung;
• - Durchführen einer Diagnose mithilfe des Werts des Fehleranzahlzählers.

According to a first aspect, a method for operating an error memory in a technical system is provided, comprising the following steps:

• - Performing a check regularly to detect an error event;
• - Incrementing an error event counter and an error count counter in an error memory when the error event is detected;
• - decrementing the error event counter if it is not equal to 0 and the check has not resulted in an error event, wherein the error memory corresponds to a data unit that can be processed jointly by a processor, in particular in a byte, a word or a double word, so that a number of bits are assigned to each of the counters, wherein the incrementing of the error event counter and the error count counter is carried out by adding to the value of the error memory a value that results from the values of the least significant bit positions of the error event counter and the error count counter;
• - When the error event counter reaches an error event threshold, perform error handling;
• - Performing a diagnosis using the value of the error count counter.

As described above, error event counters are used to accumulate the number of individual error events and to decrement them when no errors are detected. The detection of individual error events therefore does not immediately trigger error handling. The error event counter is used accordingly to accumulate error events and to trigger an associated error handling when an error event threshold is exceeded or reached. However, the diagnostic capabilities are limited by a single error event counter because it cannot be determined how many error events have occurred in total, i.e., for example, over the entire lifespan of the system, that do not trigger error handling.

The fault event counter is used for detecting problems in the system and for diagnostics. The value of the fault event counter can be read periodically or only at the end of a system active working time to obtain information about problems in the safety system. Preferably, the value of the fault event counter must be low and stable (ideally the permanent zero) when no problems are detected in the system.

Therefore, a periodic or continuous reading of the error event counter provides current information about possible or upcoming safety problems in a system. If the counter value is low at the end of the system active working time, rig, this indicates that the system is in good condition.

Sporadic error events that only occur individually do not usually trigger error handling, but can indicate a problem in the technical system, in particular a slowly developing error.

Error handling is triggered when the error event counter exceeds the error event threshold, i.e. the frequency of detecting an error is too high. Error handling can include safety measures where the system stops or is brought into a safe state.

The error event counter can have a bit depth of 1 to 3 and the error count counter can have a bit depth in the number of remaining bits.

The error event threshold is usually chosen as a single-digit number of between 2 and 7 error events, so that in an 8-, 16- or 32-bit system, a corresponding error register or error memory for the error event counter is not fully used. In particular, with an error event threshold for the error event counter, only one to three bits are needed to implement the counter. The remaining bits are not used further in the usual way.

In this regard, it is intended to use the additional bits of the error register or the error memory to accumulate the total number of detected error events as the number of errors. This makes it possible to provide an additional diagnostic option without additional memory space being required or having to be provided in a control unit of the technical system.

According to the above method, an error register or error memory is operated in such a way that the number of consecutive error events can be determined using an error event counter in order to regularly compare this with the error event threshold value, and on the other hand the total number of errors of the error events that have occurred is made available in an error count counter for diagnostic purposes. This is achieved in that when an error event occurs, a single manipulation of the error memory, which implements both the error event counter and the error count counter, is sufficient or can be carried out. A value that results from the significance of the least significant bit position of the error event counter and the least significant bit position of the error count counter is added to the value stored in the error memory.

For example, if the first three bits (B0, B1, B2) of an 8-bit error memory are assigned to an error event counter and the subsequent bits (B3, B4, B5, B6, B7) are assigned to an error count counter, the value to be added when an error event occurs is 2 ³ + 2 ⁰ = 9, where 3 and 0 correspond to the corresponding least significant bit positions of the error count counter and the error event counter, respectively.

This approach is also possible with a different arrangement of the bits for the error event counter and the error count counter within the error memory. In this way, the total number of error events and the number of immediately consecutive error events can be monitored within a single error memory, providing additional diagnostic options to evaluate the sporadic occurrence of error events.

The error handling may include bringing one or more components of the technical system into a safe state or shutting down one or more of the components of the technical system depending on the counter value of the error event counter.

In particular, the event triggered by the error handling (safe state, shutdown, etc.) can be determined depending on the counter value of the error count counter.

Performing the diagnosis may include a threshold comparison of the total number of errors in the error count counter, whereby a warning is signaled if the number of errors exceeds a threshold.

Short description of the drawings

• 1 eine schematische Darstellung eines technischen Systems mit einer Steuereinheit;
• 2 ein Flussdiagramm zur Veranschaulichung eines Verfahrens zur Diagnose von Funktionen in dem technischen System und zum Betreiben und Auswerten eines Fehlerzählers; und
• 3 eine schematische Darstellung eines Fehlerspeichers mit einem Fehlerereigniszähler und einem Fehleranzahlzähler.

Embodiments are explained in more detail below with reference to the attached drawings. They show:

• 1 a schematic representation of a technical system with a control unit;
• 2 a flow chart illustrating a method for diagnosing functions in the technical system and for operating and evaluating an error counter; and
• 3 a schematic representation of an error memory with an error event counter and an error count counter.

Description of embodiments

1 shows schematically a technical system 1, such as a vehicle system, with a control unit 2 in which a microprocessor 21 or microcontroller is used. Diagnostic functions for diagnosing system functions of the technical system 1 are implemented in the control unit 1. System functions of the technical system 1 can include hardware functions of hardware components 3 external to the control unit, such as sensors or actuators, as software functions that are implemented in the control unit 2 and are intended for execution in the microprocessor or microcontroller, and functionalities of other hardware components implemented in the control unit 2, such as memory components 21, analog/digital converter 22, processor 23 and the like.

The diagnostic functions check individual system functions in a suitable manner and assign an error memory 24 to each monitored system function. The error memory can be provided in the form of a register in order to store a data unit, e.g. in the form of a byte, a word or a double word.

As in 3 Represented using a byte-sized error memory, the error memory is divided into two areas, each of which is assigned a number of bits. The error memory has an error event counter FE, which in the present embodiment is implemented by bits 0, 1, 2. The three bits of the error memory 24 enable consecutive error events to be counted up to the value 7. With the aid of a predetermined error event threshold value S, it can be recognized in a comparison unit 25 whether a certain number of consecutive error events has reached or exceeded the predetermined error event threshold value S.

The error memory may also have an error count counter FA to accumulate the total number of detected error events. This is represented by bits 3 - 7.

In 2 A method is shown in a flow chart as it can be provided for operating the diagnostic function in the control unit 2.

In step S1, it is checked whether a check has detected an error event. If an error event is detected (alternative: yes), a predetermined value is added to the entry in the error memory in step S2. The value corresponds to a sum of the values of the bit positions in the error memory at which the least significant bit is located for the error event counter FE and the error count counter FA. In the present exemplary embodiment, the error event counter FE has three bits and the error count counter FA has the remaining five bits. Thus, by adding the value 9, both the error event counter FE and the error count counter FA can be incremented.

In step S3, it is checked whether the error event counter FE has reached a predefined error event threshold value S. If this is the case (alternative: yes), error handling is started in step S4. Otherwise (alternative: no), the system returns to step S1.

The error handling of step S4 may include bringing all or individual system components into a safe state or deactivating them.

If it is determined in step S1 that the diagnostic function has not resulted in an error (alternative: no), the error event counter is decremented by a reset value of 1 in step S5 if this has a value greater than 0. This means that only the least significant bit of the error event counter is decremented. Subtracting the reset value only reduces the value of the error event counter FE, but not the value of the error count counter FA. A value is therefore available as the error count counter FA that indicates the total number of error events that have occurred, even if these do not lead to error handling.

The process then returns to step S1.

Claims (9)

Method for operating an error memory in a technical system, with the following steps: - Regularly carrying out (S1) a check to detect an error event; - Incrementing (S2) an error event counter (FE) and an error count counter (FA) in an error memory (24) when the error event is detected; - Decrementing (S5) the error event counter (FE) if it is not equal to 0 and the check has not resulted in an error event, wherein the error memory (24) corresponds to a data unit with several bits that can be processed jointly by a processor of the technical system (1), so that a number of bits are assigned to each of the counters, wherein the incrementing of the error event counter (FE) and the error count counter (FA) is carried out by adding to the value of the error memory (24) a value which results from the significances of the least significant bit positions of the error event counter (FE) and the error count counter (FA); - When an error event threshold value (S) is reached by the error event counter (FE), carrying out an error treatment; - carrying out (S4) a diagnosis using the value of the error count counter (FA). Procedure according to Claim 1 , wherein the error event counter (FE) has a bit depth of 1 to 4, in particular 2 or 3, and the error number counter (FA) has a bit depth in the number of remaining bits of the data unit. Procedure according to Claim 1 or 2 , wherein the error memory (24) is designed as an error register. Method according to one of the Claims 1 until 3 , wherein the error handling comprises bringing one or more components of the technical system (1) into a safe state or switching off one or more of the components of the technical system (1). Method according to one of the Claims 1 until 4 , wherein performing a diagnosis comprises a threshold value comparison of the total number of errors of the error count counter (FA), wherein a warning is signaled if the number of errors exceeds a threshold value. Method according to one of the Claims 1 until 5 , where the data unit that can be processed jointly by the processor corresponds to a byte, a word or a double word. Device, in particular control unit (2), which is designed to carry out a method according to one of the Claims 1 until 6 to execute. Computer program product comprising instructions which, when the program is executed by at least one data processing device, cause the device to carry out the steps of the method according to one of the Claims 1 until 6 to execute. Machine-readable storage medium comprising instructions which, when executed by at least one data processing device, cause the device to carry out the steps of the method according to one of the Claims 1 until 6 to execute.

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