DE102022207860A1 - DIGITAL HF DAC SIGNAL MODULATION - Google Patents

Abstract

A clock generator may generate clock signals for a digital front-end that includes a digital signal modulator that generates modulated digital values that include quadrature representations of a radar modulation signal that are encoded by a high-frequency digital-to-analog converter (RF-DAC). The analog RF DAC signal can be upconverted to a radar frequency and transmitted. A receiver can receive, down-convert and analyze a reflection of the radar transmission, e.g. B. to perform range finding based on a frequency ramp encoded by the radar transmission.

Description

TECHNICAL SUBJECT

The present disclosure relates to the field of signal processing and more particularly to the modulation of radar signals.

BACKGROUND

In the field of signal processing, many scenarios involve the generation, transmission, acquisition and/or analysis of signals in the radar frequency range, such as 1 gigahertz to 100 gigahertz. Signals in this range can be generated by generating a reference frequency using an oscillator such as a crystal or digitally controlled oscillator (DCO) and frequency up-converting, e.g. B. by mixing a signal with an initial (low) frequency with a mixing frequency to produce a higher frequency signal at approximately the sum of the initial frequency and the mixing frequency. The application of a series of frequency up-conversion stages can enable the reference frequency signal to be converted into a radar frequency signal that can be amplified by a power amplifier and transmitted via an antenna. Correspondingly, a radar signal detected at a radar frequency can be received and converted through a series of down-conversion stages, e.g. B. by mixing a signal with an initial (high) frequency and a mixed frequency to produce a lower frequency signal approximately equal to the difference between the initial frequency and the mixed frequency. Down-conversion allows the received signal to be down-converted to a low frequency suitable for analysis.

In many scenarios, the generated signal encodes information through modulation, such as amplitude modulation, frequency modulation, and/or phase modulation. The radar transmission provides a carrier for the information in a radar frequency range and the received signal may be converted to a lower frequency to enable detection of the information encoded by the radar carrier signal. An application example: Radar signals are often used to measure distances, e.g. B. by transmitting a radar signal, receiving a reflection of the transmitted radar signal and multiplying the transmission delay by the transmission speed through the medium. When the radar signal is transmitted continuously, the correlation of the transmitted periodic signal with the received reflection of the periodic signal depends on the signal modulation. One such modulation technique is frequency-modulated continuous-wave (FMCW) radar ranging, in which the frequency of the transmitted radar signal increases over a range of frequencies. The correlation of the ramp frequency of the transmitted signal with the ramp frequency of the received signal enables an accurate transit time determination and a correspondingly accurate distance determination.

SUMMARY

In one embodiment, a method for detecting a range at a radar frequency is provided. The method includes performing a conversion of a timing signal to an analog signal by generating, corresponding to the timing signal, a first digital value and a second digital value based on a random phase value and converting the first digital value and the second digital value with a high frequency Digital-to-analog converter for generating the analog signal, wherein the first digital value and/or the second digital value correspond to a quadrature representation of a radar modulation signal. The method includes applying the conversion to generate a transmit signal at the radar frequency. The method includes combining the transmit signal and a receive signal that includes a reflection of the transmit signal to determine the distance.

Generating the first digital value and the second digital value may include combining the random phase value with a first cyclic digital value to generate a third digital value, the first digital value being based on the third digital value and combining the random phase value with a second cyclic digital value for generating a fourth digital value, wherein the second digital value is based on the fourth digital value.

In some examples, generating the first digital value and the second digital value includes generating the first digital value as a sine of the third digital value and generating the second digital value as a cosine of the fourth digital value.

In some examples, generating the first digital value and the second digital value includes generating an increasing digital value, integrating the increasing digital value with a first integrator to produce the first cyclic digital value, and integrating the increasing digital value with a second Integrator for generating the second cyclic digital value.

In some examples, the radar modulation signal includes a frequency ramp, where the random phase value is an initial random phase value, and combining the random phase value with the first cyclic digital value and combining the random phase value with the second cyclic digital value are performed at the beginning of the frequency ramp.

According to some examples, the radar modulation signal includes a frequency ramp.

In one embodiment, a ramp generator device is provided that includes a phase-locked loop that provides a timing signal. The ramp generator device includes a clock generator that converts the timing signal into a plurality of clock signals including one or more first clock signals and one or more second clock signals. The ramp generator device comprises a digital ramp generator that generates a first digital value and a second digital value based on a random phase value using the one or more first clock signals, the first digital value and/or the second digital value being a quadrature representation of a ramp modulation signal are equivalent to. The ramp generator device includes a high frequency digital to analog converter that converts the first digital value and the second digital value to generate a high frequency analog signal comprising a frequency ramp using the one or more second clock signals.

According to some examples, the ramp generator device comprises a phase-locked loop that provides a clock signal, a clock generator that converts the clock signal into a plurality of clock signals that include one or more first clock signals and one or more second clock signals, a digital ramp generator that uses the one or the plurality of first clock signals generates a first digital value and a second digital value based on a random phase value, at least one of the first digital value and the second digital value corresponding to a quadrature representation of a ramp modulation signal, and a high-frequency digital-to-analog converter, converting the first digital value and the second digital value to generate a high frequency analog signal comprising a frequency ramp using the one or more second clock signals.

The digital ramp generator may include a first combination module that combines the random phase value with a first cyclic digital value to generate a third digital value, the first digital value being based on the third digital value, and a second combination module that combines the random phase value with a combining a second cyclic digital value to generate a fourth digital value, the second digital value being based on the fourth digital value.

According to some examples, the digital ramp generator includes: a first digital generator that generates the first digital value as a sine of the third digital value, and a second digital generator that generates the second digital value as a cosine of the fourth digital value.

According to some examples, the ramp generator includes a first integrator that generates an increasing digital value, a second integrator that integrates the increasing digital value to generate the first cyclic digital value, and a third integrator that integrates the increasing digital value to generate the second cyclic digital value integrated.

According to some examples, the random phase value is an initial random phase value and the first combining module combines the random phase value with the first cyclic digital value and the second combining module combines the random phase value with the second cyclic digital value at the beginning of the frequency ramp.

In one embodiment, a method for detecting a range at a radar frequency is provided. The method includes performing a conversion of a timing signal to an analog signal by generating a first cyclic digital value, truncating, using a first quantizer, first bits indicative of the first cyclic digital value to second bits indicative of a first truncated cyclic digital value value, generating a first digital value based on a first quantization error of the first quantizer and a second value, combining the first digital value with the first truncated cyclic digital value to generate a third digital value, generating according to the timing signal a fourth digital value value based on the third digital value, generating a second cyclic digital value, clipping using a second quantizer, generating a second cyclic digital value, clipping using a second quantizer from third bits indicating the second cyclic digital value to fourth bits indicating a second truncated cyclic digital value producing a five th digital value based on a second quantization error of the second quantizer and a sixth value, combining the fifth digital value with the second truncated cyclic digital value to generate a seventh digital value, generating, corresponding to the timing signal, an eighth digital value based on the seventh digital value, and converting the fourth digital value and the eighth digital value with a high-frequency digital-to-analog converter to generate the analog signal, the fourth digital value and/or the eighth digital value corresponding to a quadrature representation of a radar modulation signal. The method includes applying the conversion to generate a transmit signal at the radar frequency. The method includes combining the transmit signal and a receive signal that includes a reflection of the transmit signal to determine the distance.

In some examples, the method includes generating an increasing digital value, wherein generating the first cyclic digital value includes integrating the increasing digital value using a first integrator to generate the first cyclic digital value, and generating the second cyclic digital value includes integrating of the increasing digital value using a second integrator to generate the second cyclic digital value.

According to some examples, generating the fourth digital value includes generating the fourth digital value as a sine of the third digital value, and generating the eighth digital value includes generating the eighth digital value as a cosine of the seventh digital value.

According to some examples, the second value is at least one of a first random value or a first noise-shaped value and the sixth value is at least one of a second random value or a second noise-shaped value.

In one embodiment, a ramp generator device is provided that includes a phase-locked loop that provides a timing signal. The ramp generator device includes a clock generator that converts the timing signal into a plurality of clock signals including one or more first clock signals and one or more second clock signals. The ramp generator device includes a digital ramp generator that generates a first digital value and a second digital value using the one or more first clock signals. The digital ramp generator includes a first quantizer that truncates first bits indicative of a first cyclic digital value to second bits indicative of a first truncated cyclic digital value, a first noise shaping module that calculates a third digital value based on a first quantization error of the a first quantizer and a fourth value, a first combining module combining the third digital value with the first truncated cyclic digital value to produce a fifth digital value, a second quantizer combining third bits indicative of a second cyclic digital value onto fourth truncates bits indicating a second truncated cyclic digital value, a second noise shaping module that generates a sixth digital value based on a second quantization error of the second quantizer and a seventh value, and a second combining module that generates the combines the sixth digital value with the second truncated cyclic digital value to produce an eighth digital value. The first digital value is based on the fifth digital value. The second digital value is based on the eighth digital value. The first digital value and/or the second digital value correspond to a quadrature representation of a ramp modulation signal. The ramp generator device includes a high frequency digital to analog converter that converts the first digital value and the second digital value to generate a high frequency analog signal comprising a frequency ramp using the one or more second clock signals.

According to some examples, the digital ramp generator includes a first integrator that generates an increasing digital value and a second integrator that integrates the increasing digital value to generate the first cyclic digital value and a third integrator that integrates the increasing digital value to generate the second cyclic digital value integrated.

According to some examples, the digital ramp generator includes a first digital generator that generates the first digital value as a sine of the fifth digital value and a second digital generator that generates the second digital value as a cosine of the eighth digital value.

According to some examples, the fourth value is a first random value and the seventh value is a second random value.

According to some examples, the fourth value is a first noise-shaped value and the seventh value is a second noise-shaped value.

In one embodiment, a method for detecting a range at a radar frequency is provided. The method includes performing a conversion of a timing signal to an analog signal by generating, corresponding to the timing signal, a first digital value and a second digital value that are quadrature representations of a radar modulation signal, and converting the first digital value and the second digital value at a radio frequency -Digital to analog converter to generate the analog signal. The method further includes applying the conversion to generate a transmit signal at the radar frequency. The method further includes comparing the transmit signal and a receive signal that includes a reflection of the transmit signal to determine a distance.

In one embodiment, a radar modulation signal generator is provided that includes a phase locked loop that provides a timing signal. The radar modulation signal generator further includes a clock generator that converts the timing signal into a first clock signal and a second clock signal. The radar modulation signal generator further includes a digital signal modulator that uses the first clock signal to generate a first digital value and a second digital value that are quadrature representations of a modulation signal having a modulation frequency. The radar modulation signal generator further includes a radio frequency digital to analog converter that converts the first digital value and the second digital value to generate a radio frequency signal using the second clock signal. The radar modulation signal generator further includes a transmitter that generates a transmit signal at the radar frequency based on the radio frequency signal. The radar modulation signal generator also includes a receiver that receives a reflection of the transmission signal. The radar modulation signal generator further includes a range finder that compares the reflection and the radio frequency signal to determine a range.

In one embodiment, a ramp generator device is provided that includes a phase-locked loop that provides a timing signal. The ramp generator device further includes a clock generator that converts the timing signal into a first clock signal and a second clock signal. The ramp generator device further includes a digital ramp generator that generates, at the first clock signal, a first digital value and a second digital value that are quadrature representations of a ramp modulation signal. The ramp generator device further includes a high frequency digital to analog converter that converts the first digital value and the second digital value to generate a high frequency analog ramp signal using the second clock signal.

In order to achieve the foregoing and related purposes, certain aspects and embodiments are illustrated in the following description and accompanying drawings. These are just a few examples of the different ways one or more Aspects can be used. Other aspects, advantages, and novel features of the disclosure will become apparent from the following detailed description when considered in connection with the accompanying drawings.

character list

• 1 Figure 12 is an illustration of an example scenario involving generation and transmission of a frequency modulated radar signal and detection of a reflected signal to determine range to an object.
• 2 12 is an illustration of an example scenario involving generation and transmission of a frequency modulated radar signal and detection of a reflected signal to determine the range to an object according to the techniques presented herein.
• 3 Figure 12 shows an example of a method for measuring distances at a radar frequency according to the techniques presented here.
• 4 12 is a component block diagram showing an example radar modulation signal generator in accordance with the techniques presented herein.
• 5 FIG. 14 is a component block diagram depicting an example radar generator apparatus in accordance with the techniques presented herein.
• 6 Figure 12 is a component block diagram showing an example scenario for generating a modulated digital signal according to the techniques presented herein.
• 7A-7C are data sets illustrating the generation of a modulated digital signal using a high frequency digital-to-analog encoder with digital values representing quadrature representations of a modulated radar signal with a variable bit resolution according to the techniques presented herein.
• 8th Figure 12 shows an example of a method for measuring distances at a radar frequency according to the techniques presented here.
• 9A-9B 12 are component block diagrams showing an example of a digital signal modulator according to the techniques presented herein.
• 1 0A-10B show an example of a method for ranging at a radar frequency according to the techniques presented herein.
• 11 Figure 12 is a component block diagram showing an example digital signal modulator in accordance with the techniques presented herein.
• 12A-12B 12 are component block diagrams showing noise shaping modules according to the techniques presented herein.
• 13 Figure 12 is a component block diagram showing an example digital signal modulator in accordance with the techniques presented herein.
• 14 is a data set showing intermediate signals according to the techniques presented here.
• 15A-15B are spectrograms showing ramp signals according to the techniques presented here.
• 16 is a data set showing the outputs of high-frequency digital-to-analog converters (HF-DAC) according to the techniques presented here.
• 17 is a data set showing intermediate signals according to the techniques presented here.
• 18 is a data set showing intermediate signals according to the techniques presented here.
• 19 is a data set showing intermediate signals according to the techniques presented here.

DETAILED DESCRIPTION

The claimed subject matter will now be described with reference to the drawings, in which like reference numbers refer to like elements throughout. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it should be apparent that the claimed subject matter may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate the description of the claimed subject matter.

A. Introduction

In the field of signal processing, many scenarios involve the generation, transmission, detection and/or processing of an electromagnetic signal in a radar range of frequencies, such as 1 gigahertz to 100 gigahertz. The signal can be generated by an oscillator at a reference frequency and then upconverted using various techniques, such as mixing, to a radar frequency that is amplified and transmitted through an antenna. During the signal generation process, some form of modulation can be applied to adjust the radar signal. It embeds a variable element that serves as information to be transmitted by a carrier at the radar frequency. In some examples, the modulation can be frequency modulation over a range of frequencies; amplitude modulation over a range of amplitudes; and/or phase modulation over the phase of a periodic signal. The transmission at the radar frequency can be picked up by a receiving antenna, decimated to a manageable frequency and evaluated to detect the modulation of the signal carrying the transmitted information.

1 12 is an illustration of an example scenario 100 in which a radar signal is used to determine a distance 140 between a transmitter 124 and a receiver 132 and an object 128 reflecting the radar signal 126, and where the distance 140 is based on a time-of-flight measurement and the speed of the radar signal 126 in the medium between the transmitter 124 and the object 128 is determined. In many such scenarios, the radar signal 126 is continuous and periodic, and in addition to receiving a received signal 130 that includes a reflection of the radar signal 126, a range finder must be able to correlate the periodic cycles of the received signal 130 with the transmitted periodic cycles. One such technique is frequency modulated continuous wave (FMCW) radar ranging, in which a periodic radar signal 126 is continuously transmitted but steadily increasing in frequency via an increasing frequency ramp and decreasing periodicity. The frequency of the received signal 130 can then be correlated with the frequency of the transmitted radar signal 126 to determine the propagation time of the radar signal 126 . Such techniques allow the radar signal 126 to be transmitted continuously, resulting in a high-resolution time-of-flight sample that allows an accurate determination of the range 140 of the object 128 and optionally other properties such as velocity, acceleration, direction, and the Allows reflections from objects 128 to be distinguished from spurious signals and noise.

As in the example scenario 100 of 1 Also illustrated, generating the radar signal 126 includes modulating the signal to generate the frequency ramp in the following manner. A local oscillator 102, such as a crystal oscillator or a voltage controlled oscillator (VCO), generates a reference frequency 104 that is provided to a phase-locked loop 106. FIG. A frequency divider 114 with multiple modulus feedback switches on a selected switching schedule to change the phase of the reference signal (e.g., inverting the signal during switching) to approximate a higher frequency signal. A phase frequency detector 108 receives both the reference frequency 104 and the switched output of the frequency divider 114 with multi-module feedback and detects a phase difference, and a charge pump 110 provides a voltage offset translating the reference frequency 104 based on a phase difference. Mixing the reference frequency 104 with the output of the frequency divider 114 with multiple modulus feedback produces images of the reference frequency 104 at multiple image frequencies, and a loop filter 112 (e.g., a bandpass filter) attenuates the images at undesired frequencies, to that end generate an output signal at the higher frequency selected by frequency divider 114 with multi-modulus feedback. One or more stages of further upconversion, such as mixing with higher frequency signals, may further frequency increase the generated signal to a radar frequency 120, such as 1 gigahertz to 100 gigahertz, which is amplified by a power amplifier 122 and transmitted by a transmitter 124, such as an antenna, can be sent.

The modulation of the radar signal in this path is achieved through control of the frequency divider 114 with multi-module feedback, which allows the switching to occur at a selectable fraction of the reference frequency 104 period. The selection is made by a frequency ramp generator 116 that produces a steadily increasing value, such as a digital counter, and a sigma-delta modulator that signals the frequency divider 114 with multiple modulus feedback when integrating the steadily increasing value exceeds a delta threshold relative to the previous signal. The integration of the steadily increasing value causes the sigma-delta modulator to signal the frequency divider 114 with multi-modulus feedback at an increasing rate, gradually increasing the switching schedule and increasing the frequency of the generated radar frequency 120 by incremental fractions of the reference frequency 104. The frequency ramp generated by frequency ramp generator 116 may increase over a range of frequencies and reset periodically.

The modulation of the radar signal with the frequency ramp can support the evaluation of the received signal 130 and the determination of the distance 140 in the following way. The received signal 130 may be received by a receiver 132, such as a receiving antenna, and down-converted from the radar frequency 120 to a frequency range suitable for further evaluation. The down-converted signal is processed by a signal evaluator 134 which correlates the frequency of the received signal 130 with the frequency of the frequency ramp generator 116 . A range finder 136 can determine a distance to an object it is detecting and the speed of the object. In addition, the transmitter 124 components and receiver 132 components can be operated at a high sampling rate to provide an accurate series of range measurements that can be used to verify range 138; detect range 138 with high accuracy; detect changes in distance 138 indicative of the speed, acceleration, and/or direction of object 128; and/or to distinguish detection of object 128 from false detection, such as due to noise, interference, and/or signal images.

In this manner, the switching of frequency divider 114 with multi-modulus feedback by frequency ramp generator 116 allows frequency modulation of radar signal 126 at an incrementally increasing fraction of the period of reference frequency 104 that approaches an ideal frequency ramp 140 . However, several characteristics of this technique can cause the frequency ramp 142 achieved to deviate from the ideal frequency ramp 140 . A first example: the modulation by the phase frequency detector 108 and the charge pump 110 exhibits a delay as the modulation signal propagates through the phase-locked loop; ie the phase frequency detector 108 and the charge pump 110 gradually adapt the reference frequency 104 to the instantaneous value of the ideal frequency ramp 140 . As a result of the dynamic properties of the phase-locked loop 106, the frequency ramp 142 achieved tends to alternate between exceeding the ideal frequency ramp 140 and falling below the ideal frequency ramp 140. The discrepancy can affect the accuracy of the correlation achieved by the signal evaluator 134 and thus the achievable accuracy of the transit time determined by the transit time determiner 136 and the affect distance 140 determined by distance determiner 138. As a second example, the fractional switching of the frequency divider 114 with multiple modulus feedback results in discontinuities that appear as fractional excursions in the frequency spectrum of the modulated radar frequency 120 . The power of the fractionation responses can significantly reduce the signal-to-noise ratio of the radar signal 126 . The occurrence and magnitude of fractionation spikes can be reduced by operating the frequency ramp generator 116 at a lower ramp rate; however, the reduced accuracy of the frequency ramp may increase the discrepancy between the ideal frequency ramp 140 and the achieved frequency ramp 142, thereby further reducing the achievable range determination accuracy. As a third example, the correspondence between the local oscillator 102 frequency and the resulting radar signal 126 frequency may increase the power of frequencies around the resulting radar signal 126 frequency. Such "trailing" may represent noise that reduces the signal-to-noise ratio of the radar signal 126 and is difficult to attenuate due to the close proximity of the frequency of the trailing noise to the frequency of the radar signal 126 . These and other disadvantages may result from the modulation of the radar signal 126 as a fractional adjustment of the reference frequency 104 by the frequency divider 114 with multi-module feedback, as in the example scenario 100 of FIG 1 shown.

B. Techniques Featured

The techniques currently presented provide an alternative form of modulating the radar signal, such as a frequency ramp over a range of frequencies. In accordance with the present disclosure, instead of directly generating a modulated radar frequency 120, a phase-locked loop 106 may instead generate a series of clock signals at a fixed frequency for a digital front-end that generates digital signal modulation, such as a digital frequency ramp. The digital signal modulator may operate at a first clock frequency and generate quadrature digital representations of the radar modulation signal that are converted by a high frequency digital-to-analog converter (RF DAC) operating at a second clock frequency to generate an analog signal 220 containing the modulation generated by the digital signal modulator. The analog output signal of the RF DAC can be upconverted to the radar frequency range and transmitted as a radar frequency that has the modulation generated by the digital signal modulator and the RF DAC.

2 12 is an illustration of an example scenario 200 involving modulation of a radar signal 126 according to the techniques presented herein. In this example scenario 200, a local oscillator 102 (such as a crystal oscillator or a voltage controlled oscillator) provides a reference frequency 104 for a phase-locked loop 106, which includes a phase-frequency detector 108, a charge pump 110 and a loop filter 112, and a feedback signal that provides up-converting frequency modulation. Instead of a frequency divider 114 with multi-module feedback that switches on a schedule at a varying fraction of the period of the reference frequency 104, the phase-locked loop 106 in the example scenario 200 of FIG 2 however, a frequency divider 202 with integer feedback that provides switching with a static integer. The output of the phase locked loop 106 is a timing signal 204 for a clock generator 206 which converts the timing signal into a first clock signal 208 and a second, higher frequency clock signal 210 . Clock generator 206 may include multiple frequency dividers for providing the first clock signal and the second clock signal at lower frequencies than clock signal 204 . A digital signal modulator 212 operates on the first clock signal 208 to generate a digital signal as a first digital value 214 and a second digital value 216 comprising quadrature representations of the signal to be transmitted. In addition, the digital signal modulator 212 subjects the signal to modulation. The digital signal modulator 212 may include, for example, a frequency ramp generator that produces an incrementally increasing value and an integrator that produces a cyclic output that represents the instantaneous phase of the signal, such as an output in the range of 0 to 360 degrees or 2π radians, wherein the increase in cyclic output per sample by the integrator gradually increases to reflect a steadily increasing frequency of the signal and achieve a digital frequency ramp. The cyclic integrator output may be processed by a digital coordinate rotation generator (a CORDIC generator) which produces the first digital value as a sine and cosine representation of the cyclic integrator output derived from an I part and a Q part of an RF DAC 218 can be processed. As described below, the DAC 218 may include a first DAC for converting the input signal to the I section to an analog signal and a second DAC to converting the input signal to the Q section to an analog signal. The DAC 218 may further include a combiner to combine (sum) the analog output signals provided by the first and second DACs to form the analog signal 220 .

The analog signal 220 generated by the RF DAC 218 may be upconverted 222 by mixing (optionally by higher frequency clock signals generated by the clock generator 206) to generate a radar signal 126 that is in the radar frequency range, such as 1 gigahertz to 100 gigahertz. The radar signal 126 is transmitted from a transmitter 124, such as a power amplifier and a transmitting antenna, and reflected off an object 128. FIG. The reflection of the radar signal 126 is detected by a receiver 132, such as a receiving antenna, and the received signal 130 is further down-converted and processed (e.g., by a signal interpreter 134, a time-of-flight determiner 136, and a range determiner 138) to determine the 126 from the transmitter 124 to the object 128 and back to the receiver 132 route and thus the distance 140 between the transmitter 124 and the receiver 132 and the object 128 to determine. In this way, the radar signal 126, which is frequency ramp modulated by the cooperation of the phase locked loop 106, the clock generator 206, the digital signal modulator 212 and the RF DAC 218, enables radar ranging according to the techniques presented herein. Transmitting and receiving antennas may be implemented in a single antenna in some embodiments.

C. Technical Implications

Some embodiments of modulating a radar signal 126 according to the techniques presented herein may enable a variety of technical features compared to other embodiments that do not use the techniques presented here.

A first technical effect that a radar signal 126 modulated according to the techniques presented herein can have is to avoid fractionation excursions introduced by the fractional switching schedule of the frequency divider 114 with multi-module feedback. Instead of switching the reference frequency 104 on a variable switching schedule and with a variable fraction of the period of the reference frequency 104, the phase-locked loop 106 in the example scenario 200 of FIG 2 operates at a relatively fixed frequency provided by the frequency divider 202 with integer feedback, which is not responsible for generating a modulation such as a frequency ramp, but only for up-converting the reference frequency 104 to the desired frequency of the timing signal 204. By choosing the switching schedule of the frequency divider 202 with integer feedback as an octave of the reference frequency 104, the creation of fractionation excursions can be avoided.

A second technical impact that a radar signal 126 modulated according to the techniques presented herein may have relates to the correspondence of the modulation and an ideal modulation, such as the correspondence between an achieved frequency ramp 142 and an ideal frequency ramp 140. A digital signal modulator 212 and an RF -DAC 218 can impose a modulation on the signal that is not subject to the feedback delay and dynamics of the phase-locked loop 106, but rather apply phase shifting, which is an incremental increase in frequency in the digital values generated for the RF DAC 218. The resulting modulation, such as a frequency ramp 142, may therefore have a frequency ramp 142 with damped overshoot and undershoot. For example, the approximation error that results from the operating frequency and the sampling rate of the digital front end can be significantly lower than the approximation error that results from the dynamic properties of the phase-locked loop 106 . In addition, increasing the operating frequency and sampling rate of the digital signal modulator 212 and the RF DAC 218 can reduce the approximation error without introducing additional fractionation excursions that reduce the signal-to-noise ratio of the radar signal 126 . In addition, the modulation techniques do not result in an undesirable trade-off between modulation accuracy and reduction in noise due to fractionation excursions.

A third technical impact that a radar signal 126 modulated according to the techniques presented herein may have is the architectural flexibility of the frequency modulator device. A first example: Compared to the example scenario 100 of 1 In the frequency modulation technique illustrated, the use of a relatively accurate local oscillator 102 can provide a reference frequency 104 for a narrow bandwidth phase-locked loop 106 , thereby reducing the impact of phase noise on the radar signal 126 . Alternatively, a low-noise oscillator can be processed by a high-bandwidth phase-locked loop 106, which can result in a broad-band radar signal 126 with low phase noise. As a second such example, modulating the signal using the provision of digital values to an RF DAC may enhance the programmability of the signal modulation device; e.g. B. The digital modulator can have a variety of modulation techniques and the adjustment of the parameters of the modulation technique (e.g. the range or the rate of a frequency rampe), enable the selection of a specific modulation technique and/or the specification of a new modulation technique and apply the selected modulation almost instantaneously to the modulated signal generated and transmitted thereby. These and other technical implications can be achieved through various embodiments of the techniques presented herein.

D. Primary Embodiments

3 FIG. 3 is an illustration of a first exemplary embodiment of the techniques presented herein, presented as an example of a method 300 for generating a modulated radar signal. Corresponding parts of example method 300 may relate to a device and e.g. B. as a group of discrete or integrated electrical and/or electronic components; as a programmable logic circuit such as a field programmable gate array (FPGA); and/or implemented as instructions stored in a memory of the device, such as firmware, system memory, a hard disk drive, a solid state memory component, or a magnetic or optical medium, wherein execution of the instructions by a processor of the device involves operation of the Device causes according to the techniques presented here.

The example method 300 begins at 302 and includes performing 304 a conversion of a timing signal 204 to an analog signal 220 by generating 306, corresponding to the timing signal 204, a first digital value 214 and a second digital value 216 that are quadrature representations of a radar modulation signal, and converting 308 the first digital value 214 and the second digital value 216 with a high frequency digital to analog converter 218 to generate the analog signal 220. The example method 300 also includes applying 310 the conversion to generate a radar signal 126 at the radar frequency. The example method 300 also includes comparing 312 the radar signal 126 and a received signal 130 comprising a reflection of the radar signal 126 to determine a range 140. According to one example, comparing the radar signal 126 and the received signal 130 is accomplished by mixing or demodulating the transmitted radar signal 126 (or a replica of the transmitted signal with the same waveform) is performed with the received signal 130 using a mixer or an IQ demodulator. In this manner, the example method 300 enables a range 140 to be determined using a modulated radar signal generated in accordance with the techniques presented herein, and thus ends at 314.

4 FIG. 4 is an illustration of an example scenario 400 including a second example embodiment of the techniques presented herein, the second example embodiment including an example radar modulation signal generator 402. FIG. The example radar modulation signal generator 402 includes a local oscillator 102 that generates a signal at a reference frequency 104 and a phase locked loop 106 that provides a timing signal 204 based on the reference frequency 104 . The example radar modulation signal generator 402 further includes a clock generator 206 that converts the timing signal 204 into a first clock signal 208 and a second clock signal 210 . The example radar modulation signal generator 402 further includes a digital signal modulator 212 that uses the first clock signal 208 to generate a first digital value 214 and a second digital value 216 that are quadrature representations of a modulation signal having a modulation frequency. The example radar modulation signal generator 402 further includes a high frequency digital to analog converter 218 that converts the first digital value 214 and the second digital value 216 using the second clock signal 210 to generate an analog signal 220 . The example radar modulation signal generator 402 further includes a transmitter 124 that generates a transmit signal 404 at a radar frequency 406 based on the analog signal 220 . The example radar modulation signal generator 402 further includes a receiver 132 that receives a receive signal 130 that includes a reflection of the transmit signal 404 . The example radar modulation signal generator 402 further includes a range determiner 138 that compares the reflectance of the transmit signal 404 and the transmit signal 404 to determine a range 140 . In this way, the radar modulation signal generator 402 generates a modulated transmit signal 404 at the radar frequency 406 for determining the range 140 according to the techniques presented herein.

5 FIG. 5 is an illustration of an example scenario 500 including a third example embodiment of the techniques presented herein, the third example embodiment including an example ramp generator device 502. FIG. The example ramp generator device 504 includes a local oscillator 102 that generates a reference frequency 104 . The example ramp generator device 504 further includes a phase locked loop 106 that provides a timing signal 204 based on the reference frequency 104 . The example ramp generator device 504 further includes a clock generator 206 that converts the timing signal 204 into a first clock signal 208 and a second clock signal 210 . The exemplary ramp generator device Device 504 further includes a digital ramp generator 504 that generates at the first clock signal 208 a first digital value 214 and a second digital value 216 that are quadrature representations of a ramp modulation signal 506 . The example ramp generator device 504 further includes a high frequency digital to analog converter 218 that converts the first digital value 214 and the second digital value 216 using the second clock signal 210 to generate a high frequency analog ramp signal 508 . In this manner, the ramp generator device 502 generates an analog high frequency ramp signal 508 in accordance with the techniques presented herein.

E. Variations

The techniques discussed herein can be varied in many ways, and some variations may provide additional advantages and/or reduce disadvantages over other variations of these and other techniques. Furthermore, some variants can be combined, and some combinations can have additional advantages and/or minor disadvantages by working synergistically together. The variants may be incorporated into different embodiments to confer individual and/or synergistic benefits on those embodiments.

E1 scenarios

A first aspect, which may vary depending on the scenario in which the techniques can be deployed, concerns the devices with which such techniques can be deployed.

A first variant of this first aspect is that the techniques can generate a variety of modulated signals. As a first example, the modulated signals may be generated at a variety of frequencies, such as in a radar frequency range (e.g., 1 gigahertz to 100 gigahertz) or in other frequency ranges of the electromagnetic spectrum. A second example is that the signals may have various periodic functions, such as sine waves, square waves, and triangle waves, and/or combinations thereof. A third example is that the modulated signals can be modulated in various ways, such as frequency modulation, amplitude modulation, and phase modulation, and/or combinations thereof. As a fourth example, the modulated signals can be used in a variety of applications, such as range and/or location estimation; direction estimation; speed estimation; and analogue or digital communication.

As a second variant of this first aspect, the techniques presented here can use a variety of technologies to implement one or more components. As a first example, an element of a device using at least some of the techniques presented herein may include electrical or electronic active or passive components, such as a combination of resistors, capacitors, inductors, transformers, and transistors. Such components can come as a combination of discrete components; an integrated circuit, such as an application specific integrated circuit (ASIC); or a combination thereof. As a second example, an element of a device using at least some of the techniques presented herein may include programmable circuitry, such as a field programmable gate array (FPGA). As a third example, an element of an apparatus employing at least some of the techniques presented herein may include a microprocessor executing instructions stored in memory (e.g., volatile or non-volatile memory circuitry; a platter of a hard disk drive; a a solid-state memory device; a flash memory device such as a ROM, an EPROM, or an EEPROM; or an optical or magnetic memory device such as a CD-ROM, DVD-ROM, or BD-ROM), wherein execution of the instructions by the processor causes the device implements at least some of the techniques presented here.

As a third variant of this first aspect, embodiments of the presented devices can have a multiplicity of system architectures. As a first example, an embodiment of the techniques presented herein may include a single device that implements an application, such as a ranging device that uses a modulated radar signal to determine distance, and optionally includes a user interface that notifies a user of the distance. As a second example, an embodiment of the techniques presented herein may include a component of another device, such as an embodiment including a distance measuring device deployed in a vehicle and determining a distance between the vehicle and another vehicle, e.g. B. in an application such as autonomous vehicle navigation or user-assisted vehicle navigation. As a third example, an embodiment of the techniques presented herein may be implemented via a group of cooperating devices connected via a wired connection (e.g., a bus, a cable, a group of interconnects integrated into an area, a network network connection such as Ethernet) and/or wireless connections (e.g. an infrared, Bluetooth or WiFi connection), the respective devices implementing part of the techniques presented here and the group of cooperating devices implementing an embodiment of the techniques presented here implemented. There are many possible scenarios in which an embodiment of the presented techniques can be used.

E2. Modulation of the transmission signal

A second aspect that can vary in the techniques presented here relates to the modulation of the transmission signal.

As a first variation of this second aspect, embodiments of the techniques presented herein may involve a plurality of phase-locked loops for generating the timing signal 204 . In some embodiments, the phase-locked loop 106 may include an integer feedback frequency divider 202 that switches the reference frequency 104 (e.g., the output of the loop filter 112) according to a programmable switching schedule according to an integer frequency multiplier. The frequency divider 202 with integer feedback can receive the output of the loop filter 112 and generate a switching signal that causes the phase frequency detector 108 to change the reference frequency 104, e.g. by inverting the reference frequency 104 at selected portions of the period of the reference frequency 104, thereby upconverting the reference frequency 104 to produce a timing signal 204 that corresponds to an operating or base frequency of the modulation components. In some embodiments, integer feedback frequency divider 202 provides a fixed frequency division, e.g. B. a fixed switching schedule that is maintained throughout the transmission of analog signal 220. Alternatively, the switching schedule of the frequency divider 202 can be changed with integer feedback, e.g. B. to alternate between a first timing signal 204 having a first operating frequency and a second timing signal 204 having a second operating frequency. While variable switching may introduce noise, such noise may be ephemeral and/or intermittent and therefore insignificant to the signal-to-noise ratio of the transmit signal compared to the fractionation excursions caused by the highly variable switching schedule of a multi-modulus frequency divider 114. Feedback can be caused, as in the example scenario 100 of 1 is shown.

As a second variation of this second aspect, the digital signal modulator 212 can generate modulation signals using a variety of components. For example, a digital ramp can be generated by a combination of a first integrator that produces an increasing digital value and a numerically controlled oscillator that produces quadrature representations of the ramp modulation signal with frequencies proportional to the increasing digital value. The numerically controlled oscillator can e.g. a second integrator which integrates the increasing digital value generated by the first integrator to produce a cyclic digital value, e.g. B. digital values corresponding to a range of 0 to 360 degrees or the range of 0 to 2π radians. In such an embodiment, the second integrator also includes a modulus integrator that produces the cyclic digital value as a modulus integral of the increasing digital value. For example, the second integrator may comprise an eight-bit register that iteratively adds the increasing value of the first integrator, where the value of the eight-bit register has degree values ranging from 0 (represented as 0x00) to 359 degrees (represented as 0× FF) represents. Addition of incremental values that exceed the highest value of the eight-bit register results in an overflow that applies a modulus of 360 to the added values (e.g. adding 0×04 results in a register value of 0 ×FC, which corresponds to 357 degrees or 6.23 radians, a new register value of 0x02, which corresponds to 3 degrees or 0.05 radians). In this way the cyclic digital value is generated as a modular integral of the increasing value produced by the first integrator.

As a third variant of this second aspect, a digital signal modulator 212 and the RF DAC 218 can have a plurality of modulation signals. A first example: Increasing the ramping digital value produced by the first integrator, which the second integrator adds to the cyclic digital value, can cause the frequency of the generated signal to rise steadily via a frequency ramp. In some embodiments, the first integrator can increase the increasing digital value at a selected rate, resulting in a linear frequency ramp. Alternatively, the first integrator can increase the increasing digital value at a variable rate, thus producing a non-linear frequency ramp, such as an exponential or sinusoidal frequency ramp; can produce a falling digital value like a negative frequency ramp; can cycle between an increasing frequency ramp and a decreasing frequency ramp; etc. In some embodiments, the increasing digital value may be reset occasionally, causing the Fre frequency ramp modulation has a cyclic or sawtooth ramp. In some embodiments, the numerically controlled oscillator may include a digital coordinate rotation generator (e.g., a circuit implementing a CORDIC technique) that receives a cyclic digital value and the first digital value 214 as a sine of the cyclic digital value and the second digital value Value 216 generated as the cosine of the cyclic digital value. In some embodiments, the RF DAC 218 may use the first digital value 214 and the second digital value 216 to change the frequency of the transmit signal, e.g. B. as a frequency ramp. Alternatively, the RF DAC can use the first digital value 214 and the second digital value 216 to modulate other properties of the transmit signal, e.g. B. amplitude and / or phase. In some embodiments, the digital values generated by digital signal modulator 212 and used by RF DAC 218 may include bit-resolution integers, such as 6-bit, 7-bit, 8-bit, or 9-bit integers, or any other numeric format and bit resolution.

As a fourth variation of this second aspect, the components of the digital signal modulator 212 are operable at a variety of operating frequencies. As a first example, the clock generator 206 may generate the first clock signal 208 at a first clock frequency selected in a frequency range from 1 gigahertz to 10 gigahertz, e.g. B. to adjust the frequencies at the top and bottom of a frequency ramp. In a second example, the clock generator 206 may generate the second clock signal 210 at a second clock frequency that is in a frequency range of 6 gigahertz to 10 gigahertz. A frequency ramp resulting from the selection of the first clock signal 208 having a second clock frequency ƒ _d (used by the digital signal modulator 212) and the second clock signal 210 having a second clock frequency ƒ _s (used by the RF DAC 218 used), can lead to a frequency ramp over the following frequency range: $${ƒ}_s-\frac{{ƒ}_{\mathrm{i.e}}}{2}<ƒ<{ƒ}_s+\frac{{ƒ}_{\mathrm{i.e}}}{2}$$

For example, if ƒ _s is set to 8 gigahertz and ƒ _d to 4 gigahertz, the modulated signal has a frequency ramp between 6 gigahertz and 10 gigahertz. In one embodiment, the second clock frequency is chosen to be at least 60% higher than the first clock frequency, which may reduce the formation of fractional spikes. As a third example, the numerically controlled oscillator can be operated with the first clock signal 208 and corresponding to a first clock frequency, and the first integrator can be operated with a third clock signal that has a lower frequency than the first clock frequency of the first clock signal 208. As a fourth example, phase-locked loop 202 may be operated at a relatively low frequency, thereby reducing the smearing effects that may be caused by operating phase-locked loop 202 at a high frequency. Many such variations can be incorporated in generating the modulated signal according to the techniques presented herein.

E3. Upconversion and transmission of the signal

A third aspect that may vary in embodiments of the techniques presented herein is the upconversion and transmission of the analog signal 220 generated by the RF DAC 218 to generate a transmit signal 404 at a radar frequency 406.

und einem Abbild mit höheren Frequenzen bei ${ƒ}_1+{ƒ}_s-\frac{{ƒ}_d}{2}$

führen. Das aufwärtsgewandelte Abbild mit höherer Frequenz ist erwünscht, und das abwärtsgewandelte Abbild mit niedrigerer Frequenz ist wünschenswert gedämpft; dementsprechend kann in einigen Ausführungsformen ein Abbildunterdrückungsfilter beinhaltet sein, der das Zwischensignal zum Unterdrücken des niederfrequenten Abbilds filtert. In einer Ausführungsform besteht der Abbildunterdrückungsfilter aus einem Bandpassfilter zweiter Ordnung, wie etwa einem LC-Resonanztankkreis. Beispielsweise kann die Sendeaufwärtswandlungsfrequenz (aus einem Frequenzbereich von 20 Gigahertz bis 60 Gigahertz ausgewählt werden, und die Zwischenaufwärtswandlungsfrequenz wird aus einem Frequenzbereich von 10 Gigahertz bis 20 Gigahertz ausgewählt. Wenn beispielsweise eine analoge Signalrampe zwischen 6 und 10 Gigahertz mit einer Zwischenfrequenz von 10 Gigahertz und einer Sendeaufwärtswandlungsfrequenz von 60 Gigahertz gemischt wird, entsteht ein Sendesignal 404 mit einer Frequenzrampe zwischen 76 Gigahertz und 80 Gigahertz.In a first variation of this third aspect, the clock generator 206 may convert the timing signal 204 into a transmission upconversion clock signal that may be combined (e.g., mixed) with the analog signal 220 to convert the analog signal 220 from frequencies in the operational ranges of the digital signal modulator 212 and/or the RF DAC 218 to the radar frequency 406 within the radar frequency range. In some of these embodiments, mixing the analog signal at the up-conversion frequency produces the transmit signal at a transmit frequency that is a non-integer multiple of a timing signal frequency of timing signal 204 generated by phase locked loop 106, thereby matching the frequency of local oscillator 102 and the frequency of the Transmission signal 404 and the noise-related “triggering effects” that may result from this are reduced. As another example, the clock generator 296 may convert the timing signal 204 into an up-conversion intermediate clock signal, and the transmitter 124 may generate the transmit signal 404 by mixing the analog signal 220 at an up-conversion intermediate frequency ƒ ₁ corresponding to the up-conversion clock signal to generate an intermediate signal at an intermediate frequency , and then mix the intermediate signal at the transmission up-conversion frequency according to the transmission up-conversion clock signal. Intermixing can contribute to a lower frequency image ${ƒ}_{}$${}_1-{ƒ}_s+\frac{{ƒ}_{\mathrm{i.e}}}{2}$

and an image with higher frequencies ${ƒ}_{}$${}_1+{ƒ}_s-\frac{{ƒ}_{\mathrm{i.e}}}{2}$

to lead. The upconverted higher frequency image is desirable, and the downconverted Lower frequency image is desirably muted; accordingly, in some embodiments, an image suppression filter may be included that filters the intermediate signal to suppress the low-frequency image. In one embodiment, the image rejection filter consists of a second-order bandpass filter, such as an LC tank circuit. For example, the transmit upconversion frequency can be selected from a frequency range of 20 gigahertz to 60 gigahertz, and the intermediate upconversion frequency can be selected from a frequency range of 10 gigahertz to 20 gigahertz. For example, if an analog signal ramps between 6 and 10 gigahertz with an intermediate frequency of 10 gigahertz and a When the transmit upconversion frequency of 60 gigahertz is mixed, a transmit signal 404 with a frequency ramp between 76 gigahertz and 80 gigahertz is produced.

6 12 is an illustration of an example scenario involving generation and transmission of a frequency modulated radar signal and detection of a reflected signal to determine the range to an object according to the techniques presented herein. In this example scenario 600, a phase-locked loop 106 generates a timing signal 204 (e.g., converted from a reference frequency 104 provided by a local oscillator 102) for a clock generator 206, which generates four clock signals: the first clock signal 208 used by the digital signal modulator becomes; the second clock signal 210 used by the RF DAC 218, which includes an I-section 602 and a Q-section 604; an intermediate upconversion clock signal 618 at an intermediate upconversion frequency 620; and a transmit upconversion clock signal 626 having a transmit upconversion frequency 628. The digital signal modulator 212 includes a first integrator 606 that produces an increasing digital value 608 and a second integrator 610 that integrates the increasing digital value 608 to produce a cyclic digital value 612. The cyclic digital value 612 is provided to a digital coordinate rotation generator 614 (e.g., a CORDIC generator) that generates the first digital value 214 (e.g., a sine value) and the second digital value 216 (e.g., a cosine value). are generated, which are provided to the I-section 602 and the Q-section 604 of the RF DAC, respectively. The output of the I-section 602 and the Q-section 604 are added 616 (e.g., by a voltage adder) for the purpose of generating a quadrature signal that is mixed 622 with the intermediate up-conversion frequency 620 to generate an intermediate up-converted signal. The upconverted intermediate signal is passed through an image filter 624 to attenuate the low frequency image and the output of the image filter 624 undergoes a second mix 640 at the transmit upconvert frequency 628 to produce the transmit signal 404 at a radar frequency 406 . The transmit signal 404 may then be amplified by a power amplifier 632 and forwarded to a transmitter 124, such as an antenna, for transmission. In this way, a transmission signal 404 in the radar frequency range, which has a modulation in the form of a frequency ramp, can be generated and transmitted in accordance with the techniques presented here.

F. Supporting Data

7A-7C 12 shows data sets demonstrating the selection of the signal-to-noise ratio of the transmit signal 404 at different frequencies depending on the bit resolution of the digital signal modulator 212 and the RF DAC 218. In the example record 700 from 7A For example, the generation of values by a CORDIC generator for an RF DAC with a 7-bit resolution for generating transmit signals 404 in the radar frequency range results in a significant background noise 706 at all selected frequencies. In the example record 702 of 7B the generation of values by a CORDIC generator for an HF DAC with an 8-bit resolution results in a reduced background noise level 706 at all selected frequencies; and in example record 704 of 7C the generation of values by a CORDIC generator for an RF DAC with a 9-bit resolution results in an even further reduced background noise level 706 at all selected frequencies. Therefore, an application's target signal-to-noise ratio that can be achieved through the different bit resolutions can lead to the selection of a bit resolution for the digital signal modulator 212 and the RF DAC 218 that provides an adequate signal-to-noise ratio for a selected application (e.g., an average noise below a noise floor 708) while reducing component cost and power consumption.

G. Other Primary Embodiments

8th 8 is an illustration of a fourth exemplary embodiment of the techniques presented herein, presented as an example method 800 for generating a modulated radar signal and/or detecting a range at a radar frequency. Corresponding parts of example method 800 may relate to a device and e.g. B. as a group of discrete or integrated electrical and/or electronic components, as a programmable logic circuit; how about a field programmable gate array (FPGA); and/or implemented as instructions stored in a memory of the device, such as firmware, system memory, a hard disk drive, a solid state memory component, or a magnetic or optical medium, wherein execution of the instructions by a processor of the device involves operation of the Device causes according to the techniques presented here.

The example method 800 begins at 802 and includes performing 804 a conversion of a timing signal 204 to an analog signal 220 by generating 806, corresponding to the timing signal 204, a first digital value 214 and a second digital value 216 based on a random phase value (e.g., a true random phase value or a pseudo-random phase value), and converting 808 the first digital value 214 and the second digital value 216 with a high-frequency digital-to-analog converter 218 to generate the analog signal 220, the first digital value 214 and /or the second digital value 216 corresponds to a quadrature representation of a radar modulation signal. The example method 800 also includes applying 810 the conversion to generate a transmit signal (e.g., a radar signal 126 and/or a transmit signal 404) at the radar frequency. The example method 800 also includes combining 812 the radar signal 126 and a received signal 130 comprising a reflection of the radar signal 126 to determine a range 140. For example, the radar signal 126 and the received signal 130 to determine the range 140 can be compared. According to one example, combining (e.g., comparing) the radar signal 126 and the received signal 130 is accomplished by mixing or demodulating the transmitted radar signal 126 (or a replica of the transmitted signal with the same waveform) with the received signal 130 using a mixer or a IQ demodulator performed. In this way, the example method 800 enables a range 140 to be determined using a modulated radar signal generated in accordance with the techniques presented herein, and thus ends at 814.

In some examples, the random phase value may be generated with a random number generator (e.g., a true random number generator or a pseudo-random number generator). In one example, the random value generator can store a plurality of phase values that include the random phase value (e.g., the plurality of random phase values can be stored in a look-up table). The random phase value can be taken from the plurality of random phase values.

In some examples, the random phase value is combined with (e.g., summed with) a first cyclic digital value for the purpose of generating a third digital value (e.g., the third digital value may be a sum of the first cyclic digital value value and the random phase value). The first digital value 214 is based on the third digital value. For example, the first digital value 214 can be generated as a sine of the third digital value.

In some examples, the random phase value is combined with (e.g., summed with) a second cyclic digital value for the purpose of producing a fourth digital value (e.g., the fourth digital value may be a sum of the second cyclic digital value and the random phase value). The second digital value 216 is based on the fourth digital value. For example, the second digital value 216 can be generated as the cosine of the fourth digital value.

In some examples, an increasing digital value is generated. The increasing digital value can be integrated with a first integrator to generate the first cyclic digital value. The increasing digital value can be integrated with a second integrator to generate the second cyclic digital value.

In some examples, the radar modulation signal includes a frequency ramp.

In some examples, the random phase value may be a random initial phase value associated with the beginning of the frequency ramp. For example, the random phase value can be combined with the first cyclic digital value (e.g. to generate the third digital value) and the random phase value can be combined with the second cyclic digital value (e.g. to generate the fourth digital value) at the beginning of the frequency ramp become. In some examples, for each frequency ramp of the radar modulation signal, a random phase value from the plurality of phase values may be combined with the first cyclic digital value and the second cyclic digital value only once (e.g., at the beginning of the frequency ramp). In some examples, a random phase value from the plurality of phase values may be combined with the first cyclic digital value and the second cyclic digital value at the beginning of each frequency ramp of the radar modulation signal.

9A 9 is an illustration of an example scenario 900 including a fifth example embodiment of the techniques presented herein, wherein the fifth example embodiment includes an example digital signal modulator 950 of a radar modulation signal generator (e.g., example radar modulation signal generator 402) and/or a ramp generator device (e.g., example ramp generator device 502). In one example, example digital signal modulator 950 may correspond to (and/or be used as) example digital signal modulator 212 and/or example ramp generator device 504. In one example, example digital signal modulator 950 may include a direct digital frequency synthesizer (DDFS), e.g. B. a DDFS based on a numerically controlled oscillator (NCO).

The example digital signal modulator 950 may be provided with one or more clock signals including a first clock signal CLK 1, a second clock signal CLK 2, a third clock signal CLK 3, and/or a fourth clock signal CLK 4. For example, the one or more clock signals may be generated by a clock generator 206 (e.g., the clock generator 206 converts a timing signal 204 into the one or more clock signals). In some examples, a phase of the first clock signal CLK 1 and a phase of the second clock signal CLK 2 are in quadrature.

The example digital signal modulator 950 may generate a first digital value 214 and a second digital value 216, where the first digital value 214 and/or the second digital value 216 corresponds to a quadrature representation of a modulation signal having a modulation frequency. In some examples, the example digital signal modulator 950 may generate the first digital value 214 and the second digital value 216 using one or more first clock signals. The one or more first clock signals may include the first clock signal CLK1 and the second clock signal CLK2. In an example, the example digital signal modulator 950 may generate the first digital value 214 with the first clock signal CLK 1 and/or generate the second digital value 216 with the second clock signal CLK 2 .

In some examples, the example digital signal modulator 950 includes a first integrator 904 (INTEGRATOR 1) (e.g., a frequency accumulator that includes a flip-flop and/or a combination module such as a summer) that generates an increasing digital value 906 . For example, the first integrator 904 may integrate the delta frequency control word (ΔFCW) 902 to generate the increasing digital value 906 (e.g., the increasing digital value 906 may be a frequency control word (FCW), such as a sawtooth shaped FCW). In some examples, the first integrator 904 is operated with the third clock signal CLK 3 to generate the increasing digital value 906 .

In some examples, the example digital signal modulator 950 includes a second integrator 908 (e.g., a phase accumulator that includes a flip-flop and/or a combination module such as a summer) that takes the increasing digital value 906 to generate a first cyclic digital value 910 integrated. In some examples, the second integrator 908 operates on the first clock signal CLK 1 to generate the first cyclic digital value 910 (e.g., the first cyclic digital value 910 may be a phase value).

In some examples, the example digital signal modulator 950 includes a third integrator 928 (e.g., a phase accumulator that includes a flip-flop and/or a combination module such as a summer) that takes the increasing digital value 906 to generate a second cyclic digital value 930 integrated. In some examples, the third integrator 928 operates on the second clock signal CLK 2 to generate the second cyclic digital value 930 (e.g., the second cyclic digital value 930 may be a phase value).

Grad oder $\raisebox{1ex}{$2\pi $}\!\left/ \!\raisebox{-1ex}{$2^T$}\right.$

Radiant normalisiert werden. In einigen Beispielen können S und/oder T gleich einer Anzahl von Bits, N, sein (z. B. kann N der Anzahl von Bits der ersten Bits und/oder der Anzahl von Bits der dritten Bits entsprechen, die unten besprochen werden). Alternativ und/oder zusätzlich können S und/oder T verschieden von N sein. In einigen Beispielen kann S gleich T sein. Alternativ und/oder zusätzlich kann S verschieden von T sein. In einem Beispiel kann S 10, 20 oder eine andere Anzahl von Phasenwerten sein, und T kann gleich der Anzahl von Bits, N, sein. In einigen Beispielen wird der Zufallswertgenerator 926 zum Erzeugen des zufälligen Phasenwertes 924 mit dem vierten Taktsignal CLK 4 betrieben. In einigen Beispielen wird der zufällige Phasenwert 924 vom Zufallswertgenerator 926 erzeugt (und/oder aus der Mehrzahl der zufälligen Phasenwerte entnommen), und zwar zu Beginn einer Frequenzrampe eines Sendesignals (z. B. eines analogen Hochfrequenzsignals, eines Radarsignals 126 und/oder eines Sendesignals 404) und/oder eines Radarmodulationssignals. Beispielsweise kann der zufällige Phasenwert 924 durch den Zufallswertgenerator 926 erzeugt werden (und/oder aus der Mehrzahl der zufälligen Phasenwerte entnommen werden) entsprechend dem vierten Taktsignal CLK 4, wobei eine Periode des vierten Taktsignals CLK 4 einer Periode der Frequenzrampe entsprechen kann.In some examples, the example digital signal modulator 950 includes a random number generator 926 (eg, a true random number generator or a pseudo-random number generator) that generates a random phase value 924 (eg, an initial random phase value). In one example, the random value generator 926 may store a plurality of phase values that include the random phase value 924 (e.g., the plurality of random phase values may be stored in a lookup table). The random phase value 924 can be taken from the plurality of random phase values. In one example, the plurality of random phase values may be S phase values (e.g., over the range of 0 to 360 degrees or over the range of 0 to 2π radians) and/or the plurality of phase values may be defined by $\raisebox{1ex}{$360$}\!\left/ \!\raisebox{-1ex}{$2^T$}\right.$

degree or $\raisebox{1ex}{$2\pi $}\!\left/ \!\raisebox{-1ex}{$2^T$}\right.$

radians are normalized. In some examples, S and/or T may equal a number of bits, N, (e.g., N may correspond to the number of bits of the first bits and/or the number of bits of the third bits discussed below). Alternatively and/or additionally, S and/or T can be different from N. S may equal T in some examples. Alternatively and/or additionally, S may be different from T. In one example, S may be 10, 20, or some other number of phase values, and T may equal the number of bits, N. In some Bei play, the random value generator 926 for generating the random phase value 924 is operated with the fourth clock signal CLK 4 . In some examples, the random phase value 924 is generated by the random value generator 926 (and/or extracted from the plurality of random phase values) at the beginning of a frequency ramp of a transmit signal (e.g., an analog radio frequency signal, a radar signal 126, and/or a transmit signal 404) and/or a radar modulation signal. For example, the random phase value 924 may be generated by the random value generator 926 (and/or taken from the plurality of random phase values) according to the fourth clock signal CLK 4, where a period of the fourth clock signal CLK 4 may correspond to a period of the frequency ramp.

Radiant entsprechen. In einem Beispiel kann der dritte digitale Wert 914 gleich einer Summe des zufälligen Phasenwertes 924 und des ersten zyklischen digitalen Wertes 910, subtrahiert vom Phasenversatzwert 922, sein (und/oder darauf basieren).In some examples, the example digital signal modulator 950 includes a first combining module 912 (e.g., a summer) that combines (e.g., sums) the random phase value 924 with the first cyclic digital value 910 to generate a third digital value 914. In some examples, the first combining module 912 combines the random phase value 924 with the first cyclic digital value 910 to generate the third digital value 914 at the beginning of the frequency ramp. Alternatively and/or additionally, the first combining module 912 may combine the random phase value 924, the first cyclic digital value 910, and a phase offset value 922 to generate the third digital value 914. The phase offset value 922 can be generated by a phase offset generator 920 . It should be apparent that combining the random phase offset value 922 to generate the third digital value 914 is a replica that is coupled to the second integrator 902 and the third integrator 928 that are coupled to the first clock signal CLK 1 and the second clock signal CLK 2, respectively operated, mitigate and/or cancel (e.g. filter). In an example, the value of the random phase offset 922 may be 90 degrees or $\raisebox{1ex}{$\mathrm{<figure-callout\; id="2"\; label="\pi "\; filenames="DE102022207860A1\_0017.png,DE102022207860A1\_0018.png"\; state="\{\{state\}\}">\pi </figure-callout>}$}\!\left/ \!\raisebox{-1ex}{$2$}\right.$

equal to radians. In one example, the third digital value 914 may be equal to (and/or based on) a sum of the random phase value 924 and the first cyclic digital value 910 subtracted from the phase offset value 922 .

In some examples, the example digital signal modulator 950 includes a second combining module 932 (e.g., a summer) that combines (e.g., sums) the random phase value 924 with the second cyclic digital value 930 to generate a fourth digital value 934. In some examples, the second combining module 932 combines the random phase value 924 with the second cyclic digital value 930 to generate the fourth digital value 934 at the beginning of the frequency ramp. In one example, the fourth digital value 934 may be equal to (and/or based on) a sum of the random phase value 924 and the second cyclic digital value 930 .

In some examples, the example digital signal modulator 950 includes a first digital generator 916 (eg, a digital coordinate rotation generator) that generates the first digital value 214 as a sine of the third digital value 914 . In some examples, the first digital generator 916 is operated with the first clock signal CLK 1 to generate the first digital value 214 . In some examples, the first digital generator 916 includes a lookup table of sine values and/or generates the first digital value 214 based on the lookup table. The first digital value 214 may be provided to the RF DAC 218, such as for the I portion 602 of the RF DAC 218.

In some examples, the example digital signal modulator 950 includes a second digital generator 936 (eg, a digital coordinate rotation generator) that generates the second digital value 216 as the cosine of the fourth digital value 934 . In some examples, the second digital generator 936 operates with the second clock signal CLK 2 to generate the second digital value 216 . In some examples, the second digital generator 936 includes a lookup table of sine values and/or generates the second digital value 216 based on the lookup table. The second digital value 216 can be sent to the RF DAC 218, e.g. for the Q section 604 of the RF DAC 218.

wobei ϕ_rand der der zufällige Phasenwert 924(z. B. der zufällige Anfangsphasenwert) ist, X = 2π × FCW × n und/oder n in einem Bereich von 0 bis 2^G(und/oder n = 0, ..., 2^G und/oder $n=\frac{FCW}{\Delta FCW}$

) ist. In einigen Beispielen kann G gleich einer Anzahl von Bits, N, sein (z. B. kann N der Anzahl von Bits der ersten Bits und/oder der Anzahl von Bits der dritten Bits entsprechen, die unten besprochen werden). Alternativ und/oder zusätzlich kann G verschieden von N sein.In some examples, the first digital value 214 may equal and/or be based on the following expression: $$\text{sin}\left(X+{\varphi }_{\mathrm{right}an\mathrm{i.e}}\right)$$

where ϕ _rand is the random phase value 924 (e.g. the initial random phase value), X = 2π × FCW × n and/or n in a range from 0 to 2 ^G (and/or n = 0, ..., ^2G and/or $n=\frac{fCW}{\Delta fCW}$

) is. In some examples, G may equal a number of bits, N, (e.g., N may correspond to the number of bits of the first bits and/or the number of bits of the third bits discussed below). Alternatively and/or additionally, G can be different from N.

wobei ϕ_rand der der zufällige Phasenwert 924(z. B. der zufällige Anfangsphasenwert) ist, X = 2π × FCW × n und/oder n in einem Bereich von 0 bis 2^G (und/oder n = 0, ..., 2^G und/oder $n=\frac{FCW}{\Delta FCW}$

) ist. In einigen Beispielen kann G gleich einer Anzahl von Bits, N, sein (z. B. kann N der Anzahl von Bits der ersten Bits und/oder der Anzahl von Bits der dritten Bits entsprechen, die unten besprochen werden). Alternativ und/oder zusätzlich kann G verschieden von N sein.In some examples, the second digital value 216 may equal and/or be based on the following expression: $$\text{cos}\left(X+{\varphi }_{\mathrm{right}an\mathrm{i.e}}\right)$$

where ϕ _rand is the random phase value 924 (e.g. the initial random phase value), X = 2π × FCW × n and/or n in a range from 0 to 2 ^G (and/or n = 0, ..., ^2G and/or $n=\frac{fCW}{\Delta fCW}$

) is. In some examples, G may equal a number of bits, N, (e.g., N may correspond to the number of bits of the first bits and/or the number of bits of the third bits discussed below). Alternatively and/or additionally, G can be different from N.

In some examples, the RF DAC 218 converts the first digital value 214 and the second digital value 216 using one or more second clock signals to generate a transmit signal (e.g., an analog radio frequency signal, a radar signal 126, and/or a transmit signal 404) um, which includes a frequency ramp according to the techniques presented here. In some examples, the one or more second clock signals are different than the one or more first clock signals. The RF DAC 218 may operate with one or more second clock signals to convert the first digital value 214 and the second digital value 216 to generate the transmit signal. Alternatively and/or additionally, the one or more second clock signals may be the same as the one or more first clock signals. In one example, the I-section 602 of the RF DAC 218 may be operated with the first clock signal CLK 1 and the Q-section 604 of the RF DAC 218 with the second clock signal CLK 2 (e.g. to convert the first digital value 214 and convert the second digital value 216 and generate the transmit signal).

9B 9 is an illustration of an example scenario 901 in which the example digital signal modulator 950 performs truncation to truncate one or more digital values to one or more truncated digital values, according to an example embodiment. The example digital signal modulator 950 may include, for example, a first quantizer Q1 and/or a second quantizer Q2 that perform truncation.

In some examples, the first quantizer Q1 truncates first bits indicating the third digital value 914 to second bits indicating a truncated third digital value 914b. For example, a number of bits of the first bits may be N and a number of bits of the second bits may be P (e.g., the second bits may be P most significant bits of the first bits), where P is less than N. The truncated third digital value 914b may be provided to the first digital generator 916 (e.g., the first digital generator 916 may generate the first digital value 214 as a sine of the truncated third digital value 914b).

In some examples, the second quantizer Q2 truncates third bits indicative of the fourth digital value 934 to fourth bits indicative of a truncated fourth digital value 934b. For example, a number of bits of the third bits may be N and a number of bits of the fourth bits may be P (e.g., the fourth bits may be P most significant bits of the third bits), where P is less than N. The truncated fourth digital value 934b may be provided to the second digital generator 936 (e.g., the second digital generator 946 may generate the second digital value 216 as the cosine of the truncated fourth digital value 934b).

10A-10B 10 is an illustration of a sixth exemplary embodiment of the techniques presented herein, presented as an example method 1000 for generating a modulated radar signal and/or detecting a range at a radar frequency. Corresponding parts of example method 1000 may relate to an apparatus and e.g. B. as a group of discrete or integrated electrical and/or electronic components; as a programmable logic circuit such as a field programmable gate array (FPGA); and/or implemented as instructions stored in a memory of the device, such as firmware, system memory, a hard disk drive, a solid state memory component, or a magnetic or optical medium, wherein execution of the instructions by a processor of the device involves operation of the Device causes according to the techniques presented here.

The example method 1000 begins at 1002 and includes performing 1004 a conversion of a timing signal 204 to an analog signal 220 by using one or more of the 10B operations shown are performed. At least some of the one or more operations may be performed to generate a first digital value 214 and a second digital value 216 according to the timing signal 204 . The one or more acts of 1004 include generating 1016 a first cyclic digital value. Alternatively and/or additionally, the one or more acts of 1004 include truncating 1018, using a first quantizer, first bits indicative of the first cyclic digital value to second bits indicative of a first truncated cyclic digital value. For example, a number of bits of the first bits may be N and a number of bits of the second bits may be P (e.g., the second bits may be P most significant bits of the first bits), where P is less than N. Alternatively and/or additionally, the one or more acts of 1004 include generating 1020 a third digital value based on a first quantization error of the first quantizer and a fourth value. For example, the first quantization error E can be least significant bits of the first bits, where E can be a difference between N and P (e.g., a number of bits of the first quantization error can be E, where E = N - P). The fourth value can be a random value (e.g. a true random value or a pseudo-random value) and/or a noise-shaped value. Alternatively and/or additionally, the one or more acts of 1004 may include combining 1022 (e.g., summing) the third digital value with the first truncated cyclic digital value to produce a fifth digital value (e.g., the fifth digital value will be a sum of the first truncated cyclic digital value and the third digital value). Alternatively and/or additionally, the one or more acts of 1004 may include generating 1024, corresponding to the timing signal 204, the first digital value 214 based on the fifth digital value. Alternatively and/or additionally, the one or more acts of 1004 may include generating 1026 a second cyclic digital value. Alternatively and/or additionally, the one or more acts of 1004 may include truncating 1028, using a second quantizer, third bits indicative of the second cyclic digital value to fourth bits indicative of a second truncated cyclic digital value . For example, a number of bits of the third bits may be N and a number of bits of the fourth bits may be P (e.g., the fourth bits may be P most significant bits of the third bits), where P is less than N. Alternatively and/or additionally, the one or more acts of 1004 may include generating 1030 a sixth digital value based on a second quantization error of the second quantizer and a seventh value. For example, the second quantization error E can be least significant bits of the third bits, where E can be a difference between N and P (e.g., a number of bits of the second quantization error can be E, where E = N - P). The seventh value can be a random value (e.g. a true random value or a pseudo-random value) and/or a noise-shaped value. Alternatively and/or additionally, the one or more acts of 1004 may include combining 1032 (e.g., summing) the sixth digital value with the second truncated cyclic digital value to produce an eighth digital value (e.g., the eighth digital value will be a sum of the second truncated cyclic digital value and the sixth digital value). Alternatively and/or additionally, the one or more acts of 1004 may include generating 1034, corresponding to the timing signal 204, the second digital value 216 based on the eighth digital value. Alternatively and/or additionally, the one or more acts of 1004 may include converting 1036 the first digital value 214 and the second digital value 216 with a high frequency digital to analog converter 218 to generate the analog signal 220 . The example method 1000 also includes applying 1006 the conversion to generate a transmit signal (e.g., a radar signal 126 and/or a transmit signal 404) at the radar frequency. The example method 1000 also includes combining 1006 the radar signal 126 and a received signal 130 comprising a reflection of the radar signal 126 to determine a range 140. For example, the radar signal 126 and the received signal 130 to determine the range 140 can be compared. According to one example, combining (e.g., comparing) the radar signal 126 and the received signal 130 is accomplished by mixing or demodulating the transmitted radar signal 126 (or a replica of the transmitted signal with the same waveform) with the received signal 130 using a mixer or a IQ demodulator performed. In this way, the example method 1000 enables a range 140 to be determined using a modulated radar signal generated in accordance with the techniques presented herein, and thus ends at 1014.

In some examples, an increasing digital value is generated. The increasing digital value can be integrated with a first integrator to generate the first cyclic digital value. The increasing digital value can be integrated with a second integrator to generate the second cyclic digital value.

In some examples, the first digital value 214 is generated as the sine of the fifth digital value.

In some examples, the second digital value 216 is generated as the cosine of the eighth digital value.

11 11 is an illustration of an example scenario 1100 involving a seventh example embodiment of the techniques presented herein, the seventh example embodiment using an example digital signal modulator 1150 of a radar modulation signal generator (e.g., the example radar modulation signal generator 402) and/or a ramp generator device (e.g., example ramp generator device 502). In one example, example digital signal modulator 1150 may correspond to (and/or be used as) example digital signal modulator 212 and/or example ramp generator device 504. In one example, digital signal modulator 1150 may be a DDFS, such as an NCO-based DDFS , include.

The example digital signal modulator 1150 may be provided with one or more clock signals including a first clock signal CLK 1 , a second clock signal CLK 2 , and/or a third clock signal CLK 3 . For example, the one or more clock signals may be generated by a clock generator 206 (e.g., the clock generator 206 converts a timing signal 204 into the one or more clock signals). In some examples, a phase of the first clock signal CLK 1 and a phase of the second clock signal CLK 2 are in quadrature.

The example digital signal modulator 1150 may generate a first digital value 214 and a second digital value 216, where the first digital value 214 and/or the second digital value 216 corresponds to a quadrature representation of a modulation signal having a modulation frequency. In some examples, the example digital signal modulator 1150 may generate the first digital value 214 and the second digital value 216 using one or more first clock signals. The one or more first clock signals may include the first clock signal CLK1 and the second clock signal CLK2. In an example, the example digital signal modulator 1150 may generate the first digital value 214 with the first clock signal CLK 1 and/or generate the second digital value 216 with the second clock signal CLK 2 .

In some examples, the example digital signal modulator 1150 includes a first integrator 904 (INTEGRATOR 1) (e.g., a frequency accumulator that includes a flip-flop and/or a combination module such as a summer) that generates an increasing digital value 906 . For example, the first integrator 904 may integrate the delta frequency control word (ΔFCW) 902 to generate the increasing digital value 906 (e.g., the increasing digital value 906 may be a frequency control word (FCW), such as a sawtooth shaped FCW). In some examples, the first integrator 904 is operated with the third clock signal CLK 3 to generate the increasing digital value 906 .

In some examples, the example digital signal modulator 1150 includes a second integrator 908 (e.g., a phase accumulator that includes a flip-flop and/or a combination module such as a summer) that takes the increasing digital value 906 to generate a first cyclic digital value 910 integrated. In some examples, the second integrator 908 operates on the first clock signal CLK 1 to generate the first cyclic digital value 910 (e.g., the first cyclic digital value 910 may be a phase value).

In some examples, the example digital signal modulator 1150 includes a first quantizer Q1 that truncates first bits indicative of the first cyclic digital value 910 to second bits indicative of a first truncated cyclic digital value 1102 . For example, a number of bits of the first bits may be N and a number of bits of the second bits may be P (e.g., the second bits may be P most significant bits of the first bits), where P is less than N.

In some examples, the example digital signal modulator 1150 includes a first noise shaping module 1112 that generates a third digital value 1114 based on a first quantization error 1110 of the first quantizer Q1 and a fourth value. For example, the first quantization error 1110 may be E least significant bits of the first bits, where E may be a difference between N and P (e.g., a number of bits of the first quantization error 1110 may be E, where E = N - P). The fourth value can be a random value (e.g. a true random value or a pseudo-random value) and/or a noise-shaped value.

In some examples, the example digital signal modulator 1150 includes a first combining module 1104 (e.g., a summer) that combines the third digital value 1114 with the first truncated cyclic digital value 1102 to generate a fifth digital value 1106 (e.g., summed up). In one example, the fifth digital value 1106 may be equal to (and/or based on) a sum of the third digital value 1114 and the first truncated cyclic digital value 1102 .

In some examples, the example digital signal modulator 1150 includes a first digital generator 916 (eg, a digital coordinate rotation generator) that generates the first digital value 214 as a sine of the fifth digital value 1106 . In some examples, the first digital generator 916 is operated with the first clock signal CLK 1 to generate the first digital value 214 . In some examples, the first includes digital Generator 916 a lookup table of sine values and/or generates the first digital value 214 based on the lookup table. The first digital value 214 can be sent to the RF DAC 218, e.g. for the I section 602 of the RF DAC 218.

In some examples, the example digital signal modulator 1150 includes a third integrator 928 (e.g., a phase accumulator that includes a flip-flop and/or a combination module such as a summer) that takes the increasing digital value 906 to generate a second cyclic digital value 930 integrated. In some examples, the third integrator 928 operates on the second clock signal CLK 2 to generate the second cyclic digital value 930 (e.g., the second cyclic digital value 930 may be a phase value).

In some examples, the example digital signal modulator 1150 includes a second quantizer Q2 that truncates third bits indicative of the second cyclic digital value 930 to fourth bits indicative of a second truncated cyclic digital value 1124 . For example, a number of bits of the third bits may be N and a number of bits of the fourth bits may be P (e.g., the fourth bits may be P most significant bits of the third bits), where P is less than N.

In some examples, the example digital signal modulator 1150 includes a second noise shaping module 1116 that generates a sixth digital value 1120 based on a second quantization error 1118 of the second quantizer Q2 and a seventh value. For example, the second quantization error 1118 can be E least significant bits of the third bits, where E can be a difference between N and P (e.g., a number of bits of the second quantization error 1118 can be E, where E = N - P). The seventh value can be a random value (e.g. a true random value or a pseudo-random value) and/or a noise-shaped value.

In some examples, the example digital signal modulator 1150 includes a second combining module 1122 (e.g., a summer) that combines (e.g., sums) the sixth digital value 1120 with the second truncated cyclic digital value 1124 to generate an eighth digital value 1126 ). In one example, the eighth digital value 1126 may be equal to (and/or based on) a sum of the sixth digital value 1120 and the second truncated cyclic digital value 1124 .

In some examples, the example digital signal modulator 1150 includes a second digital generator 936 (eg, a digital coordinate rotation generator) that generates the second digital value 216 as the cosine of the eighth digital value 1126 . In some examples, the second digital generator 936 operates with the second clock signal CLK 2 to generate the second digital value 216 . In some examples, the second digital generator 936 includes a lookup table of sine values and/or generates the second digital value 216 based on the lookup table. The second digital value 216 can be sent to the RF DAC 218, e.g. for the Q section 604 of the RF DAC 218.

In some examples, the RF DAC 218 converts the first digital value 214 and the second digital value 216 using one or more second clock signals to generate a transmit signal (e.g., an analog radio frequency signal, a radar signal 126, and/or a transmit signal 404) um, which includes a frequency ramp according to the techniques presented here. In some examples, the one or more second clock signals are different than the one or more first clock signals. The RF DAC 218 may operate with one or more second clock signals to convert the first digital value 214 and the second digital value 216 to generate the transmit signal. Alternatively and/or additionally, the one or more second clock signals may be the same as the one or more first clock signals. In one example, the I-section 602 of the RF DAC 218 may be operated with the first clock signal CLK 1 and the Q-section 604 of the RF DAC 218 with the second clock signal CLK 2 (e.g. to convert the first digital value 214 and convert the second digital value 216 and generate the transmit signal).

In the 12A-12B Examples of the first noise shaping module 1112 and the second noise shaping module 1116 are shown. The first in 12A The noise shaping module 1112 shown is a first order sigma-delta noise shaping module. Embodiments are contemplated where the first noise shaper 1112 is other than a first order noise shaper (e.g., the first noise shaper 1112 may be a second, third, etc. order noise shaper). Embodiments are conceivable in which the first noise shaping module 1112 is a different type of noise shaping module (other than a sigma-delta noise shaping module). In an example where the first noise shaper 1112 is a first order noise shaper, the third digital value 1114 generated by the first noise shaper 1112 may be a one-bit value. The first noise shaping module 1112 may include a third combining module 1202 (e.g., a summer) that includes the combines the first quantization error 1110 with the fourth value (shown with reference numeral 1220) to produce a ninth value 1204. In one example, the ninth value 1204 may be equal to (and/or based on) the first quantization error 1110 subtracted from the fourth value 1220 . The fourth value 1220 (e.g., a noise-shaped value and/or a random value, such as a true random value or a pseudo-random value) may be provided by a first DAC 1218 . For example, the first DAC 1218 may generate the fourth value 1220 based on an output of the first noise shaping module 1112 (e.g., the output may correspond to the third digital value 1114). In some examples, the first noise shaping module 1112 may include a first flip-flop 1212 . The first flip-flop 1212 can be operated with the first clock signal CLK 1 . In some examples, the first flip-flop 1212 may provide a first flip-flop output value 1214 to a third quantizer 1216 . For example, the first flip-flop 1212 may generate the first flip-flop output value 1214 based on a tenth value 1208 generated by a fourth combination module 1206 (eg, the tenth value 1208 may be a combination of the ninth value 1204 and an output of the first flip-flop 1212). In some examples, the fourth combinational module 1206 and the first flip-flop 1212 form an integrator. In some examples, the third quantizer 1216 may generate the third digital value 1114 based on the first flip-flop output value 1214 . In an example where the third digital value 1114 is a one-bit value, the third quantizer 1216 may generate the third digital value 1114 as 1 (or 0) based on the first flip-flop output value 1214 being smaller than a threshold, and/or the third quantizer 1216 may generate the third digital value 1114 as 1 (or 0) based on the first flip-flop output value 1214 meeting the threshold. In some examples, the third digital value 1114 may be a random value (e.g., a true random value or a pseudo-random value) and/or a noise-shaped value.

The second in 12B The noise shaping module 1116 shown is a first order sigma-delta noise shaping module. Embodiments are contemplated where the second noise shaper 1116 is other than a first order noise shaper (e.g., the second noise shaper 1116 may be a second, third, etc. order noise shaper). Embodiments are conceivable in which the second noise shaping module 1116 is a different type of noise shaping module (other than a sigma-delta noise shaping module). In an example where the second noise shaper 1116 is a first order noise shaper, the sixth digital value 1120 generated by the second noise shaper 1116 may be a one-bit value. The second noise shaping module 1116 may include a fifth combining module 1224 (e.g., a summer) that combines (e.g., sums) the second quantization error 1118 with the seventh value (shown with reference numeral 1242) to produce an eleventh value 1226. In one example, the eleventh value 1226 may be equal to (and/or based on) the second quantization error 1118 subtracted from the seventh value 1242. The seventh value 1242 (e.g., a noise-shaped value and/or a random value such as a true random value or a pseudo-random value) may be provided by a second DAC 1240 . For example, the second DAC 1240 may generate the seventh value 1242 based on an output of the second noise shaping module 1116 (e.g., the output may correspond to the sixth digital value 1120). In some examples, the second noise shaping module 1116 may include a second flip-flop 1234 . The second flip-flop 1234 can be operated with the second clock signal CLK2. In some examples, the second flip-flop 1234 can provide a second flip-flop output value 1236 to a fourth quantizer 1238 . For example, the second flip-flop 1234 may generate the second flip-flop output value 1236 based on a twelfth value 1230 generated by a sixth combination module 1228 (eg, the twelfth value 1230 may be a combination of the eleventh value 1226 and an output of the second flip-flop 1234). In some examples, the sixth combinational module 1228 and the second flip-flop 1234 form an integrator. In some examples, the fourth quantizer 1238 can generate the sixth digital value 1120 based on the second flip-flop output value 1236 . In an example where the sixth digital value 1120 is a one-bit value, the fourth quantizer 1238 may generate the sixth digital value 1120 as 1 (or 0) based on the second flip-flop output value 1236, which is smaller as a threshold, and/or the fourth quantizer 1238 may generate the sixth digital value 1120 as 1 (or 0) based on the second flip-flop output value 1236 meeting the threshold. In some examples, the sixth digital value 1120 may be a random value (e.g., a true random value or a pseudo-random value) and/or a noise-shaped value.

In some embodiments, aspects of the example digital signal modulator 950 of FIG 9A-9B and the exemplary digital signal modulator 1150 of FIG 11 be combined. For example is 13 an illustration of an example scenario 1300 with an eighth example A tenth embodiment of the techniques presented herein, the eighth example embodiment comprising an example digital signal modulator 1350 of a radar modulation signal generator (e.g. example radar modulation signal generator 402) and/or a ramp generator device (e.g. example ramp generator device 502). In one example, example digital signal modulator 1350 may correspond to (and/or be used as) example digital signal modulator 212 and/or example ramp generator device 504. In one example, digital signal modulator 1150 may be a DDFS, such as an NCO-based DDFS , include. The example digital signal modulator 1150 may include one or more components (e.g., at least one of the phase offset generator 920, the random number generator 926, the first quantizer Q1, the second quantizer Q2, the first noise shaping module 1112, the second noise shaping module 1116, etc.) of the example digital signal modulator 950 and the exemplary digital signal modulator 1150. in a 13 In the example shown, the first combination module 912 can provide the third digital value 914 as an input to the first quantizer Q1 and/or the second combination module 932 can provide the fourth digital value 934 as an input to the second quantizer Q2.

H. Other Technical Implications

Some embodiments of generating a first digital value 212 and a second digital value 214 according to the techniques presented here may enable a variety of technical features compared to other embodiments that do not use the techniques presented here.

Truncation (e.g., quantization using the first quantizer Q1 and/or the second quantizer Q2) of digital values (e.g., cyclic digital values such as phase values) provides lower cost, lower power consumption, lower hardware size, and/or lower hardware complexity (e.g. by reducing the number of bits of the digital values from N to P). In one example, to reduce a number of bits of digital values from N to P (e.g., to satisfy one or more constraints, such as a hardware complexity constraint of the digital signal modulator and/or a hardware size constraint of the digital signal modulator), it may be necessary and/or mandatory for a digital signal modulator (e.g. a DDFS) to perform quantization. However, the quantization may introduce a periodic truncation error based on a quantization error of the quantization and/or a number of truncated bits of the quantization (e.g. in an example where the quantization is performed to truncate N bits to P bits, the amount of truncated bits may be a difference between N and P) where the periodic truncation error may introduce noise and/or spikes.

A fourth technical effect that a transmit signal (e.g., an analog radio frequency signal, a radar signal 126, and/or a transmit signal 404) modulated according to the techniques presented herein may have involves mitigating and/or avoiding noise and /or spurs introduced by quantization of digital values (e.g. phase values). Accordingly, quantization using one or more of the techniques described herein may be used to reduce cost, power consumption, and/or hardware while avoiding and/or mitigating noise and/or spikes associated with quantization.

The mitigation and/or prevention of noise and/or glitches may be a result of generating the first digital value 214 and the second digital value 216 based on a random phase value (e.g., a random initial phase value), such as the random phase value 924 (e.g. combining a phase value, such as the first cyclic digital value 910, with the random phase value), such as by adding a random phase value (e.g. a random initial phase value) at the beginning of each frequency ramp calculated using the first digital value 214 and the second digital value 216 is generated. 14 14 shows an example data set 1400 that demonstrates the effect of adding random phase values at the beginning of frequency ramps using one or more of the techniques described herein on noise swing levels. In the example record 1400 from 14 the solid curve represents a first intermediate signal (at intermediate frequencies) generated using the first digital value 214 and the second digital value 216 based on a random phase value according to one or more of the techniques described herein. The dotted curve represents a second intermediate signal (at intermediate frequencies) generated without using a random phase value according to one or more of the techniques described herein. A vertical axis of the example data set 1400 may correspond to the clutter levels (in units of decibels relative to the carrier (dBc)). A horizontal axis of example data set 1400 may be Fri frequency (in units of 10 ⁷ hertz). The first intermediate signal and the second intermediate signal can be mapped to B=16, P=6, and R=4, where B corresponds to a number of bits for phase resolution (e.g., a number of bits of first bits representing a first cyclic digital value 910 indicate, and/or a number of bits of third bits indicating a second cyclic digital value 930), P corresponds to a number of bits for the quantized phase resolution (e.g. a number of bits of second bits indicating a first truncated cyclic indicating digital value 1102, and/or a number of bits fourth bits indicating a second truncated cyclic digital value 1124) and/or R corresponds to a number of bits used for RF DAC amplitude resolution. The first intermediate signal is processed from 10 ramps (e.g. ramp signals with 10 frequency ramps) transmitted with 10 random initial phases (e.g. each frequency ramp of the 10 frequency ramps is transmitted with a random initial phase of the 10 random initial phases). The second intermediate signal is processed from a single ramp signal. The first intermediate signal shows an improvement in signal-to-noise ratio of 5 to 15 decibels (e.g., about 10 decibels) compared to the second intermediate signal.

Alternatively and/or additionally, the mitigation and/or avoidance of noise and/or glitches may be a result of generating the first digital value 214 and the second digital value 216 by noise shaping (e.g. with the first noise shaping module 1112 and/or the second noise shaping module 1116).

In the 15A-15B Illustrated are example spectrograms showing the effect of generating signal ramps based on digital values (e.g., first digital value 214 and/or second digital value 216) generated by noise shaping using one or more of the techniques described herein , pointing to the noise levels. The vertical axes of the example spectrograms may correspond to time (in units of microseconds). The horizontal axes of the example spectrograms may correspond to frequency (in units of gigahertz). The color intensity of the example spectrograms changes with power. The first sample spectrogram 1500 from 15A and the second example spectrogram 1550 of 15B show a desired ramp 1502 from 7 gigahertz to 9 gigahertz in a duration of 10 microseconds. The first example spectrogram 1500 is representative of a first ramp signal (e.g., a transmit signal, such as an analog radio frequency signal, a radar signal 126, and/or a transmit signal 404) generated without the techniques for performing noise shaping presented herein. The second example spectrogram 1550 is representative of a second ramp signal (e.g., a transmit signal, such as an analog radio frequency signal, a radar signal 126, and/or a transmit signal 404) generated with noise shaping according to one or more techniques described herein (e.g., B. using the first noise shaping module 1112 and/or the second noise shaping module 1116). The first ramp signal and the second ramp signal can be mapped to N=16, P=6, and R=4, where N corresponds to a number of bits for phase resolution (e.g., a number of bits of first bits representing a first cyclic digital value 910 indicate, and/or a number of bits of third bits indicating a second cyclic digital value 930), P corresponds to a number of bits for the quantized phase resolution (e.g. a number of bits of second bits indicating a first truncated cyclic indicating digital value 1102, and/or a number of bits fourth bits indicating a second truncated cyclic digital value 1124) and/or R corresponds to a number of bits used for RF DAC amplitude resolution. As in the sample spectrograms of 15A-15B shown, the spectral purity of the second ramp signal is improved compared to the first ramp signal. For example, the first ramp signal from 15A compared to the second ramp signal of 15B exhibits more unwanted frequency ramps centered around 8 gigahertz at lower power levels (such as due to spurious swings caused by phase clipping errors). In the second ramp signal, however, a periodic phase clipping error is mitigated and/or avoided due to the noise shaping.

In 16 Illustrated is example data sets that demonstrate the effect of generating signal ramps based on digital values (e.g., first digital value 214 and/or second digital value 216) obtained by performing noise shaping using one or more of the techniques described herein are generated pointing to the spur levels. The vertical axes of the example data sets may correspond to the noise levels (in units of decibels relative to the carrier (dBc)). The horizontal axes of the example datasets may correspond to frequency (in units of gigahertz). The first sample record 1600 from 16 FIG. 12 shows a solid curve representing a first RF DAC output (e.g., the output of the RF DAC 218 before filtering) generated based on the first digital value 214 and the second digital value 216, the generated by performing noise shaping (e.g. first-order noise shaping produced by the first noise shaping module 1112 and/or the second noise shaping module 1116 is performed). The second sample record 1650 from 16 12 shows a dotted curve representing a second RF DAC output (e.g., the output of the RF DAC 218 before filtering) generated based on the first digital value 214 and the second digital value 216, without that the techniques presented here were used to perform noise shaping. For example, the solid curve of the first sample data set 1600 may be a Fast Fourier Transform (FFT) of the first RF DAC output and the dotted curve of the second sample data set 1650 may be an FFT of the second RF DAC output. As shown in the first example data set 1600 and the second example data set 1650, the noise of the first RF DAC output may be shifted to higher frequencies compared to the second RF DAC output, such as due to a low-pass filter effect of a feedback loop associated with noise shaping (e.g., a feedback loop of the first noise shaping module 1112 and/or the second noise shaping module 1116).

In 17-19 Illustrated is example data sets that demonstrate the effect of generating signal ramps based on digital values (e.g., first digital value 214 and/or second digital value 216) obtained by performing noise shaping using one or more of the techniques described herein are generated pointing to the spur levels. The vertical axes of the sample datasets in 17-19 may correspond to noise deflection levels (in units of decibels relative to the carrier (dBc)). The horizontal axes of the sample datasets in 17-19 can correspond to frequency (in units of 10 ⁷ hertz). The sample records of 17-19 include curves representative of intermediate signals (at intermediate frequencies). An intermediate signal of the intermediate signals (and/or each intermediate signal of the intermediate signals) is processed by (i) transmitting a ramp signal comprising one or more frequency ramps via a transmitter, the ramp signal being reflected from a target, (ii) downconverting the reflected ramp signal in frequency using a mixer, and/or (iii) using a processing unit (e.g. a baseband processing unit) to generate an FFT (e.g. a 1-dimensional FFT) from an output signal of the mixer. The intermediate signals can be assigned N=16, P=6 and R=4, where N corresponds to a number of bits for the phase resolution (e.g. a number of bits of first bits indicating a first cyclic digital value 910 and/or or a number of bits of third bits indicating a second cyclic digital value 930), P corresponds to a number of bits for the quantized phase resolution (e.g. a number of bits of second bits indicating a first truncated cyclic digital value 1102, and/or a number of bits of fourth bits indicating a second truncated cyclic digital value 1124) and/or R corresponds to a number of bits used for RF DAC amplitude resolution. The target ranges of the sample data sets from 18-19 can be smaller than a target range of the sample dataset from 17 .

In the sample records 1700, 1800, and 1900 from 17-19 the solid curves represent first intermediate signals based on the first digital value 214 and the second digital value 216, where the first digital value 214 and the second digital value 216 are generated by performing noise shaping using one or more of the techniques described herein . The dotted curves represent second intermediate signals based on the first digital value 214 and the second digital value 216, where the first digital value 214 and the second digital value 216 are generated without the techniques for performing noise shaping presented herein.

I. Summary of Claims

One embodiment of the techniques disclosed herein includes a method of detecting a range at a radar frequency. The method includes: performing a conversion of a timing signal to an analog signal by: generating, corresponding to the timing signal, a first digital value and a second digital value based on a random phase value and converting the first digital value and the second digital value at a radio frequency - digital-to-analog converter for generating the analog signal, wherein the first digital value and/or the second digital value correspond to a quadrature representation of a radar modulation signal; applying the conversion to generate a transmit signal at the radar frequency; and combining the transmit signal and a receive signal that includes a reflection of the transmit signal to determine the distance.

One embodiment of the techniques disclosed herein includes an apparatus for determining a range at a radar frequency. The apparatus comprises: means for performing a conversion of a timing signal into an analog signal by: generating, corresponding to the timing signal, a first digital value and a second digital value based on a random phase value and converting the first digital value and the second digital value value with a high-frequency digital-to-analog converter for generating the analog signal, the first digital value and/or the second digital value corresponding to a quadrature representation of a radar modulation signal; means for applying the conversion to generate a transmit signal at the radar frequency; and means for combining the transmitted signal and a received signal comprising a reflection of the transmitted signal to determine the distance.

An embodiment of the techniques disclosed herein includes a ramp generator apparatus comprising: a phase locked loop providing a clock signal; a clock generator that converts the clock signal into a plurality of clock signals including one or more first clock signals and one or more second clock signals; a digital ramp generator that generates a first digital value and a second digital value based on a random phase value using the one or more first clock signals, the first digital value and/or the second digital value corresponding to a quadrature representation of a ramp modulation signal; and a high frequency digital to analog converter that converts the first digital value and the second digital value to generate a high frequency analog signal comprising a frequency ramp using the one or more second clock signals.

One embodiment of the techniques disclosed herein includes a method of detecting a range at a radar frequency. The method includes performing a conversion of a timing signal to an analog signal by generating a first cyclic digital value, truncating, using a first quantizer, first bits indicative of the first cyclic digital value to second bits indicative of a first truncated cyclic digital value value, generating a first digital value based on a first quantization error of the first quantizer and a second value, combining the first digital value with the first truncated cyclic digital value to generate a third digital value, generating according to the timing signal a fourth digital value value based on the third digital value, generating a second cyclic digital value, clipping using a second quantizer, generating a second cyclic digital value, clipping using a second quantizer from third bits indicating the second cyclic digital value to fourth bits indicating a second truncated cyclic digital value, generating a fifth digital value based on a second quantization error of the second quantizer and a sixth value, combining the fifth digital value with the second truncated cyclic digital value for generating a seventh digital value, generating, according to the timing signal, an eighth digital value based on the seventh digital value, and converting the fourth digital value and the eighth digital value with a high frequency digital to analog converter for generating the analog signal, wherein the fourth digital value and/or the eighth digital value correspond to a quadrature representation of a radar modulation signal; applying the conversion to generate a transmit signal at the radar frequency; and combining the transmit signal and a receive signal that includes a reflection of the transmit signal to determine the distance.

One embodiment of the techniques disclosed herein includes an apparatus for detecting a range at a radar frequency. The apparatus comprises: means for performing a conversion of a timing signal to an analog signal by generating a first cyclic digital value, truncating, using a first quantizer, first bits indicative of the first cyclic digital value to second bits indicative of a first truncated cyclic digital value, generating a first digital value based on a first quantization error of the first quantizer and a second value, combining the first digital value with the first truncated cyclic digital value to generate a third digital value, generating, according to the timing signal, a fourth digital value based on the third digital value, generating a second cyclic digital value, truncation using a second quantizer, generating a second cyclic digital value, truncation using a second quantizer rers, from third bits indicating the second cyclic digital value to fourth bits indicating a second truncated cyclic digital value, generating a fifth digital value based on a second quantization error of the second quantizer and a sixth value, combining the fifth digital value with the second truncated cyclic digital value to generate a seventh digital value, generating, according to the timing signal, an eighth digital value based on the seventh digital value, and converting the fourth digital value and the eighth digital value with a high frequency digital analog converters for generating the analog signal, wherein the fourth digital value and/or the eighth digital value correspond to a quadrature representation of a radar modulation signal; means for applying the transformation to generate a transmit signal on the radar frequency; and means for combining the transmitted signal and a received signal comprising a reflection of the transmitted signal to determine the distance.

One embodiment of the techniques disclosed herein includes a ramp generator apparatus comprising: a phase locked loop providing a timing signal; a clock generator that converts the timing signal into a plurality of clock signals including one or more first clock signals and one or more second clock signals; a digital ramp generator that generates a first digital value and a second digital value using the one or more first clock signals, the digital ramp generator having a first quantizer that converts first bits indicative of a first cyclic digital value to second bits that specifying a first truncated cyclic digital value, a first noise shaping module that generates a third digital value based on a first quantization error of the first quantizer and a fourth value, a first combining module that combines the third digital value with the first truncated cyclic digital value for generating a fifth digital value, a second quantizer truncating third bits indicative of a second cyclic digital value to fourth bits indicative of a second truncated cyclic digital value, a second noise shaping module providing a sixth di generates a digital value based on a second quantization error of the second quantizer and a seventh value, and a second combining module that combines the sixth digital value with the second truncated cyclic digital value to generate an eighth digital value, and wherein the first digital value is based on the fifth digital value, the second digital value is based on the eighth digital value, and at least one of the first digital value and the second digital value corresponds to a quadrature representation of a ramp modulation signal; and a high frequency digital to analog converter that converts the first digital value and the second digital value to generate a high frequency analog signal comprising a frequency ramp using the one or more second clock signals.

One embodiment of the techniques disclosed herein includes a method of detecting a range at a radar frequency. The method includes: performing a conversion of a timing signal to an analog signal by: generating a first digital value and a second digital value that are quadrature representations of a radar modulation signal corresponding to the timing signal, and converting the first digital value and the second digital value at a radio frequency -digital-to-analog converter for generating the analog signal; applying the conversion to generate a transmit signal at the radar frequency; and comparing the transmitted signal and a received signal that includes a reflection of the transmitted signal to determine a distance.

One embodiment of the techniques disclosed herein includes an apparatus for determining a range at a radar frequency. The apparatus comprises: means for performing a conversion of a timing signal to an analog signal by: generating, corresponding to the timing signal, a first digital value and a second digital value which are quadrature representations of a radar modulation signal, and converting the first digital value and the second digital value with a high-frequency digital-to-analog converter for generating the analog signal; means for applying the conversion to generate a transmit signal at the radar frequency; and means for comparing the transmitted signal and a received signal that includes a reflection of the transmitted signal to determine a distance.

One embodiment of the techniques disclosed herein includes a radar modulation signal generator that includes: a phase-locked loop that provides a timing signal; a clock generator that converts the timing signal into a first clock signal and a second clock signal; a radar modulator that generates at the first clock signal a first digital value and a second digital value that are quadrature representations of a modulation signal at a modulation frequency; a high frequency digital to analog converter that converts the first digital value and the second digital value to generate an analog signal using the second clock signal; a transmitter that generates a transmit signal at the radar frequency based on the analog signal; a receiver that receives a reflection of the transmission signal; and a range finder that compares the reflection and the transmit signal to determine a range.

One embodiment of the techniques disclosed herein includes an apparatus for generating a ramp. The device comprises: means for providing a timing signal; means for converting the timing signal into a first clock signal and a second clock signal; means for generating, with the first clock signal, a first digital value and a second digital value that are quadrature representations of a ramp modulation signal; and Means of Converting, under Ver using the second clock signal, the first digital value, and the second digital value to generate an analog high frequency ramp signal.

J. Use of Terms

Although the subject matter has been described in language related to structural features and/or methodical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

As used in this application, the terms “component,” “module,” “system,” “interface,” and the like generally refer to a computing-related entity, either hardware, a combination of hardware and software, software, or software in implementation. One or more components may be localized on one computer and/or distributed across two or more computers.

Furthermore, the claimed subject matter may be implemented as a method, apparatus, or article of manufacture using standard programming and/or engineering techniques to generate software, firmware, hardware, or any combination thereof to control a computer to implement the disclosed subject matter . The term “article of manufacture” as used herein is intended to encompass a computer program accessible from any computer-readable device, carrier, or medium. It will be apparent to those skilled in the art that many changes can be made in this design without departing from the scope or spirit of the claimed subject matter.

Various embodiments are provided here. In one embodiment, one or more of the acts described may represent computer-readable instructions, stored on one or more computer-readable media, that, when executed by a computing device, cause the computing device to perform the acts described. The order in which some or all acts are described should not be construed to imply that those acts are necessarily order dependent. Alternative orders will be apparent to those skilled in the art based on the present description. It should be understood that not all acts are necessarily present in every embodiment provided herein.

Any aspect or design described herein as an "example" is not necessarily to be construed as advantageous over any other aspect or design. Rather, the use of the word "example" is intended to represent one possible aspect and/or implementation that may pertain to the techniques presented herein. Such examples are not required of these techniques, nor are they intended to be limiting. Various embodiments of such techniques may include such example alone or in combination with other features and/or vary and/or omit the example presented.

As used in this application, the term "or" is to be understood as an inclusive "or" and not as an exclusive "or". That is, unless otherwise stated or clear from the context, "X uses A or B" means any of the natural, inclusive permutations. That is, if: X uses A; X uses B; or X uses both A and B, then "X uses A or B" is true in either of the above cases. Additionally, as used in this application and the appended claims, the articles "a" and "an" can generally be construed to mean "one or more" unless otherwise specified or clear from the context that they refer to a singular form.

Although the disclosure has been shown and described with respect to one or more implementations, equivalent changes and modifications will be made by others skilled in the art based on a reading and understanding of this specification and the accompanying drawings. The disclosure includes all such modifications and alterations and is limited only by the scope of the following claims. With particular regard to the various functions performed by the components described above (e.g., elements, resources, etc.), the terms used to describe such components, unless otherwise specified, are intended to correspond to any component that has the specified performs the function of the described component (e.g., which is functionally equivalent), even if not structurally equivalent to the disclosed structure, which performs the function in the example implementations of the disclosure presented herein. Furthermore, while a particular feature of the disclosure may have been disclosed with respect to only one of multiple implementations, that feature may times combined with one or more other features of the other implementations as may be desirable and advantageous for any given or specific application. Furthermore, to the extent that the terms "includes,""having,""has,""having," or variants thereof are used in the detailed description or the claims, those terms are to be construed as inclusive in a manner similar to the term "comprising."

Claims (20)

A method of detecting a range at a radar frequency, the method comprising the acts of: Performing a timing signal to analog signal conversion by: generating, corresponding to the timing signal, a first digital value and a second digital value based on a random phase value, at least one of the first digital value and the second digital value corresponding to a quadrature representation of a radar modulation signal, and converting the first digital value and the second digital value with a high frequency digital to analog converter to generate the analog signal; applying the conversion to generate a transmit signal at the radar frequency; and Combining the transmit signal and a receive signal that includes a reflection of the transmit signal to determine the distance. procedure after claim 1 wherein generating the first digital value and the second digital value comprises: combining the random phase value with a first cyclic digital value to generate a third digital value, the first digital value being based on the third digital value; and combining the random phase value with a second cyclic digital value to produce a fourth digital value, the second digital value being based on the fourth digital value. procedure after claim 2 , wherein generating the first digital value and the second digital value comprises: generating the first digital value as a sine of the third digital value; and generating the second digital value as the cosine of the fourth digital value. procedure after claim 2 or 3 , wherein generating the first digital value and the second digital value comprises: generating an increasing digital value; integrating the increasing digital value using a first integrator to produce the first cyclic digital value; and integrating the increasing digital value with a second integrator to produce the second cyclic digital value. Procedure according to one of claims 2 until 4 , wherein: the radar modulation signal comprises a frequency ramp; the random phase value is a random initial phase value; and combining the random phase value with the first cyclic digital value and combining the random phase value with the second cyclic digital value are performed at the beginning of the frequency ramp. Procedure according to one of Claims 1 until 5 , wherein: the radar modulation signal comprises a frequency ramp. Ramp generator device comprising: a phase locked loop providing a timing signal; a clock generator that converts the timing signal into a plurality of clock signals including one or more first clock signals and one or more second clock signals; a digital ramp generator that generates a first digital value and a second digital value based on a random phase value using the one or more first clock signals, at least one of the first digital value and the second digital value corresponding to a quadrature representation of a ramp modulation signal; and a high frequency digital to analog converter that converts the first digital value and the second digital value to generate a high frequency analog signal comprising a frequency ramp using the one or more second clock signals. Ramp generator device according to claim 7 wherein the digital ramp generator comprises: a first combining module that combines the random phase value with a first cyclic digital value to generate a third digital value, the first digital value being based on the third digital value; and a second combining module that combines the random phase value with a second cyclic digital value to generate a fourth digital value, the second digital value being based on the fourth digital value. Ramp generator device according to claim 8 , where the digital ramp generator comprises: a first digital generator that generates the first digital value as a sine of the third digital value; and a second digital generator that generates the second digital value as the cosine of the fourth digital value. Ramp generator device according to claim 8 , wherein the digital ramp generator comprises: a first integrator that generates an increasing digital value; a second integrator that integrates the increasing digital value to generate the first cyclic digital value; and a third integrator that integrates the increasing digital value to generate the second cyclic digital value. Ramp generator device according to claim 8 , where: the random phase value is a random initial phase value; and the first combining module combines the random phase value with the first cyclic digital value and the second combining module combines the random phase value with the second cyclic digital value at the beginning of the frequency ramp. A method of detecting a range at a radar frequency, the method comprising the acts of: Performing a timing signal to analog signal conversion by: generating a first cyclic digital value; truncating, using a first quantizer, first bits indicative of the first cyclic digital value to second bits indicative of a first truncated cyclic digital value; generating a first digital value based on a first quantization error of the first quantizer and a second value; combining the first digital value with the first truncated cyclic digital value to produce a third digital value; generating, according to the timing signal, a fourth digital value based on the third digital value; generating a second cyclic digital value; truncating, using a second quantizer, third bits indicative of the second cyclic digital value to fourth bits indicative of a second truncated cyclic digital value; generating a fifth digital value based on a second quantization error of the second quantizer and a sixth value; combining the fifth digital value with the second truncated cyclic digital value to produce a seventh digital value; generating, corresponding to the timing signal, an eighth digital value based on the seventh digital value, wherein at least one of the fourth digital value and the eighth digital value corresponds to a quadrature representation of a radar modulation signal; and converting the fourth digital value and the eighth digital value with a high frequency digital to analog converter to generate the analog signal; applying the conversion to generate a transmit signal at the radar frequency; and Combining the transmit signal and a receive signal that includes a reflection of the transmit signal to determine the distance. procedure after claim 12 comprising: generating an increasing digital value, wherein: generating the first cyclic digital value comprises integrating the increasing digital value using a first integrator to generate the first cyclic digital value; and generating the second cyclic digital value comprises integrating the increasing digital value using a second integrator to generate the second cyclic digital value. procedure after claim 12 or 13 , wherein: generating the fourth digital value comprises generating the fourth digital value as a sine of the third digital value; and generating the eighth digital value comprises generating the eighth digital value as the cosine of the seventh digital value. Procedure according to one of Claims 12 until 14 , wherein: the second value is at least one of a first random value and a first noise-shaped value; and the sixth value is at least one of a second random value and a second noise-shaped value. A ramp generator apparatus comprising: a phase locked loop providing a timing signal; a clock generator that converts the timing signal into a plurality of clock signals including one or more first clock signals and one or more second clock signals; a digital ramp generator generating a first digital value and a two generates the th digital value, wherein: the digital ramp generator comprises: a first quantizer that truncates first bits indicative of a first cyclic digital value to second bits indicative of a first truncated cyclic digital value; a first noise shaping module that generates a third digital value based on a first quantization error of the first quantizer and a fourth value; a first combining module that combines the third digital value with the first truncated cyclic digital value to generate a fifth digital value; a second quantizer that truncates third bits indicative of a second cyclic digital value to fourth bits indicative of a second truncated cyclic digital value; a second noise shaping module that generates a sixth digital value based on a second quantization error of the second quantizer and a seventh value; and a second combining module that combines the sixth digital value with the second truncated cyclic digital value to produce an eighth digital value; the first digital value is based on the fifth digital value; the second digital value is based on the eighth digital value; and at least one of the first digital value and the second digital value corresponds to a quadrature representation of a ramp modulation signal; and a high frequency digital to analog converter that converts the first digital value and the second digital value to generate a high frequency analog signal comprising a frequency ramp using the one or more second clock signals. Ramp generator device according to Claim 16 , wherein the digital ramp generator comprises: a first integrator that generates an increasing digital value; and a second integrator that integrates the increasing digital value to produce the first cyclic digital value; and a third integrator that integrates the increasing digital value to generate the second cyclic digital value. Ramp generator device according to Claim 16 or 17 , wherein the digital ramp generator comprises: a first digital generator that generates the first digital value as a sine of the fifth digital value; and a second digital generator that generates the second digital value as the cosine of the eighth digital value. Ramp generator device according to one of Claims 16 until 18 , where: the fourth value is a first random value; and the seventh value is a second random value. Ramp generator device according to one of Claims 16 until 19 , where: the fourth value is a first noise-shaped value; and the seventh value is a second noise-shaped value.

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