DE102022203733A1 - Method for generating control signals for power switches in a resonant DC/DC converter - Google Patents

Abstract

Control signals for power switches in a resonant DC/DC converter, for example an LLC converter, are generated by counting a cycle number, for example 1000, of clock cycles of a high frequency, for example 100 MHz. For a given target switching frequency, a sequence of two or more different cycle numbers is used, which is repeated periodically and thus generates the target switching frequency on average over time, although the switching distance between two switching processes is different from the target switching frequency.

Description

The invention relates to a method for generating control signals for power switches in a resonant DC/DC converter and a resonant DC/DC converter in which such a method is used.

High-performance resonance converters require control signals with very high frequency resolutions for precise power adjustment. Frequency resolutions of less than 1 Hz may be required. High frequency resolutions enable designs of a resonance converter in which the entire operating range can be set over a narrow frequency band near the resonance point. This results in better efficiency over the working range compared to designs with a wider frequency band.

Furthermore, a frequency resolution that is too imprecise in applications with a wide working range can mean that this application cannot be represented with a resonance converter with reasonable effort.

Control signals with high frequency resolution can be generated using high-performance microcontrollers or FPGAs. If the resolution is to be increased even further, a microcontroller-controlled VCO (Voltage Controlled Oscillator) can be used, from whose signals an FPGA generates the control signals.

If the use of the electronic components mentioned is excluded for reasons of economic efficiency, designs with a wider frequency band are disadvantageously used at the expense of efficiency.

It is the object of the invention to provide a method for generating control signals for power switches in a resonant DC/DC converter and a resonant DC/DC converter, in which a simplified generation of control signals with high frequency resolution is possible.

This task is achieved by a method with the features specified in claim 1. Furthermore, the task is solved by a resonant DC/DC converter with the features of claim 7.

In the method according to the invention for generating control signals for power switches in a resonant DC/DC converter, a target switching frequency is determined with which the control signals are to be generated at a given operating point of the DC/DC converter over several switching cycles. Furthermore, at least two different cycle numbers are determined from the target switching frequency and the frequency of a clock generator in a microcontroller. A cycle number is a number of cycles of the clock generator, the elapse of which determines the time interval between two successive control signals. Furthermore, a resulting switching frequency due to the first cycle number is higher than the target switching frequency and a resulting switching frequency due to the second cycle number is lower than the target switching frequency. Finally, within a plurality of switching cycles, the first and second cycle numbers are each used at least once to determine the time interval between two successive control signals.

The resonant DC/DC converter according to the invention includes several power switches and a microcontroller. The microcontroller is designed to generate control signals for the power switches and is further designed to determine a target switching frequency with which the control signals are to be generated at a given operating point of the DC/DC converter over several switching cycles, from the target switching frequency and the frequency of a clock generator in a microcontroller to determine at least two different cycle numbers, whereby a cycle number is a number of cycles of the clock generator, the elapse of which determines the time interval between two successive control signals and a resulting switching frequency is higher than the target due to the first cycle number -Switching frequency and a resulting switching frequency due to the second cycle number is less than the target switching frequency. Finally, the microcontroller is designed to use the first and second cycle numbers at least once within a plurality of switching cycles in order to determine the time interval between two successive control signals.

The control signals are the signals that ultimately cause the circuit breakers to be switched on and off. In this case, post-processing of the control signals can take place; for example, dead times can be waited for a control signal. The circuit breakers are, for example, those of a primary-side inverter that feeds a transformer of the DC/DC converter. This can be two circuit breakers that form a half bridge or four circuit breakers that form a full bridge.

The target switching frequency corresponds to a frequency of switching of the circuit breakers to be used for the current operating point, at which, for the example of a full bridge, the two pairs of diagonal switches are switched on or off, with the switching on is delayed by a dead time compared to switching off. The time range in which a single switching takes place is called a switching cycle. The target switching frequency is valid and constant for several switching cycles, but can change in periods that are longer than one switching cycle.

The clock generator is, for example, an oscillator of a microcontroller used in the DC/DC converter, which provides a clock frequency of, for example, 100 MHz or 1 GHz or 5.4 GHz. A clock cycle refers to one period of the clock, i.e. 10 ns at a clock frequency of 100 MHz.

The cycle numbers denote a number of clock cycles that elapse to determine the length of a switching cycle, i.e. the interval between two switches. The cycle numbers therefore correspond to a multiplier of the clock cycle or a divisor of the clock frequency. A cycle number N _Z of 1000 corresponds to a switching frequency of f _T / N _Z = 100 kHz at a clock frequency f _T of 100 MHz. It goes without saying that the cycle numbers are always integers.

The invention ensures that a switching frequency that cannot be precisely achieved with an integer multiple of the frequency of the clock generator can nevertheless be produced as an average at least over a plurality of switching cycles. The majority of switching cycles are at least two switching cycles.

Advantageously, square-wave control signals with a high switching frequency of, for example, 100 kHz or more and a very high frequency resolution below 0.1% of the switching frequency can be generated directly with a simple microcontroller.

This eliminates the need to use technically more complex and cost-intensive components such as a voltage-controlled oscillator and FPGA or high-performance microcontrollers. The invention enables the use of resonance converters in applications with very high requirements for frequency resolution with reasonable effort.

The DC/DC converter in particular has a nominal power of more than 20 kW. Especially with such high power levels, it is difficult to provide a current transformer with acceptable properties such as weight and size. For this purpose, it is useful if the power switches installed in the DC/DC converter have a current carrying capacity of at least 100 A and/or a reverse voltage strength of at least 100 V.

• Die erste und die zweite Zykluszahl sind bevorzugt aufeinanderfolgende ganze Zahlen. Durch ein Abwechseln zwischen möglichst nahe aneinander liegenden Schaltabständen werden höherfrequente Anteile des Schaltfrequenzmusters gering gehalten.

Advantageous embodiments of the method according to the invention and DC/DC converters emerge from the dependent claims. The embodiment of the independent claims can be combined with the features of one of the subclaims or preferably also with those from several subclaims. Accordingly, the following additional features can be provided:

• The first and second cycle numbers are preferably consecutive integers. By alternating between switching distances that are as close to one another as possible, higher-frequency components of the switching frequency pattern are kept low.

Within a plurality of switching cycles, the first and second cycle numbers can be used alternately to determine the time interval between two successive control signals. In this way, a target switching frequency can be set on average, which corresponds to the average of two actually achievable switching frequencies. For example, an average switching frequency of approx. 88025 Hz can be set if the actually achievable switching frequencies are 88050 Hz and 88000 Hz by counting cycle numbers.

Preferably, a first integer number for the first cycle number and a second integer number for the second cycle number are determined in such a way that a switching frequency results on average when the first number of switching cycles with the first cycle number and the second number of switching cycles with the second cycle number are lined up , which deviates from the target switching frequency by less than 5 Hz, in particular less than 1 Hz. This means that any target switching frequency can be approximated by appropriately repeating the switching distances that can be achieved by counting the clock cycles. In this case, the plurality of switching cycles over which the first and second cycle numbers are used includes a number of switching cycles that corresponds to the sum of the first number and the second number.

Preferably, a sequence is created from the cycle numbers whose length corresponds to the sum of the first and second integer numbers and in which the first cycle number occurs according to the first number and the second cycle number occurs according to the second number. The sequence is written to a memory area along with an indicator of its length. This means that the data is completely available for ongoing switching operation and no longer needs to be recalculated until a new target switching frequency is determined.

It is expedient to periodically repeat the sequence of cycle numbers, which contains at least two different cycle numbers. In other words, the cycle numbers are used once in sequence and then, after using the last cycle number of the sequence, it returns to the first cycle number of the sequence and uses the sequence one more time. With each repetition, the first and second number of cycle numbers are retained, but the arrangement of the cycle numbers is also preferred.

Preferably, the entire duration over which the average is taken, i.e. the sum of all the number of cycles in the sequence multiplied by the clock period duration, is smaller than a period duration of the overall circuit of the DC/DC converter, the period duration of the overall circuit being the inverse time constant results from the components of the DC/DC converter, these components also including, for example, an output capacitor.

Within a switching cycle, the number of cycles used for the switching cycle can be written into a register used for counting the clock cycles using direct memory access. This advantageously relieves the microcontroller of the task of writing the cycle numbers into the register. Since this task must be performed with a frequency equal to the switching frequency, this can save significant load on the microcontroller. It is particularly advantageous if the cycle numbers are already available as a sequence in the memory and can be read out one after the other.

The resonant DC/DC converter can be a DC/DC converter based on the LLC principle. With these converters, a design can be achieved with a very precise frequency setting in which the entire working range can be set over a narrow frequency band close to the resonance point. This results in better efficiency over the working range compared to designs with a wider frequency band.

• 1 ein Schaltbild eines DC/DC-Wandlers nach dem LLC-Prinzip,
• 2 ein Schema der Erzeugung der Ansteuersignale durch Abzählung der Zyklen eines Taktgebers,
• 3 und 4 Schemata der Erzeugung der Ansteuersignale für verschiedene Soll-Schaltfrequenzen.

The invention is described and explained in more detail below using the exemplary embodiments shown in the figures. Show it:

• 1 a circuit diagram of a DC/DC converter based on the LLC principle,
• 2 a scheme for generating the control signals by counting the cycles of a clock generator,
• 3 and 4 Schemes for generating the control signals for different target switching frequencies.

1 shows an electrical circuit diagram of an LLC-type DC/DC converter 10. The DC/DC converter 10 includes a full bridge 110 made of a first to fourth MOSFET (metal-oxide-semiconductor field-effect transistor) 11...14. The MOSFETs 11...14 are in 1 shown together with its body diode. In this exemplary embodiment, these additional components are not actually separate components.

The MOSFETs 11...14 form two half-bridges connected in parallel in a known manner, each of the half-bridges comprising two of the MOSFETs 11...14 in series connection in the same direction. The full bridge 110 is connected to the external connections of the half bridges to input connections 15, 16 for a direct voltage.

A series circuit consisting of a series resonance inductance 191, a resonance capacitor 192 and a parallel circuit consisting of the primary side 21 of a transformer 20 and a parallel resonance inductance 193 is connected between the midpoints 17, 18 of the half bridges. The secondary side 22 of the transformer 20 is in turn connected to a bridge rectifier 23. The bridge rectifier 23 includes four diodes 24...27, which are connected together to form a full bridge. A smoothing capacitor 29 is connected parallel to the output of the bridge rectifier and parallel to a symbolic load 35.

To control the DC/DC converter 10, accurate and dynamic measurement of the current is required. This current measurement is indicated by the current measuring device 194. This is in 1 shown in series to the serial resonance inductance 191. The current measuring device 194 is connected to a controller which is in 1 is not shown. The control provides, among other things, the control signals for the MOSFETs 11...14. It is formed by a microcontroller 30.

In the case of the DC/DC converter 10, it is very advantageous for its efficiency if the control signals for the MOSFETs 11...14 have a very high frequency resolution of less than 1 Hz. Such high frequency resolutions enable designs of a resonance converter in which the entire operating range can be set over a narrow frequency band near the resonance point. This results in better efficiency over the working range compared to designs with a wider frequency band.

In the present exemplary embodiment, these control signals are generated from a clock generator of the microcontroller 30. In this example, the clock should have a frequency of 100 MHz have. In other examples, the frequency can also be significantly higher, for example 5.44 GHz.

The distance between two successive control signals for one of the MOSFETs 11...14 is determined by counting an integer number of clock cycles of the clock generator. If, for example, 1000 cycles are counted between two control signals with a clock generator with a 100 MHz clock frequency, the time interval between the control signals is 1000 * 1 / 100 MHz = 10 ps. This time interval corresponds to a switching frequency of 100 kHz. This situation is in 2 shown.

2 shows a time course of the processing of the control by the microcontroller 30. In the microcontroller 30, a counter is incremented with each cycle of the clock generator, i.e. here with a frequency of f _T = 100 MHz, i.e. increased by one with each clock cycle. After each increase, a comparison is made with the contents of a timer register. The timer register contains the current cycle number, here 1000. If this value is reached in the counter, a control signal for switching the MOSFETs 11...14 is triggered. The counter is then reset to 0.

The resulting time course of the counter value is in 2 shown as counter line 201. For better visibility of the gradient, part of the gradient is omitted, as 1000 levels would not be displayable or would appear as a continuous line. In 2 The clock period T _T = 1 / f _T and the switching period T _A = 1 / f _A are also visible. In this example, the switching period corresponds exactly to the target switching period T _S = 1 / f _S with the target switching frequency f _S .

If only 999 cycles of the clock generator are counted instead of 1000 cycles, then the time interval between the control signals is 9.99 ps, which corresponds to a frequency of 100, 100, 100... Hz or approx. 100.1 kHz. A resolution of approx. 100 Hz can therefore be achieved in the range at 100 kHz switching frequency.

In order to achieve optimal control for the DC/DC converter, it is very advantageous if switching frequencies between these values can also be achieved, for example 100,050 Hz or 100,030 Hz. It was recognized that it is not necessary for these frequencies , i.e. the corresponding time interval is maintained exactly for each switching process. Rather, it is sufficient if these switching frequencies are achieved over a time range that includes several switching operations (switching cycles).

To generate a switching frequency between 100 kHz and 100.1 kHz, different numbers of cycles are advantageously counted alternately for the respective switching distance. The number of cycles used for this is calculated by the microcontroller or looked up in a table as soon as the new frequency is required.

In a first example, a target switching frequency of 100,050 Hz should be used. The microprocessor calculates that this frequency can be achieved on average with a very small error from a sequence of just two different lengths of the switching cycle. It is only necessary to alternately use the cycle numbers 1000 and 999. The resulting frequency of approximately 100050.05 Hz only deviates from the target switching frequency by approximately 50 mHz.

The resulting sequence of switching cycles is analogous to 2 in 3 shown. The resulting time course of the counter value is in 3 shown as counter line 301. As in 2 Some areas are not shown for better visibility of the course.

In 3 The clock period duration T _T = 1 / f _T and one of the switching periods T _A = 1 / f _A are again visible. In this example, the switching period does not correspond to the target switching period T _S = 1 / f _S with the target switching frequency f _S . Rather, different switching period durations are used alternately, which, on average over two switching periods, result in almost exactly the desired target switching frequency of 100,050 Hz. The target switching period T _S is therefore only achieved when averaging over two switching cycles.

• ... 999, 1000, 999, 1000, 999, 1000, 999, 1000, 999, 1000, 999, 1000, 999, 1000, ...

The minimum sequence of cycle numbers that is used for control is: 999, 1000. Since this sequence is repeated until a changed target switching frequency is present, the sequence of cycle numbers used looks like this:

• ... 999, 1000, 999, 1000, 999, 1000, 999, 1000, 999, 1000, 999, 1000, 999, 1000, ...

In a second example, a target switching frequency of 100,030 Hz should be used. If the very short periodic sequence of only three cycle numbers 999 and twice 1000 is used, the result is a frequency of approx. 100033 Hz, which means a deviation of approx. 3 Hz from the target switching frequency. This deviation may be too large and therefore undesirable.

In this case, the microprocessor can calculate a more precise sequence of cycle numbers that must be used to achieve the target switching frequency with a given maximum deviation. For example, as a periodic sequence three times the cycle number 999 and seven times the cycle number 1000 can be used to achieve a frequency of approx. 100030.03 Hz. The resulting distance from the target switching frequency is only approx. 0.03 Hz and is therefore significantly smaller than 1 Hz. To do this, 10 switching cycles must be averaged over a time of approx. 0.1 ms in order to actually reach this switching frequency to reach. It goes without saying that it is preferred to alternate between cycle numbers 1000 and 999 and that each of the cycle numbers is repeated as rarely as possible, as far as this is possible given the given periodic sequence of cycle numbers.

4 shows an analog representation 3 with the cycle sequence that can be used for a target switching frequency of 100030 Hz.

The resulting sequence of switching cycles is analogous to 3 in 4 shown. The resulting time course of the counter value is in 4 shown as counter line 401. As in 2 Some areas are not shown for better visibility of the course.

In 4 The clock period T _T = 1 / f _T and the switching period T _A = 1 / f _A are again visible. Here too, the switching period T _A does not correspond to the target switching period T _S = 1 / f _S with the target switching frequency fs for any of the switching cycles. Rather, different switching period durations are also used here, which, on average over ten switching periods, result in almost exactly the desired target switching frequency of 100,030 Hz.

Wobei f_T die Taktgeberfrequenz, beispielsweise 100 MHz ist und f_S die Soll-Schaltfrequenz. Floor() bezeichnet eine Funktion, die die nächstniedrigere ganze Zahl des Eingangswerts zurückgibt.If a target switching frequency is to be displayed that lies outside the frequency range between 100,000 Hz and 100,100 Hz, then other cycle numbers are used. The cycle numbers Z ₁ and Z ₂ used are preferably adjacent, so in other words Z ₁ = 1 + Z ₂ applies. Furthermore, the resulting frequency with only the first cycle number Z ₁ is smaller than the target switching frequency and the resulting frequency with only the second cycle number Z ₂ is greater than the target switching frequency. The second cycle number can therefore be formed by calculating: $${\text{<figure-callout id="2" label="Z" filenames="DE102022203733A1\_0003.png" state="{{state}}">Z</figure-callout>}}_2=\text{floor}\left({\text{f}}_{\text{T}}/{\text{f}}_{\text{S}}\right)$$

Where f _T is the clock frequency, for example 100 MHz, and f _S is the target switching frequency. Floor() denotes a function that returns the next lower integer of the input value.

The microcontroller 30 only has to determine the cycle numbers when a new target switching frequency is used. The microcontroller 30 can then calculate the cycle numbers or take them from a table that has been pre-filled or filled during operation. Even if only the two switching frequencies associated with the current cycle numbers are buffered, a new calculation is only required if a new target switching frequency is no longer between these two switching frequencies.

The timer register, whose contents determine how long the switching intervals are, must be filled with the switching frequency. In order to avoid having to use the microcontroller 30's computing time for this, the currently used sequence of cycle numbers can be saved in advance as a sequence of numbers. The cycle number for the next switching process can then advantageously be written from the number sequence into the timer register using DMA (direct memory access, i.e. writing to a memory cell without direct involvement of the processor). The pointer for the DMA is then incremented so that the next cycle number is accessed during the next write operation.

• 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999

So for the target switching frequency of 100030 Hz, the following sequence of cycle numbers would be written into memory and provided to the DMA:

• 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999

• ... 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999 ...

Since this sequence is also repeated until a new target switching frequency is available, the sequence of cycle numbers used looks like this:

• ... 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 999, 1000 , 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 999, 1000, 1000, 1000, 999, 1000, 1000, 999 ...

It is understood that when the end of the number sequence is reached, the first value of the number sequence is returned. If there is a changed target switching frequency, the microcontroller 30 calculates a new number sequence, which expediently sets the DMA pointer back to the first value of the new number sequence. By using the DMA, the computing power of the microcontroller 30 is only required when a new target switching frequency is set.

A target switching frequency of 99980 Hz can be achieved very precisely with a sequence of four times a cycle number of 1000 and once a cycle number of 1001. This cycle number sequence results in a frequency of approx. 99980.02 Hz. The deviation of approx. 0.2 Hz is again very small. The averaging of the frequency and the periodic repetition of the switching sequence In this case, it takes place over five switching cycles.

To determine the sequence of numbers, a target cycle number is first determined as Z _S = f _T / f _S . This can be, for example, 999.72 and will typically not be an integer. The second cycle number is subtracted from this target cycle number, so that only the decimal remainder remains, i.e. 0.72 in this example. The resulting number sequence is constructed as a sequence of the numbers 0 and 1, where 0 represents the second cycle number 999 and 1 represents the first cycle number 1000.

The number sequence is started with a 0 and then a 0 is chosen for each next number if the mean of the number sequence is greater than the remainder and otherwise a 1. If the mean of the sequence of 0 and 1 corresponds exactly to the determined remainder, then the Target switching frequency is exactly reached with the sequence of numbers shown in this way and the sequence is complete. Otherwise, further numbers, i.e. 0 or 1, are added to the number sequence until a predefined maximum length is reached.

• 0,
• 1 (Mittelwert 0 < 0,72, Abstand 0,72),
• 1 (Mittelwert 0,5 < 0,72, Abstand 0,22),
• 1 (Mittelwert 0,666666 < 0,72, Abstand 0,0533333),
• 0 (Mittelwert 0,75 > 0,72, Abstand 0,03),
• 1 (Mittelwert 0,6 < 0,72, Abstand 0,12),
• 1 (Mittelwert 0,666666 < 0,72, Abstand 0,0533333),
• 1 (Mittelwert 0,714285 < 0,72, Abstand 0,0057143),
• 0 (Mittelwert 0,75 > 0,72, Abstand 0,03), ...

For the example with a remainder of 0.72, the following numbers result:

• 0,
• 1 (mean 0 < 0.72, distance 0.72),
• 1 (mean 0.5 < 0.72, distance 0.22),
• 1 (mean 0.666666 < 0.72, distance 0.0533333),
• 0 (mean 0.75 > 0.72, distance 0.03),
• 1 (mean 0.6 < 0.72, distance 0.12),
• 1 (mean 0.666666 < 0.72, distance 0.0533333),
• 1 (mean 0.714285 < 0.72, distance 0.0057143),
• 0 (mean 0.75 > 0.72, distance 0.03), ...

In this example, the number sequence ends with 25 numbers and 18 times the number 1, since this results in exactly the value 18 / 25 = 0.72. In real examples, where the frequencies are any real numbers and the number of their decimal places is usually limited by the representation in the microprocessor 30, the number sequence usually only ends when the maximum length is reached.

After determining the number sequence, which will usually be exactly the same length with a maximum length of, for example, 1000 entries, it can be determined at which length the greatest accuracy is achieved, since this is not necessarily the case with the greatest length. Even from the few numbers in the example above it is clear that the accuracy, i.e. the distance to the rest, fluctuates. Within the first 9 numbers, the accuracy is highest after the seventh number.

To do this, subsequences of the number sequence are considered, which range from the first number to the nth number, and their accuracy is determined. This determination can also take place during the determination of the number sequence, since such partial sequences are always present in this step. The resulting distance is therefore already stated above. The subsequence with the smallest distance is now actually used. If the maximum length of the number sequence were 9 numbers, then the number sequence up to the seventh number would be used in the example above, as this achieves the smallest distance from the rest and thus the greatest accuracy.

5 schematically represents the method used, which is implemented programmatically in the microcontroller 30. The method is based on a first step 501, in which a target switching frequency was determined and this target switching frequency should now be used.

In a second step 502, a suitable first and second cycle number is determined from the target switching frequency. These are integers and, as already described, are preferably such that the switching frequencies resulting from using the two cycle numbers enclose the target switching frequency. Furthermore, the cycle numbers are preferably, but not necessarily, adjacent numbers. Furthermore, a sequence of cycle numbers is determined from the target switching frequency, when used, on average, almost the target switching frequency results as the mean switching frequency. The sequence of numbers is stored in a memory area of the microcontroller 30, expediently with information about the length of the sequence or an end marker after the end of the sequence. A pointer to a number to be used next in the sequence is set to the first number in the sequence.

In a third step 503, the number of the sequence pointed to by the pointer is written into a timer register. After calculating a new sequence in the second step 502, this is the first number of the sequence, but later also the following numbers. After writing to the timer register, the pointer is incremented, so it now points to the next number in the sequence. If the end of the sequence has been exceeded, the pointer is reset to the first number, which results in a periodic repetition of the sequence becomes. A counter for counting the number of cycles is set to 0.

In the fourth step 504, which contains sub-steps, a time is counted and thus waited for, which results from the number of cycles in the timer register and the frequency of the clock generator. For this purpose, in a fifth step 505 the counter is incremented and in a sixth step 506 it is determined whether the counter is equal to (or greater than) the value in the timer register. If this is not the case, the process returns to the fifth step 505, the speed of this sequence of steps being regulated by the cycles of the clock generator.

If the value of the timer register is reached, a switching process is triggered in a seventh step 507. This process can contain further steps such as maintaining dead times, so it is itself a complex step, but the details of which do not influence the procedure shown.

In an eighth step 508 following the seventh step 507, it is determined whether a new target switching frequency is necessary. If this is the case, the second step 502 returns. If this is not the case, the method continues with the third step 503.

Reference symbols

10

DC/DC converter

11...14

MOSFET

15, 16

Input connections

17, 18

Center points of the half bridges

191

serial resonance inductance

192

Resonance capacitor

193

parallel resonance inductance

194

Current measuring device

20

transformer

21

primary page

22

Secondary side

23

Bridge rectifier

24...27

diodes

29

Smoothing capacitor

30

Microcontroller

35

load

110

Full bridge

201, 301, 401 501...507

Switching lines first to seventh step

fS

Target switching frequency

fa

Switching frequency

fT

Clock frequency

Claims (10)

Method (500) for generating control signals for power switches (11...14) in a resonant DC/DC converter (10), in which - a target switching frequency (f _S ) is determined with which the control signals in a given Operating point of the DC/DC converter (10) is to be generated over several switching cycles, - at least two different cycle numbers are determined from the target switching frequency (f _S ) and the frequency (f _T ) of a clock generator in a microcontroller (30), where - a cycle number is a number of cycles of the clock generator, the elapse of which determines the time interval between two successive control signals, - a resulting switching frequency (f _A ) is higher than the target switching frequency (f _S ) due to the first cycle number and a resulting switching frequency (f _A ) due to the second number of cycles is less than the target switching frequency (f _S ), - within a plurality of switching cycles, the first and second number of cycles are each used at least once to determine the time interval between two successive control signals. Procedure (500). Claim 1 , where the first and second cycle numbers are consecutive integers. Procedure (500). Claim 1 or 2 , in which the first and second cycle numbers are used alternately within a plurality of switching cycles to determine the time interval between two successive control signals. Method (500) according to one of the preceding claims, in which a first integer number for the first cycle number and a second integer number for the second cycle number are determined such that when the first number of switching cycles are lined up with the first cycle number and the second number of switching cycles with the second number of cycles results in a switching frequency (f _A ) on average that deviates from the target switching frequency (f _S ) by less than 5 Hz, in particular less than 1 Hz. Procedure (500). Claim 4 , in which - a sequence is created from the cycle numbers, the length of which corresponds to the sum of the first and second integer numbers and in which the first cycle number occurs according to the first number and the second cycle number occurs according to the second number, - the sequence together with a Indicator of their length is written into a memory area of the microcontroller (30). Procedure (500). Claim 5 , in which the sequence of cycle numbers is used periodically repeatedly. Method (500) according to one of the preceding claims, in which, within a switching cycle, the number of cycles used for the switching cycle is written into a register used for counting the clock cycles by means of direct memory access. Resonant DC/DC converter (10), comprising several power switches (11...14) and a microcontroller (30), designed to generate control signals for the power switches (11...14) and further designed - a target Determine the switching frequency (f _S ) with which the control signals are to be generated at a given operating point of the DC/DC converter (10) over several switching cycles, - from the target switching frequency (f _S ) and the frequency (f _T ) of a clock generator in a microcontroller (30) to determine at least two different cycle numbers, a cycle number being a number of cycles of the clock generator, the elapse of which determines the time interval between two successive control signals and a resulting switching frequency (f _A ) higher due to the first cycle number is than the target switching frequency (f _S ) and a resulting switching frequency (f _A ) due to the second cycle number is less than the target switching frequency (f _S ), - within a plurality of switching cycles, the first and second cycle numbers each at least once to be used to determine the time interval between two successive control signals. Resonant DC/DC converter (10). Claim 8 according to the LLC principle. Resonant DC/DC converter (10). Claim 8 or 9 , in which the current carrying capacity of the circuit breakers (11...14) is at least 100 A and/or in which the blocking voltage strength of the circuit breakers (11...14) is at least 100 V.

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