DE102022203328A1 - Method and device for processing data associated with a computing device - Google Patents

Abstract

Method, for example computer-implemented method, for processing data associated with a computing device, comprising: providing at least a first queue in a first memory area which can be accessed, for example exclusively, by a first process associated with the computing device and a second process associated with the computing device .

Description

State of the art

The disclosure relates to a method for processing data associated with a computing device.

The disclosure further relates to a device for processing data associated with a computing device.

Disclosure of the invention

Exemplary embodiments relate to a method, for example a computer-implemented method, for processing data associated with a computing device, comprising: providing at least a first queue in a first memory area to which, for example exclusively, a first process associated with the computing device and a second process associated with the computing device can access. In further exemplary embodiments, this enables an efficient provision of means for data exchange between processes, for example the computing device, for example in a shared memory (i.e., for example a “shared”) memory area to which the relevant processes, but not other, further processes, for example , can access.

In further exemplary embodiments it is provided that the method comprises: using the at least one first queue for a data exchange between the first process and the second process, for example using at least one of the following elements: a) sending data, for example in the form at least one first message, from the first process to the second process, b) sending data, for example in the form of at least one second message, from the second process to the first process.

In further exemplary embodiments it is provided that the at least one first queue is provided and at least one further, for example second, queue, whereby, for example, the at least one further, for example second, queue is also provided in the first memory area, for example exclusively , the first process associated with the computing device and the second process associated with the computing device can access. In further exemplary embodiments, this enables efficient data communication between the first process and the second process, for example in both directions (e.g. from the first process to the second process and vice versa). For example, the first queue may be used for a first direction of data communication between the first process and the second process, and the second queue may be used, for example, for a second direction of data communication between the first process and the second process.

In further exemplary embodiments it is provided that the method has: Preventing, for example, apart from the first process and the second process, further processes associated with the computing device from accessing the first memory area, for example on the at least one first queue (and/or the second queue).

In further exemplary embodiments, it is provided that the method comprises: assigning access rights to the first memory area and/or to the at least one first queue (and/or the second queue), for example exclusively, for the first process and the second process.

In further exemplary embodiments it is provided that the method comprises: plausibility check of at least one component of the at least one first queue. In further exemplary embodiments, this enables an increase in the security, for example, of the data associated with the at least one first queue. For example, the plausibility check in further exemplary embodiments can identify situations in which a memory area associated with the at least one first queue has been undesirably modified, for example accidentally or due to an error, or in which a different, undesirable change to the content of the at least one queue has been made a memory area associated with a first queue (e.g. flipping of a bit in the memory area).

In further exemplary embodiments it is provided that the method has at least one of the following elements: a) using at least one FIFO (first in first out) memory for the at least one queue, for example the at least one FIFO memory has a first state variable, for example Tail variable, which characterizes a read position, for example, the at least one FIFO memory has a second state variable, for example head variable, which characterizes a write position, for example, each element of the at least one FIFO memory has a sequence number and useful data has, b) specifying a size of one or the at least one FIFO memory, for example determining a number of elements, c) statically allocating one or the number of elements, d) using index variables for the at least one state variable, e) not using pointer variables for the at least one state variable, f) using a, for example statically coded, modulo operator for accessing elements of the at least one FIFO memory, for example the modulo operator being associated with the number of elements of the at least one FIFO memory, in particular not using a variable for accessing elements of the at least one FIFO memory, g) storing at least one component of the at least one FIFO memory, for example a size of the at least one FIFO memory, by means of a variable that is associated with a private memory area of at least one process, for example a high ASIL process , is associated, h) modifying at least one component of the at least one FIFO memory, for example a size of the at least one FIFO memory, for example during a runtime of the at least one process, for example reducing the size of the at least one FIFO memory during the runtime of the at least one process.

In further exemplary embodiments, it is provided that the method has at least one of the following elements: a) storing components of the at least one queue, for example the at least one FIFO memory, together with a comparison value, b) checking the plausibility of at least one component of the at least one queue , for example the at least one FIFO memory, based on one or the comparison value, c) carrying out a plausibility check for at least some, for example all, read accesses to the at least one component of the at least one queue, d) initiating an error reaction, for example Propagating a detected error, for example based on a plausibility check, for example the error reaction having at least one of the following elements: d1) initializing, for example reinitializing, the at least one first queue, d2) resending a message, for example in the case of defective user data , d3) restarting at least one process, e) atomically executing accesses to at least one component of the at least one queue, for example the at least one FIFO memory, f) lock-free executing accesses to at least one component of the at least one queue, for example the at least one FIFO memory.

In further exemplary embodiments it is provided that the method has at least one of the following elements: a) determining at least one comparison value for at least one component of the at least one queue, for example the at least one FIFO memory, and, optionally, storing the at least one component of the at least one queue, for example of the at least one FIFO memory, together with the comparison value.

In further exemplary embodiments, it is provided that the determination of the at least one comparison value has at least one of the following elements: a) forming a value that is inverse to a value of the at least one component of the at least one queue, for example by inverting, b) executing a logical operation, for example an

In further exemplary embodiments it is provided that the method has at least one of the following elements: a) incrementing the at least one state variable, b) assigning a value of the second state variable to one or the sequence number, for example when writing to the at least one queue, c) comparing the sequence number with a value of the first state variable, for example when reading from the at least one queue, d) based on the comparison, for example if necessary, initiating an error reaction.

Further exemplary embodiments relate to a device for carrying out the method according to the embodiments.

Further exemplary embodiments relate to a product, for example a motor vehicle or a control device, for example for a motor vehicle, with at least one device according to the embodiments.

Further exemplary embodiments relate to a computer-readable storage medium comprising instructions that, when executed by a computer, cause the computer to carry out the method according to the embodiments.

Further exemplary embodiments relate to a computer program, comprising send commands that, when a computer executes the program, cause it to carry out the method according to the embodiments.

Further exemplary embodiments relate to a data carrier signal that transmits and/or characterizes the computer program according to the embodiments.

Further exemplary embodiments relate to a use of the method according to the embodiments and/or the device according to the embodiments and/or the product according to the embodiments and/or the computer-readable storage medium according to the embodiments and/or the computer program according to the embodiments and/or the Data carrier signal according to the embodiments for at least one of the following elements: a) processing data associated with at least one process for a computing device, b) selectively granting access to the at least one queue for a predeterminable set of processes associated with the computing device, c) ensuring freedom from interference, for example freedom from interference, communication between a predeterminable set of processes associated with the computing device, for example with regard to interference from other processes, for example also associated with the computing device, d) exclusion, for example conceptual exclusion, of out-of-bounds Accesses, for example to components of the at least one queue, e) detecting, for example unwanted, memory overwrites, for example with regard to a memory area associated with the at least one queue, f) using a shared memory area to enable an, for example fail-safe, for example efficient, inter-process -Communication, for example independently of an operating system, g) enabling use of the method and/or a device executing the method in security-relevant applications or systems, for example in mixed-ASIL systems, h) restricting access rights for processes to the at least one queue .

Further features, possible applications and advantages of the invention result from the following description of exemplary embodiments of the invention, which are shown in the figures of the drawing. All features described or illustrated, individually or in any combination, form the subject matter of the invention, regardless of their summary in the claims or their relationship and regardless of their formulation or representation in the description or in the drawing.

• 1 schematisch ein vereinfachtes Flussdiagramm gemäß beispielhaften Ausführungsformen,
• 2 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 3 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 4 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 5 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 6 schematisch ein vereinfachtes Flussdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 7 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 8 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 9 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 10 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 11 schematisch ein vereinfachtes Blockdiagramm gemäß weiteren beispielhaften Ausführungsformen,
• 12 schematisch Aspekte von Verwendungen gemäß weiteren beispielhaften Ausführungsformen.

In the drawing shows:

• 1 schematically a simplified flowchart according to exemplary embodiments,
• 2 schematically a simplified block diagram according to further exemplary embodiments,
• 3 schematically a simplified block diagram according to further exemplary embodiments,
• 4 schematically a simplified block diagram according to further exemplary embodiments,
• 5 schematically a simplified block diagram according to further exemplary embodiments,
• 6 schematically a simplified flowchart according to further exemplary embodiments,
• 7 schematically a simplified block diagram according to further exemplary embodiments,
• 8th schematically a simplified block diagram according to further exemplary embodiments,
• 9 schematically a simplified block diagram according to further exemplary embodiments,
• 10 schematically a simplified block diagram according to further exemplary embodiments,
• 11 schematically a simplified block diagram according to further exemplary embodiments,
• 12 schematic aspects of uses according to further exemplary embodiments.

Example embodiments, see 1 , refer to a method, for example a computer-implemented method, for processing with a computing device 12 ( 2 ) associated data, comprising: Provide 100 ( 1 ) at least one first queue WS-1 in a first memory area 14-1 ( 2 ), which can be accessed, for example exclusively, by a first process P-1 associated with the computing device 12 and a second process P-2 associated with the computing device 12. In further exemplary embodiments, this enables efficient provision of resources for one Data exchange between processes P-1, P-2, for example the computing device 12, for example in a shared memory (i.e., for example a “shared”) memory area to which the relevant processes P-1, P-2, but not others, for example, other processes P-3 can access.

For example, the computing device 12 is designed to execute the processes P-1, P-2, P-3 and forms, for example together with a memory device 14 to which it can access, a device 10, for example for an embedded system or the like.

In further exemplary embodiments, the computing device 12 is designed to at least temporarily execute at least some aspects of the method according to the embodiments.

In further exemplary embodiments it is provided that the method comprises: using 102 the at least one first queue WS-1 for a data exchange A1, A2 between the first process P-1 and the second process P-2, for example using 102 at least one which has the following elements: a) sending 102a of data, for example in the form of at least a first message, from the first process P-1 to the second process P-2, b) sending 102b of data, for example in the form of at least a second message, from the second process P-2 to the first process P-1.

In further exemplary embodiments it is provided that the at least one first queue WS-1 is provided and at least one further, for example second, queue WS-2, see for example block 100 according to 1 , wherein, for example, the at least one further, for example second, queue WS-2 is also provided, for example, in the first memory area 14-1, to which, for example exclusively, the first process P-1 associated with the computing device 12 and the second with the computing device 12 associated process P-2 can access, see the block arrows A1, A2. In further exemplary embodiments, this enables efficient data communication between the first process P-1 and the second process P-2, for example in both directions (eg from the first process to the second process and vice versa).

For example, the first queue WS-1 may be used for a first direction of data communication between the first process P-1 and the second process P-2, and the second queue WS-2 may be used, for example, for a second direction of data communication between the first process P-1 and the second process P-2 can be used.

In further exemplary embodiments, 1 , it is provided that the method has: Preventing 105 that, for example, in addition to the first process P-1 and the second process P-2, further processes P-3 associated with the computing device 12 ( 2 ) access the first memory area 14-1, for example the at least one first queue WS-1 (and/or the second queue WS-2). This is in 2 symbolized by the crossed-out block arrow A3, which symbolizes that access by the further process P-3 to the first memory area 14-1 is not permitted or not possible.

In further exemplary embodiments, 1 , it is provided that the method comprises: assigning 106 access rights to the first memory area 14-1 and/or to the at least one first queue WS-1 (and/or the second queue WS-2), for example exclusively, for the first Process P-1 and the second process P-1.

In further exemplary embodiments, 1 , it is provided that the method comprises: plausibility check 104 of at least one component of the at least one first queue WS-1. In further exemplary embodiments, this enables an increase in the security, for example, of the data associated with the at least one first queue WS-1. For example, in further exemplary embodiments, the optional plausibility check 104 can be used to recognize situations in which a memory area 14-1 associated with the at least one first queue WS-1 has been undesirably modified, for example accidentally or due to an error, or in which a different type of An undesirable change in the content of the first memory area 14-1, for example associated with the at least one first queue WS-1, has occurred (for example, a bit in the memory area has been flipped).

In further exemplary embodiments, 3 , it is provided that the method has at least one of the following elements: a) using 110 at least one FIFO (first in first out) memory FIFO-1, FIFO-2 for the at least one queue WS-1, WS-2 ( 2 ), for example, the at least one FIFO memory FIFO, FIFO-1, FIFO-2, see for example the schematic representation according to 4 , a first state variable ZV-1, for example tail variable, which characterizes a reading position, for example the at least one FIFO memory has a second state variable ZV-2, for example Head variable, which characterizes a write position, for example each element FIFO-EL-1, FIFO-EL-2, ... of the at least one FIFO memory FIFO has a sequence number SN-EL-1, SN-EL- 2, ... and user data ND-EL-1, ND-EL-2, ... has. For example, each of the FIFO memories has FI FO-1, FIFO-2 3 , block 110 a structure according to FIFO 4 on.

In further exemplary embodiments, 3 , it is provided that the method has at least one of the following elements: b) specifying 111 a size FIFO-GR of one or the at least one FIFO memory FIFO-1, FIFO-2, for example specifying 111a a number of elements, c) static allocation 112 of one or the number of FIFO-EL-ANZ elements, d) using 113 of index variables ZV-1-IDX, ZV-2-IDX for the at least one state variable ZV-1, ZV-2, e) not using 114 of pointer variables POINT for the at least one state variable ZV-1, ZV-2, f) using 115 a, for example statically coded, modulo operator MOD-OP for access to elements of the at least one FIFO memory, for example the modulo operator MOD-OP is associated with the number FIFO-EL-ANZ of elements of the at least one FIFO memory FIFO-1, FIFO-2, in particular not using 115a a variable for accessing elements of the at least one FIFO memory FIFO-1, FIFO -2, g) storing 116 at least one component of the at least one FIFO memory, for example a size FIFO-GR of the at least one FIFO memory, by means of a variable V-FIFO-GR, which is linked to a private memory area 14-PR-1 ( 2 ) at least one process, for example a high ASIL (Automotive Safety Integrity Level) process (process with a comparatively high ASIL), is associated, h) modifying 117 at least one component of the at least one FIFO memory, for example a size FIFO-GR of the at least one FIFO memory, for example during a runtime of the at least one process, for example reducing the size FIFO-GR of the at least one FIFO memory during the runtime of the at least one process.

In further exemplary embodiments, 5 , it is provided that the method has at least one of the following elements: a) storing 120 of components (e.g. sequence number and/or payload data and/or at least one state variable) of the at least one queue WS-1, WS-2, for example the at least one FIFO memory, together with a comparison value COMPARISON-VALUE, b) plausibility check 121 of at least one component of the at least one queue, for example the at least one FIFO memory, based on one or the comparison value COMPARISON-VALUE, c) executing 122 one or the plausibility check 121 (see also 1 , block 104) for at least some, for example all, read accesses to the at least one component of the at least one queue WS-1, WS-2, d) initiating 123 an error reaction FR, for example propagating a detected error, for example based on one or the Plausibility check 121, for example the error reaction FR having at least one of the following elements: d1) initializing, for example reinitializing, the at least one first queue WS-1, WS-2, d2) resending a message, for example in the case of defective user data, d3) Restarting at least one process P-1, P-2, e) atomically executing 124 accesses FIFO-ZUGR to at least one component of the at least one queue WS-1, WS-2, for example the at least one FIFO memory FIFO-1, FIFO -2, f) lock-free execution 125 of FIFO-ZUGR accesses to at least one component of the at least one queue WS-1, WS-2, for example the at least one FIFO memory.

In further exemplary embodiments, 6 , it is provided that the method has at least one of the following elements: a) determining 130 at least one comparison value COMPARISON VALUE for at least one component (e.g. sequence number and / or payload data and / or at least one state variable) of the at least one queue WS-1, WS-2, for example the at least one FIFO memory FIFO-1, FIFO-2, and, optionally, storing 132 the at least one component of the at least one queue WS-1, WS-2, for example the at least one FIFO memory FIFO- 1, FIFO-2, together with the comparison value COMPARISON-VALUE, whereby, for example, the plausibility check 104, 121 already described above as an example (for example during a, for example, subsequent, read access) is possible.

In further exemplary embodiments, 6 , it is provided that the determination 130 of the at least one comparison value COMPARISON VALUE has at least one of the following elements: a) forming 130a a value inverse to a value of the at least one component of the at least one queue WS-1, WS-2, for example by means of Inverting, b) executing 130b a logical operation, for example an XOR operation, with the value of the at least one component of the at least one queue WS-1, WS-2, c) forming 130c a checksum, for example of the CRC type, for example then , if a data quantity or size associated with the at least one component (e.g. size of the user data ND-EL-1, ND- EL-2, ...) exceeds a predeterminable threshold value.

In further exemplary embodiments, 7 , it is provided that the method has at least one of the following elements: a) incrementing 140 the at least one state variable ZV-1, ZV-2, b) assigning 141 a value of the second state variable to one or the sequence number SN-EL-2 , for example when writing to the at least one queue, c) comparing 143 the sequence number SN-EL-2 with a value of the first state variable ZV-1, for example when reading from the at least one queue, d) based on the comparing 143, for example, if necessary, initiating 144 an error reaction FR', for example if the comparison 143 results in a deviation between the sequence number SN-EL-2 and the value of the first state variable ZV-1.

Further exemplary embodiments, 8th , refer to a device 200 for carrying out the method according to the embodiments. For example, in further exemplary embodiments, the device 10 according to 2 one of which is given below by way of example with reference to 8th Have a comparable configuration to the configuration 200 described.

In further exemplary embodiments it is provided that the device 200 ( 8th ) has: a computing device (“computer”) 202 having at least one computing core 202a, a memory device 204 assigned to the computing device 202 for at least temporarily storing at least one of the following elements: a) data DAT (e.g. with at least one process P-1, P -2, P-3 associated data, for example data of at least one queue WS-1, WS-2,), b) computer program PRG, for example for executing the method according to the embodiments. In further exemplary embodiments, the memory device 204 also has, for example, at least one of the memory areas 14-1, 14-PR-1 2 on.

In further exemplary embodiments, 8th , the memory device 204 has a volatile memory (e.g. random access memory (RAM)) 204a, and/or a non-volatile (NVM) memory (e.g. flash EEPROM) 204b, or a combination thereof or with other memory types not explicitly mentioned. For example, the first memory area is 14-1 ( 2 ) in the RAM 204a ( 8th ) feasible.

Further exemplary embodiments relate to a computer-readable storage medium SM comprising instructions PRG that, when executed by a computer 202, cause the computer 202 to carry out the method according to the embodiments.

Further exemplary embodiments relate to a computer program PRG, comprising instructions that, when the program PRG is executed by a computer 202, cause the computer 202 to carry out the method according to the embodiments.

Further exemplary embodiments relate to a data carrier signal DCS that characterizes and/or transmits the computer program PRG according to the embodiments. The data carrier signal DCS can be received, for example, via an optional data interface 206 of the device 200. The data DAT, for example, can also be transmitted (sendable and/or received) via the optional data interface 206.

9 schematically shows a simplified block diagram according to further exemplary embodiments. Element Pa symbolizes a first process associated with the computing device 12, 202 (i.e. executable by the computing device 12, 202, for example), element Pb symbolizes a second process associated with the computing device 12, 202 (i.e. executable by the computing device 12, 202, for example), which, for example, should exchange data with the first process Pa using the principle according to the embodiments.

For example, each of the processes P-a, P-b is assigned a respective private address space pAS-a, pAS-b, to which only the respective process P-a, P-b has access.

Element AS-ab symbolizes an address space shared between the two processes Pa, Pb, which each of the two processes Pa, Pb can access, for example reading and writing, and which is used for secure and efficient data exchange A1, A2 (see. also 1 , 2 ) can be used between the two processes Pa, Pb. The shared address space AS-ab is, for example, with the first memory area 14-1 according to 2 associated or implemented or arranged in the first memory area 14-1.

By way of example, a first queue WS-1 is for sending data, for example messages, from the first process Pa to the second process Pb and a second queue WS-2 for sending data, for example messages, from the second process Pb to the first process Pa is provided, for example the first queue WS-1 in further exemplary embodiments also being the first channel ch_0 and for example the second In further exemplary embodiments, queue WS-2 can also be understood as a second channel ch_1 for data communication between the two processes Pa, Pb.

In further exemplary embodiments, the two queues WS-1, WS-2 or channels ch_0, ch_1 form, for example, a socket SOCKab for secure data communication between the two processes P-a, P-b.

10 schematically shows a simplified block diagram according to further exemplary embodiments.

E1 symbolizes, for example, a first element of a queue WS, for example of the FIFO type, element E2 symbolizes, for example, a second element of the queue WS, element E3 symbolizes, for example, a third element of the queue WS, and the points E3 'symbolize further possible elements of the queue WS , which are not shown separately for reasons of clarity.

The elements E1, E2, E3, ... each have a first area B1 for data data and possibly a comparison value -data associated with the data data, and a second area B2 for a sequence number seq and possibly for one with the Sequence number seq associated comparison value -seq. The comparison values -data, ~seq are, for example, according to further exemplary embodiments 6 can be formed, for example as inverted data values with respect to the data data, seq.

It is noted that in 10 Due to the clarity, the respective data and sequence numbers of individual elements E1, E2, E3, ... are each labeled the same. It is understood that in exemplary embodiments, the data contents of the first area B1 of different elements E1, E2, E3, ... of the exemplary queue, for example in pairs to one another, for example identical or different from one another, for example the sequence numbers of different elements E1, E2, E3, ... of the exemplary queue are each different from each other.

A first pseudocode listing (“Listing 1”) is given below, which in further exemplary embodiments describes, for example, aspects of sending data, for example messages, according to the principle according to the embodiments. Each line in Listing 1 is preceded by a line number.

***Start of Listing 1***

1. 1 send(const &msg):
2. 2 curHead= atomic_load(head);
3. 3 if (corrupt(curHead)) return corruption;
4. 4 slot = slots[idx(curHead)];
5. 5 slot.data.construct(msg);
6. 6 slot.seq= atomic_store(curHead);
7. 7 head= atomic_store(curHead+1);
8. 8 return OK;

***End of Listing 1***

Line 1 of Listing 1 describes sending a message msg, e.g. using a function call “send()”, where a reference &msg to the message msg to be sent is passed as a parameter. Line 2 describes a, for example atomic, loading of a current head variable (see, for example, the second state variable ZV-2 according to 4 ) a queue to use for sending and assigning the value of the head variable to a variable curHead. Line 3 describes a check of the value of the head variable, for example in the sense of plausibility 104 according to 1 , and the optional initiation of an error response, in this case returning an error code “corruption”. Line 4 describes the assignment of a value from the array slots[] to the variable slot based on the value of the variable curHead, using an index function idx(), which, for example, has a statically coded modulo operator MOD-OP (see. 3 ), used. Line 5 describes the assignment of the content of the message to be sent into the slot. Line 6 describes the assignment of the updated sequence value of the message. Line 7 describes the assignment of the updated head variable. Line 8 describes a return from the send() function.

A second pseudocode listing (“Listing 2”) is given below, which in further exemplary embodiments describes, for example, aspects of receiving data, for example messages, according to the principle according to the embodiments. Each line in Listing 2 is preceded by a line number.

***Start of Listing 2***

1. 1 receive(&msg):
2. 2 curTail= atomic_load(tail);
3. 3 if (corrupt(curTail)) return corruption;
4. 4 slot = slots[idx(curTail)];
5. 5 curSeq= atomic_load(slot.seq));
6. 6 if (corrupt(curSeq)) return corruption;
7. 7 if (corrupt(slot.data.copy(msg)) return corruption;
8. 8 tail= atomic_store(curTail+1);
9. 9 return OK;

***End of Listing 2***

Line 1 of Listing 2 describes the receipt of a message, for example using a function call “receive()”, where a reference &msg to a variable msg that characterizes the message to be received is passed as a parameter. Line 2 describes, for example, atomic loading of a current tail variable (see, for example, the first state variable ZV-1 according to 4 ) a queue to use for receiving and assigning the value of the tail variable to a variable curTail. Line 3 describes a check of the value of the tail variable, for example in the sense of plausibility 104 according to 1 , and the optional initiation of an error response, in this case returning an error code “corruption”. Line 4 describes the assignment of a value from the array slots[] to the variable slot based on the value of the variable curTail, using the index function idx(), which contains, for example, a statically coded modulo operator MOD-OP (see. 3 ), used. Line 5 describes, for example, an atomic loading of the sequence number of the slot previously identified in line 4. Line 6 describes a check of the value of the sequence number, for example in the sense of plausibility 104 according to 1 , and the optional initiation of an error response, in this case returning an error code “corruption”. Line 7 describes a check of the content of the message to be received, for example in the sense of plausibility 104 1 , and the optional initiation of an error response, in this case returning an error code “corruption”. Line 8 describes the assignment of the updated tail variable. Line 9 describes a return from the receive() function.

Further exemplary embodiments, 11 , refer to a product, for example a motor vehicle 1000 or a control device 1002, for example for a motor vehicle 1000, with at least one device 10, 200 according to the embodiments.

Further exemplary embodiments, 12 , refer to a use 300 of the method according to the embodiments and / or the device 10, 200 according to the embodiments and / or the product 1000, 1002 according to the embodiments and / or the computer-readable storage medium SM according to the embodiments and / or the computer program PRG according to the embodiments and/or the data carrier signal DCS according to the embodiments for at least one of the following elements: a) processing 301 of data associated with at least one process P-1, P-2 for a computing device 12, 202, b) selective granting 302 of Access to the at least one queue WS-1, WS-2 for a predeterminable set of processes P-1, P-2 associated with the computing device 12, 202, c) ensuring 303 freedom from interference, for example freedom from interference, of communication between one predeterminable set of processes P-1, P-2 associated with the computing device, for example with regard to interference from other processes P-3, for example also associated with the computing device, d) exclusion 304, for example conceptual exclusion, of out-of-bound accesses , for example on components ZV-1, ZV-2, FIFO-EL-1, FIFO-EL-2, ... of the at least one queue WS-1, WS-2, e) detecting 305, for example unwanted, memory overwrites, for example with regard to a memory area 14-1 associated with the at least one queue WS-1, WS-2, f) using 306 a shared memory area 14-1, AS-ab to enable, for example interference-free, for example efficient, inter-process communication , for example independently of an operating system, g) enabling 307 use of the method and/or a device 12, 200 executing the method in security-relevant applications, for example in mixed-ASIL systems, h) restricting 308 access rights for processes P-3 to the at least one queue WS-1, WS-2.

Further exemplary aspects and embodiments are described below, which, in further exemplary embodiments, can each be combined individually or in any combination with one another with at least one of the aspects described above and/or with at least one of the embodiments described above.

The principle according to the embodiments can be used, for example, for a method for inter-process communication A1, A2, which is, for example, both high-performance and suitable for use in mixed-ASIL systems. For example, a 64-bit compare-and-swap operation of a computing device 12, 202 can advantageously be used for the principle according to the embodiments.

The use of shared memory, for example a RAM 204a, offers speed advantages, for example, and the control of the access rights of processes to the respective queue(s) WS-1, WS-2 increases ensures security in communication or data exchange between processes P-1, P-2.

In further exemplary embodiments, variables associated with the at least one queue WS-1, WS-2 and/or their (optional) comparison values are accessed e.g. atomically and/or lock-free: e.g. atomically to ensure a consistent state, e.g. lock -free to prevent the possibility of corruption of the lock variables and thus ensure, for example, consistent reading and writing of the variables by hardware mechanisms. In further exemplary embodiments, the use of a 64-bit compare-and-swap operation is useful for this, which is available, for example, on the computing device 12, 202, as already mentioned above.

In further exemplary embodiments, for example in the case of the payload (payload data, see, for example, reference symbol data according to 10 ), atomic access is not provided; During a write operation, the data is written, for example, piece by piece with the normal value (i.e. its actual value) and, as a comparison value COMPARE-VALUE, for example a respective inverse, into the shared memory 14-1; during a read operation, for example, the data is written piece by piece from the shared memory 14 -1 read out, e.g. compared and e.g. into a protected memory pAS-a, pAS-b ( 9 ) of the reading process is copied.

In further exemplary embodiments, the comparison value is, for example, the inverse of the original value (e.g. obtainable by inverting bit by bit). Alternatively, in further exemplary embodiments, for example XOR links, for example with a user-defined value or, for example in the case of larger data such as the payload, a CRC value are conceivable.

In further exemplary embodiments, for example in a rare case that a memory corruption represents a supposedly correct value, a cross-comparison can be carried out, for example using the sequence number seq of the payload elements data: In further exemplary embodiments, head and tail are, for example, not saved with the modulo, but rather e.g. just incremented. In further exemplary embodiments, the complete value of the head variable is entered into the sequence number when writing; when reading out, in further exemplary embodiments it can be checked whether the sequence number matches the value of the tail variable. Should the head variable appear to have been overwritten correctly during operation, in further exemplary embodiments the incorrect sequence number would result in this error being detected during the read operation.

In further exemplary embodiments, error detection can take place in two ways, for example: A first way consists, for example, in checking the plausibility of the sequence number in the two, for example legal, options. In the case of an element that has already been read, it is the number of the last iteration, i.e. “Tail-N” for N FIFO elements, or in the case of a new readable element, the tail value. Any other value would be an error case in further exemplary embodiments.

In further exemplary embodiments, the second type combines a simple comparison of the sequence number during read operations with the tail value and a cyclic function test between the two FIFOs FIFO-1, FIFO-2 for communication between the communication partners. In further exemplary embodiments, the cyclic functional test consists, for example, of sending “ping-pong” messages at regular intervals. In the event of an invalid sequence number, in further exemplary embodiments, read operations would no longer take place in one of the two FIFOs, so that the cyclic function test fails due to communication stopping in one direction.

In both described options for error detection according to further exemplary embodiments, there may be a certain delay between the occurrence of the error and its detection: In the first type, for example, the error is only detected when the reader reaches the first element with the invalid sequence number. Depending on the position of the moved head index, this can mean up to N-1 additional write operations.

In the second type according to further exemplary embodiments, detection takes place with the latency of the selected frequency of, for example, a cyclic functional test. If this is not sufficiently fast, for example in some target systems, in further exemplary embodiments the error detection can be further improved, for example with a higher-level mechanism: A counter, which is incremented during write operations and decremented during read operations, shows how many new elements are in the FIFO. In multi-producer scenarios according to further exemplary embodiments, write operations can then be serialized, for example with a lock, for example in a private address area of the writing process, for example in order to avoid false positives in the plausibility check logic.

Claims (16)

Method, for example computer-implemented method, for processing data associated with a computing device (12), comprising: providing (100) at least a first queue (WS-1, WS-2) in a first memory area (14-1), on which, For example, exclusively, a first process (P-1) associated with the computing device (12) and a second process (P-2) associated with the computing device (12) can access. Procedure according to Claim 1 , comprising: using (102) the at least one first queue (WS-1, WS-2) for a data exchange (A1, A2) between the first process (P-1) and the second process (P-2), for example using (102) at least one of the following elements: a) sending (102a) of data, for example in the form of at least a first message, from the first process (P-1) to the second process (P-2), b) Sending (102b) of data, for example in the form of at least a second message, from the second process (P-2) to the first process (P-1). Method according to at least one of the preceding claims, comprising: Preventing (105) that, for example in addition to the first process (P-1) and the second process (P-2), further processes (P-3) associated with the computing device (12). ) access the first memory area (14-1), for example the at least one first queue (WS-1). Method according to at least one of the preceding claims, comprising: assigning (106) access rights (ZR-1) to the first memory area (14-1) and/or to the at least one first queue (WS-1), for example exclusively for first process (P-1) and the second process (P-2). Method according to at least one of the preceding claims, comprising: plausibility checking (104) of at least one component of the at least one first queue (WS-1, WS-2). Method according to at least one of the preceding claims, comprising at least one of the following elements: a) using (110) at least one FIFO memory (FIFO; FIFO-1, FIFO-2) for the at least one queue (WS-1, WS-2 ), for example, the at least one FIFO memory (FIFO; FIFO-1, FIFO-2) having a first state variable (ZV-1), for example tail variable, which characterizes a reading position, for example the at least one FIFO memory (FIFO; FIFO-1, FIFO-2) has a second state variable (ZV-2), for example head variable, which characterizes a write position, for example one element (FIFO-EL-1, FIFO-EL-2, ...) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), a sequence number (SN-EL-1, SEN-EL-2, ...) and user data (ND-EL-1, ND -EL-2, ...), b) specifying (111) a size (FIFO-GR) of one or the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example specifying (111a) a number of elements (FIFO-EL-1, FIFO-EL-2, ...), c) static allocation (112) of one or the number (FIFO-EL-ANZ) of elements (FIFO-EL-1, FIFO-EL-2, ...), d) Using (113) index variables (ZV-1-IDX, ZV-2-IDX) for the at least one state variable (ZV-1, ZV-2), e) Not using (114) of pointer variables (POINT) for the at least one state variable (ZV-1, ZV-2), f) using (115) a, for example statically coded, modulo operator (MOD-OP) for access to elements (FIFO -EL-1, FIFO-EL-2, ...) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example, the modulo operator with the number (FIFO-EL-ANZ) of elements (FIFO-EL-1, FIFO-EL-2, ...) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), in particular not using (115a) a variable for accessing elements (FIFO-EL-1, FIFO-EL-2, ...) of the at least one FIFO memory ( FIFO; FIFO-1, FIFO-2), g) storing (116) at least one component of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example a size (FIFO-GR) of the at least one FIFO -Memory (FIFO; FIFO-1, FIFO-2), by means of a variable (V-FIFO-GR) that has a private memory area (14-PR-1) of at least one process (P-1, P-2), for example a high ASIL process (P-1), h) modifying (118) at least one component of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example a size (FIFO-GR ) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), for example during a runtime of the at least one process (P-1, P-2), for example reducing (117a) the size (FIFO-GR) of the at least one FIFO memory (FIFO; FIFO-1, FIFO-2) during the runtime of the at least one process (P-1, P-2). Method according to at least one of the preceding claims, comprising at least one of the following elements: a) storing (120) components of the at least one queue (WS-1, WS-2), for example the at least one FIFO memory (FIFO; FIFO-1 , FIFO-2), together with a comparison value (COMPARISON VALUE), b) plausibility check (121) of at least one component of the at least one queue (WS-1, WS-2), for example of the at least one FIFO memory (FIFO; FIFO -1, FIFO-2), based on a or the comparison value (VERGL-WERT), c) executing (122) one or the plausibility check (121) for at least some, for example all, read accesses to the at least one component of the at least one queue (WS-1, WS-2) , d) initiating (123) an error reaction (FR), for example propagating a detected error, for example based on a or the plausibility check (121), for example the error reaction (FR) having at least one of the following elements: d1) initializing, for example Reinitializing the at least one first queue (WS-1, WS-2), d2) resending a message, for example in the case of defective payload data, d3) restarting at least one process (P-1, P-2), e) atomic execution (124) accesses to at least one component of the at least one queue (WS-1, WS-2), for example the at least one FIFO memory (FIFO; FIFO-1, FIFO-2), f) lock-free execution (125 ) of accesses to at least one component of the at least one queue (WS-1, WS-2), for example the at least one FIFO memory (FIFO; FIFO-1, FIFO-2). Method according to at least one of the preceding claims, comprising at least one of the following elements: a) determining (130) at least one comparison value (COMPARISON VALUE) for at least one component of the at least one queue (WS-1, WS-2), for example the at least a FIFO memory (FIFO; FIFO-1, FIFO-2), and, optionally, storing (132) the at least one component of the at least one queue (WS-1, WS-2), for example the at least one FIFO memory ( FIFO; FIFO-1, FIFO-2), together with the comparison value (COMPASS VALUE). Procedure according to Claim 8 , wherein the determination (130) of the at least one comparison value (COMPARISON VALUE) has at least one of the following elements: a) forming (130a) a value of the at least one component of the at least one queue (WS-1, WS-2) inverse value, for example by inverting, b) executing (130b) a logical operation, for example an XOR operation, with the value of the at least one component of the at least one queue (WS-1, WS-2), c) forming (130c) a checksum, for example of the CRC type, for example when a data quantity or size associated with the at least one component exceeds a predeterminable threshold value. Method according to at least one of the Claims 6 until 9 , comprising at least one of the following elements: a) incrementing (140) the at least one state variable (ZV-1, ZV-2), b) assigning (141) a value of the second state variable (ZV-2) to one or the sequence number (SN-EL-1, SEN-EL-2, ...), for example when writing to the at least one queue (WS-1, WS-2), c) comparing (143) the sequence number (SN-EL- 1, SEN-EL-2, ...) with a value of the first state variable (ZV-1), for example when reading from the at least one queue (WS-1, WS-2), d) based on comparing ( 143), for example, if necessary, initiating (144) an error reaction (FR'). Device (10; 200) for carrying out the method according to at least one of the preceding claims. Product, for example motor vehicle (1000), with at least one device (10; 200). Claim 11 . Computer-readable storage medium (SM), comprising instructions (PRG) which, when executed by a computer (202), cause it to carry out the method according to at least one of Claims 1 until 10 to carry out. Computer program (PRG), comprising commands which, when the program (PRG) is executed by a computer (202), cause the computer (202) to carry out the method according to at least one of Claims 1 until 10 to carry out. Disk signal (DCS) that the computer program (PRG) follows Claim 14 transmitted and/or characterized. Use (300) of the method according to at least one of Claims 1 until 10 and/or the device (10; 200). Claim 11 and/or the product (1000). Claim 12 and/or the computer-readable storage medium (SM). Claim 13 and/or the computer program (PRG). Claim 14 and/or the data carrier signal (DCS). Claim 15 for at least one of the following elements: a) processing (301) of data associated with at least one process (P1, P2) for a computing device (12), b) selectively granting (302) access to the at least one queue (WS-1 , WS-2) for a predeterminable set of processes (P1, P2) associated with the computing device (12), c) ensuring (303) freedom from interference, for example freedom from interference, communication between a predeterminable set of processes (P1, P2) associated with the computing device (12 ) associated processes (P1, P2), for example with regard to interference from other processes (P3), for example also associated with the computing device (12), d) exclusion (304), for example conceptual exclusion, of out-of-process Bound accesses, for example to components of the at least one queue (WS-1, WS-2), e) detecting (305) of, for example unwanted, memory overwrites, for example with regard to one with the at least one queue (WS-1, WS-2) associated memory area (14-1), f) using (306) a shared memory area (14-1) to enable inter-process communication, for example interference-free, for example efficient, for example independent of an operating system, g) enabling (307) a use of the method and/or a device (10; 200) executing the method in security-relevant applications, for example in mixed-ASIL systems, h) restricting (308) access rights for processes (P-1, P-2, P-3 ) to the at least one queue (WS-1).

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