DE102022131588A1 - Degradation diagnosis procedure, control unit and power electronics module - Google Patents

Abstract

A method for degradation diagnosis of a power electronics module (2) with a semiconductor component (3), the method comprising providing an input signal of the power electronics module (2) containing a large-signal part intended for switching on the semiconductor component (3); receiving an output signal of the power electronics module based on the input signal in order to enable a degradation diagnosis of the power electronics module (2); and the input signal contains a sinusoidal small-signal part.

Description

TECHNICAL AREA

The invention relates to a method having the features of the preamble of claim 1 as well as a control device and a power electronics module.

The following Background is intended only to provide information necessary to understand the context of the inventive ideas and concepts disclosed herein. Therefore, this Background section may contain patentable subject matter and should not be considered prior art per se.

BACKGROUND

Power electronics are used in many applications, such as the distribution of electrical energy or electromobility. However, the failure of power electronic components of a power electronic module, such as a power converter, is one of the most common causes of errors in modern systems, such as wind turbines or photovoltaic systems. These errors can be traced back to defects in the construction and connection technology of the power electronic module or to the aging of the semiconductor component itself. In order to ensure high reliability in such applications without costly over-dimensioning of power electronic components, reliable information about the aging state of the power electronic module is necessary. This enables safe operation of the power electronic module over an extended period of time until critical aging is reached and predictive maintenance is triggered.

The invention is based on the object of creating a simpler degradation diagnosis with less effort.

SHORT VERSION

This summary is intended to introduce a selection of features and concepts of the invention that are discussed later in the specification. This summary is not intended to identify important or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

According to the invention, the above-mentioned object is solved by the features of the independent claims.

Specifically, the problem is solved by a method for degradation diagnosis of a power electronics module. The power electronics module has a semiconductor component. The method includes providing an input signal of the power electronics module. The input signal has a large signal part. The large signal part is provided for switching on the power electronics module, preferably the semiconductor component. The method includes recording an output signal of the power electronics module, preferably the semiconductor component. The output signal of the power electronics module is based on the input signal. Recording the output signal enables a degradation diagnosis of the power electronics module. The input signal also contains a sinusoidal small signal part.

The invention has the advantage that the prerequisites are created to carry out degradation detection or degradation diagnosis in a power electronics module with power electronic components, such as a semiconductor component, in a simpler and more cost-effective manner. This makes localization possible so that the aging state of individual components of the power electronics module can be determined.

For example, the large signal part of the input signal can be a DC signal, corresponding to a direct voltage or a direct current. The small signal part of the input signal can be an AC signal, corresponding to an alternating voltage or an alternating current. The input signal can essentially consist of the large signal part and the small signal part. An amount of the large signal part can be greater than 2.5 times (or 5 times or 7.5 times) an amplitude of the small signal part. The amount of the large signal part can be less than 25 times (or 20 times or 15 times) the amplitude of the small signal part. For example, the large signal part can be in a range of 7.5 times to 12.5 times the amplitude of the small signal part.

In one example, the large signal part can have a voltage in a range of 5V to 15V (or 7.5V to 12.5V). The input signal can have a voltage in a range of 3V to 17V (or 5V to 15V). The output signal can be a voltage signal that is shifted in time to the input signal. An amplitude of the output signal can be larger than an amplitude of the input signal, for example deviating by up to 2V (or 1V or 0.5V).

The power electronics module can be a circuit designed for high power or high voltage/high current, such as a rectifier, inverter, DC/DC converter, AC controller or switching power supply. The power electronics module can be designed to convert electrical energy. The power electronics module can be used as a converter or frequency converter, for example in the field of electrical drive technology, solar inverters and converters for wind turbines for feeding renewable energy into the grid or switching power supplies.

The semiconductor device can comprise a diac, bipolar power transistor, power MOSFET, thyristor, GTO thyristor, IGC thyristor, MC thyristor, IGBT, triac or diodes for rectification or freewheeling diodes.

The power electronics module, preferably the semiconductor component, can change the input signal in such a way that an output signal different from the input signal with a changed large-signal part and/or small-signal part is obtained.

The small signal part can be a continuous sinusoidal signal. The small signal part can be specified by input phase information and associated input frequency information. The small signal part can thus be a function of input phase information and associated input frequency information. The output signal can also contain output phase information and associated output frequency information. The input frequency information can be substantially equal to the output frequency information, in particular frequency information. In particular, output phase information and input phase information can represent a phase response with respect to the frequency information. For example, a degradation diagnosis can be made from the output phase information and the input phase information with associated frequency information, in particular by evaluating the phase response. An amplitude response from the output signal and input signal, in particular the amplitude of the output signal and the amplitude of the small signal part, can be neglected here. The output phase information can be compared, preferably frequency-resolved with associated frequency information, with a target output phase information in order to make the degradation diagnosis. The target output phase information can be based on a target output signal that results from providing a target input signal to a reference power electronics module. The target input signal can correspond to the input signal or at least contain the same small signal part.

Advantageous embodiments of the invention are specified in the subclaims.

The small-signal sinusoidal part may be a chirp. The chirp may be provided by varying a frequency of the small-signal sinusoidal part over time.

In this way, a frequency-adjusted measurement can be carried out to check various components of the power electronics module for degradation in one run.

The chirp may have a frequency range between 0.1 mHz and 100 Hz. For example, the chirp may have a frequency greater than 0.1 mHz (or 0.5 mHz or 1 mHz). For example, the chirp may have a frequency less than 100 Hz (or 10 Hz or 1 Hz).

This allows the chirp to be adjusted to suit the component in order to perform a degradation diagnosis.

The large-signal part of the input signal can ensure that the semiconductor component is switched on for the duration of the chirp. The large-signal part can thus ensure that the semiconductor component is switched on as long as the chirp is fed into or modulated into the power electronics module or the semiconductor component.

This allows conduction losses to be effectively modulated onto the semiconductor device and provides a simple solution for degradation diagnosis.

The input signal can be provided at a control terminal of the semiconductor component. In this case, an input current can be impressed into the control terminal or an input voltage that is at least connected to the control terminal, for example the input voltage between the control terminal and a source terminal of the semiconductor element, can be provided. The output signal can be received at a sink terminal of the semiconductor component. In this case, an output current can be received in the sink terminal or from the sink terminal to the source terminal (or vice versa) or an output voltage that is at least connected to the sink terminal, for example the output voltage between the sink terminal and the source terminal of the semiconductor element, can be received.

This allows for cost-effective and easy implementation in the field.

The terms control connection, drain connection and source connection can be gate, drain and source or base, collector and emitter depending on the technology of the semiconductor component. However, in this case, there is no explicit reference to a specific technology.

The method may further comprise determining a degradation of one or more components. The one or more components may be associated with the power electronics module. Preferably, the one or more components are part of or are themselves components of the power electronics module. The determination may be carried out by frequency-resolved comparison, preferably within the frequency range, of a phase of the output signal with a phase of the input signal. The phase of the input signal may correspond to the phase of the small-signal part of the input signal.

The degradation of the plurality of components associated with the power electronics module can be determined by phase differences between the output signal and the input signal in corresponding frequency sub-ranges associable with the plurality of components associated with the power electronics module, preferably within the frequency range. The frequency sub-ranges can differ from component to component of the components associated with the power electronics module.

Put simply, the power electronics module put into operation can have a phase response (between the output signal and the input signal). The phase response during operation, which results from the recorded output signal and the input signal provided, can be referred to here as the operating phase response. The operating phase response of the power electronics module can differ from a target phase response of the power electronics module, e.g. in a state before the power electronics module is put into operation. By comparing the operating phase response and the target phase response, for example by comparing curves between the operating phase response and the target phase response, the degradation of (individual) components of the power electronics module can be determined. For example, a degradation of a component associated with a predetermined frequency sub-range can be present if a difference between the operating phase response and the target phase response in the predetermined frequency sub-range of the frequency range exceeds a threshold value, for example 0.1° or 0.25°. The frequency sub-range can be smaller than 0.2 times (or 0.1 times) the bandwidth of the frequency range. For example, predetermined different frequency sub-ranges of the frequency range may be associated with the components of the power electronics module. If the difference between the operating phase response and the desired phase response in one or more of the predetermined frequency sub-ranges exceeds the threshold, degradation may be present at the components associated with the one or more frequency sub-ranges.

The above-mentioned object is also achieved by a computer program. The computer program comprises instructions which, when the computer program is executed by a computer or by a control unit, cause the computer or the control unit to carry out the method described above or at least one of the steps thereof. The computer program can, for example, be a module for starting/operating the power electronics module as described herein.

The above-mentioned task is also achieved by a data carrier. The computer program can be stored on the machine-, processor- or computer-readable data carrier, such as on a permanent or rewritable storage medium. This also includes the fact that the computer program can be made available for download on a server or a cloud server, e.g. via a data network such as the Internet or a communication connection such as a wireless connection.

The above-mentioned object is also achieved by a control device. The control device is used for degradation diagnosis of a power electronics module with a semiconductor component. The control device is designed to provide an input signal of the power electronics module, preferably of the semiconductor component, containing a large-signal part intended for switching on the semiconductor component. The control device is designed to receive an output signal of the power electronics module, preferably of the semiconductor component, based on the input signal in order to enable degradation diagnosis of the power electronics module. The input signal contains a sinusoidal small-signal part.

The control unit can be designed as a module and integrated into or attached to the power electronics module. This can result in simple implementation options that are also cost-effective.

The control device may be configured to adapt a power to be delivered to the semiconductor device based on a result of the degradation diagnosis, which is performed based on a comparison of output signal to input signal.

The above-mentioned object is also achieved by a power electronics module. The power electronics module has a semiconductor component. The power electronics module is designed to receive an input signal from the power electronics module, preferably the semiconductor component, containing a large-signal part intended for switching on the semiconductor component. The power electronics module is designed to transfer an output signal from the power electronics module, preferably the semiconductor component, based on the input signal in order to enable a degradation diagnosis of the power electronics module. The input signal contains a sinusoidal small-signal part.

The power electronics module can have components such as a carrier, a substrate for thermally connecting the semiconductor component to the carrier and a heat sink. The semiconductor component can be connected to the substrate via a solder connection. The heat sink can be connected to the carrier via a thermally conductive layer. The control unit can be designed to carry out the degradation diagnosis of at least one of the components of the power electronics module.

The above task can also be solved by a power electronic system. The power electronic system is used for degradation diagnosis and has a power electronic module as described above and a control unit as described above.

The power electronic system can form an integral part of a motor vehicle, a photovoltaic system or a wind turbine.

Thus, a complete system as well as modular components can be provided, which enable a more cost-efficient implementation of degradation diagnostics without having to resort to temperature sensors.

In other words, the invention relates to a new method that diagnoses various degradation or aging effects in power electronic modules (also power electronics modules) in a minimally invasive manner and without the use of expensive sensors. In particular, the invention can relate to degradation diagnosis in power electronic modules by detecting the phase shift of the electrical response. Different states of degradation influence the phase of the frequency response of the thermal impedance at certain frequencies. At these frequencies, a phase shift between semiconductor losses and junction temperature therefore differs for different degradation/aging effects.

In order to use the phase shift, previous methods determine the semiconductor losses and the junction temperature. To do this, previous methods use precise loss calculations and temperature sensors with a high bandwidth. Temperature-sensitive electrical parameters (TSEPs) can be used here. However, these usually depend not only on the temperature, but also on the degradation, among other things. For this reason, previous methods may require recalibration at different degrees of degradation.

The method proposed here, on the other hand, can use information about the phase of the thermal impedance without determining the thermal impedance itself. This means that both temperature sensors and loss calculations can be dispensed with. For the indirect determination of the phase of the thermal impedance, periodic conduction losses can be impressed or added at low frequency, for example using small-signal manipulation of the control electrode of the power semiconductor. In addition, the phase shift between the loss impression and a temperature-dependent voltage (as TSEP), for example the forward voltage, can be measured. The phase shift can essentially result from a dynamic response of the thermal impedance, since the phase-shifted junction temperature influences the TSEP. Changes in the phase shift can therefore identify corresponding types of degradation.

In other words, small signal losses with different frequencies can be impressed into the semiconductor component. One possible implementation for this can be a modulation of a small signal excitation onto the gate-source voltage of a transistor as a semiconductor component, for example a SiC MOSFET. The resulting drain-source voltage of the SiC MOSFET is also superimposed with this small signal due to the dependence of the on-resistance on the gate-source voltage. In addition, the on-resistance can depend on the temperature. The temperature reacts with a time delay to changes in the conduction losses, which can be seen in the phase of the thermal impedance. This phase shift between conduction losses and temperature response can be influenced by various aging mechanisms, such as changes in the thermal path between semiconductor and heat sink. The phase-shifted temperature signal can therefore lead to a phase shift between the gate-source voltage and the drain-source voltage due to the temperature dependence of the on-resistance of the semiconductor component. Alternatively, other voltages or currents dependent on the junction temperature of the semiconductor component under consideration can also be considered. Changes in the phase shift between the excitation signal and the temperature-dependent voltage/current at certain frequencies can indicate degradation in the power electronics module. The frequencies at which the change in the phase shift occurs can enable the localization of the degradation phenomenon.

Small-signal excitation of the gate-source voltage of a transistor as a semiconductor component can be used for Si MOSFETs, IGBTs, and wide bandgap transistors such as GaN HEMTs and SiC MOSFETs. Small-signal excitation of the base current is possible for bipolar transistors as a semiconductor component. One possible implementation can be that the sinusoidal gate-source voltage is set via a digital-to-analog converter (DAC) that is controlled by a microcontroller (e.g. as part of the control unit described here). The voltage measurement of the gate-source voltage and the drain-source voltage can be carried out via a high-impedance voltage tap using a respective instrument amplifier. The tapped voltages can be converted into digital signals by respective analog-to-digital converters (ADCs). The tapped voltages can be previously conditioned depending on the requirements of the ADCs, for example using a single-ended-to-differential amplifier and an anti-aliasing filter. A fundamental frequency of both voltages can be determined using a fast Fourier transform. The phase information associated with the fundamental frequency can then be used to determine the phase shift.

In contrast to previous methods, the method presented here does not require precise loss and temperature determination, including temperature sensors, which makes implementation in a power electronic system much easier and more cost-effective. For example, it can be used by module manufacturers to test their modules before selling them. In addition, it can be used for predictive maintenance of power components in hard-to-reach locations, such as offshore wind turbines.

Thermomechanically induced degradation modes, such as fatigue of line electronic components such as solder and thermal interfaces, can be identified, for example without having to monitor changes in the thermal response, and correlated with localized degradation modes. This eliminates the need for methods that only imprint periodic losses into the semiconductors and extract the junction temperature response using TSEPs. In particular, a magnitude of the thermal impedance and the phase changes can be correlated with the degradation mode that has a peak sensitivity at the excitation frequency.

In contrast to the present invention, previous thermal impedance spectroscopy has the following disadvantages: 1) The required accurate temperature measurement is complex and expensive when performed using TSEPs because it requires high bandwidth measurement of electrical parameters; 2) The accurate calculation or measurement of device losses is difficult to realize; and 3) Most TSEPs are affected by device degradation, so recalibration is required at different levels of degradation.

Although some of the aspects described above relate to the method, the power electronics module or the power electronics system, these aspects may also apply to the other aspects thereof in a corresponding manner.

In one example, the power electronic system, power electronic module and/or control unit can be implemented using hardware circuits, software means or a combination thereof. For example, multiple units of the power electronic system, power electronic module and/or control unit can each be realized in a single physical unit, for example when multiple functions are implemented in software. The units of the power electronic system, power electronic module and/or control unit can also be implemented in hardware components. The units of the power electronic system, power electronic module and/or control unit are each to be understood as functional units that are not necessarily physically separated from one another. For example, the power electronic system, power electronic module and/or control unit can be implemented at least partially as a computer, field pro programmable logic array (FPLA), field programmable gate array (FPGA), microcontroller, CPU (e.g. with multiple cores), graphics processing unit (GPU), application specific integrated circuit (ASIC) and/or digital signal processor (DSP).

All technical and scientific terms used herein have the meaning that corresponds to the general understanding of the person skilled in the art in the technical field of power electronics; they are to be interpreted based on the definitions found in the dictionary or the technical jargon about this technical field. If technical terms are used incorrectly and thus do not express the technical idea of the present invention, they can be replaced by technical terms that give the person skilled in the art a correct understanding.

If it is said here that a component is "connected" to another component, this can mean for the purposes of the present disclosure that these components can also be directly connected to one another. The term "directly" indicates that there is no further component in between.

The method steps described herein should not be interpreted as requiring that they be performed in a particular order, unless expressly or implicitly stated otherwise, for example if these method steps cannot be interchanged for technical reasons. The method steps may also be performed directly one after the other (without any further intervening steps) and/or continuously.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects, features, advantages and possible applications will become apparent from the following description of non-limiting embodiments with reference to the accompanying drawings. The same or similar elements in the drawings are always provided with the same or similar reference numerals. Detailed explanations of known functions and structures are omitted if they detract from the invention.

• 1 eine schematische Darstellung eines leistungselektronischen Systems;
• 2 eine schematische Darstellung eines Verfahrens zur Degradationsdiagnose;
• 3 eine schematische Darstellung eines Steuergeräts;
• 4 ein regelungstechnisches Blockschaltbild zur Degradationsdiagnose; und
• 5 frequenzaufgelöste Phasendiagramme.

The drawings show in:

• 1 a schematic representation of a power electronic system;
• 2 a schematic representation of a method for degradation diagnosis;
• 3 a schematic representation of a control unit;
• 4 a control block diagram for degradation diagnosis; and
• 5 frequency-resolved phase diagrams.

DETAILED DESCRIPTION

The method, the power electronic system, the power electronic module and the controller will now be described with reference to the embodiments. Without being limited thereto, specific details are set forth to provide a deeper understanding of the invention.

1 shows a schematic representation of a power electronic system 1. The power electronic system 1 has a power electronic module 2 with a semiconductor component 3. The semiconductor component has a control connection 4, drain connection 5 and source connection 6. It is assumed below that the semiconductor component 3 is a MOSFET, for example a SiC-MOSFET. In this case, conduction losses are modulated in such a way that the gate-source voltage v _GS and the drain-source voltage v _ds can be measured (cf. 4 ). The power electronics module 2 to be tested can be connected to a heat sink on the underside of the semiconductor component 3, for example. The electrical contacts of the power electronics module 2 are connected to a circuit board of the remaining circuit elements 7 to 14 of the power electronics system 1. The power electronics system 1 also has a control unit 7, which is used to dynamically adjust the gate-source voltage v _GS of the semiconductor component 3 via a digital-to-analog converter (DAC) 8, for example a 12-bit digital-to-analog converter IC.

Gate-source voltage and drain-source voltage are determined via respective measuring units 9, 10 and 12, 13 and analog-digital converters (ADC 11, 14). One or more of these elements 9 to 14 can also be part of the control unit 7 or integrated into it. For better understanding, these are listed separately. The measuring units are in 1 divided into the elements 9 and 10 or 12 and 13. In the measuring unit associated with the drain-source voltage, a first instrument amplifier 9 is connected upstream of a first anti-aliasing filter 10, the output of which is connected to the first ADC 11. In the measuring unit associated with the gate-source voltage, a second instrument amplifier 12 is connected upstream of a second anti-aliasing filter 13, the output of which is connected to the second ADC 14.

As a further possibility, the respective measuring unit can also be divided into three parts: The voltage to be measured (gate-source or drain- Source) is connected to the power electronics module 2 via an instrumentation amplifier with high input impedance. A single-ended-to-differential amplifier with a cascaded operational amplifier can then convert the voltage into a differential signal, which can be converted into a digital signal, for example by a 24-bit sigma-delta ADC of the control unit 7, after being filtered by an anti-aliasing filter.

For example, in both alternatives the voltage tap can be made at high impedance via gate-source and drain-source.

The control unit 7 sets the gate-source voltage by setting the output voltage of the DAC 8, for example via Serial Peripheral Interface (SPI). This output voltage can be connected to an instrument amplifier that converts the output voltage into gate-source voltages in the range from -5 V to 20 V. The modulation of the gate-source voltage is realized by generating a sinusoidal voltage with a variable sampling frequency at the output of the DAC 8. The variable update frequency is selected so that the number of sampling points per period remains constant. The advantage of this method is that the values for a period of the sinusoidal voltage can be stored on the control unit 7 and do not have to be calculated in real time. The frequency with which the gate-source and drain-source voltage values are updated via the DAC 8 corresponds to the sampling frequency of the ADCs 11 and 14. The time- and/or frequency-resolved voltage values recorded via the ADCs 11 and 14 can be sent to an external computer for evaluation.

In post-processing, the fundamental frequency of the gate-source voltage v _GS and the drain-source voltage v _ds can be determined using a fast Fourier transformation (FFT). The phase information of the fundamental frequency is then used to determine the phase shift between the gate-source voltage v _GS and the drain-source voltage v _ds .

When carrying out the method, the MOSFET can be kept permanently switched on and conduct any drain-source current i _ds , for example around 5 A, which is only constant in special cases. A sinusoidal small-signal voltage v _ac with a variable frequency and an amplitude of 1 V is modulated onto the constant gate-source voltage V ₀ of 10 V. Each frequency is applied to the gate for half or a whole sine period. For example, an integer sine period component or an integer divisor (e.g. 1/2, 1/3, 1/4, ... 1/8) of the sine period can be used. The method is not limited to a single sinusoidal oscillation, but modulation methods can be used in which the sinusoidal small-signal voltage v _ac has several frequencies, whole frequency ranges or several frequency sub-ranges within the frequency range described here. This can reduce the time required.

The bandwidth (also called frequency sub-range) over which thermal impedance changes occur provides information about the location of aging effects in the thermal path. The closer the aging effect is to the device, the higher the frequency to consider.

In relation to 1 shows 2 very generally a schematic representation of a method S0 for degradation diagnosis of the power electronics module 2 with the semiconductor component 3. The method S0 comprises providing S1 an input signal of the power electronics module 2 containing a large signal part intended for switching on the semiconductor component 3. The method S0 further comprises receiving S2 an output signal of the power electronics module 2 based on the input signal in order to enable a degradation diagnosis of the power electronics module 2. The input signal contains a sinusoidal small signal part. For this purpose, the degradation of one or more components associated with the power electronics module 2 is optionally determined by frequency-resolved comparison of a phase of the output signal with a phase of the input signal.

The blocks of the block diagram in 2 The method steps described may, for example, be substantially represented in a machine-, processor- or computer-readable data carrier and thus executed by a computer or processor, such as described below with respect to 3 Examples may also be or refer to a computer program that includes program code for executing at least part of the method steps of 2 when the computer program is executed on the computer or processor. An example may also include volatile memory or persistent memory, such as also described below with respect to 3 described, which is machine-, processor- or computer-readable and encodes machine-executable, processor-executable or computer-executable programs containing instructions that cause execution of some or all of the method steps.

3 shows a schematic representation of a control unit in the form of a computer. The control unit 7 implements one or more steps of the method as shown in 2 . In particular, the controller 7 provides functionality, such as computer software running on the controller 7 that performs one or more steps of the method. In particular, the controller 7 may execute instructions associated with the input signal and/or output signal that are included in the computer program described herein and cause the controller 7 to perform the one or more steps of the method.

It is contemplated herein that controller 7 may take any suitable physical form. As an example, controller 7 may be embodied at least in part as an embedded computer, microcontroller, system-on-chip (SOC), and/or single-board computer (SBC). Controller 7 may be unified or distributed, or may span one or more locations. Controller 7 may perform one or more steps of the method without significant spatial or temporal limitations. As an example, controller 7 may perform one or more steps of the method in real time, in parallel, or in batch mode. Controller 7 may perform step(s) of the method at different times or at different locations.

The control unit 7 has at least one or more of the following components: a processor 15, a volatile memory 16, a permanent memory 17 with controller 18 and non-volatile memory device (NVM) 19, a bus 20, an arbiter 21, a communication interface 22, a power connection 23, a main power supply 24 and an auxiliary power supply 25. The components of the control unit 7 can be at least partially implemented in hardware and/or software. The interconnection of the components of the control unit 7 is shown as in 3 structured. In particular, the interconnection and connection can differ in implementation due to signal processing and signaling.

The processor 15 has means for executing instructions related to the input signal/output signal, eg of the computer program described herein. For example, the processor 15 can load the instructions related to the input signal/output signal contained in the computer program described herein, eg from the volatile memory 16 and/or the persistent memory 17 and then execute the instructions, which in turn causes the processor 15 to carry out the one or more steps of the method, eg as in 2 , illustrated. The processor 15 may include an internal register/cache for the data based on the input/output signal, the instructions associated with the data based on the input/output signal, and/or associated addresses. The processor 15 may include an FPGA, an FPGA, a microcontroller, a CPU, a GPU, an ASIC, and/or a DSP to access the internal register/cache. As an example, to execute the instructions associated with the input/output signal, the processor 15 may retrieve them from the internal register/cache of the processor 15, the volatile memory 16, or the persistent memory 17; decrypt and execute them; and then write a result to the internal register/cache of the processor 15, the volatile memory 16, or the persistent memory 17.

As an example, processor 15 may include an instruction cache, a data cache, and/or a translation buffer (TLB). The input/output-related instructions in the instruction cache may be copies of instructions in volatile memory 16 and/or persistent storage 17, and the instruction cache may speed up the retrieval of these input/output-related instructions by processor 15. The input/output-based data in the data cache may be copies of data for the input/output-related instructions currently executing on processor 15 in volatile memory 16 and/or persistent storage 17. The results of previous input/output related instructions executed on processor 15 may be provided for access by subsequent input/output related instructions executed on processor 15 or for writing to volatile memory 16 and/or persistent storage 17. The data cache may speed up the read or write operations of processor 15. The input/output related addresses in the TLB may be address references to addresses in volatile memory 16 and/or persistent storage 17 to speed up virtual address translation for processor 15.

The volatile memory 16 can be a dynamic RAM (DRAM) or a static RAM (SRAM). The volatile memory 16 can be designed in particular as the data carrier described herein on which the computer program described herein can be stored at least temporarily. In addition, the volatile memory 16 can be a single or multi-channel ger RAM. The volatile memory 16 may include main memory for storing instructions related to the input/output signal for the processor 15, which then executes those instructions; or include the input/output-based data for the processor 15 that the processor 15 uses to operate on them. As an example, the controller 7 may load these instructions into the volatile memory 16 from the persistent memory 17 or another source (such as another computer, the network, or the cloud). The processor 15 may then load these instructions from the volatile memory 16 into the internal register/cache of the processor 15. To execute these instructions, the processor 15 may retrieve and decrypt these instructions from the corresponding internal register/cache. During or after executing these instructions, the processor 15 may write a result (which may be intermediate or final results) to the internal register/cache. The processor 15 can then write the result into the volatile memory 16.

For example, processor 15 executes only the input/output related instructions in processor 15's internal register/cache or volatile memory 16 (as opposed to persistent memory 17), and operates only on the input/output based data in processor 15's internal register/cache or volatile memory 16 (as opposed to persistent memory 17). A memory management unit (MMU - not shown) may be located between processor 15 and volatile memory 16 and may support input/output related access to volatile memory 16 requested by processor 15.

The volatile memory 16 may be a memory shared by the processor 15 and the communication interface 22. The communication interface 22 accesses the shared volatile memory 16 via the processor 15. The communication interface 22 may, for example, contain no built-in memory. In this case, the communication interface 22 may share the volatile memory 16 connected to the processor 15. The processor 15 may have a memory access path that enables input/output signal-related access to the shared volatile memory 16. The communication interface 22 accesses the shared volatile memory 16 via the memory access path of the processor 15. The communication interface 22 is enabled input/output signal-related access to the shared volatile memory 16 while the memory access path is active and the processor 15 is inactive. Here, the memory access path is active without intervention by the processor 15. The memory access path is switched off while the processor 15 and the communication interface 22 are inactive. The memory access path is switched on without intervention by the processor 15 as soon as a request to couple the memory access path to the processor 15 is received while the memory access path is switched off and the communication interface 22 is active.

The persistent memory 17 has a mass storage, e.g. a non-volatile memory (NVM) 19 for the data based on the input signal/output signal or the commands related to the input signal/output signal. The persistent memory 17 can in particular be designed as the data carrier described herein, on which the computer program described herein can be stored. As an example, the persistent memory 17 can be a solid state memory (SSD), a flash memory, a non-volatile memory card, a Secure Digital Memory Card (SD), an Embedded Multi Media Card (eMMC) and/or a Universal Serial Bus (USB). The persistent memory 17 can store the data based on the input signal/output signal in an erasable or non-erasable manner. The persistent memory 17 can be located in the control unit 7, i.e. internally, or externally thereto. The persistent memory 17 may include the controller 18 that supports communication for passing on the data based on the input signal/output signal between the processor 15 and the persistent memory 17, in particular the NVM 19 of the persistent memory 17.

The bus 20 can be understood here as a subsystem of the control unit 7 that transmits the data based on the input signal/output signal and/or electrical power between the components of the control unit 7. The (one) bus 20 can connect the components of the control unit 7 to one another via the same set of lines. The bus 20 can be designed for dedicated communication of the data based on the input signal/output signal between two or more of the components of the control unit 7. The bus 20 can have a ring topology, star topology, (partially) meshed topology, bus topology, tree topology and/or line topology. The bus 20 can have one or more of the following bus types: Accelerated Graphics Port (AGP), HyperTransport (HT), Industry Standard Architecture (ISA), Peripheral Component Interconnect (PCI), PCI-Express (PCIe), Serial Advanced Technology Attachment (SATA) and/or INFINIBAND.

The bus 20 can be a system bus via which the processor 15 is connected to the other components of the control unit 7. In this case, the bus 20 can be synchronous - the data based on the input signal/output signal is accepted bidirectionally with a clock edge of a clocking of the bus 20 - and/or asynchronous - no clocking, but a handshake is carried out to accept the data based on the input signal/output signal. In such a semi-synchronous system bus, the bus 20 is clocked, but control lines enable wait cycles in order to also use slow components such as the permanent memory 17 via the bus 20.

The arbiter 21 can be provided for at least partial control over the bus 20. The arbiter 21 can be understood as a coprocessor arranged parallel to the processor 15. The arbiter 21 regulates the access to the bus 20 related to the input signal/output signal based on a two-way handshake or three-way handshake. The three signals Bus-Request (BREQ) for forwarding the data based on the input signal/output signal, Bus-Grant (BGRT) for confirming and approving the forwarding and Bus-Grant-Acknowledge (BGA) for optional forwarding feedback are used for this purpose.

The arbiter 21 receives several BREQs from different components of the control unit 7 simultaneously via the bus 20. The arbiter 21 sorts the BREQs according to priority and forwards them sequentially - in a pipeline - to the processor 15. As soon as the processor 15 has received the BREQ, the processor 15 sends the BGRT to the arbiter 21 or directly to the component of the control unit 7 sending the BREQ. A subordinate BREQ of the BREQs in the pipeline - e.g. from another component of the control unit 7 - is forwarded to the processor 15 in response to a BGRT sent by the processor 15 in relation to the BREQ that has priority in the pipeline and is related to at least part of the data based on the input signal/output signal. The BGRT related to the subordinate BREQ is sent from the processor 15 to the arbiter 21 after at least part of the data based on the input signal/output signal has been processed. The arbiter 21 can, for example, in response to the BGRT that refers to the subordinate BREQ, send a BREQ that is further down the pipeline - which refers, for example, to another part of the data based on the input signal/output signal - of the BREQs to the processor 15. Likewise, in response to each BGRT from the processor 15, the arbiter 21 can send a respective BGA related to it to the processor 15. With the procedure described here, a BGA can also be omitted entirely. This saves overhead in the communication between the components of the control unit 7. This means that a two-way handshake is provided instead of a three-way handshake.

The bus 20 may also comprise a data bus, address bus, and control bus. The data based on the input signal/output signal is transmitted bidirectionally between the components of the control device 7 via the data bus. The address bus is operated solely by the processor 15 and unidirectionally transmits memory addresses associated with the input signal/output signal. The control bus is controlled solely by the arbiter 21, e.g. in the sense of a watchdog, and passes control of it to the processor in the pipelined manner described above to control the transmission of the data based on the input signal/output signal.

The communication interface 22 enables the control unit 7 to communicate with a network, e.g. with an ad hoc network, a wireless personal area network ((W)PAN), e.g. a Bluetooth WPAN, a local area network (LAN), a WI-FI network, a WI-MAX network, a mobile radio system (e.g. 4G, 5G or 6G) and/or at least part of the Internet. The communication interface 22 can use this to forward the data based on the input signal/output signal to an evaluation unit. The communication interface 22 can also provide a direct and/or fixed connection to the evaluation unit, for example a PC.

The power connection 23 can be arranged at a dedicated connection point on a housing of the control unit 7. The power connection 23 can represent a central power supply point for the components of the control unit 7 (but also of the power electronics module 2) and connects the control unit 7 or its components, preferably the main power supply 24, to an external power source (outside the control unit 7). In the case of an integrated main power supply 24, the power connection 23 can also be an integrated part of the control unit 7 or the main power supply 24.

The main power supply 24 supplies at least one or more of the components of the control unit 7 with electrical power, e.g. via the bus 20. In particular, the main power supply 24 charges the auxiliary power supply 25 with electrical power, e.g. from outside the control unit 7, e.g. in case the main power supply 24 is connected to the power source outside is connected to the main power supply 24. The main power supply 24 can represent a preferred component used to supply power to the components of the control unit 7 and can comprise, for example, an accumulator or a battery. The main power supply 24 can comprise further components such as voltage regulators, DC voltage stabilizers, series regulators, buck converters and/or boost converters in order to meet the corresponding requirements of the components of the control unit 7. The power connection 23 can either have a dedicated fixed power supply connection to the external power source, such as a power grid, or a detachable power supply connection for charging the accumulator or the battery of the main power supply 24. For this purpose, the main power supply 24 can have an inverter in order to provide a predetermined direct current supply from an alternating current source connected via the power connection 23 as the external power source. The predetermined direct current supply can also already be provided by a direct current source connected via the power connection 23 as the external power source. The DC power supply can be regulated by the voltage regulators mentioned above and supplied to the components of the control unit 7 as adjusted DC power supplies.

The auxiliary power supply 25 is connected to the volatile memory 16 and/or the permanent memory 17 via the bus 20. The auxiliary power supply 25 is charged by the electrical power of the main power supply 24. The auxiliary power supply 25 can be arranged inside or outside the control unit 7, or inside or outside the volatile memory 16 and/or the permanent memory 17. For example, the auxiliary power supply 25 can be accommodated on a main board of the control unit 7 in order to supply the volatile memory 16 and/or the permanent memory 17 with an auxiliary power. The auxiliary power supply 25 can in particular be designed in the form of a supercapacitor, an accumulator and/or a battery. The power capacity/energy capacity of the main power supply 24 can be many times, for example at least 10 times or 50 times greater than the power capacity/energy capacity of the auxiliary power supply 25.

The processor 15 monitors changes in the electrical power supplied by the main power supply 24. In the event of a sudden power failure, e.g. if the power source external to the controller 7 is disconnected from the main power supply 24 or the main power supply 24 otherwise degrades or fails, and the processor 15 determines that the electrical power supplied by the main power supply 24 to one or more of the components of the controller 7 has fallen below a threshold, e.g. 0.8 or 0.75 of an operating power of the main power supply 24, the processor 15 causes the auxiliary power supply 25 to take over a remaining supply power for a shutdown of the controller 7. The shutdown process includes supplying at least the processor 15, the volatile memory 16 and/or the persistent memory 17 with electrical power for the time of the shutdown process. During the shutdown process, the data based on the input signal/output signal that is currently located in the volatile memory 16 and/or the data based on the input signal/output signal that is currently being processed in the processor 15, for example in the register/cache of the processor 15, are transferred from the volatile memory 16 and/or the processor 15 to a meta area of the permanent memory 17. For this purpose, the meta area of the permanent memory 17 can be reserved specifically for the shutdown process.

In the event of a start-up process of the control unit 7 in which the main power supply 24 again provides the operating power, the processor 15 loads the data based on the input signal/output signal from the meta area of the permanent memory 17 in order to enable faster data processing. The meta area of the permanent memory can be released after the start-up process or successively during the start-up process.

4 shows a control engineering block diagram for degradation diagnosis. The block diagram illustrates the method presented here. In order to diagnose the degradation of the power electronics module 2, the periodic conduction losses in the semiconductor component are stimulated. In the example of the MOSFET, these conduction losses can be calculated by P _loss = v _ds * i _ds = R _DS,on (v _GS , T _j ) * i _ds ² , where v _{ds is} the forward voltage (drain-source voltage), R _DS,on is the on-resistance and i _ds is the drain-source current of the MOSFET. In order to generate periodic conduction losses within the device, the on-resistance R _DS,on is manipulated in the on state. The on-resistance R _DS,on of a MOSFET depends on the gate-source voltage v _GS and the junction temperature T _j . The modulation of the on-resistance R _DS,on can therefore be achieved by superimposing the gate-source direct voltage V ₀ with a sinusoidal gate-source alternating voltage v _ac .

This periodic excitation of the on-resistance R _DS,on leads to a periodic small-signal modulation of the conduction losses P _cond and the drain-source voltage v _ds , both of which have a constant phase delay of 180° with respect to v _GS for low frequencies. The thermal impedance Z _tn (jω), which is 4 simplified as the thermal resistance R _th and the thermal capacitance C _th , describes how the junction temperature T _j responds to the periodic loss excitation in magnitude and phase. In addition to the gate-source voltage v _GS affecting the on-resistance R _DS,on , the junction temperature T _j occurring in response to the loss excitation causes an additional phase shift in the drain-source voltage v _ds . Consequently, the phase shift of the drain-source voltage v _ds changes when degradation affects the phase of the thermal impedance Z _th (jω), e.g. due to changes in the total R _th . Therefore, changes in the phase shift between gate-source voltage v _GS and drain-source voltage v _ds indicate changes in the phase of the thermal impedance ∠Z _th (jω) that occur when the characteristics of the thermal heat dissipation path change due to degradation modes or changes in convection conditions. Therefore, the method proposed here is able to detect different modes of degradation separately by focusing on the phase delay at different frequencies, since the different degradation modes leave traces at clearly definable bandwidths.

5 shows frequency-resolved phase diagrams with corresponding phase responses F1-F3 for a better understanding of the process. The three phase responses F1-F3 above differ in 5 by artificially introducing small changes in the thermal path beneath the semiconductor component 3. In this example, the thermally conductive layer to the heat sink of the power electronics module 2 was removed by a little F2 and all of F3 in order to depict degradation effects. Such degradation effects beneath the power electronics module 2 can be recognized by the phase of the thermal impedance in the millihertz range. Small signal frequencies in the range of 1 mHz to 5 Hz are particularly suitable for this.

At this point, it should be noted that all of the parts described above, viewed individually and in any combination, in particular the details shown in the drawings, are claimed as essential to the invention. Modifications to this are familiar to the person skilled in the art.

LIST OF REFERENCE SYMBOLS

1

Power electronic system

2

Power electronics module

3

Semiconductor component

4

Control connection

5

Sink connection

6

Source connection

7

Control unit

8th

DAC

9

first instrument amplifier

10

first anti-aliasing filter

11

first ADC

12

second instrument amplifier

13

second anti-aliasing filter

14

second ADC

15

processor

16

Volatile memory

17

Permanent storage

18

Controller

19

NVM

20

bus

21

Arbitrator

22

Communication interface

23

Power connection

24

Main power supply

25

Auxiliary power supply

F1

Phase response without degradation

F2

Phase response with 1st type degradation

F3

Phase response with 2nd type degradation

V0

Gate-source DC voltage

vac

Gate-source alternating voltage

vGS

Gate-source voltage

RDS,on

On resistance

Tj

Junction temperature

vds

Drain-source voltage

ids

Drain-Source Current

Pcond

Performance losses

Cth

thermal capacity

Rth

thermal resistance

Claims (10)

Method (S0) for degradation diagnosis of a power electronics module (2) with a semiconductor component (3), the method (S0) comprising: providing (S1) an input signal (v _GS ) of the power electronics module (2) containing a large-signal part (V ₀ ) provided for switching on the semiconductor component (3); receiving (S2) an output signal (v _ds ) of the power electronics module (2) based on the input signal (v _GS ) in order to enable a degradation diagnosis of the power electronics module (2); characterized in that the input signal (v _GS ) contains a sinusoidal small-signal part (v _AC ). Procedure (S0) according to Claim 1 , characterized in that the sinusoidal small-signal part (v _AC ) is a chirp which is provided (S1) by temporally varying a frequency of the sinusoidal small-signal part (v _AC ). Procedure (S0) according to Claim 2 , characterized in that the chirp has a frequency range between 0.1mHz and 100Hz. Procedure (S0) according to Claim 3 , characterized in that the large signal part (V ₀ ) of the input signal (v _GS ) ensures an on state of the semiconductor component (3) over the duration of the chirp. Method (S0) according to one of the preceding claims, characterized in that determining (S3) a degradation of one or more components associated with the power electronics module (2) by frequency-resolved comparison of a phase of the output signal (v _ds ) with a phase of the input signal (v _GS ). Procedure (S0) according to Claim 5 , characterized in that the degradation of the plurality of components associated with the power electronics module (2) is determined (S3) by phase differences between the output signal (v _ds ) and the input signal (v _GS ) in corresponding frequency sub-ranges that can be associated with the plurality of components associated with the power electronics module (2), and that the frequency sub-ranges differ from component to component of the components associated with the power electronics module (2). Computer program, characterized in that the computer program comprises instructions which, when the computer program is executed by a computer or by a control device (7), cause the computer or the control device (7) to execute or initiate the method (S0) according to one of the preceding claims or at least one of the steps thereof. Data carrier (C42, C43, C45), characterized in that the data carrier (C42, C43, C45) contains the computer program according to Claim 7 is stored. Control unit (7) for degradation diagnosis of a power electronics module (2) with a semiconductor component (3), wherein the control unit (7) is designed: to provide an input signal (v _GS ) of the power electronics module (2) containing a large-signal part (V ₀ ) provided for switching on the semiconductor component (3); to receive an output signal (v _ds ) of the power electronics module (2) based on the input signal (v _GS ) in order to enable a degradation diagnosis of the power electronics module (2); characterized in that the input signal (v _GS ) contains a sinusoidal small-signal part (v _AC ). Power electronics module (2) with a semiconductor component (3), wherein the power electronics module (2) is designed to receive (S1) an input signal (v _GS ) of the power electronics module (2) containing a large-signal part (V ₀ ) provided for switching on the semiconductor component (3); to transfer (S2) an output signal (v _ds ) of the power electronics module (2) based on the input signal (v _GS ) in order to enable a degradation diagnosis of the power electronics module (2); characterized in that the input signal (v _GS ) contains a sinusoidal small-signal part (v _AC ).

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