DE102022131564A1 - Control device for a zone control device, zone control device and method for operating a zone control device - Google Patents

Abstract

The invention relates to a control device (21) for a zone control device (20) which has a system processor (22) for controlling external devices of a vehicle, wherein the external devices can be connected to the zone control device (20) via a plurality of first connection elements (35, 35', 35"). The control device (21) is designed as an independent control device (21) which is different from the system processor (22) of the zone control device (20), wherein the control device (21) has a first control interface (27) which can be connected to the system processor (22), and wherein the control device (21) is designed to be controlled by the system processor (22) when the system processor (22) is connected to the control interface (27) of the control device (21), and wherein the control device (21) is designed to control the first connection elements (35, 35', 35") according to the control specifications provided by the system processor (22).

Description

The invention relates to a control device for a zone control device, wherein the zone control device comprises a system processor for controlling external devices of a vehicle, wherein the external devices can be connected to the zone control device via a plurality of first connection elements. The invention further relates to a zone control device and a method for operating a zone control device.

A zone control device typically controls various devices of a vehicle, for example in a specific area of the vehicle, such as devices located in a front left area of the vehicle or in a front right area of the vehicle, and so on. These devices can be connected to the zone control device via a plurality of first connection elements, which can be designed as pins, for example. The current architecture of such a zone control device has several limitations, which makes it difficult to provide a competitive technical and financial solution. First, the developed power architecture is usually carried out on an additional board, in particular a power connection board, and there is a board connection between the power connection board and the system processor board on which the system processor of the zone control device is located. This leads to a high number of lines, which complicates the design of the board-to-board connector and increases its cost. In addition, the routing of this high number of lines complicates the design of the system processor PCB (Printed Circuit Board) as well as the power connection board. In addition, the number of controllers required complicates the selection of the system processor, as a system processor capable of communicating with all the required interfaces is required, which requires a larger system processor. To save some pins, the signals can be multiplexed over several lines, but this usually results in delays and performance degradation of the real-time signals. In addition, the wake-up controllers according to the current state of the art do not meet all the required schemes for waking up the zone controller.

The EN 10 2020 209 469 A1 discloses a sensor arrangement of a vehicle, which comprises a central control unit and at least two zone control units as well as a plurality of environmental sensors, which are designed to detect an environment of the vehicle. Each environmental sensor is connected to one of the zone control units, wherein each zone control unit is connected to the central control unit. Each zone control unit comprises an application-specific integrated circuit and is designed to preprocess sensor data of the environmental sensors, wherein the central control unit comprises a universal integrated circuit and is designed to process the preprocessed sensor data in order to detect objects in the environment of the vehicle.

US 2021/0397178 A1 describes a navigation system for remotely moving modular vehicle subassemblies through a plurality of assembly zones of a vehicle assembly facility. This navigation system includes a predefined primary path configured for the modular vehicle subassemblies to move along during assembly of cylinder head covers on the modular vehicle subassemblies, a plurality of sensors, a plurality of zone controllers, and a central management system having a navigation algorithm. The plurality of sensors are configured to transmit proximity data and visual data about the modular vehicle subassemblies moving through the plurality of assembly zones to the plurality of zone controllers. The central management system is in communication with each of the plurality of zone controllers, and the navigation algorithm receives the proximity data and visual data and calculates movement instructions for remotely moving the modular vehicle subassemblies moving through the plurality of assembly zones.

However, this does not simplify the design of a zone controller as such.

It is an object of the present invention to provide a control device, a zone controller and a method that enable a more cost-effective implementation of a zone controller.

This object is achieved by a control device, a zone control device and a method having the features according to the independent claims. Advantageous embodiments of the invention are specified in the dependent claims, the description and the drawings.

According to the invention, a control device for a zone control device is provided, wherein the zone control device has a system processor for controlling external devices of a vehicle, wherein the external devices can be connected to the zone control device via a plurality of first connection elements. The control device is designed as an independent device, controlled by the system processor of the zone control device and the control device has a first control interface that can be connected to the system processor. In addition, the control device is designed to be controlled by the system processor when the system processor is connected to the control interface of the control device, and the control device is designed to control the first connection elements according to the control specifications provided by the system processor.

The invention is based on the realization that the many pins or generally the many first connection elements can be controlled by very simple control circuits. This allows these control circuits to be implemented on an external device, namely the control device, which is located outside the actual system processor of the zone control device. The control device itself can be designed very simply and thus configured very inexpensively. Usually, the communication between the system processor and the first connection elements requires a considerable number of connectors, which makes the hardware design and in particular the design of the system processor very expensive. This can now advantageously be avoided because the system processor, which is the actual main processor of the zone control device, no longer has to provide so many connection elements itself. The system processor can be connected to the control device via very few connecting lines. The structure of the system processor can be enormously simplified and the costs for the system processor and the zone control device as a whole can be enormously reduced. Thus, the control device, which may also be referred to as a remote signal control device, may provide a stand-alone controller, for example in the form of a stand-alone programmable FPGA (Field Programmable Gate Array) controller or ASIC (Application Specific Integrated Circuit) controller. This control device may additionally, as described later, extend the number of required digital and analog signals according to a stored configuration. This solution has the advantage of simplifying the design of the entire PCB layout of the circuit board on which the system processor is located and reducing the number of board-to-board connection pins, in particular board-to-board connection elements, and in particular the number of connection elements to be provided by the system processor. In addition, the required costs for the system processor are reduced by reducing the expected number of input pins or connection elements in general. In addition, the additional costs for using additional integrated circuits for processing wake-up signals are reduced, as will be explained later. Furthermore, the solution, especially the control device, is configurable and can be adapted to specific needs, so that it can be optimized in terms of cost and PCB size.

The system processor of the zone control device is the main processor of the zone control device, which is designed to control the external devices connected to the zone control device via the control device. The system processor can thus provide control specifications to the control device via the first control interface, and the control device can control the external devices accordingly. Furthermore, the communication between the system processor and the control device and between the zone control device as a whole and the external devices is preferably provided in the form of wired communication. The control device as a stand-alone control device is to be understood in the sense that the control device is a separate physical device, namely separate from the system processor. However, the system processor and the control device can both be arranged on the same PCB. Optionally, the control device can also be arranged on a separate PCB, which can be connected to the PCB of the system processor via a board-to-board connector. The control device can also be part of the power connection board mentioned above, for example.

The first connection elements can be designed as pins or can comprise such. The control device comprises the first control interface, which is provided for connection to the system processor. If the system processor is connected to the control device via this first control interface, the control device can receive the control specifications provided by the system processor, according to which the control device controls the first connection elements and in particular the external devices connected to them, e.g. when the control device is arranged, connected and operated as intended.

The first interface, as well as other elements, interfaces, controllers, units and modules of the control device and/or the zone controller, which are further described in further embodiments of the invention, may generally be provided in the form of software and/or hardware.

According to a further embodiment of the invention, the control device comprises the first connection elements, in particular first pins, and/or a plurality of second connection elements, in particular second pins, which can be connected or are connected to the first connection elements. The first connection elements, in particular one or more of the first connection elements, can also be part of the above-mentioned power connection board. The power connection board can provide the plurality of first connection elements via which external devices of the vehicle to be controlled can be connected to the zone control device. The power connection board can also provide intelligent fuses, in particular a plurality of intelligent fuses to which different maximum currents are assigned. The control device can be part of the power connection board or can be located on the same circuit board as the components of this power connection board. The connections between the first pins and the control device can be provided in the form of hard-wired connections. Otherwise, the control device can also be arranged on a separate circuit board, and the control device can comprise second connection elements which are connected to the first connection elements of the power connection board. This connection can e.g. B. be provided in the form of a board-to-board connector. Some of the first connection elements to which external devices can be connected may also be part of the control device itself and not belong to the power connection board.

According to a further advantageous embodiment of the invention, a first group of the first and/or second connection elements is designed as multiplexed connection elements and the control device comprises a pin multiplexer and a plurality of first interface modules, in particular a digital input port controller, a digital output port controller and an analog-to-digital converter (ADC), wherein the pin multiplexer is designed to assign each of the multiplexed connection elements to one of the plurality of first interface modules.

The multiplex connection elements can be designed, for example, as multiplex connection pins. These multiplexed pins can also be referred to as multiplexed port pins. These multiplex connection pins can make it possible to multiplex the pin or generally the connection element as a digital input (DIN), digital output (DOUT) or ADC. Preferably, the system supports 172, 256 and 320 pins. The pin multiplexer can also be referred to as a signal multiplexer and is designed to assign the various digital input pins, i.e. the pins assigned to the digital input port controller, the digital output pins, i.e. the pins assigned to the digital output port controller, and the ADC pins, i.e. the pins assigned to the ADC, to one or more of the first and/or second connection elements of the first group, which can be provided in the form of corresponding port pins. This multiplexer can be controlled directly by a port multiplexing configuration ROM (Read Only Memory). The use of such a multiplexer has the great advantage that the total number of pins required or, in general, the number of connection elements required can be reduced. In addition, significantly more flexibility and options are provided to adapt the control device to different situations or applications.

The digital input port controller may be configured to control up to 128 digital inputs, support interrupt leveling and edge detection, support a frequency input and a PWM (pulse width modulation) input and fast signal changes. The digital output port controller may preferably be configured to control up to 128 digital outputs, a frequency output and a PWM output and fast signal changes. The analog-to-digital converter may be configured to control up to 128 analog inputs, support up to 16-bit delta-sigma ADC with fast processing and group sampling.

According to a further advantageous embodiment of the invention, the control device comprises a first memory, in particular a port multiplexing and configuration ROM, wherein a port multiplexing configuration can be stored or is stored in the first memory and the pin multiplexer is designed to assign one or more of the multiplexed connection elements to the first interface modules according to the stored port multiplexing configuration. The port multiplexing and configuration ROM thus contains the configurations of the signal multiplexer, i.e. the pin multiplexer. The configurations for the port multiplexing and configuration ROM can advantageously be adapted to the respective situation or application. In this way, the number of digital and analog signals required can advantageously be expanded according to the stored configuration.

According to a further advantageous embodiment of the invention, a second group of the first and/or second connection elements is connected by dedicated SPI (Serial Peripheral Interface) ports for Control of SPI devices that can be connected to the SPI ports is provided, wherein the control device comprises a second interface module in the form of an SPI control module that is connected to the SPI ports or comprises the SPI ports and that comprises one or more SPI controllers. Thus, the control device can advantageously also have dedicated SPI ports that can be connected to external SPI devices and can be used to control these external SPI devices. Each port can be made up of several control lines, in particular one for SDO (serial data out), one for SDI (serial data in), one for SCLK (serial clock) and one or more, preferably up to eight, for CS (chip select) and optionally one or more, preferably up to four, for WP (write protect). In particular, the speed of the SPI lines is up to 60 Mbit/s. The SPI control module preferably comprises several SPI controllers, in particular SPI master controllers. For example, the SPI control module can include up to 16 controllers. Each controller can be a BUS master for up to eight slaves. Each slave can be controlled via its own chip select pin. The controller can be designed so that its maximum speed is up to 60 Mbit/s.

According to a further advantageous embodiment of the invention, the control device comprises a first wake-up port connectable to the system processor, wherein the control device comprises a first module, in particular a module for a programmable input with wake-up function, wherein the first module is configured to provide a wake-up signal at the wake-up port in order to wake up the system processor in dependence on a signal received from one of the first and/or second connection elements of the first group, for example via the digital input controller.

By means of the wake-up port, wake-up signals can be sent to the system processor if the system processor is connected to the wake-up port, which is the case depending on the intended use of the control device. The first module is able to read inputs from at least one of the first interface modules, e.g. from the digital input received from the digital input port controller and inputs from the ADC. In general, the first module must not only be used to implement a wake-up functionality, but also to send received inputs back to the system processor via the control interface of the control device. Advantageously, the first module can process wake-up events from the various inputs and trigger the wake-up port accordingly. In general, the first module can be designed to read digital signals, frequency inputs, PWM inputs and ADC values. Thus, advantageously, the control device can also be equipped with a wake-up functionality. Consequently, the controller, namely the control device, can wake up the zone control device, in particular the system processor, for the wake-up sources.

• - aktiv low bei offenem Stromkreis,
• - aktiv high bei offenem Stromkreis

ist.In particular, the implementation of the first module, namely the module for programmable inputs with wake-up function, also called unit, can be as follows: The unit is connected to digital inputs (DIN) and analog inputs (from ADC). The programmable input with wake-up function allows programming each input to detect if the input is connected to

• - active low when circuit is open,
• - active high when circuit is open

is.

• - Eingangspegeländerungen,
• - fallende und steigende Flanken,
• - Eingangssignalfrequenz in PWM,
• - einen logischen Pegel des Stromeingangs im eingeschwungenen Zustand zu erkennen.

This means that for each input or input pin, it can be determined whether it is active low or active high in the event of an open circuit. This allows the programmable input module with wake-up function to detect whether the corresponding input is connected or not. For digital inputs, each input can be programmed individually.

• - Input level changes,
• - falling and rising edges,
• - Input signal frequency in PWM,
• - to detect a logic level of the current input in the steady state.

• - Eingangspegeländerungen,
• - Eine Eingangssignalfrequenz und PWM,
• - den stationären analogen Pegel des Stromeingangs im digitalen Format,
• - einen offenen und geschlossenen Schaltkreis zu erkennen.

For analog inputs, each input can also be programmed individually,

• - Input level changes,
• - An input signal frequency and PWM,
• - the stationary analog level of the current input in digital format,
• - to detect an open and closed circuit.

• - Änderung des Pegels des digitalen Eingangs,
• - Änderung der Flanke am digitalen Eingang,
• - Änderung des Pegels des Analogeingangs.

For the analog and digital inputs together, the unit, i.e. the first module, can group them into up to 16 groups, where each group can provide a wake-up source. The wake-up source is activated when a the following conditions are programmed for activation:

• - Changing the level of the digital input,
• - Change of edge at the digital input,
• - Change the level of the analog input.

This makes it easy to implement a wake-up functionality.

According to a further advantageous embodiment of the invention, the control device comprises a second module for accelerating the safety-critical real-time signal processing and a second memory, in particular a configuration ROM, which is assigned to the second module, wherein the second module is connected to the first interface modules and the SPI control module and is designed to carry out certain actions with signals according to a configuration stored in the second memory.

Advantageously, the safety-critical real-time signal processing accelerator may implement several different processings such as signal sampling state machine, signal updating state machine and signal monitoring state machine based on the information stored in the configuration ROM or generally in the second memory. The goal of this accelerator, i.e. the second module, is to process the fast applications that cannot be delayed until they can be transmitted to the system processor to make a decision about them. The accelerator, i.e. the second module, may be connected to the digital inputs, digital outputs, ADC and SPI. In other words, it may be connected to one or more of the above-mentioned first interface modules and/or the SPI control module. It may also be designed to make decisions based on complex relationships between different types of pins.

According to a further advantageous embodiment of the invention, the control device comprises a third module for a locked output, which is designed to provide an output signal to one of the first interface modules, in particular to the digital output controller, depending on a control signal received from the first control interface. Alternatively, the third module for the locked output can also be equipped with PWM support. This third module can generate digital outputs based on data coming from the first control interface, in particular from the SPI protocol. In certain pre-configured interfaces, some outputs are locked to ensure that this output is maintained in the event of a power failure or a system reset. Also in the event of security problems, the output is reset to certain values.

• - Erzeugen der gewünschten logischen Ausgabe,
• - Erzeugen der erforderlichen PWM und falls nötig einer Frequenzmodulation,
• - Verriegelung der Ausgabe, wenn die Ausgabe so programmiert ist, dass sie ihren letzten sicheren Zustand beibehält,
• - Erzeugen einer ausfallsicheren Ausgabe, falls die Ausgabe einen bestimmten sicheren Zustand hat.

In particular, the implementation of this third module for the latched output with PWM support can be as follows: The unit, that is, the third module, can be connected to the digital outputs, in particular to the controller of the digital output port. The latched output with the PWM support module implements the following functions for each connected output:

• - Generate the desired logical output,
• - Generate the required PWM and if necessary frequency modulation,
• - Output locking if the output is programmed to maintain its last safe state,
• - Generate a fail-safe output if the output has a certain safe state.

These described outputs can be provided at one or more of the above-mentioned connection elements, in particular first and/or second connection elements of the first group.

According to a further advantageous embodiment of the invention, the control device comprises a fourth module for safety monitoring, which is designed to determine whether one or more modules of the control device, in particular the first interface modules, the SPI control module, the first module, the second module and the third module, are in a safe state or not, and to report a safety status to a safety status port of the control device.

Advantageously, a malfunction of one or more of the aforementioned modules can be detected and reported. This safety monitoring module can thus monitor the state of each sub-device within the control device, namely the remote control processor, and ensure that it is in a safe state. If one of the sub-devices is not in a safe state, it resets, for example, the entire device, i.e. the entire control device, or only this specific sub-device. In addition, it sends the safety status via a safety status port. A device connected to the safety status port tus port, e.g. the system processor, can read the security status.

• - Status interner Zähler,
• - Ergebnisse interner Berechnungen,
• - Status interner Prüfpunkte.

For example, the implementation of the safety monitoring module, i.e. the fourth module, may be as follows: Each of the connected units, i.e. the above-mentioned modules or sub-devices, such as the first interface modules, the SPI control module, the first, second and third modules, is responsible and designed to create its internal safety checks and then periodically reports its safety status to the safety monitoring module, i.e. the fourth module. The units can create internal safety checks based on the following options:

• - Status of internal counters,
• - Results of internal calculations,
• - Status of internal checkpoints.

If any of these checks fail, the corresponding unit or module stops reporting its safety status to the monitor, i.e. the fourth module. In this case, the monitor detects that something has gone wrong. Depending on the programming of the safety monitoring system, i.e. the fourth module, it can reset either this unit specifically or the entire device, i.e. the entire control device. The monitor also reads the status of a temperature monitor, which can also be part of the control device, to ensure that the control device chip is running properly within the required temperature range.

The monitor, i.e. the fourth module, reports its status itself to the system processor if it is connected to the security status port. This allows the monitor to report its status to the system processor via the status port. The monitor itself is monitored by a window watchdog, for example, which has its own independent external oscillator clock. This watchdog cannot be stopped and preferably requires handshaking with command and counter protocol to be updated.

Thus, safety functions can also advantageously be implemented by the control device.

According to a further advantageous and preferred embodiment, the control device is provided in the form of an ASIC or FPGA. Alternatively, the control device can also be provided in the form of a microcontroller, in particular an additional slave processor, or comprise this. Thus, a microcontroller can be used, which preferably has a central processing unit, GPIO (General Purpose Input Output), ADC, SPI and additional ports for the SPI controller through the system processor and the wake-up interfaces. However, providing the control device in the form of an ASIC or FPGA is preferred, since the added value of the ASIC or FPGA design is that the required number of pins can be flexibly defined according to the project requirements. In addition, the cost of the ASIC/FPGA is likely to be lower than the cost of using a complete microcontroller, given the required number of pins.

The control interface of the control device can comprise several individual modules or units. In particular, the control interface can comprise an SPI port interface for the control port, an SPI controller which is connected to the host, which is preferably the system processor, in particular via the SPI port interface, wherein the SPI controller is preferably designed to enable slave operation with a communication speed of up to 60 Mbit/s. In addition, the control interface can also comprise an SPI control protocol acceleration module which implements the control protocol to be specified in order to enable communication between the control device and the system processor. With the aid of the SPI control protocol acceleration module, the entire device, i.e. the control device, can be controlled and monitored from the system processor via the SPI control protocol. According to one example, the protocol can be defined such that the system processor can communicate with up to four devices simultaneously. The protocol can, for example, accept 16-bit SPI communication. The protocol defines commands which are to be executed by the main processor, i.e. the system processor, to the remote controller, i.e. the control device. The protocol can also define commands to be sent from the remote controller, i.e. the control device, to the main processor, i.e. the system processor.

• - Schreiben eines einzelnen digitalen Ausgangs,
• - Schreiben eines einzelnen Frequenzausgangs,
• - Schreiben eines einzelnen PWM-Ausgangs,
• - Schreiben eines digitalen Port-Ausgangs,
• - Lesen eines einzelnen digitalen Ausgangswerts,
• - Lesen eines einzelnen Frequenzausgangswerts,
• - Lesen eines einzelnen PWM-Ausgangswerts,
• - Lesen eines digitalen Port-Ausgangswerts,
• - Lesen eines einzelnen digitalen Eingangswerts,
• - Lesen eines einzelnen Frequenzeingangswerts,
• - Lesen eines einzelnen PWM-Eingangswerts,
• - Lesen eines digitalen Ports-Eingangswerts,
• - Lesen eines analogen Eingangswertes,
• - Lesen eines analogen Port-Eingangswertes,
• - Schreiben des Mutliplexer-ROM,
• - Lesen des Mutliplexer-ROM,
• - Löschen des Mutliplexer-ROM,
• - Schreiben des sicherheitskritischen-Echtzeit-Signalverarbeitungs-Beschleuniger-ROM,
• - Löschen des sicherheitskritischen-Echtzeit-Signalverarbeitungs-Beschleuniger-ROM,
• - Lesen des sicherheitskritischen-Echtzeit-Signalverarbeitungs-Beschleuniger-ROM
• - Schreiben des programmierbaren-Eingangs-mit-Wakeup-ROM,
• - Löschen des programmierbaren Eingangs mit Wakeup-ROM,
• - Lesen des programmierbaren Eingangs mit Wakeup-ROM,
• - Schreiben des Systemmonitor-Konfigurationsregisters,
• - Lesen des Systemmonitor-Konfigurationsregisters,
• - Schreibe der Systemmonitor-Konfigurationsregister-Liste,
• - Lesen der Systemmonitor-Konfigurationsregister-Liste,
• - Lesen des nächsten Frames,
• - Lesen des ersten Frames,
• - Lesen des letzten Frames,
• - Schreiben des ersten Frames,
• - Schreiben des nächsten Frames,
• - Schreiben des letzten Frames,

The protocol preferably defines one or more or all of the following commands to be sent from the main processor to the remote control device:

• - Writing a single digital output,
• - Writing a single frequency output,
• - Writing a single PWM output,
• - Writing a digital port output,
• - Reading a single digital output value,
• - Reading a single frequency output value,
• - Reading a single PWM output value,
• - Reading a digital port output value,
• - Reading a single digital input value,
• - Reading a single frequency input value,
• - Reading a single PWM input value,
• - Reading a digital port input value,
• - Reading an analog input value,
• - Reading an analog port input value,
• - Writing the multiplexer ROM,
• - Reading the multiplexer ROM,
• - Erase the multiplexer ROM,
• - Writing the safety-critical real-time signal processing accelerator ROM,
• - Erasing the safety-critical real-time signal processing accelerator ROM,
• - Reading the safety-critical real-time signal processing accelerator ROM
• - Writing the programmable input with wakeup ROM,
• - Clearing the programmable input with Wakeup ROM,
• - Reading the programmable input with wakeup ROM,
• - Writing the system monitor configuration register,
• - Reading the system monitor configuration register,
• - Write the system monitor configuration register list,
• - Reading the system monitor configuration register list,
• - Reading the next frame,
• - Reading the first frame,
• - Reading the last frame,
• - Writing the first frame,
• - Writing the next frame,
• - Writing the last frame,

• - Lesen des nächsten Frames,
• - Lesen des ersten Frames,
• - Lesen des letzten Frames,
• - Schreiben des ersten Frames,
• - Schreiben des nächsten Frames,
• - Schreiben des letzten Frames,
• - Letzter Befehls-Status.

In addition, the protocol preferably specifies one or more or all of the following commands sent from the remote control to the main processor:

• - Reading the next frame,
• - Reading the first frame,
• - Reading the last frame,
• - Writing the first frame,
• - Writing the next frame,
• - Writing the last frame,
• - Last command status.

The controller can be used to provide a standalone programmable FPGA/ASIC controller that expands the number of required digital and analog signals according to the stored configuration. The controller is programmed via the SPI interface, which controls the signal output, update rates, diagnostics and safety reactions.

The controller, i.e. the control device, can wake up the zone control device, in particular the system processor, for the wake-up sources and implements critical real-time performance and takes into account the vehicle safety requirements. In addition, the solution defines a control protocol over SPI that is used to efficiently control the ASIC, i.e. the control device, and ensures the safety of the device operation. The remote signal control device, i.e. the control device, implements all the necessary signal extensions and the required control logic to ensure that the signal processings meet the required real-time and safety requirements. In this way, the high-speed remote signal control device for a zone control device can be provided.

The invention also relates to a zone control device for a vehicle with a control device according to the invention or one of its embodiments.

According to a further advantageous embodiment, the zone control device comprises the system processor connected to the control device. The system processor and the connection to the control device can be implemented as previously described with reference to the control device and its embodiments.

According to a further advantageous embodiment of the invention, the system processor further comprises a second wake-up interface connected to the first wake-up interface of the control device, and a second Control interface connected to the first control interface of the control device.

This allows the number of interfaces provided by the system processor itself to be reduced to a minimum. This simplifies the system processor and reduces its cost.

According to a further advantageous embodiment of the invention, the zone control device comprises a power connection board which comprises at least a part of the first connection elements, wherein the system processor is connected to the first connection elements exclusively via the control device. In order to be connected to the first connection elements via the control device, the system processor only requires the above-mentioned interfaces, namely the second wake-up interface and/or the second control interface.

The invention also relates to a vehicle with a zone control device according to the invention or one of its embodiments. In particular, the vehicle can also comprise several zone control devices according to the invention or zone control devices according to embodiments of the invention. Each zone control device can be assigned to a specific control zone or a specific control area of the vehicle. In particular, each zone control device is designed to control devices of the vehicle that are located in the control area assigned to a corresponding zone control device, in particular to control only the devices that are located in the assigned control area. Thus, each zone control device is responsible for controlling the devices of its own associated control zone. The one or more zone control devices can be electrically and communicatively connected to a central control unit of the vehicle.

In general, one or more zone controllers may be designed to control certain functions of devices of the vehicle, in particular in a certain area of the vehicle, e.g. the front left side of the vehicle. The zone controller may be designed to control certain functions of certain devices of the vehicle in this certain area, e.g. those of the vehicle mirrors, the headlights, the engine and so on. As such, these control functions are entirely contained in the system processor and/or are carried out by the system processor and not by the control device. The control device merely serves as an interface between the system processor and these devices to be controlled by the system processor in order to simplify the system processor.

The invention further relates to a method for operating a zone control device for controlling external devices of a vehicle, i.e. devices located outside the zone control device, which can be connected to the zone control device via a plurality of first connection elements, wherein the zone control device comprises a system processor for controlling the external devices. The zone control device comprises a control device which is designed as an independent control device different from the system processor or the zone control device and the control device has a first control interface connected to the system processor, wherein the control device is controlled by the system processor and the control device controls the first connection elements according to control specifications of the system processor.

The advantages described with respect to the control device according to the invention and the zone control device according to the invention and their embodiments apply accordingly to the method according to the invention.

Preferred embodiments which have been described with regard to the control device according to the invention and the zone control device according to the invention also provide further corresponding embodiments of the method according to the invention.

Further features of the invention emerge from the claims, the figures and the description of the figures. The features and combinations of features mentioned above in the description as well as the features and combinations of features mentioned below in the description of the figures and/or shown in the figures alone can be used not only in the combination specified in each case, but also in other combinations, without thereby departing from the scope of the invention. Thus, embodiments are also to be regarded as encompassed and disclosed by the invention that are not explicitly shown and explained in the figures, but result from the embodiments explained and can be produced by separate combinations of features. Embodiments and combinations of features that do not have all the features of an originally formulated independent claim are also to be regarded as disclosed. Furthermore, embodiments and combinations of features are deemed to be disclosed, in particular by the embodiments set out above, that go beyond or deviate from the combinations of features set out in the relationships of the claims.

• 1 eine schematische Darstellung eines Zonensteuergeräts gemäß einer nicht zur Erfindung gehörenden Ausführungsform;
• 2 eine schematische Darstellung eines Zonensteuergeräts gemäß einer Ausführungsform der Erfindung;
• 3 eine schematische Darstellung einer Steuervorrichtung für ein Zonensteuergerät gemäß einer Ausführungsform der Erfindung,
• 4 eine schematische Darstellung eines Zonensteuergeräts gemäß einer weiteren Ausführungsform der Erfindung;
• 5 eine schematische Darstellung eines Zustandsmaschinendiagramms, das von einem Modul der Steuervorrichtung gemäß einer Ausführungsform der Erfindung implementiert wird;
• 6 eine schematische Darstellung eines weiteren Zustandsmaschinendiagramms, das von einem Modul der Steuervorrichtung gemäß einer Ausführungsform der Erfindung implementiert wird;
• 7 eine schematische Darstellung eines Verfahrens zur Eingangsmittelung und Statusmeldung, die von einem Modul der Steuervorrichtung gemäß einer Ausführungsform der Erfindung implementiert wird; und
• 8 eine schematische Darstellung eines Zustandsmaschinendiagramms zur Ausgabe von Sicherheitsreaktionen auf der Grundlage eines oder mehrerer Diagnoseeingänge, das von einem Modul der Steuervorrichtung gemäß einer Ausführungsform der Erfindung implementiert wird.

Shown here:

• 1 a schematic representation of a zone control device according to an embodiment not belonging to the invention;
• 2 a schematic representation of a zone control device according to an embodiment of the invention;
• 3 a schematic representation of a control device for a zone control device according to an embodiment of the invention,
• 4 a schematic representation of a zone control device according to another embodiment of the invention;
• 5 a schematic representation of a state machine diagram implemented by a module of the control device according to an embodiment of the invention;
• 6 a schematic representation of another state machine diagram implemented by a module of the control device according to an embodiment of the invention;
• 7 a schematic representation of a method for input averaging and status reporting implemented by a module of the control device according to an embodiment of the invention; and
• 8th a schematic representation of a state machine diagram for outputting safety reactions based on one or more diagnostic inputs, which is implemented by a module of the control device according to an embodiment of the invention.

1 shows a schematic representation of a zone control device 1 according to an embodiment not according to the invention. In particular, 1 a zone controller 1 that combines several vehicle system functions and end-user functions into one unit. This architecture requires several power lines. The power lines are controlled by smart fuses 2a, 2b, 2c, 2d, 2e that require several digital input lines, digital output lines and ADC input lines and SPI lines to control them. The digital input and output lines are designated 3a, the ADC input lines 3b and the SPI lines 3c. These lines 3a, 3b, 3c are controlled by the system processor 4 of the zone controller 1 to ensure signal quality, sampling and diagnostics. The fuses 2a, 2b, 2c, 2d, 2e are designed in this example as one or more first intelligent fuses 2a for currents less than 500 mA (milliamperes), one or more second intelligent fuses 2b for currents less than 1A (amperes), one or more third intelligent fuses 2c for currents less than 2A, one or more fourth intelligent fuses 2d for currents less than 5A and one or more fifth intelligent fuses 2e for currents less than 10A.

This implementation requires extensive multiplexing of the signals and also takes up many pins of the system processor 4. This means that the chosen system processor 4 should meet certain pin requirements, which complicates the price and, moreover, the design of the circuit board 5 itself on which the various components are arranged. In addition to the power control interfaces, other digital and analog inputs are used as wake-up sources for the zone controller 1. As shown in 1 Thus, as shown, the system processor may comprise a GPIO controller 6 for controlling the digital input/output lines 3a, an ADC 7 for controlling the ADC input lines 3b and an SPI controller 8 for controlling the SPI lines 3c. Furthermore, the system processor 4 comprises a wake-up interface 9 for receiving the wake-up input, in particular in this example from a wake-up and input device 10 for receiving digital inputs 11a and analog inputs 11b as wake-up sources for the zone controller 1.

The developed power supply architecture is typically located on an additional board, referred to here as the power connection board 12. The system processor 4 can be housed on another board, namely the system processor board 13. The zone controller 1 then comprises a board-to-board connector 14 between the power connection board 12 and the system processor board 13, in particular to connect the power connection board 12 to the system processor board 13. Therefore, the board-to-board connector 14 requires a high number of lines, which complicates the construction of the board-to-board connector 14 and increases its cost. In addition, routing this high number of lines complicates the design of the system processor board 13 and the power connection board 12. The number of GPIO, ADC and SPI controllers 6, 7, 8 required complicates the selection of the system processor, since a system processor 4 is required that can communicate with all required interfaces, which requires a larger system processor 4. In order to save some pins, the signals can be multiplexed over several lines, but this usually leads to delays and performance losses in real-time signal processing. Wake-up controllers according to the current The current state of the art does not correspond to all the necessary schemes for waking up the zone controller 1.

2 shows a schematic representation of a zone control device 20 according to an embodiment of the invention. The zone control device comprises a system processor 22 and an additional control device 21, which can also be referred to as a remote signal control device 21. In this example, the remote signal control device 21 is implemented in the form of an ASIC 21a. The remote signal control device 21 can implement all the necessary signal extensions and the necessary control logic to ensure that the signal processing meets the necessary real-time and safety requirements.

Also in this case, several power lines are provided which are controlled by corresponding intelligent fuses 23a, 23b, 23c, 23d, 23e which require several digital input/output lines and ADC input lines as well as SPI lines for their control. In this case, the intelligent fuses comprise one or more first intelligent fuses 23a for currents less than 500 mA, one or more second intelligent fuses 23b for currents less than 1A, one or more third intelligent fuses 23c for currents less than 2A, one or more fourth intelligent fuses 23d for currents less than 5A and one or more fifth intelligent fuses 23e for currents less than 10A. The digital input and output lines are designated 24a, the ADC input lines 24b and the SPI lines 24c. These lines are now not controlled directly by the system processor 22, but indirectly via the control device 21. For this purpose, the control device 21 comprises various interface modules 25, in particular first interface modules in the form of a digital input/output interface module 25a for controlling the digital input/output lines 24a and an ADC interface module 25b for controlling the ADC lines 24b and a second interface module in the form of an SPI interface module 25c for controlling the SPI lines 24c. The control device 21 also comprises a further digital input interface module 25d for receiving additional digital inputs 26e as wake-up sources and a further ADC interface module 25e for receiving additional analog inputs 26b as wake-up sources for waking up the zone control device 20, in particular the system processor 22.

The control device 21 further comprises a control interface 27 and a wake-up interface 28. These two interfaces 27, 28 are connectable or connected to the system processor 22. For this purpose, the system processor also comprises a second wake-up interface 29, which is connectable or connected to the first wake-up interface 28 of the control device 21, and a second control interface 30, which is connectable or connected to the first control interface 27 of the control device. The control interfaces 27, 30 can use a control protocol via SPI, with which the ASIC 21a, in particular the control device 21, can be efficiently controlled by the system processor 22 and which ensures the safety of the operation of the device. Optionally, the control device 21 can have further wake-up interfaces 31, e.g. for expansion purposes.

In this case too, the developed power architecture can be implemented on an additional board, which in turn can be referred to as a power connection board 32. The system processor 22 can be implemented or positioned on a corresponding system processor board 33. The system processor board 33 can be connected to the power connection board 32 via a board-to-board connector 34. In this example, the control device 21 is located on the same board, namely the system processor board 33, as the system processor 22. In an alternative embodiment, the control device 21 can also be located on the power connection board 32. In this case, the board-to-board connector 33 connects the system processor 22 to the control device 21.

To connect external devices to the zone control device 20, the zone control device 20 comprises first connection elements 35, 35". Some of these first connection elements 35, 35" are part of the control device 21 in this example, in particular the connection elements designated 35", and some are part of the power connection board 32, in particular the connection elements designated 35. In particular, the power connection board 32 can comprise a plurality of first connection elements 35, which in this example are represented by circles or ellipses. Each circle or ellipse can stand for one or more connection elements 35, for example pins. To connect the power connection board 32 to the control device 21, the control device 21 can also have a plurality of second connection elements 35'. These connection elements 35' are also represented by corresponding circles or ellipses, each circle or ellipse representing one or more such connection elements 35', e.g. B. second pins 35'. The power connection board 32 can also have additional connection elements to connect the power connection board 32 to the board-to-board connector 34, which is connected to the second connection element 35' of the control device 21. If the control device 21 itself is part of the power connection board 32, no board-to-board connector 34 is required between the first connection elements 35 and the second connection elements 35'.

As already mentioned, the control device 21 can also have additional first connection elements 35", in particular for the additional digital inputs 26a and the additional analog inputs 26b. Here too, the ellipses representing the first connection elements 35" can stand for one or more connection elements 35", for example pins.

Both the control device 21 and the system processor 22 can have further connection elements, which are not explicitly shown here, in order to connect the control device 21 and the system processor 22 to one another, in particular to connect the control interfaces 27, 30 and the wake-up interfaces 28, 29.

3 shows a schematic representation of the control device 21 of the zone control device 20 provided by means of an ASIC 21 a according to an embodiment of the invention. There are several embodiments for the implementation of the control device 21. An example is shown in 3 The internal structure of the control device 21 according to this example is as follows: The control device 21 comprises multiplexed port pins 35'a. The multiplexed port pins 35'a may have some of the 2 shown second connection elements, designated 35', and in particular some of the first connection elements shown in 2 designated 35". These multiplexed port pins 35'a allow a single pin 35'a to be multiplexed as a digital input, digital output or ADC. The system preferably supports 172, 256 and 320 pins. These multiplexed port pins 35'a are connected to a pin multiplexer 36, which can also be referred to as a signal multiplexer 36. This pin multiplexer 36 is designed to assign the various digital input pins, the digital output pins and ADC pins to the ASIC port pins, i.e. the multiplexed port pins 35'a. The control device 21 also includes a digital input port controller 35a', which is designed to preferably control up to 128 digital inputs, support interrupt leveling and edge detection, frequency input and PWM input as well as fast signal changes. The control device 21 includes further a digital output port controller 25a", which is configured to control preferably up to 128 digital outputs, frequency outputs, a PWM output and fast signal changes. The controller 21 further comprises an ADC 25b', which can preferably control up to 128 analog inputs, supports up to 16 bit delta-sigma ADC, with fast processing and group sampling. Thus, the digital input port controller 25a' may include the corresponding digital input pins, which are not explicitly shown here, and the digital output port controller 25a" may include corresponding digital output pins, and the ADC 25b' may include corresponding ADC pins. The signal multiplexer 36 is designed to map the various digital input, digital output and ADC pins of the corresponding controllers, namely the digital input port controller 25a', the digital output port controller 25a" and the ADC 25b', to the corresponding ASIC port pins 35'a. This multiplexer 36 is directly controlled by the port multiplexing and configuration ROM 37. This port multiplexing and configuration ROM 37 contains the configurations of the signal multiplexer 36.

In addition, the control device 21 comprises dedicated SPI ports 35'b. All of these ports 35'b may be formed as or comprise some of the above-mentioned second connectors 35'. These dedicated SPI ports 35'b are configured to control ASPI devices, each port consisting of SDO, SDI, SCLK and preferably up to eight CS and up to four WP. Each of these ports may be connected to a corresponding pin 35'. The SPI line may have a speed of up to 60 Mbit/s. These dedicated SPI ports 35'b are connected to the SPI master controller 25c'. This master controller 25c' preferably consists of up to 16 controllers. Each controller may be a bus master for up to eight slaves, and each slave may be controlled via a dedicated chip select pin. The maximum speed of the controllers may be up to 60 Mbit/s.

In addition, the control device 21 comprises several further modules, which are explained below. Thus, the control device 21 comprises a first module, which can also be referred to as a programmable input with wake-up module 28b. This module 28b is able to read inputs from the digital input port controller 25a' and the ADC 25b' and send them back to the system processor 22 via the SPI protocol, in particular via the SPI control protocol accelerator 27c, which will be explained later. The first module 28b can also process the wake-up events from the various inputs and trigger the wake-up port 28a, which is connected or connectable to the system processor 22. Thus, this wake-up port 28a and the programmable input with wake-up module 28b can be used as part of the wake-up interface. point 28. The input system of the first module 28b can read digital signals, frequency inputs, PWM inputs and ADC values.

In addition, the control device 21 comprises a second module 38, which is a safety-critical real-time signal processing accelerator 38.

This accelerator 38 implements various processing such as signal sampling, signal refreshing and signal monitoring based on the information stored in the configuration ROM 39.

The safety-critical real-time signal processing accelerator 38 implements several different processing and state machines, some of which are described below using 6 , 7 , 8th and 9 will be explained in more detail. In particular, the accelerator 38 for processing safety-critical real-time signals can implement one or more of the following state machines to process the input signals.

6 shows a schematic example of a first state machine 50 implemented by the real-time accelerator 38 for safety-critical signals according to an embodiment of the invention. This state machine 50 is used for input sampling and status confirmation by means of a confirmation timer. Sampling certain inputs with multiple samples during a certain period of time ensures the stability of the signal, eg debouncing.

• Die erste Bedingung C1 beinhaltet, dass ein neuer Wert, der vom sicherheitskritischen Echtzeit-Signalverarbeitungs-Beschleuniger 38 empfangen wird, nicht gleich dem alten Wert ist. In diesem Fall beinhaltet die erste Bedingung C1 auch, dass ein Bestätigungs-Timer gestartet wird und der neue Wert auf den alten Wert gesetzt wird und ein Probenzähler auf 1 gesetzt wird.

S0 indicates the initial state. If a first condition C1 is met, the transition from the initial state S0 to a first state S1 occurs, whereby this first state S1 is a confirming state. If a second condition C2 is met when the system is in the confirming state S1, the system remains in the confirming state S1. The same applies if a third condition C3 is met when the system is in the first state S1. If the system is in the first state S1 and a fourth condition C4 is met, the system goes to the second state S2, which is a confirmed state. If the system is in the second state S2 and a fifth condition C5 is met, the system remains in the confirmed state S2. If the sixth condition C6 is met and the system is in the confirmed state S2, it goes back to the first state S1. The conditions are now explained below:

• The first condition C1 includes that a new value received from the safety-critical real-time signal processing accelerator 38 is not equal to the old value. In this case, the first condition C1 also includes that an acknowledgement timer is started and the new value is set to the old value and a sample counter is set to 1.

The fourth condition C4 includes that the new value is equal to the old value, the confirmation timer has expired, and the sample counter is equal to a confirmation counter, which is a predefined number for the sample counter. The confirmation counter is greater than 1. If these conditions are met, the reported value is set to the new value, the reported status is updated, and the confirmation timer is stopped. Under these conditions C4, the system can transition from the first state S1 to the second state S2.

The fifth condition C5 consists in or implies that the new value is equal to the old value. In other words, as long as the new value is equal to the old value, the system remains in the second state S2.

The sixth condition C6 consists in or implies that the new value is not equal to the old value. In this case, the confirmation timer is restarted, the new value is set to the old value and the sample counter is set to 1. The system then transitions from the second state S2 to the first state S1.

If the system is in the first state S1 and the third condition C3 is met, which consists in or implies that the new value is equal to the old value and the confirmation timer has already expired, the sample counter is incremented by 1. In other words, if the system is in the first state S1, the sample counter is incremented by 1 each time the confirmation timer has expired if the new value is still equal to the old value.

The second condition C2 consists or implies that the new value is not equal to the old value. In this case, the confirmation timer is started, the new value is set to the old value and the sample counter is set to 1.

6 shows a schematic representation of a state machine 51 which is executed or implemented by the module 38 according to another embodiment of the invention. In particular, according to the state machine 51, the sampling of the inputs and the status confirmation is carried out using the number of samples. In other words, a sampling certain inputs for a certain number of samples independent of time, such as a status confirmation. The state machine 51 corresponds to the state machine in 5 described state machine 50, with the difference that the first, second, third, fourth and sixth conditions C1', C2', C3', C4', C6' are defined slightly differently, in particular without a confirmation timer.

So in this case the first condition C1' is or implies that the new value is not equal to the old value. Then the new value is set equal to the old value and the sample counter is set to 1.

The fourth condition C4' consists in or includes that the new value is equal to the old value and the sample counter is equal to the predefined confirmation counter. Then the reported value is set to the new value.

The sixth condition C6' consists in or includes that the new value is not equal to the old value. Then the new value is set to the old value and the sample counter is reset to 1.

The condition C3' consists or includes that the new value is the old value. Then the sample counter is increased by 1.

The second condition C2' consists in or includes that the new value is not equal to the old value. Then the new value is set equal to the old value and the sample counter is set to 1.

If the system is in the initial state S0 and a new value is received that is different from the last old value, the system enters the confirming state S1. From then on, if all new values received are equal to the previous old values, the sample counter is increased by 1 each time until it reaches the confirming counter. Then the system goes from the confirming state S1 to the confirmed state S2 and stays in the confirmed state S2 as long as each new value is equal to the old value. If this is not the case, the system goes back to the confirming state S1 and the sample counter starts over. Each time a new value is received that does not match the old value, the sample counter starts again from 1, which means that the sample counter is reset to 1 again.

shows a schematic representation of an input averaging and status reporting procedure performed by the module 38. Using this procedure, a sampling of certain inputs can be performed for several samples and the mathematical or logical mean or a value interpolation can be calculated using a linear interpolation table. The procedure starts with an initial state S0'. In step S10, a pin value is read and received as a new value. In step S12, it is determined which operation is to be performed, namely the calculation of a mathematical mean according to the left path of the flow chart shown, the calculation of a median as a mean value represented by the middle path of the flow chart, or the calculation of an interpolation represented by the right path of the flow chart.

If a mathematical mean is to be calculated, the number of samples is increased by 1 in step S13. In step S14 it is determined whether the current number of samples corresponds to a predefined value. If this is not the case, the method returns to step S12 and the steps explained are repeated until the number of samples in step S14 corresponds to the predetermined number. If this is the case, the mathematical mean is calculated by taking the sum of all the new values received and dividing it by the predefined value of the number of samples required according to step S14. The value to be calculated, in this case the mathematical mean, is then reported in step S16 and the method ends in state SE. If it is determined in step S12 that a median is to be calculated, the number of samples is increased by 1 in step S17 and in step S18 it is determined whether the current number of samples already corresponds to the predefined value. This predefined value can be the same as that defined in step S14 or a different one. If this is the case, these steps are repeated until the current number of samples is equal to the predefined value in step S18. Then, in step S19, the median value is determined from all the new values received corresponding to the respective samples. Then, the value to be calculated, in this case the median found, is reported in step S16 and the method proceeds to the final state SE. If it is determined in step S12 that an interpolation should be performed, this interpolation is performed in step S20 using the new value and an interpolation table. The result is reported again in step S16 and the system proceeds to its final state SE.

8th shows a schematic representation of another state machine 52 for outputting safety reactions based on one or more diagnostic inputs and in particular for implementing fast reactions for output based on one or more diagnostic inputs. This state machine 52 can in turn be implemented by the module 38. The state machine 52 comprises four states, namely an asserting state S1, an asserted state S2, an un-asserting state S3 and an un-asserted state S4. If the system is in the unasserted state S4, the system can transition to the first state S1 if the first condition C11 is met. This condition C11 consists or includes that an error status is true. Then an assertion timer is started, the new value is set to the old value, and the sample counter is set to 1. If the system is then in the first state S1, it can return to the fourth state S4 if the second condition C12 is met, which consists or includes that the error status is false. Then the assertion timer is stopped and the system transitions to the fourth state S4. If the system is in the first state S1 and the third condition C13 is met, the system transitions to the second state S2. The third condition C13 consists or includes that the error status is true, the acknowledgement timer has expired, and the sample counter is equal to a predefined acknowledgement counter. Then, in addition, the reported status is updated as the error status and the error response is issued, and the acknowledgement timer is stopped.

If the system is in the second state S2 and the fourth condition C14 is met, which consists in or includes that the error status is true, the system remains in the second state S2. If the system is in the second state S2, i.e. the confirmed state, and the fifth condition C15 is met, it goes to the third state S3, i.e. the de-confirming state. The fifth condition C15 consists in or includes that the error status is false. The de-confirming timer is then started, the error status is set to false, and the sample counter is set to 1. If the system is in the third state S3, i.e. the de-confirming state S3, and a sixth condition C16 is met, it returns to the second state S2. The sixth condition C16 consists in or includes that the error status is false. In this case, the de-confirming timer is stopped. If the system is in the third state S3 and a seventh condition C17 is met, the system remains in the third state S3. This seventh condition C17 consists in or includes that the error status is false and the de-acknowledge timer has expired. In this case, the sample counter is incremented, in particular by 1. If the system is in the third state S3 and an eighth condition C18 is met, the system transitions to the fourth state S4, namely the de-acknowledged state S4. This eighth condition C18 consists in or includes that the error status is false, the de-acknowledged timer has expired and the sample counter is equal to a predefined de-acknowledged counter. Then, in addition, the reported status is updated as an error-free status and a normal output is provided by the module 38 and the de-acknowledged timer is stopped. If the system is in the fourth state S4, i.e. in the de-asserted state, and if a ninth condition C19 is met, it remains in the fourth state. This ninth condition C19 consists in or includes that the error status is false.

For example, the safety-critical real-time signal processing accelerator 38, as shown in shown, perform several different applications such as signal sampling, signal refreshing and signal monitoring based on the stored information and the configuration ROM.

The goal of this accelerator 38 is to handle the fast processing that cannot be delayed until it can be communicated to the system processor 22 to make a decision about it. Back to : The accelerator 38 is connected to the digital input port controller 25a', the digital output port controller 25a", the ADC 25b' and SPI 25c'. The second module 38 may be configured to make decisions based on complex relationships between different types of pins. The configuration ROM 39 associated with the second module 38 is used to configure the operation of the safety-critical real-time signal processing accelerator 38.

In addition, the control device 21 also comprises a further configuration ROM 40 which is associated with the first module 28b. This configuration ROM 40 serves to configure the operation of the module 28b for the programmable input with wake-up.

The control device 21 comprises a third module 41 for the latched output with PWM support. This third module 41 can generate digital outputs based on data coming from the SPI protocol, in particular from the SPI control protocol accelerator 27c. For certain pre-configured interfaces, some outputs can be latched to ensure that the output is preserved in case of power failure or system reset. Also in case of security issues, the output can be reset to the specified values.

The control device 21 also comprises an SPI port interface 27a for the control connection, in particular for the control interface 27, as previously described. In addition, the control device 21 comprises an SPI controller 27b, which is connected to the host, in this case to the system processor 22, via the SPI port interface 27a. The SPI controller 27b is configured to enable slave operation with a communication speed of up to 60 Mbit/s. In addition, the control device 21 also controls the already mentioned SPI control protocol accelerator 27c, which implements the control protocol to be specified in order to enable communication between the device 21 and the system processor 22. The entire device 21 can thus be controlled and operated from the system processor side via the SPI control protocol. The protocol is defined so that the system processor 22 can communicate with up to four devices simultaneously. The protocol can define various commands that are sent from the main processor 22 to the remote control 21 and from the remote control 21 to the main processor 22.

The control device 21 also includes a security monitor 42 in the form of a fourth module 42. The security monitor 42 monitors the state of each sub-device within the remote control processor 21 and ensures that it is in a secure state. If one of the sub-devices is not in a secure state, it resets the entire device or the specific unit, i.e. the specific sub-device. The security monitor 42 also sends the security state via the security status port 43. The control device 21 also includes a window-triggered watchdog 44 that monitors the security monitor 42. If the security monitor 42 does not refresh the watchdog 44, the watchdog 44 resets the security monitor 42, resulting in the reset of the entire device 21. The controller 21 further includes a temperature monitor 45 for monitoring the temperature status of the device 21 and reporting the status to the security monitor 42. The controller 21 also includes a standalone dedicated watchdog oscillator port 46 for the device's internal watchdog 44. The controller 21 also has a device oscillator port 47 for the device's internal clock system 48. The monitor 42 can also read the status of the temperature monitor 45 to ensure that the chip is operating properly within the required temperature range. The monitor 42 is monitored by the window watchdog 44, which has its own independent external oscillator clock 46. The watchdog cannot be stopped and requires handshaking with the command and counter protocol to be refreshed.

4 shows a schematic representation of a zone control device 20 according to a further embodiment of the invention. In particular, the zone control device 20 and/or the control device 21 can be as described above, in particular with regard to 2 , with the difference that the control device 21 is provided with an additional slave processor, in particular a microcontroller 21b. This microcontroller 21b preferably has a central processor unit, GPIO, in particular for providing the digital input/output interface 25a, ADC 25b, SPI 25c and additional ports for SPI control by the system processor 22, namely for the control interface 27 and the wake-up interfaces 28.

However, it is preferred to provide the control device 21 in the form of an ASIC 21a, since the added value of the ASIC design is that it can flexibly set the required number of pins according to the project requirements. In addition, the cost of an ASIC is likely to be lower than the cost of using a complete microcontroller 21b, given the required number of pins.

The invention and its embodiment thus enable the provision of a standalone programmable FPGA or ASIC controller that extends the number of required digital and analog signals according to the stored configuration. The controller can be programmed via the SPI interface controlling the signal output, update rates, diagnostics and safety reactions. The controller can wake up the zone control device for the wake-up sources and implements critical real-time performance and takes into account the vehicle safety requirements. In addition, the solution defines the control protocol via SPI that is used to efficiently control the ASIC and ensure the safety of the device operation. The remote signal controller can implement all required signal extensions and control logic to ensure that the signal processing meets the required real-time and safety requirements. In this way, a high-speed remote signal control device for a zone control device can be provided, which has the advantages of simplifying the design of the PCB layout and reducing the number of PCB connection pins, of reducing the required cost of the system processor by reducing the expected number of input pins, of reducing the additional cost of the use of additional ICs to handle the wake-up signals and that it is easily configurable and adaptable to specific needs so that it can be optimized in terms of both cost and PCB footprint.

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions.

Cited patent literature

• DE 102020209469 A1 [0003]
• US 20210397178 A1 [0004]

Claims (15)

Control device (21) for a zone control device (20) which has a system processor (22) for controlling external devices of a vehicle, wherein the external devices can be connected to the zone control device (20) via a plurality of first connection elements (35, 35', 35"), characterized in that - the control device (21) is designed as an independent control device (21) different from the system processor (22) of the zone control device (20), - the control device (21) has a first control interface (27) which can be connected to the system processor (22), - the control device (21) is designed to be controlled by the system processor (22) when the system processor (22) is connected to the control interface (27) of the control device (21); and - the control device (21) is designed to control the first connection elements (35, 35', 35") according to the control specifications provided by the system processor (22). steer. Control device (21) according to Claim 1 , characterized in that the control device (21) comprises the first connection elements (35, 35', 35"), in particular first pins (35, 35', 35"), and/or a plurality of second connection elements (35, 35', 35"), in particular second pins (35, 35', 35"), which are connectable or connected to the first connection elements (35, 35', 35"), in particular first pins (35, 35', 35"). Control device (21) according to one of the preceding claims, characterized in that a first group (35'a) of the first and/or second connection elements (35, 35', 35") are designed as multiplexed connection elements (35'a) and the control device (21) has a pin multiplexer (36) and a plurality of first interface modules (25), in particular a digital input port controller (25a'; 25a), a digital output port controller (25a"; 25a) and an analog-digital converter (25b', 25b, 25e), wherein the pin multiplexer (36) is designed to assign each of the multiplexed connection elements (35'a) to one of the plurality of first interface modules (25). Control device (21) according to one of the preceding claims, characterized in that the control device (21) comprises a first memory (37), in particular a port multiplexing and configuration ROM (Read Only Memory) (37), wherein a port multiplexing configuration can be stored or is stored in the first memory (37) and the pin multiplexer (36) is designed to assign one or more of the multiplexed connection elements (35'a) to the first interface modules (25) according to the stored port multiplexing configuration. Control device (21) according to one of the preceding claims, characterized in that a second group (35'b) of the first and/or second connection elements (35', 35") is provided by dedicated SPI (Serial Peripheral Interface) ports (35'b) for controlling SPI devices that can be connected to the SPI ports (35'b), wherein the control device (21) comprises a second interface module (25) in the form of an SPI control module (25c', 25c) that is connected to the SPI ports (35'b) or comprises the SPI ports (35'b), wherein the SPI control module (25c', 25c) comprises one or more SPI controllers. Control device (21) according to one of the preceding claims, characterized in that the control device (21) has a first wake-up port (28a; 28) which can be connected to the system processor (22), wherein the control device (21) has a first module (28b), in particular a module (28b) for a programmable input with wake-up function, wherein the first module (28b) is configured to provide a wake-up signal at the wake-up port (28a) in order to wake up the system processor (22) in response to a signal received from one of the first and/or second connection elements (35', 35") of the first group (35'a). Control device (21) according to one of the preceding claims, characterized in that the control device (21) has a second module (38) for accelerating the safety-critical real-time signal processing and a second memory (39), in particular a configuration ROM (39), which is assigned to the second module (38), wherein the second module (38) is connected to the first interface modules (25) and the SPI control module (25c, 25c') and is designed to carry out certain actions with signals according to a configuration stored in the second memory (39). Control device (21) according to one of the preceding claims, characterized in that the control device (21) comprises a third module (41) for a locked output, which is designed to provide an output signal to one of the first interface modules (25), in particular to the digital output controller (25a"; 25a), depending on a control signal received from the first control interface (27). Control device (21) according to one of the preceding claims, characterized in that the control device (21) comprises a fourth module (42) for safety monitoring, which is designed to determine whether one or more modules of the control device (21) are in a safe state or not, in particular the first interface modules (25), the SPI control module (25c, 25c'), the first module (28b), the second module (38) and the third module (41), and to report a safety status to a safety status port (43) of the control device (21). Control device (21) according to one of the preceding claims, characterized in that the control device (21) is provided in the form of an ASIC (21 a) or FPGA or the control device (21) comprises a microcontroller (21 b). Zone control unit (20) for a vehicle with a control device (21) according to one of the preceding claims. Zone control unit (20) to Claim 11 , characterized in that the zone controller (20) comprises the system processor (22) which is connected to the control device (21). Zone control device (20) according to one of the Claims 11 and 12 , characterized in that the system processor (22) comprises a second wake-up interface (29) connected to the first wake-up interface (28) of the control device (21) and a second control interface (30) connected to the first control interface (27) of the control device (21). Zone control device (20) according to one of the Claims 11 until 13 , characterized in that the zone control device (20) has a power connection board (32) which has at least a part of the first connection elements (35), wherein the system processor (22) is connected to the first connection elements (35) exclusively via the control device (21). Method for operating a zone control device (20) for controlling external devices of a vehicle which can be connected to the zone control device (20) via a plurality of first connection elements (35, 35', 35"), wherein the zone control device (20) comprises a system processor (22) for controlling the external devices, characterized in that - the zone control device (20) comprises a control device (21) which is designed as an independent control device (21) different from the system processor (22) of the zone control device (20), and - the control device (21) has a first control interface (27) which is connected to the system processor (22), - wherein the control device (21) is controlled by the system processor (22), and - the control device (21) controls the first connection elements (35, 35', 35") according to control specifications of the system processor (22).

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