DE102022122793A1 - RADIATION INTERFACE TEST WITH QUANTIZATION AND INTERVAL REPRESENTATIONS - Google Patents

Abstract

Techniques for primitive interface tests for ray tracing in graphics processors are disclosed. In some embodiments, a graphics processor includes ray interface circuitry configured to perform an interface test that includes: quantizing a first representation of the primitive to generate a reduced-precision interval representation of the primitive, quantizing a first representation of the ray, to generate an interval representation of the ray with reduced precision, and determining, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray. The initial intersection result may be a conservative result, such that a miss indicated by the initial intersection result is guaranteed to be a no-hit for the first representation of the primitive and the first representation of the ray. The disclosed techniques may improve performance, reduce power consumption, or both compared to conventional techniques.

Description

BACKGROUND

technical field

This disclosure relates generally to graphics processors and more particularly to primitive interface tests for ray tracing.

Description of the prior art

In computer graphics, ray tracing is a rendering technique used to create an image by tracing the path of light in the form of pixels in an image plane and simulating the effects of encounters with virtual objects. Ray tracing can enable visibility resolution in three dimensions between any two points in the scene, which is also the source of most of the computational effort. A common ray tracer scans the light's path through the scene in the reverse direction of light propagation, i. H. emanating from the camera and into the scene, rather than from the light sources (sometimes referred to as "backward ray tracing"). Going out from the camera has the advantage of only tracing rays that are visible to the camera. This system can model a rasterizer where rays simply stop at the first surface and call a shader (analogous to a fragment shader) to compute a color. Secondary impacts are more commonly modelled, i. H. the exchange of light between scene elements, such as diffuse interreflection and transmission. Shaders that evaluate the reflectance properties of surfaces can perform additional intersection queries (e.g. create new rays) to capture the lighting coming from other surfaces. This recursive process has many phrasings, but is commonly referred to as path tracing.

Graphics processors that implement ray tracing typically provide more realistic scenes and lighting effects than traditional rasterization systems. However, ray tracing is usually very computationally intensive. Improvements in ray tracing techniques can increase the realism of graphics scenes, improve performance (e.g. tracing more rays per frame, tracing in more complex scenes, or both), reduce power consumption (which can be especially important in battery-powered devices), etc.

The interrogation of ray intersections can be performed by shaders, by dedicated hardware, or by a combination of both. Different types of intersection queries can provide different types of information. For example, a "nearest hit" query can locate the closest intersected geometry along a ray and within the parametric interval that the ray is valid (this is probably the most common type of query). An "any hit" query can indicate whether there is intersected geometry along the ray and within the parametric interval. This type of query can be used for shadow rays, for example, to determine whether a point in the scene is visible to the light or is obscured. Once the intersected geometry has been determined, this geometry can be shaded based on the intersection points, which in turn can generate further rays for interface testing, e.g. B. from reflective surfaces.

Motion blur is a phenomenon that occurs when the captured image changes during the capture of a single exposure. For example, a photograph of a moving freight train with a sufficiently long exposure time can show the train out of focus while not blurring out non-moving objects. In the context of computer graphics, a graphics processor can simulate the effect of motion blur on an image of the graphics data. In this context, an animated graphics primitive (e.g., a triangle) can be modeled with multiple different positions during a virtual camera's open shutter interval (also referred to herein as a motion blur interval), thus affecting pixel values at the multiple positions in the image to create a blurring effect cause.

Each ray is usually assigned an accurate time stamp, e.g. B. within a motion blur interval. When both ray tracing and motion blur are implemented, testing for ray/primitive intersections can be costly in terms of processor resources and power consumption.

character list

• 1A 12 is a diagram illustrating an overview of example graphics processing operations, according to some embodiments.
• 1B 10 is a block diagram illustrating an example graphics unit, according to some embodiments.
• 2A 14 is a block diagram illustrating example low-precision test circuitry, according to some embodiments.
• 2 B 12 is a block diagram illustrating an example interface testing technique, according to some embodiments.
• 3 14 is a diagram illustrating example interval plots for various values used in an initial interface test, according to some embodiments.
• 4 12 is a diagram illustrating example interpolation circuitry configured to generate an interval representation of an interpolated primitive in a motion blur interval, according to some embodiments.
• 5 12 is a block diagram illustrating example shear factor circuitry configured to generate shear factor intervals, in accordance with some embodiments.
• 6 14 is a diagram illustrating example switching logic configured to translate and shear vertices using shear factor intervals, in accordance with some embodiments.
• 7 12 is a diagram illustrating example circuitry configured to generate an initial interface test result, in accordance with some embodiments.
• 8th 12 is a diagram illustrating example circuitry for generating a modified interval product, in accordance with some embodiments.
• 9 12 is a diagram illustrating example processing circuitry for triangle pairs and sequential pairs, according to some embodiments.
• 10 12 is a diagram illustrating an example of the boundaries of a quantized primitive representation and a unique hit region, according to some embodiments.
• 11 12 is a diagram illustrating example test circuitry configured to produce a hit or an ambiguous output, according to some embodiments.
• 12 12 is a diagram illustrating example circuitry configured to generate an initial interface test result, in accordance with some embodiments.
• 13 12 is a diagram illustrating example test primitive sequences in various orders, including a center-outer order, according to some embodiments.
• 14 10 is a flow chart illustrating an example method, according to some embodiments.
• 15 12 is a flow chart illustrating another example method, according to some embodiments.
• 16 10 is a block diagram illustrating an example computing device, according to some embodiments.
• 17 12 is a diagram illustrating example applications of disclosed systems and devices, according to some embodiments.
• 18 12 is a block diagram illustrating an example computer-readable medium storing circuit design information, according to some embodiments.

DETAILED DESCRIPTION

In disclosed embodiments, a lower precision hardware triangle test is performed first than filter, and a higher precision triangle test is performed when the test with less accuracy results in a potential hit. This low-precision test can be conservative (e.g., it can result in false hits, but should not result in false misses). US Pat. note
No. 17/136,542 , filed December 29, 2020, entitled Primitive Testing for Ray Intersection at Multiple Precisions, is incorporated herein by reference in its entirety. The '542 application describes example techniques with testing at different precisions and how potential errors due to quantization of the inputs can be tracked with reduced precision throughout the test to ensure that the results are conservative.

The present disclosure uses interval arithmetic to track and limit potential quantization errors for a primitive hardware test that uses quantization of one or more inputs. In some embodiments, the disclosed techniques may advantageously provide tighter error bounds than the embodiments of the '542 application. Furthermore, in some implementations, the disclosed techniques may use less circuit area for performing primitive tests with a certain accuracy.

Furthermore, the disclosed embodiments described in detail below generate an interpolated spatial coordinate interval to represent a moving triangle for a conservative interface test for a given beam time in a motion blur interval. Furthermore, the disclosed techniques provide efficient encoding and processing techniques for moving and non-moving triangle pairs.

Further, the disclosed techniques may provide definitive hit results using a lower accuracy interface test without performing an original accuracy interface test (e.g., for "any hit" rays).

Finally, the traversal ordering techniques disclosed for an acceleration data structure (e.g., "center-outer" ordering rather than front-to-back or back-to-front) may improve performance, reduce power consumption, or both for traversing certain types of beams.

Graphics processing overview

With reference to 1A 1 is a flowchart illustrating an example processing flow 100 for processing graphics data. In some embodiments, the transformation and lighting procedure 110 may include processing lighting information for vertices received from an application based on defined light source locations, reflectance, etc., assembling the vertices into polygons (e.g., triangles), and transforming of polygons to the correct size and orientation based on position in three-dimensional space. The clipping procedure 115 may include discarding polygons or vertices that fall outside of a visible area. The rasterization procedure 120 may involve defining fragments within each polygon and assigning initial color values for each fragment, e.g. B. based on the texture coordinates of the vertices of the polygon. Fragments can specify attributes for pixels that they overlap, but the actual pixel attributes can be based on combining multiple fragments (e.g. in a framebuffer), ignoring one or more fragments (e.g. if they are obscured by other objects be determined) or both. The shading procedure 130 may involve changing pixel components based on lighting, shadows, bump mapping, translucency, and so on. The shaded pixels can be collected in a frame buffer 135 . Modern GPUs typically include programmable shaders that allow application developers to customize shading and other processing steps. Thus, in various embodiments, the exemplary elements of FIG 1A performed in different orders, performed in parallel, or omitted. Additional processing procedures can also be performed.

Referring now to 1B 1 is a simplified block diagram illustrating a graphics unit 150, in accordance with some embodiments. In the illustrated embodiment, the graphics unit 150 includes a programmable shader 160, a vertex pipe 185, a fragment pipe 175, a texture processing unit (TPU) 165, an image writing unit 170, and a memory interface 180. In some embodiments, the graphics engine 150 is configured to process both vertex and fragment data using the programmable shader 160 that configures to process graphics data in parallel using multiple execution pipelines or instances.

Vertex pipe 185 in the illustrated embodiment may include various fixed-function hardware configured to process vertex data. Vertex pipe 185 may be configured to communicate with programmable shader 160 to coordinate vertex processing. In the illustrated embodiment, vertex pipe 185 is configured to send processed data to fragment pipe 175 or programmable shader 160 for further processing.

The fragment pipe 175 in the illustrated embodiment may include various fixed function hardware configured to process pixel data. Fragment pipe 175 may be configured to communicate with programmable shader 160 to coordinate fragment processing. Fragment pipe 175 may be configured to perform rasterization on polygons from vertex pipe 185 or programmable shader 160 to generate fragment data. Vertex pipe 185 and fragment pipe 175 may be coupled to memory interface 180 (coupling not shown) to access graphics data.

Programmable shader 160 is configured in the illustrated embodiment to receive vertex data from vertex pipe 185 and fragment data from fragment pipe 175 and TPU 165 . The programmable shader 160 may be configured to perform vertex processing tasks on vertex data, which may include various transformations and adjustments of vertex data. The programmable shader 160 in the illustrated embodiment is also configured to perform fragment processing tasks on pixel data, such as texturing and shading. The programmable shader 160 may include multiple sets of multiple execution pipelines for processing data in parallel.

In some embodiments, the programmable shader includes pipelines configured to execute one or more different SIMD groups in parallel. Each pipeline can include various stages that are configured to perform operations such as fetch, decode, issue, execute, etc. in a given clock cycle. The concept of a processor "pipeline" is well known and refers to the concept of dividing the "work" that a processor performs on instructions into multiple stages. In some embodiments, instruction decode, dispatch, execution (i.e., power), and retire may be examples of different pipeline stages. Many different pipeline architectures with different ordering of elements/sections are possible. Various pipeline stages perform such steps on an instruction during one or more processor clock cycles and then forward the instruction or operations associated with the instruction to other stages for further processing.

The term "SIMD group" should be understood in its generic sense, which includes a set of threads in which the processing hardware processes the same instruction in parallel using different input data for the different threads. Various types of computer processors may include sets of pipelines configured to execute SIMD instructions. For example, graphics processors often include programmable shader cores that are configured to execute instructions for a set of related threads in a SIMD manner. Other examples of names that can be used for a SIMD group include: a wavefront, a clique, or a warp. A SIMD group can be part of a larger thread group, which can be divided into multiple SIMD groups depending on a computer's parallel processing capabilities. In some embodiments, each thread is assigned a hardware pipeline that fetches operands for that thread and performs the specified operations in parallel with other pipelines for the set of threads. It should be noted that processors can have a large number of pipelines, so several separate SIMD groups can also be executed in parallel. In some embodiments, each thread has private operand storage, e.g. B. in a register file. Thus, reading a particular register from the register file can provide the version of the register for each thread in a SIMD group.

In some embodiments, multiple programmable shader units 160 are included in a GPU. In these embodiments, the global control circuitry can assign work to the various subsections of the GPU, which in turn can assign work to the shader cores to be processed by shader pipelines.

The TPU 165 in the illustrated embodiment is configured to schedule fragment processing tasks from the programmable shader 160 . In some embodiments, TPU 165 is configured to prefetch texture data and assign initial colors to fragments for further processing by programmable shader 160 (e.g., via memory interface 180). The TPU 165 may be configured to provide fragment components in normalized integer formats or floating point formats, for example. In some embodiments, the TPU 165 is configured to provide fragments in groups of four (a “fragment quad”) in a 2x2 format for processing by a group of four execution pipelines in the programmable shader 160 .

The Image Write Unit (IWU) 170 is configured in some embodiments to store processed tiles of an image and may perform operations on a rendered image before it is transferred for display or to memory for storage. In some embodiments, graphics engine 150 is configured to perform tile-based deferred rendering (TBDR). With tile-based rendering, different sections of screen space (e.g., squares or rectangles of pixels) can be processed separately. The memory interface 180, in various embodiments, may facilitate communications with one or more of various memory hierarchies.

In the illustrated example, graphics engine 150 includes ray intersection accelerator (RIA) 190, which may include hardware for performing various ray intersection operations, as described in detail below.

Overview of the interval-based interface test

2A 12 is a block diagram illustrating example quantization circuitry and circuitry for low precision interface tests, according to some embodiments. In the illustrated embodiment, a graphics processor includes test circuitry 220 .

In some embodiments, the quantization circuitry is configured to quantize ray data and generate interval representations of the quantized values. In various embodiments, the upper and lower bounds of the generated intervals are represented with less precision than the input representation, but the interval is guaranteed to cover the initial value with the input precision. Note that the primitive data can also be stored in a quantized interval format (e.g. in an acceleration data structure).

The low precision interval arithmetic based test circuitry 220 is configured in the illustrated embodiment to produce a conservative intersection result by performing interval arithmetic on the interval representations. The conservative cut result can guarantee that a failure signaled by the circuitry 220 will not result in a hit on an interface test with higher precision (e.g. on values with the input precision before quantization). A positive output of switching logic 220 indicates a potential hit in these embodiments.

In various embodiments, performing initial interface tests with less accuracy may advantageously improve performance, reduce power consumption, or both compared to traditional techniques. In particular, failures or definite hits generated by the initial test can avoid the need to perform a higher accuracy test for a particular ray and primitive. Therefore, both improving the accuracy of the test (e.g. by tightening the error limits) and improving the performance or power consumption of the initial test itself can have technical benefits.

2 B 12 is a flow chart illustrating a high-level example of an interface testing technique, according to some embodiments. In the illustrated embodiment, element 210 converts the ray direction to a lower precision floating point interval representation. Element 230 determines the shear factors based on a quantization frame transform (used for quantization of vertices, as discussed in detail below), and element 244 converts the shear factors into a fixed point interval representation.

Element 242 generates a fixed point interval representation for the ray origin, also based on the quantization frame transform. Element 246 creates a fixed point interval representation of the beamtime. For motion blur processing, element 250 temporally interpolates the quantized vertices of the triangle based on the ray time (this element can be omitted or pass the quantized vertices of the triangle directly if no motion blur operations are performed). Element 260 transforms the vertices according to the shear factors and ray origin, and element 270 evaluates the edge equations to determine whether it is a miss or a potential hit. Different items from 2 B are explained in more detail below. The specific operations in 2 B are included for illustration and are not intended to limit the scope of the present disclosure. However, in some embodiments, the described operations may advantageously provide tight intervals with reasonable circuit area and power consumption.

Example of quantized interval plots of interface test values

3 14 is a diagram illustrating example interval plots for various values used in an initial interface test, according to some embodiments. In the illustrated example, intervals are generated for vertex positions, ray origin, direction and time, shear factors, and interpolated vertices of the triangle. Note that these specific interval values are discussed for illustrative purposes, but are not intended to limit the scope of the present disclosure. In other embodiments, each of the various values used in determining an initial interface result may be represented by intervals.

In the illustrated embodiment, for each quantized vertex position (e.g., for each of the three vertices of a triangle), three corresponding intervals are determined for the X dimension, the Y dimension, and the Z dimension. Similar intervals are determined for the ray origin and the ray direction. In some embodiments that support motion blur, an upper and lower bound for the beam time is also set.

In some embodiments where shear is used as part of the ray triangle interface test, upper and lower bounds are determined for two shear factors in the non-dominant coordinate directions for the ray.

In some embodiments that support motion blur, the graphics processor determines, for each vertex, X, Y, and Z intervals for an interpolated triangle that corresponds to the beam time within a motion blur interval. 4 is discussed in detail below and provides exemplary techniques for generating an interval representation of an interpolated triangle. In general, more detailed techniques for determining various specific intervals are discussed in detail below.

As explained in more detail below, the data structures may represent triangles, moving triangles, triangle pairs, moving triangle pairs, or a combination thereof. In some embodiments, a triangle with three vertices, a moving triangle with six vertices, a triangle pair with four vertices, and a moving triangle pair with eight vertices are presented.

In some embodiments, quantized triangle coordinates are stored as unsigned integer values with limited fixed-point precision and are rounded toward zero. These coordinates may correspond to a local coordinate system stored in an acceleration data structure ADS, e.g. e.g., as described in the '542 application. Quantized values can be N-bit values. In some embodiments, each coordinate value uses a number of bits that facilitate packing into an array of a particular size. For example, 7-bit values per quantized coordinate interval value for a single triangle can be packed into two 64-bit fields (x top/bottom, y top/bottom, and z top/bottom 7-bit values for each vertex given three vertices = 126 Bit). In other embodiments, fixed-point encodings with various suitable numbers of bits can be used. In some embodiments, unsigned values are translated into a new coordinate frame in which the values become signed integers. Note that in some situations only one boundary of an interval may be stored and the other boundary may be implied. This can reduce memory requirements for certain parts of the processor.

Im Allgemeinen beziehen sich die hierin erwähnten Mengen auf Intervalle.In this context, if p is a quantized value for a triangular coordinate, the interval that represents that coordinate in local quantized coordinate space is, p = [p, p + δp], where δp represents a unit of least precision (ULP) in quantized format in some embodiments. The original coordinate value before quantization is guaranteed to be within this interval. For an N-bit fixed-point representation, $\delta p=\frac{1}{2^N}.$

In general, the quantities mentioned herein refer to intervals.

Therefore, a given non-moving triangle can be encoded with nine values (three vertices with three coordinate lower bounds for each vertex, where the upper bound is implicitly greater than the lower bound by one ULP).

In some embodiments, moving triangles are stored as two (or more) sets of coordinates, e.g. B. a position p(0) at time t=0 and a position p(1) at time t=1. This can define an interval of linear motion in the normalized time interval [0,1]. Note that multiple linear motions in subintervals can also be used to encode non-linear motions over a larger motion blur interval. In this case, a moving triangle can enclose more than two sets of coordinates. A moving triangular coordinate at time t can be divided by the interval p (t) = [p(t), p(t) + δp] can be represented.

In some embodiments, the beam time is scaled to a lower accuracy interval as part of the low accuracy interface test t = [t, t + δt] quantized, where t is encoded with M bits of sub-interval resolution (e.g. implicit setting of 1.0 at ^2M ). M may or may not match the number of bits N used to represent the spatial coordinates of the triangle (or the number of bits used to represent the spatial coordinates of the ray). As with other quantized intervals, the original high-precision value is guaranteed to be found within the lower-precision interval. In some embodiments, time is a fourth coordinate axis that is independent of other coordinates such as x, y, and z.

Interval-based motion blur processing example

In some embodiments, the interval interpolation circuitry is configured to calculate conservative spatial intervals for moving triangular coordinates over the quantized temporal interval t of a ray reconstructed. 4 12 is a block diagram illustrating an example of interpolation circuitry configured to generate an interval representation of an interpolated primitive within a motion blur interval, according to some embodiments. Switching logic 410 may be as described above with reference to element 250 in FIG 2 B perform the operations described.

In the illustrated embodiment, the interpolation circuitry 410 is configured to receive a beam time interval representation and a moving triangle interval representation (e.g., x, y, and z intervals for each of the six vertices) and an interpolated triangle interval representation (e.g. x, y and z intervals for each of the three vertices).

As an example, the circuitry 410 may determine the interpolated spatial coordinate interval as follows: $$\overline{p\left(\overline{t}\right)}=\overline{p\left(0\right)}\left(1.0-\overline{t}\right)+\overline{p\left(0\right)}\overline{t}$$

bestimmen, das garantiert das quantisierte Zeitintervall [t, t + δt] für jedes t ∈ [0,1 - δt] abdeckt: $$\overline{p\left(\overline{t}\right)}=\left[z,z+2\delta p\right]$$

wobei $$z=p^0\left(1-t-\delta t\right)+p^{1}t$$

Using the notation p ⁰ =p(0) and p ¹ =p(1), switching logic 410 can calculate an interpolated position coordinate interval $\overline{p\left(\overline{t}\right)}$

determine that is guaranteed to cover the quantized time interval [t, t + δt] for any t ∈ [0,1 - δt]: $$\overline{p\left(\overline{t}\right)}=\left[\mathrm{e.g},\mathrm{e.g}+2\delta p\right]$$

whereby $$\mathrm{e.g}=p^0\left(1-t-\delta t\right)+p^{1}t$$

This equation can provide a good fit with reasonable performance and circuit area in various embodiments. Furthermore, it has been determined that the interval provided by this equation is conservative.

gemäß dieser Gleichung bestimmt. Es ist zu beachten, dass in anderen Ausführungsformen andere Gleichungen durch die Computerschaltlogik implementiert werden können, um konservative interpolierte Dreiecksintervalle zu bestimmen; die offenbarten Gleichungen sind zur Veranschaulichung eingeschlossen, sollen aber den Schutzumfang der vorliegenden Offenbarung nicht einschränken.In some embodiments, the switching logic 410 is configured to determine the interval $\overline{p\left(\overline{t}\right)}$

determined according to this equation. Note that in other embodiments, other equations may be implemented by the computer circuitry to determine conservative interpolated triangle intervals; the disclosed equations are included for illustration but are not intended to limit the scope of the present disclosure.

In various embodiments, the interpolated triangle interval may be tested using an initial interface test with low accuracy, at least in motion blur modes of operation. Therefore, various primitive inputs discussed below can apply to a conventional triangle or to an interpolated triangle, e.g. B. depending on whether motion blur is used. Also, while various techniques discussed herein use interval arithmetic; disclosed interpolated triangle techniques for motion blur can also be used with other quantized representations and techniques, e.g. B. with the techniques of the application '542.

Example of shear factor determination

P

Strahlursprung, Gleitkommaobjektraum

p

Strahlursprung, Festkommaquantisierungsraum

D

Strahlrichtung, Gleitkommaobjektraum

vv

Dreiecks-Eckpunktkoordinaten, Festkommaquantisierungsraum

As discussed in the '542 application, shearing techniques can be used to perform an interface test. The following naming conventions are used in the following discussion:

P

Ray origin, floating point object space

p

Ray origin, fixed point quantization space

D

Ray direction, floating point object space

vv

Triangle vertex coordinates, fixed point quantization space

In some embodiments, the transformation to sheared 2D space is given by: $$\left[\begin{array}{c}{v}_x^{\text{'}}\\ v_y^{\text{'}}\end{array}\right]=\left[\begin{array}{cccc}1& 0& -\frac{{\mathrm{i.e}}_x}{{\mathrm{i.e}}_{\mathrm{e.g}}}& 0\\ 0& 1& -\frac{{\mathrm{i.e}}_y}{{\mathrm{i.e}}_{\mathrm{e.g}}}& 0\end{array}\right]\left[\begin{array}{cccc}1& 0& 0& -{\mathrm{<figure-callout\; id="0"\; label="p\; x"\; filenames="DE102022122793A1\_0043.png,DE102022122793A1\_0045.png"\; state="\{\{state\}\}">p</figure-callout>}}_x\\ 0& 1& 0& -{\mathrm{<figure-callout\; id="0"\; label="p\; y"\; filenames="DE102022122793A1\_0043.png,DE102022122793A1\_0045.png"\; state="\{\{state\}\}">p</figure-callout>}}_y\\ 0& 0& 1& -p_{\mathrm{e.g}}\\ 0& 0& 0& 1\end{array}\right]\left[\begin{array}{c}{v}_x\\ v_y\\ v_{\mathrm{e.g}}\\ 1\end{array}\right]=\left[\begin{array}{c}\left(v_x-p_x\right)-\frac{{\mathrm{i.e}}_x}{{\mathrm{i.e}}_{\mathrm{e.g}}}\left(v_{\mathrm{e.g}}-p_{\mathrm{e.g}}\right)\\ \left(v_y-p_y\right)-\frac{{\mathrm{i.e}}_y}{{\mathrm{i.e}}_{\mathrm{e.g}}}\left(v_{\mathrm{e.g}}-p_{\mathrm{e.g}}\right)\end{array}\right]$$

$$d_i=\frac{D_i}{S_i}\forall i\in \left\{x,y,z\right\}$$

In order to be able to perform these calculations with fixed-point arithmetic, the device can convert the ray quantities P and D from the object space into the quantization space p and d as follows: $$p=\frac{p_{v,i}-N_i}{S_i}=\frac{\left(P_i+v{D}_i\right)-N_i}{S_i}\forall i\in \left\{x,y,\mathrm{e.g}\right\}$$

$${\mathrm{i.e}}_i=\frac{D_i}{S_i}\forall i\in \left\{x,y,\mathrm{e.g}\right\}$$

Before proceeding further, the device can determine which axis of the scaled beam direction has the greatest magnitude and rotate the axis names so that the longest axis is in the third ("z") position. Furthermore, if this directional component is negative, the device can swap the other two axes to preserve handedness. For the following discussions it is assumed that this renaming has been applied to all Cartesian quantities.

Back-substitution in Equation 1 and simplification gives: $$\left[\begin{array}{c}{v}_x^{\text{'}}\\ v_y^{\text{'}}\end{array}\right]=\left[\begin{array}{c}\left(v_x-p_x\right)-\frac{{\mathrm{i.e}}_x}{{\mathrm{i.e}}_{\mathrm{e.g}}}\left(v_{\mathrm{e.g}}-p_{\mathrm{e.g}}\right)\\ \left(v_y-p_y\right)-\frac{{\mathrm{i.e}}_y}{{\mathrm{i.e}}_{\mathrm{e.g}}}\left(v_{\mathrm{e.g}}-p_{\mathrm{e.g}}\right)\end{array}\right]=\left[\begin{array}{c}\left(v_x-\frac{\left(P_x+t{D}_x\right)-N_x}{S_x}\right)-\frac{D_x{S}_{\mathrm{e.g}}}{D_{\mathrm{e.g}}{S}_x}\left(v_{\mathrm{e.g}}-\frac{\left(P_{\mathrm{e.g}}+t{D}_{\mathrm{e.g}}\right)-N_{\mathrm{e.g}}}{S_{\mathrm{e.g}}}\right)\\ \left(v_y-\frac{\left(P_y+t{D}_y\right)-N_y}{S_y}\right)-\frac{D_y{S}_{\mathrm{e.g}}}{D_{\mathrm{e.g}}{S}_y}\left(v_{\mathrm{e.g}}-\frac{\left(P_{\mathrm{e.g}}+t{D}_{\mathrm{e.g}}\right)-N_{\mathrm{e.g}}}{S_{\mathrm{e.g}}}\right)\end{array}\right]$$

$$v=B_x^{\text{'}}\cdot C_y^{\text{'}}-B_y^{\text{'}}\cdot C_x^{\text{'}}$$

$$w=C_x^{\text{'}}\cdot A_y^{\text{'}}-C_y^{\text{'}}\cdot A_x^{\text{'}}$$

In the context of the disclosed interval techniques, the various values represented in Equation 4 are interval representations, as explained above. In 2D shear space, the beam position reduces to the origin of this coordinate frame, its direction aligned with the z-axis which the device points towards the three directed edges of the 2D triangle defined by the three sheared coordinates v' ∈ {A', B', C'} can be checked as follows: $$\mathrm{and}=A_x^{\text{'}}\cdot B_y^{\text{'}}-A_y^{\text{'}}\cdot B_x^{\text{'}}$$

$$v=B_x^{\text{'}}\cdot C_y^{\text{'}}-B_y^{\text{'}}\cdot C_x^{\text{'}}$$

$$w=C_x^{\text{'}}\cdot A_y^{\text{'}}-C_y^{\text{'}}\cdot A_x^{\text{'}}$$

If all of u, v, w have the same sign, then the triangle covers the origin and the ray intersects the triangle with numerical precision.

5 12 is a block diagram illustrating example shear factor circuitry configured to generate shear factor intervals, in accordance with some embodiments. In the illustrated embodiment, the shear factor circuitry (which may be included in the low precision test circuitry 220) includes down conversion circuits 5 10A-5 10C, subtraction circuits 520A-520B, reciprocal circuits 530, interval product and scale matching circuits 540A-540B, and floating point to fixed point interval conversion circuits 550A-550B a. In some embodiments, the circuitry implements FIG 5 the functionality of element 230 of 2 B .

The down conversion circuitry 510 is configured in the illustrated embodiment to convert the x, y, and z directions (after rotation so that the longest axis is the z direction) to a reduced precision floating point interval representation. In some embodiments, the downconversion rounds towards negative infinity (RTNI) to generate the lower interval boundary and rounds towards positive infinity (RTPI) to generate the upper interval boundary.

The subtraction circuits 520 are each configured in the illustrated embodiment to subtract the x- and y-scale values from the z-scale value to produce unsigned division results for S _z /S _x and S _z /S _y in an unsigned integer representation . In some embodiments, the scale values are powers of two, such that subtracting the exponents is equivalent to dividing. These scale factors can be determined based on the quantization framework for the primitive. In general, a set of quantized values can share a "quantization frame" that defines the parameters for the values. In some embodiments, the quantized values are represented as fixed-point offsets relative to a common origin and scale factor. Therefore, the quantization frame can specify the origin (e.g., in x, y, and z coordinates) and scale factors (e.g., as a power of 2 scale factors for each of the z, y, and z dimensions). The quantized primitive intervals discussed herein can be represented with fixed-point coordinates that are interpreted in the context of the quantization framework. Note that the outputs of the circuits 520 are not intervals in the illustrated example.

The reciprocal circuit 530 is configured in the illustrated embodiment to generate a reciprocal of the down-converted z-direction value.

Interval product circuits and scale matching circuits 540 are configured in the illustrated embodiment to provide a

perform interval product operations on their inputs to produce outputs in a reduced precision floating point interval format. In some embodiments, the circuits 540 are configured to limit their outputs to the range [-1, 1]. In some embodiments circuits 540 also apply the scaling from circuits 520 by using exponent adjustment to multiply by a power of two.

The floating point to fixed point interval conversion circuits 550 are configured in the illustrated embodiment to convert the reduced precision floating point interval representations to fixed point interval representations for the shear factors D _x S _z /D _{z S x} and D _y S _z /D _z S _y (which in the switching logic of 6 entered, which is explained below).

6 14 is a diagram illustrating example switching logic configured to translate and shear vertices using shear factor intervals, in accordance with some embodiments. In 6 For example, the operations of equation (4) above can be performed using interval arithmetic. In 6 the above with reference to element 260 in 2 B described operations are performed. In the illustrated embodiment, the circuitry receives vertex and ray position data in interval form and is configured to perform interval subtraction and multiplication operations to obtain translated and sheared vertices using the circuitry generated by the circuitry of FIG 5 generated shear factor intervals. In some embodiments, each of the outputs from 6 an interval whose lower bound with a minus sign (e.g. a _y- ) and whose upper bound with a plus sign (e.g. a _y+ ) in 7 can be displayed.

da nur das Vorzeichen erforderlich ist. Zweitens führt die Schaltlogik in 7 doppelt so viele Multiplikationen durch, in der veranschaulichten Ausführungsform, um einen konservativen Test bereitzustellen (z. B. wird nur der „äußere“ Teil des Kantenintervalls berücksichtigt), aber die Schaltlogik weiß nicht, welcher Weg „außen“ ist, da sie die im oder gegen den Uhrzeigersinn liegende Seite des Dreiecks berücksichtigen kann. Schaltungen 710 sind so konfiguriert, dass sie ein modifiziertes Intervallprodukt erzeugen, und werden im Folgenden unter Bezugnahme auf 8 näher erläutert. 7 12 is a block diagram illustrating example circuitry configured to perform an initial reduced fidelity interface test, according to some embodiments. In some embodiments, the circuitry implements FIG 7 the functionality of the element 270 of 2 B . For example can 7 Perform operations corresponding to the above equations for u, v, w to, based on the outputs of 6 to produce a cutting result. It should be noted that the switching logic in 7 has some differences to these equations. First, this circuitry performs a comparison rather than a subtraction $\left(\text{e.g}.\text{B}.A_x^{\text{'}}\cdot B_y^{\text{'}}<A_y^{\text{'}}\cdot B_x^{\text{'}}\text{instead of}{A}_x^{\text{'}}\cdot B_y^{\text{'}}-A_y^{\text{'}}\cdot B_x^{\text{'}}\right),$

since only the sign is required. Second, the switching logic in 7 performs twice as many multiplications, in the illustrated embodiment, to provide a conservative test (e.g. only the "outside" part of the edge interval is considered), but the switching logic does not know which path is "outside" since it uses the in or counterclockwise side of the triangle. Circuits 710 are configured to generate a modified interval product and are described below with reference to FIG 8th explained in more detail.

In the 7 The AND and OR logic illustrated provides a result indicating whether the reduced accuracy test yields a clear failure. As shown, the six two-tailed edge tests can use 12 multipliers and 6 comparators, all in fixed-point form. Note that different circuitry can be combined or merged, for example adders and subtractors can be implemented by a single component performing both operations in parallel, and multipliers and comparators can be merged to form a single ab<=cd operation to implement.

As mentioned earlier, the processor can perform a higher precision interface test (e.g. using the original floating point representation) when the result is ambiguous (a potential hit).

Example of a modified interval product

• [x₁,x₂] - [y_1,y₂] = [min(x₁y₁, x₁, y₂, x₂, y₁, x₂y₂), max(x₁y₁, x₁y_2, x₂y₁, x₂y₂))]. In einigen Ausführungsformen wird das Intervallprodukt mit zwei Multiplikatoren realisiert. Um das Vorzeichen der Intervallsummenprodukte vollständig aufzulösen, müssen wir das Vorzeichen der beiden Endpunkte jedes Intervallprodukts genau auflösen. Dies ist mit nur zwei Multiplikatoren pro Intervallprodukt möglich, es sei denn, die beiden Intervalleingänge des Intervallprodukts umfassen den Ursprung. In diesem Fall kann die Hardware eine Ausnahme auslösen, und der Schnittstellentest kann einen möglichen Treffer aufzeichnen. Empirische Daten zeigen, dass dieser Ausnahmefall bei üblichen Arbeitsbelastungen selten ist. Codeliste 1 implementiert ein modifiziertes vorzeichenbehaftetes Intervallprodukt unter Verwendung von nur zwei Hardware-Multiplikatoren.

 // Start von Codeliste 1: Modifiziertes vorzeichenbehaftetes
 Intervallprodukt
 template <typename T>
 struct Interval {
  T lower, upper;
  inline Interval (const T& 1, const T& u) : lower(1), upper(u) {}
  };
  // T wird als ganze Zahl mit Vorzeichen angenommen (int8_t, int16_t, int32_t, int64_t)
  // Ausnahme wird ausgelöst, wenn vier Multiplikatoren zur Auflösung benötigt werden
  // das Vorzeichen der beiden Endpunkte des Intervalls - in allen anderen Fällen sind die Vorzeichen
  // vollständig aufgelöst.
  template <typename T>
  Interval<T> intervalProduct (Interval<T> a, Interval<T> b, bool& exception) {
  uint8_t bit0_AB = a.upper >= 0;
  uint8_t bit1_AB = a.lower >= 0;
  uint8_t bit2_AB = b.upper >= 0;
  uint8_t bit3_AB = b.lower >= 0;
  uint8_t code_AB = (bit3_AB << 3) | (bit2_AB << 2) | (bit1_AB << 1)
      | bit0_AB;
  Interval<T> p = { 0, 0 };
  switch (code_AB) {
      case 0xf: p.upper = a.upper * b.upper; p.lower = a.lower *
             b.lower; break; 
      case 0xd: p.upper = a.upper * b.upper; p.lower = a.lower *
             b.upper; break;
      case 0xc: p.upper = a.upper * b.lower; p.lower = a.lower *
             b.upper; break;
      case 0x7: p.upper = a.upper * b.upper; p.lower = a.upper *
             b.lower; break;
      case 0x5:
         p.upper = std::numeric_limits<T>::max();
         p.lower = std::numeric_limits<T>::lowest();
         exception = true;
         break; // failure case - too close to call, need 4 multipliers
      case 0x4: p.upper = a.lower * b.lower; p.lower = a.lower *
             b.upper; break;
      case 0x3: p.upper = a.lower * b.upper; p.lower = a.upper *
             b.lower; break;
      case 0x1: p.upper = a.lower * b.lower; p.lower = a.upper *
             b.lower; break;
      case 0x0: p.upper = a.lower * b.lower; p.lower = a.upper *
             b.upper; break;
  }
  }return p;
 }

Typically, a signed interval product requires four multipliers, as defined as follows:

• [x ₁ ,x ₂ ] - [y _1, y ₂ ] = [min(x ₁ y ₁ , x ₁ , y ₂ , x ₂ , y ₁ , x ₂ y ₂ ), max(x ₁ y ₁ , x ₁ y _2, x ₂ y ₁ , x ₂ y ₂ ))]. In some embodiments, the interval product is implemented with two multipliers. To fully resolve the sign of the interval sum products, we must accurately resolve the sign of the two endpoints of each interval product. This is possible with only two multipliers per interval product, unless the two interval inputs of the interval product include the origin. In this case, the hardware can throw an exception and the interface test can record a possible hit. Empirical data shows that this exceptional case is rare in normal workloads. Code List 1 implements a modified signed interval product using only two hardware multipliers.

 // Start of code list 1: Modified signed
 interval product
 template <typename T>
 struct Interval {
  T lower, upper;
  inline Interval (const T& 1, const T& u) : lower(1), upper(u) {}
  };
  // T is assumed to be a signed integer (int8_t, int16_t, int32_t, int64_t)
  // Exception thrown when four multipliers are needed to resolve
  // the sign of the two end points of the interval - in all other cases are the signs
  // fully resolved.
  template <typename T>Interval<T> intervalProduct (Interval<T> a, Interval<T> b, bool& exception) {
  uint8_t bit0_AB = a.upper >= 0;
  uint8_t bit1_AB = a.lower >= 0;
  uint8_t bit2_AB = b.upper >= 0;
  uint8_t bit3_AB = b.lower >= 0;
  uint8_t code_AB = (bit3_AB << 3) | (bit2_AB << 2) | (bit1_AB << 1)
      | bit0_AB;
  Interval<T> p = { 0, 0 };
  switch (code_AB) {
      case 0xf: p.upper = a.upper * b.upper; p.lower = a.lower *
             b.lower; break; 
      case 0xd: p.upper = a.upper * b.upper; p.lower = a.lower *
             b.upper; break;
      case 0xc: p.upper = a.upper * b.lower; p.lower = a.lower *
             b.upper; break;
      case 0x7: p.upper = a.upper * b.upper; p.lower = a.upper *
             b.lower; break;
      case 0x5:
         p.upper = std::numeric_limits<T>::max();
         p.lower = std::numeric_limits<T>::lowest();
         exception = true;
         break; // failure case - too close to call, need 4 multipliers
      case 0x4: p.upper = a.lower * b.lower; p.lower = a.lower *
             b.upper; break;
      case 0x3: p.upper = a.lower * b.upper; p.lower = a.upper *
             b.lower; break;
      case 0x1: p.upper = a.lower * b.lower; p.lower = a.upper *
             b.lower; break;
      case 0x0: p.upper = a.lower * b.lower; p.lower = a.upper *
             b.upper; break;
  }
  } return p;
 }

8th 8 shows an example of switching logic 810 configured to implement the modified signed interval product, in accordance with some embodiments. In some embodiments, the circuitry of 8th into the corresponding elements 710 of 7 locked in. In this embodiment, based on the four signs of the inputs, the bypass circuitry 810 is configured to pass operands to two multipliers, e.g. B. as shown in code list 1. Switching logic 810 is also configured in this example to recognize an exception condition.

Exemplary coding and processing techniques for triangle pairs

9 12 is a diagram illustrating example processing circuitry for triangle pairs and sequential pairs, according to some embodiments. As shown is the triangle pair 910 a set of two triangles that have two vertices in common (vertex 1 and vertex 2, in the illustrated example). Therefore, the two triangles can be defined by four vertices. Because triangle pairs are common in various models, in some embodiments the processor is configured to store triangles using a four-vertex triangle pair data structure, which may reduce memory footprint.

In some embodiments, the processor includes sequential pair processing circuitry 920 configured to sequentially perform one or more operations on a triangle pair, e.g. B. Processing one triangle in a pair before processing the second triangle in a pair. The operation can be, for example, an initial interface result, but other circuitry can use similar sequential techniques. This can provide efficient processing in implementations where the same triangle pair structure is used for all triangles, but some structures may contain data for only a single triangle. In these embodiments, the sequential pair processing circuitry 920 may skip operations for the second triangle in a pair when the data structure indicates that only one triangle is encoded.

Example of a definitive hit detection with a lower accuracy interface test

In some embodiments, interface test circuitry operating with quantized inputs may still provide definitive information about whether a line corresponding to the ray intersects a primitive, which may be useful for certain types of rays. Therefore, to refer to the example of 7 Coming back, modified comparison circuitry can be implemented (in addition to or instead of the circuitry of 7 ) to provide a result that either indicates a definite match or indicates that it's not clear whether there is a match.

10 Figure 12 is a diagram illustrating example regions bounded by a quantized representation of a two-dimensional triangular primitive (e.g., after shearing). In the illustrated example, the edges 1010 show the exact edges, e.g. B. if they are represented according to the original accuracy. Outer bounds 1020 and inner bounds 1030 indicate the bounds of the quantized representation, e.g. B. using an interval representation.

As shown, a ray falling within the out-of-bounds region 1020 is a definite miss, such as that found in FIG. B. from the switching logic in 7 can be recognized. A ray falling in the region between boundaries 1020 and 1030 is ambiguous (e.g. because it is not known exactly where the triangle edges lie in this region). Rays falling in this region may require a higher accuracy test.

As shown, a ray falling within the region within boundaries 1030 is a definite hit for a line corresponding to the ray. It should be noted that an intersection found using this test may not accurately indicate where the hit occurred, e.g. B. due to the quantization. Furthermore, the intersection determined by this test may only indicate a hit on the line corresponding to the ray, e.g. B. due to the quantization of the interval in which the ray is valid.

However, in some embodiments, determining a definitive match in the region within bounds 1030 may be useful, even with the limitations noted above.

11 11 is a block diagram illustrating an example of low precision test circuitry 1120 configured to indicate whether there is a hit or whether it is ambiguous as to whether there is a hit. 12 , which will be discussed in more detail below, provides a detailed example of such switching logic. It should be noted that the switching logic 1120 may also provide an output indicating whether there is a failure or whether it is ambiguous when there is a failure, e.g. B. if the switching logic of 7 and 12 is combined.

In some embodiments, the processor may skip a higher fidelity interface test in some scenarios where the output of circuitry 1120 indicates a definite hit. In some embodiments, such a ray interrogation may be terminated under the following conditions: the ray is any hit ray, the triangle is opaque, and the active ray interval completely covers at least one bounding volume that completely encloses that triangle. The opacity of the triangle may be determined based on assigning an alpha value to the test, in some embodiments. Whether the active beam interval has at least one bounding volume ment completely enclosing the triangle can be determined based on a traversal of the ADS (which allows determination of the bounding volumes completely enclosing the triangle based on the structure of the ADS) and slab test circuitry so configured that it tests the bounding volumes for the traversal.

Under these conditions, the processor can record an intersection hit in the beam triangle without performing a higher accuracy test. This can improve performance, reduce power consumption, or both when processing beams with any hit. It should be noted that the terms discussed above are included for illustrative purposes only; in other embodiments, only a subset of these conditions may be checked, other conditions may be imposed, and so on.

12 is a map of 7 similar circuit diagram showing the test circuitry for the definite hit, according to some embodiments. In the illustrated embodiment, the switching logic 710 is configured as described above with reference to FIG 7 and 8th described. However, the outputs are routed differently to the comparators to provide a hit or ambiguous result. In some embodiments, the in 12 Comparators, AND gates and OR gates shown in addition to the in 7 circuitry shown, so the quantized interface test circuitry returns two Boolean results for a given test.

 // Start von Codeliste 2: Kantentests und Komparatoren
 // 12 Multiplikatoren für die 6 Intervallprodukte
 bool intervalProductExceptionFlag = false;
 Interval W_bx_ay = interval_product(bxInterval, ayInterval,
      intervalProductExceptionFlag); 
 Interval W_by_ax = interval product(byInterval, axInterval,
      intervalProductExceptionFlag);
 Interval U_cx_by = interval_product(cxInterval, byInterval,
      intervalProductExceptionFlag);
 Interval U_cy_bx = interval_product(cyInterval, bxInterval,
      intervalProductExceptionFlag);
 Interval V_ax_cy = interval_product(axInterval, cyInterval,
      intervalProductExceptionFlag);
 Interval V_ay_cx = interval_product(ayInterval, cxInterval,
      intervalProductExceptionFlag);
 // Innen-/Außen-Bestimmung
 // Handhaben von rück- und vorderseitigen Möglichkeiten
 // Bestimmung eines garantierten Fehlschlags (erfolgreiche
      Zurückweisung der Schnittstelle des Strahlendreiecks)
 const bool outerEdgeTestSignsFrontU = U_cy_bx.lower < U_cx_by.upper;
 const bool outerEdgeTestSignsFrontV = V_ay_cx.lower < V_ax_cy.upper;
 const bool outerEdgeTestSignsFrontW = W_by_ax.lower < W_bx_ay.upper;
 const bool outerEdgeTestSignsBackU = U_cx_by.lower < U_cy_bx.upper;
 const bool outerEdgeTestSignsBackV = V_ax_cy.lower < V_ay_cx.upper;
 const bool outerEdgeTestSignsBackW = W_bx_ay.lower < W_by_ax.upper;
 const bool insideOuterBackfacingTriangle = outerEdgeTestSignsBackU &&
      outerEdgeTestSignsBackV && outerEdgeTestSignsBackW;
 const bool insideOuterFrontfacingTriangle = outerEdgeTestSignsFrontU
      && outerEdgeTestSignsFrontV && outerEdgeTestSignsFrontW;
 const bool guaranteedRayMiss = !insideOuterBackfacingTriangle
      && !insideOuterFrontfacingTriangle;
 // Bestimmung eines garantierten Treffers (erfolgreiche Annahme der
      Schnittstelle des Strahlendreiecks)
 const bool innerEdgeTestSignsFrontU = U_cy_bx.upper <= U_cx_by.lower;
 const bool innerEdgeTestSignsFrontV = V_ay_cx.upper <= V_ax_cy.lower;
 const bool innerEdgeTestSignsFrontW = W_by_ax.upper <= W_bx_ay.lower;
 const bool innerEdgeTestSignsBackU = U_cx_by.upper <= U_cy_bx.lower; 

 const bool innerEdgeTestSignsBackV = V_ax_cy.upper <= V_ay_cx.lower;
 const bool innerEdgeTestSignsBackW = W_bx_ay.upper <= W_by_ax.lower;
 const bool insideInnerBackfacingTriangle = innerEdgeTestSignsBackU &&
      innerEdgeTestSignsBackV && innerEdgeTestSignsBackW;
 const bool insideInnerFrontfacingTriangle = innerEdgeTestSignsFrontU
      && innerEdgeTestSignsFrontV && innerEdgeTestSignsFrontW;
 const bool guaranteedLineHit = insideInnerBackfacingTriangle ||
      insideInnerFrontfacingTriangle;
 if (intervalProductExceptionFlag) return TRIANGLE_FILTER_INCONCLUSIVE;
 else if (guaranteedRayMiss) return
      TRIANGLE_FILTER_CONSERVATIVE_RAY_MISS;
 else if (guaranteedLineHit) return
      TRIANGLE_FILTER_CONSERVATIVE_LINE_HIT;
 else return TRIANGLE_FILTER_INCONCLUSIVE;

Code Listing 2 below provides example operations performed by the circuitry of 12 or other similar switching logic can be implemented.

 // Start of Code List 2: Edge Tests and Comparators
 // 12 multipliers for the 6 interval products
 bool intervalProductExceptionFlag = false;
 Interval W_bx_ay = interval_product(bxInterval, ayInterval,
      intervalProductExceptionFlag); 
 Interval W_by_ax = interval product(byInterval, axInterval,
      intervalProductExceptionFlag);
 Interval U_cx_by = interval_product(cxInterval, byInterval,
      intervalProductExceptionFlag);
 Interval U_cy_bx = interval_product(cyInterval, bxInterval,
      intervalProductExceptionFlag);
 Interval V_ax_cy = interval_product(axInterval, cyInterval,
      intervalProductExceptionFlag);
 Interval V_ay_cx = interval_product(ayInterval, cxInterval,
      intervalProductExceptionFlag);
 // interior/exterior determination
 // Handling back and front possibilities
 // Determine a guaranteed failure (successful
      rejection of the intersection of the triangle of rays)
 const bool outerEdgeTestSignsFrontU = U_cy_bx.lower <U_cx_by.upper;
 const bool outerEdgeTestSignsFrontV = V_ay_cx.lower <V_ax_cy.upper;
 const bool outerEdgeTestSignsFrontW = W_by_ax.lower <W_bx_ay.upper;
 const bool outerEdgeTestSignsBackU = U_cx_by.lower <U_cy_bx.upper;
 const bool outerEdgeTestSignsBackV = V_ax_cy.lower <V_ay_cx.upper;
 const bool outerEdgeTestSignsBackW = W_bx_ay.lower <W_by_ax.upper;
 const bool insideOuterBackfacingTriangle = outerEdgeTestSignsBackU &&
      outerEdgeTestSignsBackV &&outerEdgeTestSignsBackW;
 const bool insideOuterFrontfacingTriangle = outerEdgeTestSignsFrontU
      && outerEdgeTestSignsFrontV &&outerEdgeTestSignsFrontW;
 const bool guaranteedRayMiss = !insideOuterBackfacingTriangle
      &&!insideOuterFrontfacingTriangle;
 // Determine a guaranteed hit (successful acceptance of the
      intersection of the triangle of rays)
 const bool innerEdgeTestSignsFrontU = U_cy_bx.upper <= U_cx_by.lower;
 const bool innerEdgeTestSignsFrontV = V_ay_cx.upper <= V_ax_cy.lower;
const bool innerEdgeTestSignsFrontW = W_by_ax.upper <= W_bx_ay.lower;
 const bool innerEdgeTestSignsBackU = U_cx_by.upper <= U_cy_bx.lower; 

 const bool innerEdgeTestSignsBackV = V_ax_cy.upper <= V_ay_cx.lower;
 const bool innerEdgeTestSignsBackW = W_bx_ay.upper <= W_by_ax.lower;
 const bool insideInnerBackfacingTriangle = innerEdgeTestSignsBackU &&
      innerEdgeTestSignsBackV &&innerEdgeTestSignsBackW;
 const bool insideInnerFrontfacingTriangle = innerEdgeTestSignsFrontU
      && innerEdgeTestSignsFrontV &&innerEdgeTestSignsFrontW;
 const bool guaranteedLineHit = insideInnerBackfacingTriangle ||
      insideInnerFrontfacingTriangle;
 if (intervalProductExceptionFlag) return TRIANGLE_FILTER_INCONCLUSIVE;
 else if (guaranteedRayMiss) return
      TRIANGLE_FILTER_CONSERVATIVE_RAY_MISS;
 else if (guaranteedLineHit) return
      TRIANGLE_FILTER_CONSERVATIVE_LINE_HIT;
 else return TRIANGLE_FILTER_INCONCLUSIVE;

Example of traversal techniques to potentially reduce interface testing

The calculation of ray intersections is often facilitated by acceleration data structures (ADS). To perform ray-interface queries efficiently, a spatial data structure can reduce the number of ray-surface interface tests, thereby speeding up the query process. A common class of ADS is the Bounding Volume Hierarchy (BVH), in which surface primitives are enclosed in a hierarchy of geometric proxy volumes (e.g., boxes) that are more convenient when testing for interfaces. These volumes can be referred to as confinement regions. By traversing the data structure and performing proxy interface tests along the way, the graphics processor locates a conservative set of candidate interface primitives for a given ray. A common form of BVH uses 3D axis-aligned bounding boxes (AABB). Once constructed, an AABB BVH can be used for all ray queries and is a viewpoint independent structure. In some embodiments, these structures are constructed once for each individual mesh in a scene in the local object space or model space of that object, and the rays are transformed from global space to local space before traversing the BVH. This can allow geometric instantiation of a single mesh with many rigid transformations and material properties (analogous to instantiation in rasterization). Animated geometry typically requires the data structure to be rebuilt (sometimes with a less expensive update operation called a "refit"). For non-real-time applications where millions or billions of rays are traced against a single scene in a single frame, the cost of ADS construction is fully amortized, making it "free" so to speak. However, in a real-time context, there is usually a delicate trade-off between construction costs and traversal costs, with more efficient structures typically being more expensive to build.

In some embodiments, the interface circuitry is configured to traverse a BVH ADS that uses axis-aligned 3D boxes for its bounding volumes. The ADS can have a maximum branching factor (e.g. 2, 4, 8, 16, etc.) and a flexible user-defined payload (e.g. the contents of the tree's leaves) that does not assume triangular geometry. In some embodiments, a depth-first search is performed, e.g. B. as in US Pat. note no. 17/103,317 , filed November 24, 2020, which is incorporated herein by reference in its entirety.

In some embodiments, the RIA 190 is configured to use, for a particular node, a modified child node order for particular types of depth-first traversals. In some embodiments, the disclosed techniques are applied to secondary beams. Secondary rays are rays that emanate from where a first (already traced) ray intersects a surface. Many random-hit beams are secondary because of the types of effects commonly achieved with random-hit beams (e.g. shadows). The secondary rays therefore originate near the intersected surface and point away from the surface (and therefore do not intersect that particular surface).

Due to the nature of secondary rays, the inventors have recognized that front-to-back or back-to-front traversal of child nodes for intersecting bounding volumes can typically result in interface tests that fail. For example, in front-to-back, the ray is likely to intersect a bounding volume for the primitive that reflects the secondary ray (triggering an intersection test), but it will not actually intersect that primitive.

13 12 is a diagram comparing a front-to-back order to a center-out order for crossing child nodes of an acceleration data structure, according to some embodiments. In the illustrated example, a secondary ray is a reflection resulting from an intersection of another ray (not shown) with the primitive A . As shown, the ray ends at a light source (this may be due to the fact that ray tracing typically traces rays backwards from the camera to the light source to avoid processing irrelevant rays). The ray is an arbitrary hit ray and intersects the primitive C in this example.

Considering an example situation where the ray intersects the bounding volumes of each illustrated primitive, and the illustrated primitives are all children of a node corresponding to a larger bounding volume. In this example, the traversal circuitry can use different orders of child nodes to follow first in a depth-first search.

As shown, interface tests for primitives A and B will fail if a front-to-back ordering is used, in which the bounding volumes closer to the ray origin are traversed first before finally detecting a hit for primitive C and the query ends (since it is an arbitrary hit ray). The failure for primitive A is not surprising since the ray that produced the illustrated secondary ray intersects with primitive A.

Advantageously, the center-outer ordering provides faster hit detection that requires two fewer interface tests than the front-to-back ordering in this example. As shown, starting in the middle of the ray results in a hit for primitive C, and the query can complete without examining primitives D, A, or B.

In some embodiments, various techniques may be employed to provide one or more middle nodes with a preferred order compared to front/back nodes. As an example, consider a tree-like ADS with a branching factor N. The interface circuitry may first sort the child nodes whose bounding volumes have been intersected in front-to-back order. For M ≤ N intersected suborders (with indices 0 to M-1), the interface circuitry can reorder the intersections over the following sequences depending on whether M is odd or even.

$$\text{M/}2+1$$

$$\text{M/}2-1$$

$$\text{M/}2+2$$

$$\text{M/}2-2$$

$$\begin{array}{l}\dots \hfill \\ \text{M/}2+\text{M/}2=\text{M}-1\hfill \end{array}$$

$$\text{M/}2-\text{M/}2=0$$

If M is odd and the division means integer division (e.g. 3/2=1), the following example is a reordered sequence of subindexes: $$\text{m/}2$$

$$\text{m/}2+1$$

$$\text{m/}2-1$$

$$\text{m/}2+2$$

$$\text{m/}2-2$$

$$\begin{array}{l}...\hfill \\ \text{m/}2+\text{m/}2=\text{M}-1\hfill \end{array}$$

$$\text{m/}2-\text{m/}2=0$$

$$\text{M/}2-1$$

$$\text{M/}2+1$$

$$\text{M/}2-2$$

$$\begin{array}{l}\text{M/}2+2\hfill \\ \dots \hfill \end{array}$$

$$\text{M/}2+\left(\text{M/}2-1\right)=\text{M}-1$$

$$\text{M/}2-\text{M/}2=0$$

If M is even, the following example is a rearranged sequence: $$\text{m/}2$$

$$\text{m/}2-1$$

$$\text{m/}2+1$$

$$\text{m/}2-2$$

$$\begin{array}{l}\text{m/}2+2\hfill \\ ...\hfill \end{array}$$

$$\text{m/}2+\left(\text{m/}2-1\right)=\text{M}-1$$

$$\text{m/}2-\text{m/}2=0$$

$$\text{F}\ddot{\text{u}}\text{r M}=2:\left[\mathrm{1,0}\right]$$

$$\text{F}\ddot{\text{u}}\text{r M}=3:\left[\mathrm{1,2,0}\right]$$

$$\text{F}\ddot{\text{u}}\text{r M}=4:\left[\mathrm{2,1,3,0}\right]$$

$$\text{F}\ddot{\text{u}}\text{r M}=5:\left[\mathrm{2,3,1,4,0}\right]$$

$$\text{F}\ddot{\text{u}}\text{r M}=6:\left[\mathrm{3,2,4,1,5,0}\right]$$

$$\text{F}\ddot{\text{u}}\text{r M}=7:\left[\mathrm{3,4,2,5,1,6,0}\right]$$

$$\text{F}\ddot{\text{u}}\text{r M}=8:\left[\mathrm{4,3,5,2,6,1,7,0}\right]$$

In some hardware implementations, for a maximum branching factor, the circuitry can encode N reordering sequences for each value of M from 1 to N to quickly determine the order for a center-outside traversal. As a non-limiting example, when N=8, a table could include the following sequences: $$\text{f}\ddot{\text{and}}\text{r M}=1:\left[0\right]$$

$$\text{f}\ddot{\text{and}}\text{r M}=2:\left[1.0\right]$$

$$\text{f}\ddot{\text{and}}\text{r M}=3:\left[\mathrm{1,2,0}\right]$$

$$\text{f}\ddot{\text{and}}\text{r M}=4:\left[\mathrm{2.1.3.0}\right]$$

$$\text{f}\ddot{\text{and}}\text{r M}=5:\left[\mathrm{2,3,1,4,0}\right]$$

$$\text{f}\ddot{\text{and}}\text{r M}=6:\left[\mathrm{3,2,4,1,5,0}\right]$$

$$\text{f}\ddot{\text{and}}\text{r M}=7:\left[\mathrm{3,4,2,5,1,6,0}\right]$$

$$\text{f}\ddot{\text{and}}\text{r M}=\mathrm{8th}:\left[\mathrm{4,3,5,2,6,1,7,0}\right]$$

It should be noted that the specific sequences discussed herein are included for purposes of illustration but are not intended to limit the scope of the present disclosure. In other embodiments, different orders may be implemented in which one or more inner child nodes are prioritized over the front/back nodes.

In embodiments using binary trees (N=2), the traversal circuitry may switch between back-to-front and front-to-back traversal order when searching for child nodes at different levels of the tree (e.g., using from "front to back" for odd depths in the tree and from "back to front" for even depths in the tree, or vice versa).

Exemplary Procedures

14 12 is a flow chart illustrating an example method for performing a first interface test, according to some embodiments. This in 14 The method shown may be used in connection with any of the computer circuitry, systems, devices, elements, or components disclosed herein, among others. In various embodiments, some of the method elements shown may be performed simultaneously, in a different order than shown, or omitted. Additionally, additional process elements can also be performed as desired.

At 1410, in the illustrated embodiment, a graphics processor quantizes a first representation of a primitive to generate a reduced-precision interval representation of the primitive, where the interval representation includes interval values guaranteed to cover corresponding values that are specified by the first representation of the primitive. In some embodiments, the quantization of the first representation of the primitive uses a quantized fixed-point representation rounded to zero for a lower bound of the interval and the lower bound plus a unit of least precision (ULP) for an upper bound of the interval.

At 1420, in the illustrated embodiment, the graphics processor quantizes a first representation of a ray to generate a reduced-precision interval representation of the ray, the interval representation including interval values guaranteed to cover corresponding values specified by the first representation of the ray. In some embodiments, the reduced-precision interval representation of the beam includes a quantized beam time represented as an interval. In some embodiments, the switching logic generates the reduced precision interval representation of the primitive based on first and second positions of the primitive at different points within a motion blur time interval, such that the reduced precision interval representation of the primitive covers all possible locations of the primitive during the interval that the quantized represents beam time.

At 1430, in the illustrated embodiment, the graphics processor determines an initial intersection result using interval arithmetic based on coordinates of the interval representation of the primitive with coordinates of the interval representation of the ray, where a failure indicated by the initial intersection result guarantees no hit for the first representation of the primitive and is the first representation of the ray.

In some embodiments, the graphics processor is configured to perform an interface test using the first representation of the primitive and the first representation of the ray in response to a potential initial interface result.

In some embodiments, the shear factor switching logic generates interval representations of shear factors based on ray direction and scale information and sheared vertex intervals based on the quantized representation of the primitive and the interval representation of the shear factors. In some embodiments, the initial intersection result is based on the sheared vertex intervals. In some embodiments, the shear factor switching logic is configured to use: a first precision to represent a first coordinate for an origin of the ray in a coordinate direction that provides a threshold (e.g., the largest) contribution to a ray direction vector (e.g., e.g. the axis renamed z-direction), and a second, greater precision, to represent coordinates for the origin of the ray in other directions.

In some embodiments, the first representation of the primitive is a representation of a triangle pair that includes at most four vertices for two triangular primitives in the triangle pair, where the graphics processor includes circuitry configured to process triangles of a given triangle pair sequentially.

15 12 is a flow chart illustrating an example method for performing a first interface test, according to some embodiments. This in 15 The method shown may be used in connection with any of the computer circuitry, systems, devices, elements, or components disclosed herein, among others. In various embodiments, some of the method elements shown may be performed simultaneously, in a different order than shown, or omitted. Additionally, additional process elements can also be performed as desired.

At 1510, a graphics processor in the illustrated embodiment performs interface tests, the interface tests on reduced-precision representations of rays generated by quantization of the initial representations of the rays and on reduced-precision representations of primitives generated by quantization of the initial representations of the Primitives were generated work. In the illustrated embodiment, the interface tests produce a first result for a first ray and a first primitive, the first result indicating that the first ray intersects the first primitive according to their original representations. In some embodiments, the interface tests may also produce a second result for a second ray and the first primitive, where the second result indicates that it is not clear whether the second ray intersects the first primitive. The graphics processor may perform an interface test for the second ray using the initial representation of the second ray and the first primitive. The interface tests may be performed based on the traversal of an acceleration data structure that includes hierarchically ordered bounding volumes for at least a portion of a graphics scene.

At 1520, in the illustrated embodiment, the graphics processor records an intersection with the first primitive for the first ray based on the first result without performing an interface test for the first ray using the initial representation of the first ray and the first primitive. In the illustrated embodiment, the intersection is recorded based on the following: the first result, a determination that the first primitive is opaque, and a determination that there is at least one bounding volume in the acceleration data structure that encloses the entirety of the first primitive and for which the entirety of the included portion of the first ray is active.

In some embodiments, the graphics processor is configured to record the intersection for the first ray based on a query of a ray with any hit for the first ray (and may not record definitive intersection results based on reduced accuracy tests for other query types ).

In some embodiments, the test circuitry is further configured to output a result for the first ray and the first primitive that indicates either: the first ray missed the first primitive, according to their initial representations, or that it is ambiguous whether the first ray misses the first primitive. For example, the processor may include the comparator and circuitry of 7 and 12 lock in. For the first ray and first primitive in the example described above, this output indicates that it is not clear whether the first ray misses the first primitive, since the other output indicates a definite hit.

In some embodiments, the processor uses center-outside traversal for at least some types of rays. In some embodiments, the processor is configured to perform the interface tests based on a traversal (e.g., through traversal circuitry) of an acceleration data structure that includes nodes corresponding to hierarchically arranged bounding volumes. In particular, the processor may perform a depth-first search in the acceleration data structure and, for a set of child nodes of a first node in the acceleration data structure, select a next node for the depth-first search according to an order of intersected bounding regions for the set of child nodes , where the order begins with a bounding volume that is closer to a center of a tested ray than one or more front bounding volumes and one or more back bounding volumes.

In some embodiments, prior to determining the order, the processor determines the number of nodes in the set of sub-nodes, where the set of sub-nodes corresponds to the nodes each intersected by the ray under test. For example, once the number of intersecting child nodes has been determined, the processor may access a look-up table to determine the order. In some embodiments, the ray under test is an arbitrary hit ray, and traversal of the ray under test stops in response to detecting an intersection. In some embodiments, the order relative to a starting node for subsequent nodes alternates in order between nodes in a front direction and nodes in a back direction. As used herein, a node that is closer to the "front" of a ray is closer to the end of the ray and a node that is closer to the "back" of a ray is closer to the origin of the ray. The above with reference to 13 The example orders discussed are examples of switching between nodes in a front direction and nodes in a back direction, starting from a middle node.

Exemplary device

Referring now to 16 A block diagram illustrating an example embodiment of an apparatus 1600 is shown. In some embodiments, elements of device 1600 may be encapsulated within a system-on-chip. In some embodiments, device 1600 may be encapsulated in a mobile device, which may be battery powered. Therefore, power consumption by device 1600 can be an important design consideration. In the illustrated embodiment, the device 1600 includes a fabric 1610, a computing complex 1620, an input/output bridge (I/O bridge) 1650, a cache/memory controller 1645, the graphics unit 1675 and a display unit 1665. In some embodiments, device 1600 may include other components (not shown) in addition to or in place of the components illustrated, such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

The fabric 1610 may include various interconnects, buses, MUX, controllers, etc. and may be configured to support communication between various elements of the device 1600. In some embodiments, portions of fabric 1610 may be configured to implement various different communication protocols. In other embodiments, fabric 1610 may implement a single communication protocol and elements coupled to fabric 1610 may convert from the single communication protocol to other communication protocols.

In the illustrated embodiment, the computational complex 1620 includes a bus interface unit (BIU) 1625, a cache 1630, and cores 1635 and 1640. FIG. In various embodiments, the computing complex 1620 may include various numbers of processors, processor cores, and/or caches. For example, the computing complex 1620 may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache 1630 is a set-associative L2 cache. In some embodiments, cores 1635 and 1640 may include internal instruction and/or data caches. In some embodiments, a coherency unit (not shown) may be configured in fabric 1610, cache 1630, or elsewhere in device 1600 to maintain coherency between different caches of device 1600. BIU 1625 may be configured to manage communications between computing complex 1620 and other elements of device 1600.

Processor cores, such as cores 1635 and 1640, may be configured to execute instructions of a particular instruction set architecture (ISA), which may include operating system instructions and user application instructions.

Cache/storage controller 1645 may be configured to manage the transfer of data between fabric 1610 and one or more caches and/or storage. For example, cache/memory controller 1645 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, cache/memory controller 1645 may be coupled directly to memory. In some embodiments, cache/memory controller 1645 may include one or more internal caches.

As used herein, the term "coupled to" can indicate one or more connections between elements, and a coupling can include intervening elements. For example, in 16 the graphics unit 1675 can be described as "coupled to" memory via the fabric 1610 and the cache/memory controller 1645. In contrast, in the illustrated embodiment of FIG 16 the graphics unit 1675 is "directly coupled" to the fabric 1610 because there are no intervening elements. Graphics unit 1675 may include one or more processors, e.g. B. include one or more graphics processing units (GPUs). Graphics engine 1675 may receive graphics-oriented instructions such as OPENGL®, METAL, or DIRECT3D® instructions. Graphics unit 1675 may execute specialized GPU instructions or perform other operations based on the received graphics-oriented instructions. The graphics engine 1675 may generally be configured to process large blocks of data in parallel and construct images in a frame buffer for output to a display, which may be included in the device or a separate device. Graphics engine 1675 may include transform, lighting, triangle, and rendering engines in one or more graphics processing pipelines. The graphics engine 1675 can output pixel information for display images. Graphics engine 1675, in various embodiments, may include programmable shader circuitry including highly parallel execution cores configured to execute graphics programs that may include pixel, vertex, and computational tasks (which may or may not be graphics related). .

In some embodiments, graphics engine 1175 includes switching logic 220 that reduces power consumption, increases performance, or both, compared to conventional GPUs.

The display unit 1665 may be configured to read data from a frame buffer and provide a stream of pixel values for display. In some embodiments, display unit 1665 may be configured as a display pipeline. In addition, the display unit 1665 may be configured to merge multiple frames to generate an output frame. Further, the display unit 1665 may include one or more interfaces (e.g., MIPI® or embedded Display Port (eDP)) for coupling to a user display (e.g., a touch screen or an external display).

The I/O bridge 1650 may include various elements configured to implement: for example, Universal Serial Bus (USB) communications, security, audio, and low-power always-on functionality. The I/O bridge 1650 may also include interfaces such as pulse width modulation (PBM), general purpose input/output (GPIO), serial peripheral interface (SPI), and inter-integrated circuit (I2C). Various types of peripherals and devices may be coupled to device 1600 via I/O bridge 1650 .

In some embodiments, device 1600 includes network interface circuitry (not explicitly shown) that may be coupled to fabric 1610 or I/O bridge 1650 . Network interface circuitry may be configured to communicate over various networks, which may be wired, wireless, or both. For example, the network interface circuitry may be configured to communicate over a wired local area network, a wireless local area network (e.g., via WiFi), or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, network interface circuitry is configured to communicate over one or more cellular networks using one or more radio access technologies. In some embodiments, the circuitry of the network interface is configured to communicate via device-to-device communications (e.g., Bluetooth or WiFi Direct), and so on. In various embodiments, network interface circuitry of device 1600 may provide connectivity to various types of other devices and networks.

Application examples

Referring now to 17 various types of systems may include any of the circuits, devices, or systems described above. The system or device 1700, which may incorporate or otherwise utilize one or more of the techniques described herein, may be used in a wide range of areas. For example, the system or device 1700 may be part of the hardware of systems such as a desktop computer 1710, a laptop computer 1720, a tablet computer 1730, a cellular or mobile phone 1740, or a television 1750 (or a set-top connected to a television box) can be used.

Similarly, the disclosed elements may be used in a wearable device 1760, such as a smart watch or a health monitoring device. Smartwatches, in many embodiments, can perform a variety of different functions, such as accessing email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed to perform solely health monitoring functions, such as monitoring a user's vital signs , performing epidemiological functions such as contact tracing, providing communications with an emergency medical service, etc. Other types of devices are also conceivable, including devices worn on the neck, devices that can be implanted in the human body, Goggles or helmets that provide computer generated reality experiences, such as those based on augmented and/or virtual reality, etc.

The system or device 1700 can also be used in various other contexts. For example, the system or device 1700 can be used in conjunction with a server computing system, such as a dedicated server or on shared hardware that implements a cloud-based service 1770 . In addition, the system or device 1700 can be implemented in a wide range of specific everyday devices, including common household devices 1780 such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the "Internet of Things" (IoT ) designated. The elements can also be used in different modes of transport. The system or device 1700 could be used in the control systems, guidance systems, entertainment systems, etc. of the various vehicle types 1790, for example.

In the 17 The applications illustrated are exemplary only and are not intended to limit the possible future applications of the disclosed systems or devices. Other examples of use include, without limitation, the following: portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

Exemplary Computer-Readable Medium

Various example circuits have been described in detail above in the present disclosure. The present disclosure is intended to cover not only embodiments that include such circuitry, but also a computer-readable storage medium that includes design information that specifies such circuitry. Accordingly, the present disclosure is intended to support claims covering not only an apparatus including the disclosed circuitry, but also a storage medium specifying the circuitry in a format recognized by a production system configured to manufacture hardware (e.g., (e.g. an integrated circuit) incorporating the disclosed circuitry. Claims to such a storage medium are intended to cover, for example, an entity that creates a circuit design but does not produce the design itself.

18 12 is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information, according to some embodiments. In the illustrated embodiment, the semiconductor production system 1820 is configured to process the design information 1815 stored on the non-transitory computer-readable medium 1810 and to produce the integrated circuit 1830 based on the design information 1815 .

The non-transitory computer-readable storage medium 1810 may include any of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1810 can be an installation medium, e.g. a CD-ROM, floppy disk or tape device; a computer system memory or random access memory such as DRAM, DDR-RAM, SRAM, EDO-RAM, Rambus-RAM, etc.; non-volatile memory such as flash memory, magnetic media, e.g. B. a hard drive or optical storage; Act registers or other similar types of storage elements etc. The non-transitory computer-readable storage medium 1810 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1810 may include two or more storage media that may be in different locations, e.g. B. in different computer systems that are connected via a network.

The design information 1815 can be specified using any of various suitable computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 1815 can be used by the semiconductor production system 1820 to to produce at least a portion of the integrated circuit 1830. The format of the design information 1815 can be recognized by at least one semiconductor production system 1820 . In some embodiments, the design information 1815 may also include one or more cell libraries that specify the integrated circuit 1830 synthesis, layout, or both. In some embodiments, the design information is specified in whole or in part in the form of a netlist specifying the cell library elements and their connectivity. The design information 1815, taken alone, may or may not include sufficient information to produce a corresponding integrated circuit. For example, the design information 1815 may specify the circuit elements to be produced, but not their physical layout. In this case, the design information 1815 may need to be combined with layout information to actually produce the given circuitry.

Integrated circuit 1830 may include one or more user-defined macrocells, such as memory, analog or mixed-signal circuitry, and the like, in various embodiments. In such cases, the design information 1815 may include information related to included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to the Graphics Data System (GDSII) or any other suitable format.

Semiconductor production system 1820 may include any of various suitable elements configured to produce integrated circuits. This may include, for example, features for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, changing the shape of deposited materials, modifying materials (e.g., by doping materials, or modifying dielectric constants using ultraviolet processing), etc. The semiconductor production system 1820 may also be configured to perform various tests of circuits produced for proper operation.

In various embodiments, integrated circuit 1830 is configured to operate according to a circuit design specified by design information 1815, which may include performing any of the functionality described herein. For example, the integrated circuit 1830 can be any of various in 1B , 2 , 4-9 , 11 , 12 and 16 include items shown. Furthermore, the integrated circuit 1830 may be configured to perform various functions described herein in conjunction with other components. Furthermore, the functionality described herein may be performed by multiple interconnected integrated circuits.

As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the subject circuit must be manufactured in order for the item to be satisfied. Rather, this term indicates that the design information describes a circuit that, after manufacture, will be configured to perform the specified actions or to include the specified components.

This disclosure includes references to "an" embodiment or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are various implementations or instances of the disclosed concepts. References to "embodiment", "an embodiment", "a particular embodiment" and the like are not necessarily all referring to the same embodiment. A wide variety of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives which fall within the spirit or scope of the disclosure.

This disclosure may discuss potential benefits that may result from the disclosed embodiments. Not all implementations of these embodiments necessarily exhibit any or all potential benefits. Whether a benefit is achieved for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are a number of reasons why an implementation falling within the scope of the claims may not have some or all of the disclosed advantages. For example, a particular implementation could include other circuitry outside of the scope of the disclosure that eliminates or reduces one or more disclosed advantages in connection with any of the disclosed embodiments. Furthermore, sub-optimal design execution of a particular implementation (e.g., implementation techniques or tools) could also negate or reduce disclosed benefits. Even assuming a qualified implementation, achievement of benefits may still depend on other factors such as the environmental circumstances in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more problems addressed in this disclosure from occurring on a particular occasion, thereby possibly not obtaining the benefit of its solution. Due to the existence of possible factors outside of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations of claims that must be satisfied in order to establish infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvement available to designers having the benefit of this disclosure. Describing such benefits in a permissive sense (e.g., stating that a particular benefit "may occur") is not intended to cast doubt as to whether such benefits can actually be achieved, but rather to acknowledge technical reality that the achievement of such benefits often depends on additional factors.

Unless otherwise noted, embodiments are not limiting. That is, the disclosed embodiments are not intended to limit the scope of claims formulated based on this disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative, and not restrictive, unless otherwise stated in the disclosure. The This application is intended to allow claims to cover disclosed embodiments, as well as the alternatives, modifications, and equivalents apparent to those skilled in the art having the benefit of this disclosure.

For example, features in this application can be combined in any suitable way. Accordingly, during the prosecution of this application (or an application claiming priority therefrom) new claims may be formulated to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims dependent on other independent claims. Similarly, features from respective independent claims may be combined where appropriate.

Accordingly, while the appended dependent claims may be drafted as each dependent on a single other claim, additional dependencies are also contemplated. All combinations of features in the dependent consistent with this disclosure are contemplated and may be claimed in this or another application. In summary, combinations are not limited to those specifically recited in the appended claims.

Where appropriate, it is also contemplated that claims formulated in one format or legal type (e.g., device) should support corresponding claims of another format or legal type (e.g., method).

Because this disclosure is a legal document, various terms and phrases are subject to regulatory and legal interpretation. It is hereby acknowledged that the following paragraphs, as well as definitions provided throughout the disclosure, should be used in determining how claims formulated based on this disclosure are to be construed.

References to a singular form of an element (i.e., a noun or noun phrase preceded by "a" or "the") should, unless the context clearly dictates otherwise, be "a/ e/r or several”. Thus, a reference to "an element" in a claim without an accompanying context does not exclude additional instances of the element. A "plurality" of items refers to a set of two or more of the items.

The word "may" is used herein in a permissive sense (i.e., having the potential to be able) rather than in a mandatory sense (i.e., must).

The terms "comprising" and "including" and forms thereof are open-ended and mean "including, but not limited to."

When used in this disclosure in relation to a list of options, the term “or” is generally understood to be used in the inclusive sense unless the context dictates otherwise. Thus, specifying "x or y" is equivalent to "x or y or both" and thus covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, a phrase like "either x or y, but not both" makes it clear that "or" is used in the exclusive sense.

A statement of "w, x, y, or z, or any combination thereof" or "at least one of ... w, x, y, and z" is intended to cover all possibilities involving a single element up to the total number of elements in the set . For example, given the sentence [w, x, y, z], these phrases cover any single element of the sentence (e.g. w but not x, y or z), any two elements (e.g. w and x, but not y or z), any three elements (e.g. w, x and y, but not z) and all four elements. The phrase "at least one of ... x, y, and z" thus refers to at least one element of the set [w, x, y, z], covering all possible combinations in that list of elements. This phrase should not be construed as requiring there to be at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

Various “labels” may precede nouns or noun phrases in this disclosure. Unless the context otherwise dictates, different labels used for a feature (e.g., "first circuit", "second circuit", "specific circuit", "given circuit", etc.) refer to different instances of the feature. In addition, the imply Labels "first", "second", and "third" when applied to a feature do not have any type of sorting (e.g. spatial, temporal, logical, etc.) , unless otherwise stated.

The phrase "based on" or is used to describe one or more factors affecting a determination. This term does not exclude the possibility that additional factors may affect the determination. That is, a determination may be based solely on specified factors or based on specified factors plus other factors not specified. Consider the phrase "determine A based on B." This phrase indicates that B is a factor used to determine A or that affects the determination of A. This phrase does not exclude that the determination of A can also be based on another factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may affect or otherwise trigger the effect, either together with the factors listed or independent of the factors listed. That is, an effect may occur solely in response to those factors, or it may occur in response to the identified factors as well as other factors not identified. Consider the phrase "perform A in response to B." This phrase indicates that B is a factor that triggers A to be performed or that triggers a specific outcome for A. This phrase does not exclude that performing A can also be in response to another factor, such as C. This phrase also does not preclude performing A in response to B and C together. This phrase is also intended to cover an embodiment in which A is performed solely in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "in response at least in part to." Similarly, the phrase "in response to" is synonymous with the phrase "in response, at least in part, to."

Throughout this disclosure, different entities (which may variously be referred to as "units", "circuitry", other components, etc.) may be described or claimed as "configured" to perform one or more tasks or operations. This phrase - [entity] configured to [perform one or more tasks] - is used herein to refer to a structure (i.e., something physical). In particular, this phrase is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure may be referred to as "configured to" perform a task even if the structure is not currently operating. Thus, an entity described or indicated as "configured to perform" a task refers to something physical, such as a device, circuit, system having a processing unit and memory storing program instructions executable, to implement the task, etc. This phrase is not used herein to refer to something intangible.

In some cases, various units/circuits/components may be described herein as performing a set of tasks or operations. It is understood that these entities are "configured to" perform these tasks/operations even if not specifically stated.

The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a specific function. However, this unprogrammed FPGA may be "configurable to" perform this function. After appropriate programming, the FPGA can then be said to be "configured to" perform the particular function.

For purposes of U.S. patent applications based on this disclosure, a claim that a structure is "configured to" perform one or more tasks is expressly not intended to invoke the application of 35 U.S.C. § 112(f) for that claim element. During the prosecution of a US patent application based on this disclosure, when the applicant wishes to invoke the application of Section 112(f), he specifies claim elements using the construct "means for" [performing a function].

Various "circuits" may be described in this disclosure. These circuits or "circuit logic" form hardware that contains various types of circuit elements, such as combinatorial logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, and so on. Switching logic can be designed individually or taken from standard libraries. In various implementations, circuitry may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generically referred to as "units" (e.g., a decode unit, an arithmetic logic unit (ALU), a functional unit, a memory management unit (MMU), etc.). Such units also refer to circuits or switching logic.

The disclosed circuits/units/components and other elements illustrated in the drawings and described herein thus include hardware elements such as those described in the preceding paragraph. In many cases, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode of an instruction and redirecting that instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function . This functional specification is sufficient for one skilled in the computer art to specify a set of possible structures for the circuit.

In various embodiments, as discussed in the preceding paragraph, circuits, devices, and other elements may be defined by the functions or operations that they are configured to implement. The arrangement of these circuits/units/components in relation to each other and the way in which they interact form a micro-architectural definition of the hardware that is ultimately fabricated in an integrated circuit or programmed into an FPGA to provide a physical implementation of the micro-architectural definition to build. Thus, the microarchitecture definition is recognized by one skilled in the art as a structure from which many physical implementations can be derived, all falling within the broader structure described by the microarchitecture definition. That is, a person skilled in the art, presented with the microarchitecture definition provided according to this disclosure, without undue experimentation and by using average skill, can implement the structure by describing the circuits/units/components in a hardware description language (HDL), such as Verilog or VHDL encoded. The HDL description is often expressed in a way that can appear functional. However, for one skilled in the art, this HDL description is the manner used to transform the structure of a circuit, device or component to the next level of implementation detail. Such an HDL description may take the form of behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which, unlike behavioral code, is typically synthesizable), or structured code (e.g., a netlist, indicating the logic gates and their connectivity). The HDL description can then be synthesized against a library of cells designed for a given integrated circuit fabrication technology and modified for timing, power and other reasons to result in a final design database that conforms to sent to a foundry to create masks and ultimately fabricate the integrated circuit. Some hardware circuitry, or portions thereof, may also be customized in a schematic editor and incorporated into the integrated circuit design along with synthesized circuitry. The integrated circuits may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and provide a connection between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuitry and/or discrete elements may be used in some embodiments. Alternatively, the HDL design can be synthesized into a programmable logic device, such as a field programmable gate array (FPGA), and can be implemented in the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of those circuits usually leads to the scenario where the circuit or logic designer never specifies a specific set of structures for the low-level implementation, over and above a description of it goes beyond what the circuit is configured to do, since this process is performed at a different stage of the circuit implementation process.

The fact that many different low-level combinations of circuit elements can be used to implement the same specification of a circuit results in a large number of equivalent structures for that circuit. As indicated, these low-level circuits may vary according to changes in manufacturing technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. In many cases, the choices made by various design tools or methodologies to produce these various implementations can be arbitrary.

Furthermore, it is common for a single implementation of a particular functional specification of a circuit to include a large number of devices (e.g., millions of transistors) for a given embodiment. Accordingly, the sheer volume of this information makes it impractical to provide a complete, low-level indication of the structure used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, the present disclosure describes a structure of circuits using the functional shorthand commonly used in the industry.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US 17/136542 [0007]
• US 17/103317 [0079]

Claims (15)

facility comprising: a graphics processor configured to determine whether a ray intersects a primitive in a graphics scene, the graphics processor including: Beam interface circuitry configured to perform an interface test that includes: quantizing a first representation of the primitive to produce a reduced-precision interval representation of the primitive, the interval representation including interval values guaranteed to cover corresponding values specified by the first representation of the primitive; quantizing a first representation of the ray to produce a reduced-precision interval representation of the ray, the interval representation including interval values guaranteed to cover corresponding values specified by the first representation of the ray; and Determine, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray, where a failure indicated by the initial intersection result is guaranteed no hit for the first representation of the primitive and the first representation of the ray . setup after claim 1 , further comprising shear factor circuitry configured to: generate interval representations of shear factors based on beam direction and scale information; and generating sheared vertex intervals based on the quantized representation of the primitive and the interval representation of the shear factors; where the initial intersection result is based on the sheared vertex intervals. setup after claim 2 wherein the shear factor switching logic is configured to use: a first precision to represent a first coordinate for an origin of the ray in a coordinate direction that provides a threshold contribution to a ray direction vector; and a second, greater precision, to represent coordinates for the origin of the ray in other directions. setup after claim 1 , where the quantization of the first representation of the primitive uses a quantized fixed-point representation rounded to zero for a lower bound of the interval and the lower bound plus a unit of least precision (ULP) for an upper bound of the interval. setup after claim 1 , wherein the first representation of the primitive is a representation of a triangle pair including at most four vertices for two triangular primitives in the triangle pair, the graphics processor including circuitry configured to process triangles of a given triangle pair sequentially. setup after claim 1 , where the interval representation of the reduced precision beam includes a quantized beam time represented as an interval. setup after claim 6 , further comprising: circuitry configured to generate the reduced-precision interval representation of the primitive based on first and second positions of the primitive at different points within a motion blur interval, such that the reduced-precision interval representation of the primitive is all possible positions of the primitive during the interval representing the quantized beamtime. setup after claim 1 wherein the graphics processor is configured to perform an interface test using the first representation of the primitive and the first representation of the ray in response to a possible one of the initial interface result. setup after claim 1 wherein the facility is a computing device, further including: a central processing unit; an ad; and network interface circuitry. Method comprising: quantizing, by a graphics processor, a first representation of a primitive to generate a reduced-precision interval representation of the primitive, the interval representation including interval values guaranteed to cover corresponding values specified by the first representation of the primitive; quantizing, by the graphics processor, a first representation of a ray to generate a reduced-precision interval representation of the ray, the interval representation including interval values guaranteed to cover corresponding values specified by the first representation of the ray; and Determining, by the graphics processor using interval arithmetic, an initial interface result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray, where a failure indicated by the initial interface result guarantees no hit for the first representation of the primitive and the first representation of the beam is. procedure after claim 10 , further comprising: generating, by the graphics processor, interval representations of the shear factors based on beam direction and scale information; and generating, by the graphics processor, sheared vertex intervals based on the quantized representation of the primitive and the interval representation of the shear factors; where the initial intersection result is based on the sheared vertex intervals. procedure after claim 10 , where the quantization of the first representation of the primitive uses a quantized fixed-point representation rounded to zero for a lower bound of the interval and the lower bound plus a unit of least precision (ULP) for an upper bound of the interval. A non-transitory computer-readable storage medium having stored thereon design information specifying a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor manufacturing system configured to use the design information to produce the circuit according to the design, wherein the Design information indicates that the circuit includes: a graphics processor configured to determine whether a ray intersects a primitive in a graphics scene, the graphics processor including: Beam interface circuitry configured to perform an interface test that includes: quantizing a first representation of the primitive to produce a reduced-precision interval representation of the primitive, the interval representation including interval values guaranteed to cover corresponding values specified by the first representation of the primitive; quantizing a first representation of the ray to produce a reduced-precision interval representation of the ray, the interval representation including interval values guaranteed to cover corresponding values specified by the first representation of the ray; and Determine, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray, where a failure indicated by the initial intersection result is guaranteed no hit for the first representation of the primitive and the first representation of the ray . Non-transitory computer-readable storage medium Claim 13 wherein the design information specifies that the circuit further includes: shear factor circuitry configured to: generate interval representations of shear factors based on beam direction and scale information; and generating sheared vertex intervals based on the quantized representation of the primitive and the interval representation of the shear factors; where the initial intersection result is based on the sheared vertex intervals. Non-transitory computer-readable storage medium Claim 14 wherein the shear factor switching logic is configured to use: a first precision to represent a first coordinate for an origin of the ray in a coordinate direction that provides a threshold contribution to a ray direction vector; and a second, greater precision, to represent coordinates for the origin of the ray in other directions.

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