DE102022102588A1 - SIMULTANEOUS PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE STORAGE DEVICES - Google Patents

Abstract

Disclosed herein is the technology for simultaneously programming the same data pattern in multiple sets of non-volatile memory cells. The voltage is applied to bit lines according to a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system simultaneously applies a program pulse to control gates of a different set of selected memory cells in each corresponding set of the plurality of sets of NAND chains while applying the select voltage to the drain select gates of the plurality of sets of NAND chains and the voltages are applied to the plurality of bit lines to simultaneously program the data pattern into each set of the selected memory cells.

Description

PRIORITY CLAIM

This application is a partial continuation of U.S. Patent Application No. 17/227,820 entitled CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES, filed April 12, 2021, which is a divisional application of U.S. Patent Application No. 16/024,002 entitled CONCURRENT PROGRAMMING OF MULTIPLE CELLS FOR NON-VOLATILE MEMORY DEVICES, filed June 29, 2018; both of which are incorporated herein by reference in their entirety.

TECHNICAL AREA

The present disclosure relates, in various embodiments, to memory devices, and more particularly to systems and methods for simultaneously programming multiple cells of a non-volatile memory device.

BACKGROUND

Many data storage devices, such as flash memory devices, store data in cells of non-volatile media. A physical property of each cell, such as stored charge, voltage, material phase, electrical resistance, magnetization, or the like, can be altered to encode data. The physical property of a cell can be variable over a range that can be partitioned into discrete states, such that different states correspond to different data values. Sensing whether the cell's physical property meets one or more read thresholds (e.g., voltage thresholds, resistance thresholds, or the like) within its range determines the state of the cell so that a stored data value can be restored.

Non-volatile memory types include but are not limited to ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, Ovonic unified memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D -NAND flash memory), NOR flash memory, nano random access memory (Nano-RAM or NRAM), wire-based nanocrystal memory, silicon oxide-based sub-10 nanometer process memory, graphene memory, silicon oxide nitride oxide silicon (SONOS ), programmable metallization cell (PMC), line-bridging RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, tape), optical storage media, and the like. Among the types of non-volatile memory used to encode information in retained charges, various charge and/or charge retention technologies can be used, including but not limited to floating gate and charge trapping technologies.

In many of the above technologies, memory cells in different blocks are programmed in separate operations. In some cases, multiple copies of data are temporarily written to respective sets of memory cells before the data is stored in a multiple level cell (MLC). Examples of multi-level cells are two-level cells, three-level cells (triple level cell, TLC), four-level cells (quadruple level cell, QLC), five-level cells (penta level cell, PLC), and the like. When the temporarily stored data is written in cells of different capacities, such as single level cells (SLC), a cell compression process (folding process) or the like can be used to combine multiple bits using the data temporarily stored in the SLC cells to provide the value to be coded for the MLC cell. Conventional methods, in which the temporary copies are written and verified separately, increase the time and number of steps required to encode the MLC cell.

EXECUTIVE SUMMARY

Devices and methods for simultaneously programming multiple memory cells of one or more non-volatile memory elements are presented.

Devices and methods for simultaneously programming multiple memory cells of one or more non-volatile memory elements are presented. In one example, a memory die includes a set of non-volatile memory cells arranged in a first block including a first chain of memory cells crossing a word line at a first memory cell and a second block including a second chain of memory cells crossing a second word line at a second memory cell, a bit line electrically connectable to the first string and the second string, and a controller configured to simultaneously apply a programming pulse to the first word line and the second word line to generate the program the first and second memory cells simultaneously to a common target threshold voltage.

In another example, the controller is further configured to, after concurrent applying the programming pulse to the first word line and the second word line, simultaneously applying a verify pulse to the first word line and the second word line, sensing the current flow through one of the first memory cell and the second memory cell in response to the application of the verify pulse to determine that one of the first memory cell and the second memory cell is improperly programmed, and in response to determining that one of the first memory cell and the second memory cell is improperly programmed, initiating separate programming of the first memory cell and the second memory cell.

In one embodiment, programming the first memory cell and the second memory cell separately includes applying a conventional programming operation to the first memory cell and after verifying that the first memory cell is programmed correctly, applying a conventional programming operation to the second memory cell.

In one example, the controller is further configured to apply a second verify pulse to the first memory cell after applying the conventional programming pulses to the second cell, to sense current flow through one of the first memory cell and the second memory cell in response to the application of the second verify pulse, to determine that the first memory cell is correctly programmed, after application of the second verify pulse to the first memory cell, to apply a third verify pulse to the second memory cell and current flow through one of the first memory cell and the second memory cell in response to application of the third verify pulse sample to determine that the second memory cell is correctly programmed.

In another example, the controller is further configured to determine that the first memory cell is correctly programmed, responsive to determining that the first memory cell is correctly programmed, reading data from the first memory cell and after reading the data out of the first memory cell to overwrite the first memory cell and the second memory cell.

In one embodiment, the controller is further configured to read data from one of the first memory cell and the second memory cell and use the data to program a multi-level cell in a cell compression operation. In general, a cell compaction operation (also known as memory cell compaction) is an operation that moves data values stored in original memory cells containing one or more data values to cells that can hold more data values than the number of data values in the original memory cells. For example, in one embodiment, the cell compression process is SLC-TLC cell compression, meaning that data values in memory cells containing a single data value are moved into a single memory cell containing three data values by storage in a combined encoding. In other examples, the cell densification is SLC-MLC, MLC-QLC, TLC-QLC, SLC-QLC, or the like, as may be apparent to those skilled in the art.

In another embodiment, the second block resides in a separate physical portion of the set of non-volatile memory cells from the first block.

In one example, a device includes a set of non-volatile memory cells arranged in a first block and a second block each electrically connected to a set of bit lines, the first block having a first word line and the second block having a second word line , a selection circuit configured to electrically select a first set of memory cells in the first block and a second set of memory cells in the second block, and a programming circuit configured to apply a programming pulse to the first word line and second word line at an increased voltage to simultaneously write the same data to the first set of memory cells and the second set of memory cells in a single pulse.

In another example, the device further includes verify circuitry configured to apply a verify pulse to the first word line and second word line in response to application of the verify pulse, sensing current flow through respective memory cells connected to the set of bit lines to determine that one of the first set of memory cells and the second set of memory cells is programmed incorrectly, and in response to determining that one of the first set of memory cells and the second set of memory cells is programmed incorrectly, the first set of memory cells and the to program the second set of memory cells separately.

In another embodiment, the second block is physically offset from the first block.

In one example, a system includes a set of non-volatile memory cells arranged in a chain, the chain containing one bit line is connectable and has a word line for each memory cell, and a controller arranged to simultaneously write data in two memory cells in the chain by electrically selecting the bit line by setting a select gate transistor, electrically connecting a first word line, corresponding to a first memory cell in the chain, with a second word line corresponding to a second memory cell in the chain, and applying a programming pulse to the connected word lines simultaneously to write the data into the first memory cell and the second memory cell simultaneously.

In another example, the controller is further configured to simultaneously apply a verify pulse to the first wordline and second wordline after simultaneously applying the programming pulse to the first wordline and second wordline, responsive to current flow through one of the first memory cell and the second memory cell sense the application of the verify pulse to simultaneously determine that one of the first memory cell and the second memory cell is programmed incorrectly, and in response to determining that one of the first memory cell and the second memory cell is programmed incorrectly, the first To program memory cell and the second memory cell separately.

In another embodiment, the controller is further configured to determine that the first memory cell is correctly programmed, responsive to determining that the first memory cell is correctly programmed, reading data from the first memory cell and after reading the data out of the first memory cell to overwrite the first memory cell and the second memory cell.

In one embodiment, the controller is further configured to read data from one of the first memory cell and the second memory cell and use the data to program a multi-level cell in a cell compression operation.

In another example, the first memory cell and the second memory cell are consecutive memory cells in the chain.

In one embodiment, a method includes electrically selecting a bit line for a set of non-volatile memory cells arranged in two erase blocks, wherein the bit line can be connected to memory cells in either of the two blocks, electrically connecting separate word lines including a first word line, the one corresponding to memory cells in a first of the two blocks, and a second word line corresponding to one of the memory cells in a second of the two blocks; and simultaneously applying a programming pulse to the connected word lines to simultaneously program memory cells corresponding to the first word line and the second word line in the two blocks to a common target threshold voltage.

In one example, the method further includes, after applying the programming pulse to the connected word lines simultaneously, applying a verify pulse to the connected word lines simultaneously, sensing the current flow through the bit line in response to the application of the verify pulse to determine that one of the memory cells is improperly programmed, and in response to determining that one of the memory cells is improperly programmed, programming the memory cells separately.

In one embodiment, the method further includes determining that a first one of the memory cells is correctly programmed, responsive to determining that the first one of the memory cells is correctly programmed, reading the first one of the memory cells, and after reading the first one of the memory cells, overwriting the first of the memory cells and a second of the memory cells.

In another embodiment, the method further includes reading data from one of a first memory cell of memory cells within a first block of the two blocks and a second memory cell of memory cells within a second block of the two blocks and using the data to program another cell in a cell compression process.

In one example, a first of the two blocks is physically separated from a second of the two blocks.

In another example, a device includes means for electrically selecting a bit line for memory cells in a set of non-volatile memory cells arranged in two blocks, the bit line being connected to a first chain of memory cells in a first of the two blocks and a second chain of memory cells in a second of the two blocks, the first chain and the second chain each having a set of word lines, means for electrically connecting a first word line included in the first chain and a second Word line included in the second string, the first word line and the second word line each corresponding to a first memory cell included in the first string with a second memory cell included in the second string, and means for applying a single programming pulse to the connected word lines to simultaneously program the first memory cell in the first chain and the second memory cell in the second chain to a common target threshold voltage.

character list

• 1A ein Blockdiagramm einer Ausführungsform eines Systems ist, das eine Konponente zum gleichzeitigen Programmieren für eine nichtflüchtige Speichervorrichtung einschließt.
• 1B eine Ausführungsform einer nichtflüchtigen Speichervorrichtung veranschaulicht, die einen oder mehrere Speicher-Dies oder-Chips einschließen kann.
• 2A Blöcke von Speicherzellen in einer exemplarischen 2D-Konfiguration des Speicherarrays aus 1B darstellt.
• 2B eine Querschnittsansicht exemplarischer Ladungseinfangspeicherzellen in NAND-Ketten als Beispiel für Speicherzellen in 2A darstellt.
• 2C eine Querschnittsansicht der Struktur aus 2B darstellt.
• 2D eine exemplarische Speicherzelle darstellt.
• 3 eine perspektivische Ansicht einer Speichervorrichtung ist, die einen Satz Blöcke in einer exemplarischen 3D-Konfiguration des Speicherarrays aus 1 aufweist.
• 4 eine exemplarische Querschnittsansicht eines Abschnitts von einem der Blöcke aus 3 darstellt.
• 5 eine Nahansicht eines Bereichs des Stapels aus 4 darstellt.
• 6 eine exemplarische Ansicht von NAND-Ketten in Unterblöcken in einer 3D-Konfiguration darstellt, die mit 4 übereinstimmt.
• 7 ein zusätzliches Detail der Unterblöcke SB0 bis SB3 aus 6 darstellt.
• 8 eine Wellenform eines exemplarischen Programmiervorgangs darstellt.
• 9 einen Abschnitt der Speicherzelle MC aus 5 darstellt, die das Einspritzen von Elektronen in einen Ladungseinfangbereich bei schwacher Programmierung zeigt.
• 10 eine Draufsicht auf eine Reihe von Blöcken gemäß einem Ausführungsbeispiel darstellt.
• 11 ein Diagramm von Programmier- und Verifizierimpulsen gemäß einem Ausführungsbeispiel ist.
• 12 eine Ausführungsform von zwei Blöcken gemäß einem Ausführungsbeispiel darstellt.
• 13 eine Ausführungsform eines Verfahrens zum gleichzeitigen Programmieren von Zellen eines Speicherarrays darstellt.
• 14 eine weitere Ausführungsform eines Verfahrens zum gleichzeitigen Programmieren von Zellen eines Speicherarrays darstellt.
• 15A, 15B, 15C und 15D Vt-Verteilungen für Speicherzellen zeigen, die auf eine unterschiedliche Anzahl von Bits pro Zelle programmiert sind.
• 16 ein Flussdiagramm einer Ausführungsform eines Prozesses zum gleichzeitigen Programmieren verschiedener Sätze von Speicherzellen ist.
• 17 ein Flussdiagramm einer Ausführungsform eines Prozesses zum gleichzeitigen Programmieren von Speicherzellen auf NAND-Strings in unterschiedlichen Löschblöcken ist.
• 18 ein Flussdiagramm einer Ausführungsform des Prozesses des gleichzeitigen Programmierens von Speicherzellen in mehreren Löschblöcken in einem mehrstufigen Zellprogrammierungsprozess ist.
• 19 ein Flussdiagramm einer Ausführungsform des Prozesses zum gleichzeitigen Programmieren von Speicherzellen in mehreren Löschblöcken ist.
• 20A und 20B Blockdiagramme von Schaltungen zum Bereitstellen von Spannungen während des gleichzeitigen Programmierens von Sätzen von Speicherzellen sind.
• 21 weiterhin darstellt, wie die Schaltungen in den 20A und 20B elektrisch mit einer leitfähigen Region verbunden werden können, der mit Steuer-Gates von Speicherzellen verbunden ist.
• 22 ein Flussdiagramm einer Ausführungsform eines Prozesses zum Bereitstellen von Spannungen bei gleichzeitigem Programmieren ist.
• 23 ein Beispiel für eine mehrstufige Ladungspumpe darstellt.

A more specific description is included below with reference to specific embodiments illustrated in the accompanying drawings. Given that these drawings represent only certain embodiments of the disclosure and therefore should not be considered as limiting the scope thereof, the disclosure is described and explained with additional specificity and detail through the use of the accompanying drawings, wherein:

• 1A Figure 12 is a block diagram of one embodiment of a system including a concurrent programming component for a non-volatile memory device.
• 1B 1 illustrates one embodiment of a non-volatile memory device that may include one or more memory dies or chips.
• 2A blocks of memory cells in an exemplary 2D configuration of the memory array 1B represents.
• 2 B FIG. 12 is a cross-sectional view of exemplary charge trapping memory cells in NAND strings as an example of memory cells in FIG 2A represents.
• 2C Figure 1 shows a cross-sectional view of the structure 2 B represents.
• 2D represents an exemplary memory cell.
• 3 12 is a perspective view of a memory device comprising a set of blocks in an exemplary 3D configuration of the memory array 1 having.
• 4 Figure 14 is an exemplary cross-sectional view of a portion of one of the blocks 3 represents.
• 5 a close-up view of an area of the stack 4 represents.
• 6 Figure 1 shows an exemplary view of NAND chains in sub-blocks in a 3D configuration using 4 matches.
• 7 provides additional detail of the sub-blocks SB0 to SB3 6 represents.
• 8th Figure 12 illustrates a waveform of an example programming operation.
• 9 a portion of memory cell MC 5 Figure 12 showing the injection of electrons into a charge trapping region under weak programming.
• 10 Figure 12 illustrates a top view of a row of blocks according to one embodiment.
• 11 Figure 12 is a diagram of program and verify pulses according to one embodiment.
• 12 Figure 12 illustrates an embodiment of two blocks according to an embodiment.
• 13 Figure 12 illustrates one embodiment of a method for concurrently programming cells of a memory array.
• 14 Figure 12 illustrates another embodiment of a method for concurrently programming cells of a memory array.
• 15A , 15B , 15C and 15D show Vt distributions for memory cells programmed to different numbers of bits per cell.
• 16 Figure 12 is a flow diagram of one embodiment of a process for programming different sets of memory cells simultaneously.
• 17 Figure 12 is a flow chart of one embodiment of a process for concurrently programming memory cells to NAND strings in different erase blocks.
• 18 Figure 12 is a flowchart of one embodiment of the process of simultaneously programming memory cells in multiple erase blocks in a multi-level cell programming process.
• 19 Figure 12 is a flow chart of one embodiment of the process for simultaneously programming memory cells in multiple erase blocks.
• 20A and 20B Figure 12 are block diagrams of circuitry for providing voltages while simultaneously programming sets of memory cells.
• 21 further illustrates how the circuits in the 20A and 20B electric with one conductive region connected to control gates of memory cells.
• 22 Figure 12 is a flow chart of one embodiment of a process for providing voltages while programming.
• 23 represents an example of a multi-stage charge pump.

DETAILED DESCRIPTION

Disclosed herein is the technology for simultaneously programming the same data pattern in multiple sets of non-volatile memory cells. In one embodiment, the same data pattern is programmed into three or more sets of non-volatile memory cells simultaneously. In one embodiment, the memory cells are simultaneously programmed to one bit per cell. In one embodiment, the memory cells are simultaneously programmed to two bits per cell. In one embodiment, the memory cells are simultaneously programmed to three bits per cell. In one embodiment, the memory cells are simultaneously programmed to four bits per cell. In one embodiment, the memory cells are simultaneously programmed to five bits per cell. Each set of non-volatile memory cells can be part of a different set of NAND chains. In one embodiment, the different sets of NAND strings are associated with the same bit lines. For example, the NAND strings can be in the same plane that contains a number of bit lines. As an example, n copies of the data pattern can be programmed into "n" sets of memory cells, where n is an integer greater than 1, at one time.

In one embodiment, the data pattern is applied to the bit lines by applying either a program enable voltage or a program disable voltage to each respective bit line. In one embodiment, a select voltage is applied to drain select gates of n sets of NAND strings, where n is an integer greater than 1. As a result, each selected bit line is connected to n selected NAND chains. In addition, each selected bit line is connected to a different NAND string in each of the n sets of NAND strings. The system simultaneously applies a program pulse to control gates of n sets of memory cells while the selected bit lines are connected to the respective n selected NAND strings and the program enable voltage is applied to the selected bit lines to simultaneously convert the data pattern into each of the n sets to program the memory cells. For example, each of the n sets of memory cells is simultaneously programmed to a threshold voltage distribution associated with a data state.

In some embodiments, the control gates of each set of memory cells are connected by a conductive region. Each of these conductive regions can be quite large, such as a conductive plate in a three-dimensional NAND memory array. Therefore, there can be a large RC load associated with the conductive region. In one embodiment, multiple voltage generators are used to provide a common voltage to multiple conductive regions during simultaneous programming. In one embodiment, the system allows for a number of voltage generators based on the number of conductive regions generated during a programming operation that simultaneously programs the same data pattern in n sets of memory cells that are to receive the same voltage magnitude. This solves the technical problems of the RC load mentioned above.

Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program. Aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, or the like), or an embodiment combining software and hardware aspects, all of which are referred to generically herein as "circuit", " module”, “facility” or “system”. Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer-readable storage media storing computer-readable and/or executable program code.

Many of the hardware units described in this specification have been referred to as circuits to emphasize their implementation independence. For example, a circuit may be a custom VLSI circuit or gate array and may consist in whole or in part of an off-the-shelf semiconductor such as a logic chip, transistor, or other discrete component. Circuitry may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. Especially where multiple circuits are specified, they may in some cases share hardware elements; thus two different Circuits may be embodied as a single body of hardware configured via software or distinct hardware elements to perform the specified functions of the two circuits.

Computer program code for performing operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object-oriented programming language such as Python, Java, Smalltalk, C++, C#, Objective C or the like, conventional procedural programming languages, scripting languages and/or or other similar programming languages. The program code may be executed in part or in full on a user's computer(s) and/or on a remote computer or server via a data network or the like.

A component, as used herein, is a tangible, physical, non-transitory device. For example, a component can be implemented as a hardware logic circuit with custom VLSI circuits, gate arrays, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. A component may include one or more silicon-based integrated circuit devices (e.g., chips, dies, die-planes, packages) or other discrete electrical devices in electrical communication with one or more other components via electrical traces of a printed circuit board (PCB) or the like. Each of the modules described herein may alternatively be embodied or implemented by a component in certain embodiments.

Reference throughout this specification to “an embodiment,” “one embodiment,” “one embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is incorporated in at least one embodiment of the present invention revelation is included. Therefore, throughout this specification, the phrases "in one embodiment," "in the embodiment," and similar usage, where used, do not necessarily all refer to the same embodiment, but mean "one or more, but not all, embodiments," where applicable unless expressly stated otherwise. The terms "including," "comprising," "having," and variations thereof mean "including, but not limited to," unless expressly stated otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive unless expressly stated otherwise. The terms “a/s” and “the” also refer to “one or more” unless expressly stated otherwise.

Aspects of the present disclosure are described below with reference to schematic flowchart diagrams and/or schematic block diagrams of methods, devices, systems, and computer program products according to embodiments of the disclosure. It is understood that each block of the schematic flowchart and/or schematic block diagram, and combinations of blocks in the schematic flowchart and/or schematic block diagram, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable computing device to produce a machine such that the instructions, executed via the processor or other programmable computing device, produce means for implementing the functions and/or steps contained in the schematic flow diagrams and/or schematic block diagrams block or blocks are specified.

It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in sequence may actually be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order depending on the functionality involved. Other steps and methods that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated figures may be devised. Although various arrow styles and line styles may be used in the flowchart and/or block diagrams, they should be understood not to limit the scope of the respective embodiments. For example, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the illustrated embodiment.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, other aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements of consecutive figures. The same reference numbers may refer to the same elements in the figures, including alternative embodiments of the same elements.

1A 1 is a block diagram of one embodiment of a system 100 having a concurrent programming component 150 for a non-volatile memory device 120. The concurrent programming component 150 may be part of and/or in communication with a non-volatile media controller 126 (as described in 1A shown), a non-volatile memory element 123, a device driver, or the like. The concurrent programming component 150 may operate in a non-volatile memory system 102 of a computing device 110 that may include a processor 111 , volatile memory 112 , and a network interface 113 . Processor 111 may be one or more central processing units, one or more general purpose processors, one or more application specific processors, one or more virtual processors (e.g., computing device 110 may be a virtual machine operating in a host), one or more Include processor cores or the like. Network interface 113 may include one or more network interfaces configured to enable computing device 110 and/or non-volatile storage media controller 126 to be communicative with a communications network 115, such as an Internet Protocol (IP) network, a storage area network (SAN), a wireless network , a wired network or the like to couple.

The non-volatile storage device 120 may be located in one or more different locations relative to the computing device 110 in various embodiments. In one embodiment, non-volatile memory device 120 includes one or more non-volatile memory elements 123, such as semiconductor chips or packages or other integrated circuit devices, disposed on one or more printed circuit boards, memory packages, and/or other mechanical and/or electrical support structures. For example, the non-volatile storage device 120 may include one or more direct inline memory module (DIMM) cards, one or more add-in cards and/or daughter cards, a solid-state drive (SSD), or other hard-disk device and/or or may have a different memory and/or storage form factor. The non-volatile storage device 120 may be integrated into and/or mounted on a motherboard of the computing device 110, installed in a port and/or slot of the computing device 110, installed on another computing device 110 and/or a dedicated storage device in the communications network 115, be in communication with the computing device 110 via an external bus (e.g., an external hard drive), or the like.

Non-volatile memory device 120 may, in one embodiment, be disposed on a memory bus of processor 111 (e.g., on the same memory bus as volatile memory 112, on a different memory bus than volatile memory 112, instead of volatile memory 112, or the like). . In another embodiment, the non-volatile storage device 120 on a peripheral bus of the computing device 110, such as a Peripheral Component Interconnect Express bus (PCI Express or PCIe bus), a Serial Advanced Technology Attachment bus (SATA bus), a Parallel Advanced Technology Attachment bus (PATA bus), Small Computer System Interface (SCSI) bus, FireWire bus, Fiber Channel connection, Universal Serial Bus (USB), PCIe Advanced Switching bus (PCIe-AS-Bus) or the like. In another embodiment, the non-volatile storage device 120 may be deployed on a communications network 115, such as an Ethernet network, an Infiniband network, SCSI-RDMA over a communications network 115, a storage area network (SAN), a local area network, LAN) a wide area network (WAN) such as the Internet, another wired and / or wireless network or the like.

The computing device 110 may further include a non-transitory computer-readable storage medium 114 . Computer-readable storage medium 114 may include executable instructions configured to cause computing device 110 (e.g., processor 111) to perform steps of one or more of the methods disclosed herein. Alternatively or additionally, the component for the simultaneous Programming 150 may be embodied as one or more computer-readable instructions stored on computer-readable storage medium 114 .

The non-volatile memory system 102 includes a concurrent programming component 150 in the illustrated embodiment. As will be further described, the simultaneous programming component 150 may be configured to electrically select a bit line for a set of non-volatile memory cells arranged in the same block or in two different blocks to electrically connect separate word lines corresponding to memory cells and applying a programming pulse to the connected word lines to simultaneously program the memory cells corresponding to each word line to a common target threshold voltage. The memory cells may optionally be in two different blocks, which may be physically separated within the memory array to minimize the likelihood that a fault occurring in one of the memory cells will also be present in the other memory cell. As used herein, "electrically selecting" includes applying an electrical potential to enable a power source to transfer to a component. In one example, electrically selecting includes adjusting one or more hardware components to connect the bitline to another component.

Simultaneous programming component 150 can program separate cells in separate blocks at the same time with the same data and to a common target threshold voltage. In some embodiments, writing the same data to separate blocks concurrently provides increased performance because if one block fails to store the written data, the data can be recovered from the other block without requesting the data from non-volatile media controller 126 again. This allows the system 100 to transition to other operations more quickly because fewer requests from the non-volatile storage media controller 126 are required.

Furthermore, in some embodiments, a cell compression operation that uses two copies of the same data can use the same data in the separate blocks without requiring the non-volatile storage media controller 126 to separately write another copy of the data. This simplifies the operations performed by the non-volatile storage media controller 126 involved in MLC, TLC, QLC programming, or the like.

In one embodiment, concurrent programming component 150 writes the same data into blocks located in physically separate areas. The individual areas can be defined by distance, a number of blocks between the selected blocks and/or the like. As can be appreciated by those skilled in the art, an array of NAND cells can fail in certain physical locations or areas. Writing the same data to physically remote areas of the NAND array provides increased protection against failure because if a particular section of the NAND array fails, a second copy of the data located in a different physical location is likely to remain unaffected. As described herein, in some embodiments, this benefit does not cost additional operations because the concurrent programming component 150 writes both copies of the same data at the same time (e.g., writing the same data to the second cell costs compared to writing the data to the first cell no more time).

In another embodiment, the concurrent programming component 150 writes the same data into two separate cells in the same chain. Simultaneously programming multiple cells in a chain to a common target threshold voltage can provide benefits similar to writing to separate blocks. In addition to the advantages previously described, simultaneously programming two consecutive cells in a chain to a common target threshold voltage can reduce electrical interference because the two word lines corresponding to the same programmed cells are biased at the same time. Furthermore, the word line to word line capacitance is reduced in this scenario. Simultaneous programming component 150 may write the same data to cells in the chain at different locations to achieve physical separation, as previously described in connection with writing to separate blocks simultaneously.

In another embodiment, after verifying that a first cell was programmed correctly, the concurrent programming component 150 may discard the data in the second cell. Simultaneous programming component 150 may accomplish this by erasing the second cell, marking the second cell for reuse, or overwriting the second cell with different data. Additionally or alternatively, the data may be retained in both cells until used, for example for a cell aggregation operation in which the data is combined with other data and in a multi-level cell (MLC) or the like (e.g. TLC, QLC, etc.).

In some embodiments, an SLC-TLC compression process (an example of a cell compression process) may be used after the data for a multi-level cell (MLC), such as a tri-level cell (TLC), has been temporarily stored in a series of SLC cells. In some embodiments, three pairs of SLC cells may be used to store the data for the TLC, with each pair storing identical versions of the data for a single bit to be stored in the TLC for data redundancy purposes. With SLC-TLC compression, the data of at least one SLC cell can be read from each of the three pairs of SLC cells and encoded into one bit within the TLC, such that three bits are encoded in the TLC. Optionally, the bits encoded in the TLC can be compared to those of the three SLC pairs to confirm that the TLC was programmed correctly. Once the TLC has been properly programmed, the SLC can be erased. The same SLC cells can then be used as a buffer for TLC programming with built-in temporary data redundancy.

After cell compression, the first and second cell can both be deleted. A new programming operation can be used to program the cells with new data, e.g. B. for use in another SLC-TLC compression process. The combination of erasing data from the cells and programming the cells with new data (or choosing not to program the cells if the new data to be stored implies leaving the cells in the erased or unprogrammed state) is called "overwriting". of the content of the cells.

As used herein, a "block" includes a set of wordlines, with each wordline connected to a set of memory cells. In one embodiment, a "block" comprises a portion of an array of memory cells (e.g., non-volatile memory elements) where the memory cells are connected such that all of the memory cells in the block can be erased in a single operation. Those skilled in the art will appreciate that a block is the smallest unit of memory cells that can be erased using a single memory/memory erase command and may be referred to as "erase blocks" in certain embodiments. In certain embodiments, a "block" includes a set of chains of non-volatile memory elements.

As used herein, a "NAND string" includes a set of NAND memory cells electrically connected in series to a bit line via a NAND channel. A "NAND channel" includes an electrical connection that connects memory cells in a NAND string to their respective bit lines and source lines (e.g. 5 : channel 665). The control gate of a memory cell on a NAND string may be connected to a conductive region to allow voltages to be applied to the control gate. As used herein, a "bit line" includes a line of conductive material that is connectable to a voltage source and connectable (e.g., via channels) to the ends of NAND strings. In one example, a block includes 64 strings, and a separate bit line may be connected to each of the 64 strings. In another example, a bitline traverses many blocks and is connectable to corresponding strings in each block.

As used herein, "cross" includes two components (e.g., word lines, bit lines, memory cells, etc.) that are physically arranged so that they can electrically affect each other. A wordline crossing a memory cell means that the wordline is electrically connected to the memory cell, so applying a programming pulse to the wordline programs the memory cell.

As used herein, "electrically connectable" includes two components (e.g., word lines, bit lines, memory cells, etc.) that are configured and/or positioned to be readily connected together to allow electrical current to flow between them. Electrical connectivity may include using a secondary component to connect the electrically connectable components. In one example, a gate transistor may be configured to electrically connect a wordline to a voltage source. Thus, the word line and the voltage source are electrically connectable to each other, but are not electrically connected to each other unless the gate transistor connects them together.

As used herein, "simultaneously program", "simultaneously program", "simultaneously apply a program (ier) pulse", or the like means that a programming pulse is applied to two or more separate memory cells substantially simultaneously. "Substantially simultaneously" means that the two or more cells are programmed by the same programming pulse, although the memory cells may not receive the programming pulse at exactly the same time due to physical locations or electrical spacing. In one example, due to physical distance from a source for the Pro grammierimpuls a first memory cell receives the programming pulse before a second memory cell. In another embodiment, the two or more memory cells receive the programming pulse simultaneously, but a first memory cell is successfully programmed before a second memory cell. Furthermore, simultaneously programming multiple memory cells to a common target threshold voltage means that a common voltage is applied to each of the memory cells substantially simultaneously. Of course, as can be appreciated by those skilled in the art, this need not mean that the memory cells will be successfully programmed to a target threshold voltage by the same pulse.

In one embodiment, the component for simultaneously programming 150 may include logic hardware of one or more non-volatile memory devices 120, such as a non-volatile media controller 126, a non-volatile memory element 123, a device controller, a field-programmable gate array (FPGA) or other programmable logic, firmware for an FPGA, or other programmable logic, microcode for execution on a microcontroller, an application specific integrated circuit (ASIC), or the like. In another embodiment, concurrent programming component 150 may include executable software code, such as a device driver or the like, stored on computer-readable storage medium 114 for execution on processor 111 . In another embodiment, the concurrent programming component 150 may include a combination of both executable software code and logic hardware.

In one embodiment, the concurrent programming component 150 is configured to receive memory requests from a device driver or other executable application via a bus 125 or the like. The concurrent programming component 150 may further be configured to transfer data to/from a device driver and/or memory clients 116 via the bus 125 . Accordingly, in some embodiments, concurrent programming component 150 may include and/or be in communication with one or more direct access memory (DMA) modules, remote DMA modules, bus controllers, bridges, buffers, etc. to facilitate the transfer of memory requests and associated data to allow. In another embodiment, the concurrent programming component 150 may receive memory requests as an API call from a memory client 116, as an IO CTL command, or the like.

According to various embodiments, a non-volatile storage media controller 126 in communication with one or more program sequencing components 140 may manage one or more non-volatile storage devices 120 and/or non-volatile storage elements 123 . The non-volatile memory device(s) 120 may include recording, storage, and/or storage devices, such as solid-state memory device(s) and/or semiconductor memory device(s), arranged and/or partitioned as multiple addressable media storage locations. As used herein, a media location refers to any physical unit of storage (e.g., any amount of physical storage media on a non-volatile storage device 120). Storage units may include, but are not limited to, pages, extents, blocks, sectors, collections or sets of physical storage locations (e.g., logical pages, logical blocks), or the like.

A device driver and/or non-volatile storage medium controller 126 may present a logical address space 134 to storage clients 116 in certain embodiments. As used herein, a logical address space 134 refers to a logical representation of memory resources. The logical address space 134 may include multiple logical addresses (e.g., range). As used herein, a logical address refers to any identifier for referencing a storage resource (e.g., data), including but not limited to: a logical block address (LBA), a cylinder/head/sector (Cylinder/Head /Sector, CHS) address, a file name, an object identifier, a globally unique identifier (GUID), a hash code, a signature, an index entry, a region, a scope, or the like.

A device driver for the non-volatile storage device 120 may maintain metadata 135, such as a logical-to-physical address mapping structure, to map logical addresses of the logical address space 134 into media storage locations on the non-volatile storage device(s) 120 . A device driver may be configured to provide storage services to one or more storage clients 116 . Storage clients 116 may include local storage clients operating on computing device 110 and/or remote storage clients 116 accessible via communications network 115 and/or network interface 113. The storage clients 116 may include, but not being limited to: operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

A device driver may be communicatively coupled to one or more non-volatile memory devices 120 . The one or more non-volatile storage devices 120 may include different types of non-volatile storage devices, including but not limited to: solid state storage devices, solid state storage devices, SAN storage resources, or the like. The one or more non-volatile storage devices 120 may include one or more corresponding non-volatile storage media controllers 126 and non-volatile storage media 122 . A device driver may provide access to the one or more non-volatile memory devices 120 via a conventional block I/O interface 131 . In addition, a device driver can provide access to enhanced functionality via the SCM interface 132 . Metadata 135 may be used to manage and/or track data operations performed by any of block I/O interface 131, SCM interface 132, cache interface 133, or other related interfaces.

Cache interface 133 may expose cache specific features that may be accessed via a device driver for non-volatile memory device 120 . Also, in some embodiments, the SCM interface 132 presented to the storage clients 116 provides access to data transformations implemented by the one or more non-volatile storage devices 120 and/or the one or more non-volatile storage media controllers 126 .

A device driver may present a logical address space 134 to storage clients 116 via one or more interfaces. As discussed above, the logical address space 134 may include a plurality of logical addresses that each correspond to media locations of the one or more non-volatile storage devices 120 . A device driver may manage metadata 135 including any associations between logical addresses and media locations or the like.

A device driver may further include a non-volatile memory device interface 139 configured to transmit data, commands, and/or requests to the one or more non-volatile memory devices 120 via a bus 125, which may include, but is not limited to: a memory bus of a processor 111, a PCI Express or PCIe bus (Peripheral Component Interconnect Express), a serial ATA bus (Advanced Technology Attachment), a parallel ATA bus, a SCSI interface (Small Computer System Interface), Fire Wire, Fiber Channel, a Universal Serial Bus (USB), a PCIe-AS-Bus (PCIe Advanced Switching), a communication network 115, Infiniband, SCSI-RDMA or the like. The interface of a non-volatile storage device 139 may communicate with the one or more non-volatile storage devices 120 using input-output control commands (EA-CTL), EA-CTL command extension(s), direct remote memory access, or the like.

Network interface 113 may include one or more network interfaces configured to communicatively couple computing device 110 and/or non-volatile storage media controller 126 to a communications network 115 and/or to one or more remote network-accessible storage clients 116 . Storage clients 116 may include local storage clients operating on computing device 110 and/or remote storage clients 116 accessible via communications network 115 and/or network interface 113. Non-volatile storage media controller 126 is part of and/or in communication with one or more non-volatile storage devices 120. Although 1A Although FIG. 1 illustrates a single non-volatile memory device 120, the disclosure is not so limited and may be adapted to accommodate any number of non-volatile memory devices 120. FIG.

The non-volatile memory device 120 may include one or more non-volatile memory elements 123 of non-volatile memory media 122, which may include but not be limited to: ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, ovonic unified memory, chalcogenide RAM or C-RAM), NAND flash memory (eg, 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano-random access memory (Nano-RAM or NRAM), wire-based nano-crystal memory, silicon oxide based sub-10 nanometer process memory, graphene memory, silicon oxide nitride oxide silicon (SONOS), programmable metallization cell (PMC), line-bridging RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g. hard disk). , tape), optical storage media and/or the like. The one or more non-volatile storage elements 123 of non-volatile storage media 122 include, in certain embodiments, storage class memory (SCM). Examples herein relate to a NAND memory, or in particular an SLC NAND memory; however, the systems and methods provided herein may be applied to other types of memory, including but not limited to those listed above.

While legacy technologies such as NAND flash may be block and/or page addressable, in one embodiment, memory class memory is byte addressable. In other embodiments, memory-class memory may be faster and/or have longer endurance (e.g., endurance) than NAND flash; may be lower cost, use less power, and/or have higher storage density than DRAM; or provide one or more other advantages or improvements over other technologies. For example, the memory class memory may be one or more non-volatile memory elements 123 of ReRAM, memristor memory, programmable metallization cell memory, phase change memory, nano-RAM, wire-based nanocrystal memory, silicon oxide-based sub-10 nanometer process memory, graphene memory, SONOS memory, MANOS memory, PMC memory , CBRAM, MRAM and/or variations thereof.

While non-volatile storage medium 122 is referred to herein as a "storage medium," in various embodiments, non-volatile storage medium 122 may more generally include one or more non-volatile recording media capable of recording data that may be referred to as non-volatile storage medium, non-volatile storage medium, or the like . Further, in various embodiments, the non-volatile memory device 120 may include a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, or the like.

The non-volatile storage medium 122 may include one or more non-volatile storage elements 123, which may include, but is not limited to, chips, packages, planes, dies, or the like. A non-volatile storage media controller 126 may be configured to manage data operations on the non-volatile storage media 122 and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, or the like. In some embodiments, the non-volatile storage medium controller 126 is configured to store data and/or read data from the non-volatile storage medium 122, transfer data to/from the non-volatile storage device 120, and so on.

The non-volatile storage medium controller 126 may be communicatively coupled to the non-volatile storage medium 122 via a bus 127 . Bus 127 may include an I/O bus for communicating data to/from non-volatile memory elements 123 . Bus 127 may further include a control bus for communicating addressing and other command and control information to non-volatile memory elements 123 . In some embodiments, bus 127 may communicatively couple non-volatile storage elements 123 in parallel with non-volatile storage medium controller 126 . This parallel access may allow the non-volatile storage elements 123 to be managed as a group, thereby forming a logical storage element 129 . The logical storage element may be divided into corresponding logical storage units (e.g. logical pages) and/or logical storage areas (e.g. logical blocks). The logical storage units may be formed by logically combining physical storage units from each of the non-volatile storage elements.

Non-volatile storage media controller 126 may organize a block of word lines within non-volatile storage element 123 in certain embodiments using addresses of the word lines such that the word lines are logically organized in a monotonically increasing sequence (e.g., decoding and/or translating addresses for word lines in a monotonically increasing sequence or the like). In another embodiment, word lines of a block within a non-volatile memory element 123 may be physically arranged in a monotonically increasing sequence of word line addresses, where sequentially addressed word lines are also physically adjacent (e.g., WL0, WL1, WL2, ...WLN).

Non-volatile storage media controller 126 may include and/or be associated with a device driver executing on computing device 110 . A device driver may provide storage services to storage clients 116 via one or more interfaces 131, 132, and/or 133. In some embodiments, a device driver provides a block I/O interface 131, or device interface, through the storage clients 116 perform block-level I/O operations. Alternatively or additionally, a device driver may provide a storage class storage (SCM) interface 132 that may provide storage clients 116 with other storage services. In some embodiments, SCM interface 132 may include extensions to block I/O interface 131 (e.g., storage clients 116 may access SCM interface 132 via extensions or additions to block I/O interface 131 access). Alternatively or additionally, the SCM interface 132 may be provided as a separate API, service, and/or library. A device driver may further be configured to provide a cache interface 133 for caching data using the non-volatile memory system 102 .

A device driver may further include a non-volatile storage device interface 139 configured to transfer data, commands, and/or queries to the non-volatile storage media controller 126 via a bus 125, as described above.

1B 12 illustrates one embodiment of a non-volatile memory device 210 that may include one or more memory dies 212 or chips. Memory die 212 includes, in some embodiments, a memory array 200 (two-dimensional or three-dimensional) of memory cells, die controller 220, and read/write circuitry 230A/230B. In one embodiment, access to the memory array 200 by the various peripheral circuits is implemented in a symmetrical manner on opposite sides of the array such that access line and circuit densities on each side are reduced by half. The read/write circuits 230A/230B, in another embodiment, include multiple read blocks 250 that allow a page of memory cells to be read or programmed in parallel.

Memory array 200 is addressable by word lines via row decoders 240A/240B and by bit lines via column decoders 242A/242B in various embodiments. In some embodiments, a controller 244 is included in the same non-volatile storage device 210 (e.g., a removable memory card or enclosure) as the one or more storage dies 212 . Commands and data are communicated between the host and the controller 244 over lines 232 and between the controller and the one or more memory dies 212 over lines 234 . An implementation may include multiple memory dies 212 .

Die controller 220 may share a die with memory array 200 such that die controller 220 forms an "on-die" controller. Die controller 220 may take any form known in the art, including but not limited to microprocessors, microcontroller units (MCUs), finite state machines (FSMs), central processing units (CPUs), graphics processing units (GPUs), and the like; an "on-die control" or a "control" may both refer to any of them.

Die controller 220 cooperates with read/write circuitry 230A/230B to perform memory operations on memory array 200 in one embodiment. The die controller 220 includes a concurrent programming component 150 , a state machine 222 , and an on-chip address decoder 224 in certain embodiments. In one embodiment, state machine 222 forms a portion of concurrent programming component 150. In another embodiment, controller 244 forms a portion of concurrent programming component 150. Controller 244 may optionally be located on one or more of memory die 212 or reside on a separate die from memory die 212.

In some embodiments, each of the memory arrays 200 may be a single-level cell (SLC) NAND array in which each of the non-volatile memory elements 123, or "non-volatile memory cells," is programmable by applying a programming pulse to the cell. Each of the memory arrays 200 can also be programmed with a single pulse, achieving speeds approaching the theoretical limit for NAND programming. According to the prior art, each of the non-volatile memory elements 123 may comprise an electrically insulating element such as a gate oxide layer or tunnel oxide layer, whereby electrons are selectively movable, and which provides a gate function by allowing the cells to be programmed with a charge and the maintain the charge with which they are programmed. An “insulating element” or “insulating layer” may include any structure configured to allow electrical charge to selectively enter and/or exit a non-volatile memory cell.

The term "programming pulse" or "programming pulse" refers to an electrical pulse applied to the non-volatile memory elements 123 that causes the non-volatile memory elements 123 to enter or approach a programmed state. This may be a peak voltage value, an RMS voltage, an average voltage of a pulse, a voltage value of a specific pulse in a pulse train, and/or the like. In another embodiment, a programming pulse involves the application of a current including a peak current, an RMS current value, an average current of a pulse, a particular current sequence, and/or the like. The "programming pulse" is not limited to NAND memory, but can be applied to any non-volatile memory that is programmed by applying an electrical potential. Thus, programming settings such as the programming pulse may be adjusted using the systems and methods of the present disclosure in non-volatile memory types, including but not limited to the non-volatile memory types listed in the background section above.

The term "verify pulse" includes an electrical pulse applied to a non-volatile memory element 123 (e.g., a memory cell), where the flow of current indicates whether the memory cell has been sufficiently programmed. A verify pulse may or may not be the same for different memory cells.

Similarly, different "sampling settings" can be used to sample the contents of one or more non-volatile storage elements 123 of memory array 200 . The term "sensing" refers not only to non-volatile memory structures with cells that hold electrical charge, but also to non-volatile memory types that use a different storage mechanism. For example, some types of non-volatile memory use a voltage and/or current to sense the resistance of the cell (rather than the stored charge). With other non-volatile memory types, current flow through the cell is detected; a current level above or below a certain threshold may indicate that a cell is programmed. If the contents of individual cells are to be determined, this can be referred to as "reading" the cells. However, "sensing" the contents of a non-volatile memory array may also include reading the contents of individual cells or detecting individual or common characteristics of the cells, e.g. B. whether the voltage or resistance of the cells is above or below a predetermined threshold.

In some embodiments, changing the programming settings may include reducing the programming voltage applied to the non-volatile memory elements 123 one or more times during the operational life of the non-volatile memory device 120 to extend the useful life of the non-volatile memory device 120 and reduce the likelihood of erroneous data reads due to over-programming of the cells to reduce.

State machine 222, in one embodiment, provides chip-level control of memory operations. The on-chip address decoder 224 provides an address interface to convert the address used by the host or a memory controller to the hardware address used by the decoders 240A, 240B, 242A, 242B. In certain embodiments, state machine 222 includes an embodiment of concurrent programming component 150 .

In one embodiment, die controller 220, concurrent programming component 150, on-chip address decoder 224, state machine 222, decoder 242A, decoder 242B, decoder 240A, decoder 240B, read/write circuitry 230A, read/write circuitry 230B, and/or controller 244 may be referred to individually or in any combination as one or more management circuits. In one embodiment, the die controller 220 includes one of a select circuit 282, a program circuit 284, and a verify circuit 286. FIG.

In another embodiment (in 1B not shown), the selection circuit 282, the programming circuit 284 and the verification circuit 286 are implemented as part of the controller 244. In another embodiment, die controller 220 includes one or more of circuits 282,284,286 and controller 244 includes one or more of circuits 282,284,286. Therefore, the various circuits 282, 284, 286 are not required to be implemented on either the die controller 220 or the controller 244.

The selection circuit 282 may be configured to electrically select a first set of memory cells in the first erase block and a second set of memory cells in the second erase block. In one example, non-volatile storage media controller 126 is set to write data to a first erase block and to a given depth of memory cells (e.g., the top row of memory cells in the block or another row). Simultaneous programming component 150, in another embodiment, sets up a set of select gate transistors to connect bit lines for strings enclosing the memory cells and a programming pulse source to word lines enclosing the memory cells correspond to memory cells. Also, the selection circuit 282 may similarly connect word lines in a second erase block to the voltage source so that when the voltage source is applied, the voltage is simultaneously applied to both the first word line in the first erase block and the second word line in the second erase block. In a specific example, select circuit 282 sets one or more select gate transistors to connect word lines to source select gates and drain select gates.

In certain embodiments, selection circuit 282 selects word lines corresponding to the same row in the first erase block with the same row in the second erase block. However, this is not necessarily the case since the selection circuit 282 can select any word line in the block.

In another embodiment, the programming circuit 284 is configured to apply a programming pulse with an increased voltage to memory cells of the first word line and memory cells of the second word line in order to simultaneously write the same data in a single pulse to the memory cells in the first erase block and the memory cells in the second erase block write. In some embodiments, the first wordline and the second wordline are separate wordlines in different physical locations. In other embodiments, the first wordline and the second wordline are the same physical wordline. In one example, the first erase block and the second erase block may have adjacent erase blocks and share the same physical word line, while the memory cells being programmed simultaneously have different memory channels.

In another embodiment, programming circuitry 284 is configured to program memory cells in three or more erase blocks simultaneously. In one embodiment, the programming circuit 284 is configured to apply a programming pulse with an increased voltage to memory cells connected to a first word line in a first erase block, to memory cells connected to a second word line in a second erase block, and to memory cells that connected to a third word line in a third erase block to simultaneously write the same data in a single pulse to the memory cells in the first erase block, the memory cells in the second erase block and the memory cells in the third erase block. In another example embodiment, programming circuitry 284 is configured to program memory cells in four erase blocks simultaneously.

In some embodiments, programming circuitry 284 is configured to simultaneously program memory cells in different erase blocks to one bit per memory cell (SLC). In some embodiments, programming circuitry 284 is configured to simultaneously program memory cells in different erase blocks to two bits per memory cell. In some embodiments, programming circuitry 284 is configured to simultaneously program memory cells in different erase blocks to three bits per memory cell. In some embodiments, programming circuitry 284 is configured to simultaneously program memory cells in different erase blocks to four bits per memory cell. In some embodiments, programming circuitry 284 is configured to simultaneously program memory cells in different erase blocks to five bits per memory cell. In some embodiments, the simultaneous programming of the memory cells in different erase blocks is performed without verification.

In one embodiment, verify circuit 286 is configured to apply a verify pulse to the word lines that are currently programmed. For example, verify circuit 286 is configured to apply a verify pulse to the word lines in various erase blocks that are being programmed. In one embodiment, the verify circuit 286 is configured to apply a verify pulse to a first wordline and a second wordline. However, verify circuit 286 may apply a verify pulse to more than two word lines for cases where memory cells connected to more than two word lines are programmed simultaneously.

The verify circuit 286 prepares sample blocks 250 connected to bit lines for a verify operation. The verify circuit 286 then senses an amount of current flowing from the sense amplifiers through the memory cells that received the programming pulse. In one embodiment, if current flows through one of multiple cells that are programmed and connected to the same bitline in response to the application of the verify pulse, then the threshold voltage at one of the cells has not reached the target value. For example, if two cells are programmed to the same target value and current flows in one of the two cells in response to the application of the verify pulse, then the threshold voltage of one or both cells has not reached the target value. As a result, at least one of the cells has not been adequately programmed. If one or If several of the cells have not met the target value, the verification circuit 286 may initiate another programming procedure as described herein. In one embodiment, sensing an amount of current includes determining whether current is flowing. In an example embodiment, sensing an amount of current includes charging a sense capacitor to a sense voltage, connecting the sense capacitor to the bitline for a sense period (integration time) to allow the bitline current (if any) to discharge the sense capacitor, and then sensing a voltage at capture capacitor on. If the voltage across the sense capacitor has fallen below a clipping voltage, this indicates that the threshold voltage for at least one of the cells has not reached the target value.

In another embodiment, sensing the current includes measuring the current and determining whether the measured current is above a current threshold (eg, 0 amps). In one example, current sensing includes sensing the current on a bit line connected to NAND strings enclosing the memory cells to be programmed. In this embodiment, while current may flow through the bit line because the bit line may be connected to multiple NAND strings, it may not be known which NAND string the current is flowing through.

In another example, current sensing includes current sensing at a current sensing component attached to the NAND chain. In another embodiment, the current sensing includes current sensing at the respective memory cells. Of course, a wide variety of different architectures may be apparent to those skilled in the art and current sensing may be accomplished in different ways.

In one embodiment, programming circuitry 284 programs the first memory cell and separately the second memory cell in response to the current sensing in response to application of the verify pulse.

The separate programming method may include applying programming loops at successively increasing voltages to the first memory cell, as may be apparent to those skilled in the art. In another embodiment, the separate programming method includes applying the programming loops to the second memory cell after applying the programming loops to the first memory cell and verifying that the first cell is correctly programmed. A "raised" programming pulse indicates that a previous programming pulse was not sufficient to correctly program a particular memory cell, and a programming pulse is "raised" (e.g., at a higher voltage) to attempt the memory cell again to program. Thus, "correctly programmed" means that the application of a programming pulse has resulted in a threshold voltage level for a particular memory cell being above a threshold or within a threshold range. A specific example of such a series of programming pulses is in 8th shown and described below.

In another embodiment, the concurrent programming component 150 is configured to determine whether the first and/or second memory cell is correctly programmed and, in response to determining that the first and/or second memory cell is correctly programmed, overwriting the to initiate the first and/or second memory cell. In some examples, the concurrent programming component 150 marks the second memory cell for reuse, initiates erasing of the second memory cell, repurposes the second memory cell, and/or the like.

In one embodiment, the controller is further configured to read data from one of the first memory cell and the second memory cell and use the data to program a multi-level cell in a cell compression operation. As previously described, given two copies of the same data, the concurrent programming component 150 is able to perform a multi-level cell SLC-TLC compaction operation without having to make a copy of the data stored in the cells. The data stored in the first and second memory cell can thus be intended for temporary use. Having two copies of the data can help to avoid data loss in the time between initially storing the data in the storage array 200 and using the data in the SLC-TLC compression process.

In another embodiment, the simultaneous programming component 150 uses two memory cells along a single NAND chain. In this embodiment, a NAND chain includes a set of memory cells. The NAND chain may be connected to a bit line and crosses a separate word line for each of the two memory cells along the NAND chain. Similarly, as previously described, the simultaneous programming component 150 may select two separate word lines representing two separate memory cells along the correspond to a NAND chain to be programmed simultaneously to a common target threshold voltage.

In one embodiment, the selected word lines can be optionally separated from each other so that they are at different locations along the NAND chain. For example, the selected word lines can be at opposite ends of the NAND chain. As previously described, such an offset can help reduce the risk of data loss by reducing the likelihood that the memory cells will be affected by a common fault.

In another embodiment, the simultaneous programming component 150 connects separate word lines in more than two different erase blocks, wherein by applying a programming pulse to the connected word lines, the programming pulse is applied to memory cells in each of the different erase blocks.

In this embodiment, select circuit 282 electrically selects the bit line by turning on a select gate transistor or by using one or more other components, as may be apparent to those skilled in the art. The selection circuit 282 then electrically connects a first word line corresponding to a first memory cell in the NAND chain to a second word line corresponding to a second memory cell in the NAND chain. The programming circuit 284 then applies a programming pulse to the connected word lines to simultaneously write the data to the first memory cell and the second memory cell in the NAND chain.

In another embodiment, after the programming circuit 284 simultaneously applies the programming pulse to the first word line and the second word line, the verify circuit 286 applies a verify pulse to the first word line and the second word line to determine whether the first memory cell and/or the second memory cell has been programmed correctly. In response to the current flow through the NAND chain, the verification circuit 286 determines that one or more of the first memory cell and the second memory cell have not been fully programmed (e.g., have an insufficient threshold voltage). In response to this determination, verification circuit 286 may then begin a subsequent programming process for each memory cell in any manner, as described herein.

In some embodiments, verification circuit 286 does not determine whether a particular memory cell has been programmed correctly, but rather determines that one of the memory cells has not been programmed correctly by current sensing in the bit line shared by both memory cells. In response to this determination, the programming circuit 284 reprograms the first and second memory cells. Because both memory cells are programmed, it may not be necessary to determine which memory cell or cells were programmed incorrectly.

In one embodiment, the first memory cell in the NAND chain and the second memory cell in the NAND chain are consecutive memory cells in the NAND chain. Although the physical skew between the memory cells storing duplicate data provides advantages, programming consecutive word lines in a NAND string to a common target threshold voltage simultaneously also has advantages. In some embodiments, two word lines storing the same data may tend to have a lower likelihood of electromagnetic interference with each other.

2A 12 depicts blocks of memory cells in an exemplary 2D configuration of memory array 200. FIG 1B The memory array 200 may include many blocks. Each example block 202, 204 includes a number of NAND strings and corresponding bit lines, e.g. B. BL0, BL1,.. shared between the blocks. Each NAND string is connected to a drain select gate (SGD) at one end, and the control gates of the drain select gates are connected by a common SGD line. The NAND chains are connected at their other end to a source select gate SGS which in turn is connected to a common source line 206 . Sixteen word lines, for example WL0 through WL15, run between the source select gates and the drain select gates.

In some cases, dummy word lines that do not contain user data may also be used in the memory array adjacent to the select gate transistors (SGS/SGD). Such dummy word lines can shield an edge data word line from certain edge effects. In some examples, dummy word lines are positioned adjacent to the SGD and SGS lines. Thus, in the embodiment 2A Dummy word lines WLD0 adjacent to the SGS lines of each of the blocks 202, 204 and dummy word lines WLD1 adjacent to the SGD lines of each of the blocks 202, 204 positioned. In other examples, multiple (e.g., two or three) dummy wordlines are positioned between wordlines WL0 through WL15 and each of the SGD and SGS lines. In some embodiments, the dummy word lines are not erased with the rest of the block 202, 204 to which they belong. Thus, any data stored on the dummy word lines persists during erase operations, which are commonly used to erase user data, and can only be changed by programming bits of the dummy word lines that have not yet been programmed.

As in 2A , the bit lines BL0, BL1, ... define columns of the word lines of each block 202, 204. In addition to the bit lines BL0, BL1, ... storing user data, each block 202, 204 has several spare columns SC0, SC1, ... , which can be used for various purposes such as replacing the bit lines BL0, BL1, ... which are or will be unusable. Therefore, in some cases, the replacement columns do not store any user data.

Each of the word lines of memory array 200 may have a word line driver 208 that decodes and/or otherwise processes the data on that word line. Therefore, in 2A the word lines WL0 through WL15 have word line drivers 208 as shown. The word line drivers 208 can be placed in the in 1B row decoders 240A/240B shown.

The non-volatile memory elements 123 may include a wide variety of technologies, including but not limited to all of the non-volatile memory types referred to in the background section above. One type of non-volatile memory that can be provided in the memory array is a charge trapping memory cell. Other types of non-volatile memory can also be used. For example, a charge trapping memory cell may use a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. In one example, a three-layer silicon oxide, silicon nitride, and silicon oxide ("ONO") dielectric is sandwiched between a conductive control gate and a semiconductor. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a confined area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a way that is detectable. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split gate configuration, in which a doped polysilicon gate extends over a portion of the memory cell channel, thereby forming a separate select transistor.

Another approach uses NROM cells. For example, two bits are stored in each NROM cell in which an ONO dielectric layer extends across the channel between source and drain diffusion. The charge for one data bit is localized in the dielectric layer adjacent the drain and the charge for the other data bit is localized in the dielectric layer adjacent the source. Multi-state data storage is achieved by separately reading binary states of the physically separate charge storage regions within the dielectric. Other types of non-volatile memory are also known.

2 B FIG. 12 shows a cross-sectional view of exemplary charge-trapping memory cells in NAND strings as an example of memory cells in FIG 2A The view is in a word line direction of memory cells having a flat control gate and charge trapping regions as a 2D example of memory cells in the memory array 200. FIG 1B exhibit. The charge trapping memory can be used in a NOR and NAND flash memory device. This technology uses an insulator such as SiN film to store electrons, as opposed to floating gate MOSFET technology which uses a conductor such as doped polycrystalline silicon to store electrons. For example, a word line (WL) 423 spans NAND strings that include channel regions 406, 416, and 426, respectively. Sections of the word line provide control gates 402, 412 and 422. Below the word line is an inter-poly dielectric (IPD) layer 428, charge trapping layers 404, 414, and 424, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge trapping layer extends continuously in a respective NAND -Chain.

A memory cell 400 includes the control gate 402, the charge trapping layer 404, the polysilicon layer 405 and a portion of the channel region 406. FIG. A memory cell 410 includes the control gate 412, the charge trapping layer 414, a polysilicon layer 415 and a portion of the channel region 416. FIG. A memory cell 420 includes the control gate 422, the charge trapping layer 421, the polysilicon layer 425 and a portion of the channel region 426. FIG.

An advantage of a flat control gate is that the charge trapping layer can be made thinner than a floating gate. In addition, the memory cells can be placed closer together.

2C displays a cross-sectional view of the structure 2 B The view shows a NAND chain 430 with a flat control gate and a charge trapping layer. NAND chain 430 includes SGS transistor 431, example memory cells 400, 433, ..., 434, and 435, and SGD transistor 436.

The NAND chain can be formed on a substrate having a p-type substrate region 455, an n-type well 456 and a p-type well 457. N-type source/drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6 and sd7 are formed in p-type well 457. A channel voltage, Vch, can be applied directly to the channel region of the substrate. Memory cell 400 includes control gate 402 and IPD layer 428 over charge trapping layer 404, polysilicon layer 405, tunnel layer 409, and channel region 406. FIG.

The control gate layer can be polysilicon, for example, and the tunnel layer can be silicon oxide, for example. The IPD layer can be a stack of high-k dielectrics such as AIOx or HfOx that help increase the coupling ratio between the control gate layer and the charge trapping or charge storage layer. For example, the charge trapping layer may be a mixture of silicon nitride and silicon oxide.

The SGD and SGS transistors have the same configuration as the memory cells, but with a longer channel length to ensure current is turned off in a locked NAND string.

In this example, layers 404, 405 and 409 extend continuously in the NAND chain. In another approach, portions of layers 404, 405, and 409 located between control gates 402, 412, and 422 may be removed such that an upper surface of channel region 406 is exposed.

2D 12 illustrates an exemplary memory cell 500. The memory cell has a control gate CG receiving a wordline voltage Vwll0, a drain with a voltage Vd, a source with a voltage Vs, and a channel with a voltage Vch.

3 12 is a perspective view of a memory device 600 showing a set of blocks in an exemplary 3D configuration of memory array 200. FIG 1 having. On the substrate are exemplary blocks BLK0, BLK1, BLK2, and BLK3 of memory cells (memory elements) and a peripheral area 604 with circuitry for use by the blocks. For example, the circuitry can include voltage drivers 605 that can be connected to control gate layers of the blocks. In one approach, control gate layers are commonly driven at a common level in the blocks. The substrate 601 may also support circuitry underneath the blocks along with one or more lower metal layers patterned into conductive traces to carry circuitry signals. The blocks are formed in an intermediate region 602 of the memory device. In a top region 603 of the memory device, one or more top metal layers are patterned into conductive lines to carry signals of circuitry. Each block has a stacked array of memory cells, with alternate levels of the stack representing word lines. In one possible approach, each block has opposite stepped sides from which vertical contacts extend up to a top metal layer for making connections to conductive traces. While four blocks are exemplified, two or more blocks extending in the x and/or y direction may be used.

In one possible approach, the x-direction length of the plane represents a direction in which signal paths extend to wordlines in the top one or more metal layers (a wordline or SGD line direction), and the y-direction width of the plane represents Direction represents a direction in which signal paths extend to bit lines in the one or more upper metal layers (a bit line direction). The z-direction represents a height of the storage device.

4 Figure 12 shows an exemplary cross-sectional view of a portion of one of the blocks 3 The block has a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers (or word lines) WLD1, WLD2, WLD3, and WLD4 in addition to data word line layers (or word lines) WLL0 through WLL10. The dielectric layers are referred to as DL0 through DL19. Also shown are regions of the stack that include NAND chains NS1 and NS2. Each NAND string has a memory hole 618 or 619 filled with materials forming memory cells adjacent to the word rows. A region 622 of the stack is in 5 shown in more detail.

The stack includes a substrate 611, an insulating layer 612 on the substrate and a Section of a source line SL. NS1 has a source end 613 at a bottom 614 of the stack and a drain end 615 at a top 616 of the stack. Metal filled slots 617 and 620 may be provided periodically across the stack as interconnects extending through the stack to connect the source line to a line across the stack, for example. The slots can be used during the fabrication of the word lines and then filled with metal. A portion of a bit line BL0 is also shown. A conductive via 621 connects the drain end 615 of NS1 to BL0. The connection from NS2 to its bit line is in 4 not shown.

5 Figure 6 shows a close-up view of portion 622 of the stack 4 Memory cells are formed at the various levels of the stack at the intersection of a word line layer and a memory hole. In this example, SGD transistors 680 and 681 are provided over dummy memory cells 682 and 683 and a data memory cell MC. A series of layers may be deposited along the sidewall (SW) of the memory hole 630 and/or within each wordline layer, e.g. B. using atomic layer deposition. For example, each column (e.g., the pillar formed by the materials within a memory hole) may include a charge trapping layer 663 or foil such as SiN or other nitride, a tunneling layer 664, a channel 665 (e.g., comprising polysilicon), and a dielectric Include core 666. A wordline layer may include a blocking oxide/block high-k material 660, a barrier metal 661, and a conductive metal 662 such as tungsten as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal and the blocking oxide/block high-k material 660 are provided in the memory hole. In other approaches, additional layers can be in the control gate layer. Additional pillars are similarly formed in the various storage holes. A pillar can form a pillar-shaped active area (AA) of a NAND string.

When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are drawn into the charge trapping layer from the channel and through the tunneling layer. The Vth of a memory cell is increased in proportion to (e.g., depending on the increase) the amount of stored charge. During an erase operation, the electrons return to the channel.

Each of the storage holes may be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers are located between the core region and the word line in each of the memory holes.

The NAND chain can be considered to have a floating body channel since the length of the channel is not formed on a substrate. Furthermore, the NAND chain is provided by a plurality of word line layers arranged one on top of the other in a stack and separated from one another by dielectric layers.

6 Figure 1 shows an exemplary view of NAND chains in sub-blocks in a 3D configuration using 4 matches. Each sub-block includes multiple NAND strings, with an example NAND string shown. For example, SB0, SB1, SB2, and SB3 have example NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have data word lines, dummy word lines, and select gate lines connected with 4 to match. In a block BLK, each sub-block has a set of NAND strings that extend in the x-direction and that share a common SGD line. NAND chains 700n, 710n, 720n, and 730n are in sub-blocks SB0, SB1, SB2, and SB3, respectively. Programming of the block can be done one sub-block at a time. Within each sub-block, a word line programming order can be followed, e.g. B. starting at WL0, the source-side wordline, and continuing one wordline at a time up to WLL10, the drain-side wordline. As previously described, a sub-block may include multiple chains, while in other embodiments a sub-block includes a single chain.

The NAND chains 700n, 710n, 720n and 730n have channel regions 700a, 710a, 720a and 730a, respectively.

In addition, NAND chain 700n includes SGS transistors 700 and 701, dummy memory cells 702 and 703, data memory cells 704, 705, 706, 707, 708, 709, 710, 711, 712, 713 and 714, dummy memory cells 715 and 716, and SGD transistors 717 and 718 on.

NAND chain 710n includes SGS transistors 720 and 721, dummy memory cells 722 and 723, data memory cells 724, 725, 726, 727, 728, 729, 730, 731, 732, 733 and 734, dummy memory cells 735 and 736 and SGD transistors 737 and 738.

NAND chain 720n includes SGS transistors 740 and 741, dummy memory cells 742 and 743, data memory cells 744, 745, 746, 747, 748, 749, 750, 751, 752, 753 and 754, dummy memory cells 755 and 756, and SGD -Transistors 757 and 758 on.

NAND chain 730n includes SGS transistors 760 and 761, dummy memory cells 762 and 763, data memory cells 764, 765, 766, 767, 768, 769, 770, 771, 772, 773 and 774, dummy memory cells 775 and 776 and SGD -Transistors 777 and 778 on.

7 provides additional detail of sub-blocks SB0 through SB3 6 Example memory cells are shown extending in the x-direction along word lines in each sub-block. Each memory cell is shown as a cube for simplicity. SB0 includes NAND strings 700n, 701n, 702n, and 703n. SB1 includes NAND strings 710n, 711n, 712n and 713n. SB2 includes NAND strings 720n, 721n, 722n and 723n. SB3 includes NAND strings 730n, 731n, 732n and 733n. Bit lines are connected to sets of NAND strings. For example, a bit line BL0 is connected to NAND strings 700n, 710n, 720n, and 730n, a bit line BL1 is connected to NAND strings 701n, 711n, 721n, and 731n, a bit line BL2 is connected to NAND strings 702n, 712n, 722n, and 732n, and a bit line BL3 is connected to NAND strings 703n, 713n, 723n and 733n. Sense circuitry may be connected to each bit line. For example, sense circuitry 780, 781, 782, and 783 is connected to bit lines BL0, BL1, BL2, and BL3.

During a programming operation, the final Vth distribution can be reached with one or more programming loops. A multi-pulse programmed memory device can be programmed using multiple programming loops. Conversely, a single pulse programmed memory device can be programmed via a single programming loop or pulse without a verify step. For multi-pulse programming, each subsequent loop can use an increased programming pulse. During a program loop, in certain embodiments, program verification iterations are performed for a selected wordline. A program verification iteration comprises a programming step/phase in which a programming voltage is applied to the word line, followed by a verify step/phase in which one or more verify tests are performed. Each programmed state may include a verify pulse used in the verify test for the state.

8th FIG. 12 illustrates a waveform of an exemplary conventional programming operation. In particular, FIG 8th Fig. 1 shows a multi-pulse programming operation in which programming pulses are applied incrementally to program one or more memory cells. The horizontal axis represents a program loop (PL) number and the vertical axis represents a memory cell control gate, also known as a word line voltage. In general, a programming operation may involve the application of a pulse train to a selected wordline, where the pulse train includes multiple program loops or program verification iterations. The programming portion of the program verification iteration includes a programming voltage and the verifying portion of the program verification iteration includes one or more verify pulses.

Each programming loop includes two steps in one approach. Also, this example uses Incremental Step Pulse Programming (ISPP) in which the programming voltage increases by a fixed or varying step size in each successive programming loop.

Waveform 800 includes a series of programming voltages 852, 854 and 856 which are applied to a word line selected for programming and to an associated set of non-volatile memory cells. As an example, one or more verify pulses may be provided after each programming voltage based on the verified target data states. 0V can be applied to the selected word line between the program and verify pulses. For example, the concurrent programming component 150 may apply the first programming pulse 852, apply a verify pulse 860, apply the second programming pulse 854, apply the verify pulse 860 again, and then apply the third programming pulse 856. In another embodiment, a trigger condition includes a memory cell programmed to a target voltage threshold. In this embodiment, the simultaneous programming component 150 may abort the pulse programming sequence, for example after the first programming pulse 852 or after the second programming pulse 854, in response to determining that both the first memory cell and the second memory cell have reached the target threshold voltage. Additional examples for single pulse programmers phases are in U.S. Patent No. 8,134,871 set forth herein, which is incorporated herein by reference.

In other embodiments, programming a memory cell using a "single pulse" involves applying a single programming pulse at an elevated voltage to program the cell to the target threshold voltage, rather than performing sequential programming loops, as in 8th shown. In one example, programming circuitry 284 applies a single programming pulse at Vpgm3 without applying Vpgm1 or Vpgm2. In another example, the programming circuit 284 applies 20 volts to the word line for the memory cell and a lower threshold voltage difference to the bit line for the memory cell. In this example, the voltage difference between the word line and the bit line is applied to the memory cell. In certain embodiments, an "elevated voltage" includes a voltage level that is higher than the initial conventional programming loops in a conventional programming operation. In one example, an "elevated voltage" is 18 volts. In another embodiment, an "elevated voltage" is between 16 and 20 volts.

In other embodiments, the simultaneous programming component 150 first applies a single-pulse programming sequence and then applies a multi-phase programming sequence when one of the first memory cell and the second memory cell has not been programmed correctly. In particular, in such an embodiment, the programming circuit 284 initially applies single-pulse programming to simultaneously program the first and second memory cells to a common target threshold voltage, and then the verifying circuit 286 simultaneously verifies the programming level of the first memory cell and the second memory cell. In one embodiment, if verification circuit 286 determines that one of the first and second memory cells is improperly programmed, programming circuit 284 may use multi-pulse programming to program the first and second memory cells separately, as may be appreciated by those skilled in the art. This programming step can be performed at different times for the first and second memory cells (e.g. by programming the first memory cell and then the second memory cell). The verification circuit 286 then verifies the first and second memory cells for proper programming. This may be done for the first and second memory cells at the same time or at different times (e.g. by verifying the first memory cell and then the second memory cell for proper programming).

In another embodiment, the first memory cell and the second memory cell are independently programmed in a series of conventional program verification iterations in one programming operation. Upon completion of the programming pass, the concurrent programming component 150 independently verifies that each of the memory cells has been programmed correctly.

Those skilled in the art will recognize that a variety of alternative cell programming methods can be used to separately program multiple memory cells. Single pulse programming, multiple pulse programming, and/or combinations thereof may be used. Additional examples of single pulse programming are in U.S. Patent 9,343,141 set forth herein, which is incorporated herein by reference.

9 turns off a portion of memory cell MC 5 10 showing the injection of electrons into a charge trapping region during programming. The memory cell includes a control gate 694, a barrier metal 661a, a blocking oxide 660a, a charge trapping layer 663, a tunneling layer 664, a channel 665 and a dielectric core 666. Due to the increased wordline voltage, an electric field (E) is created that pulls electrons from channel 665 (see example electron 650) into charge trapping layer 663, thereby increasing the Vth. This programming can be caused by the Fowler-Nordheim tunneling effect. This is a type of electron tunneling by traps.

10 10 is a top view of an array of memory cells 1000 having a set of bit lines 1050 and an S/A data latch 1010. FIG. In this embodiment, bit lines 1050 are set according to data received at S/A data latch 1010 and the data is to be written into specific memory cells corresponding to selected word lines, as described herein.

In one embodiment, the bit lines 1050 are set according to data to be written to a memory cell in each chain of memory cells corresponding to the selected bit lines and in the first erase block 1020. FIG. Simultaneous programming component 150 selects a different word line (in 10 not shown) for a memory cell located in the second erase block 1030. As previously described, the component connects to the concurrent Pro 150 electrically program 150 in this embodiment the wordline for the first erase block 1020 and the wordline for the second erase block 1030, thereby allowing the memory cells in both blocks 1020, 1030 to be simultaneously programmed to a common target threshold voltage in response to the application of a programming pulse to one of the wordlines . Thus, the memory cells in each block 1020, 1030 are programmed simultaneously according to the bit pattern set for the bit lines 1050.

In certain embodiments, the concurrent programming component 150 selects the first erase block 1020 and the second erase block 1030 to be at least one block apart. i.e. there may be at least one block between the first erase block 1020 and the second erase block 1030 . In other embodiments, the concurrent programming component 150 selects the two blocks that are at least a minimum physical distance from each other. For example, the minimum distance is 50 nanometers, but of course this disclosure is not limited in this regard.

As previously described, the physical separation of the first erase block 1020 from the second erase block 1030 makes it less likely that a physical failure of the array of memory cells will affect both the first erase block 1020 and the second erase block 1030 . In one embodiment, the concurrent programming component 150 separates the array of memory cells into separate physical partitions or sections. In one example, the concurrent programming component 150 divides the array into four sections by dividing the array in half vertically and horizontally. Of course, other partitioning or physical partitioning techniques can also be used, and this disclosure is not limited in this regard. Thus, as described herein, a "physical portion" includes a sub-portion of an array of memory cells that is physically distinct from other memory cells in the array. In some examples, the physical section is determined based on logical boundaries. Therefore, there may not be physical differences between different physical sections.

11 Figure 12 is a diagram of program and verify pulses according to one embodiment. In this embodiment, to perform a simultaneous programming operation, the concurrent programming component 150 sets the voltage of unselected bit lines (data "1") to a high voltage (e.g., 2.5 volts) and the voltage of selected bit lines (data "0") to a low voltage (e.g. 0 volts), the drain select gate (SGD) in each block 1020, 1030 to VSGD (e.g. 2.5 volts), the selected word lines in the first erase block 1020 and in the second erase block 1030 to a programming pulse (VPGM, e.g. 18 volts), unselected word lines in each block 1020, 1030 to a boosting voltage (VPASS, e.g. 10 volts), the source select Gate at 0 volts and the source line voltage (CELSRC) at PROGGRC (e.g. 2 volts).

In another embodiment, to perform a simultaneous verify operation, the concurrent programming component 150 sets the bitline to a bitline clamp voltage (VBLC), the SGD to a selected gate voltage (VSG), each selected wordline in each block to a verify pulse (Vverify ), each unselected word line to a read voltage (Vread), the SGS to the selected gate voltage VSG, and the source line voltage (CELSRC) to VCELSRC (e.g., 1 volt).

12 12 illustrates portions of two blocks according to one embodiment. Bit lines 1210a, 1210b, 1210c are set according to data written to memory cells in each of the blocks. In this embodiment, the blocks include a first erase block 1220 and a second erase block 1230 . Although in 12 As three bit lines 1210 are shown, an array of memory cells can of course include many more bit lines. Furthermore, although two blocks are illustrated, one or more additional copies may optionally be made, for example on a third block (not shown), a fourth block (not shown), and so on.

In one embodiment, simultaneous programming component 150 electrically selects a bit line to program cells in NAND strings connected to bit line 1210 . In this particular example, simultaneous programming component 150 selects bit line 1210c. The simultaneous programming component 150 also connects a first word line 1250 corresponding to a first memory cell 1221 to a second word line 1240 corresponding to a second memory cell 1231 . For example, the simultaneous programming component 150 may select a select gate transistor to electrically connect both the first wordline 1250 and the second wordline 1240 to a common connection. In particular, the first erase block 1220 includes a first NAND chain 1260 crossing a first word line 1250 at a first memory cell 1221 and a second erase block 1230 includes a second chain 1261 crossing a second word line 1240 a second memory cell 1231 crosses. The simultaneous programming component 150 applies a programming pulse to the connected word lines 1240 , 1250 , the programming pulse being applied to the first memory cell 1221 and the second memory cell 1231 .

In another embodiment, the simultaneous programming component 150 applies a verify pulse to the first wordline and second wordline after simultaneously applying the programming pulse to the first wordline and second wordline. In particular, the concurrent programming component 150 applies the voltages described in FIG 11 described verification process are described. In this embodiment, the simultaneous programming component 150 then senses the current flow through one of the first memory cell 1221 and the second memory cell 1231 (e.g., by sensing the current at a memory cell or an end of the NAND chain) in response to the Applying the verify pulse to simultaneously determine that one of the first memory cell 1221 and the second memory cell 1231 is programmed incorrectly. In one embodiment, the concurrent programming component 150 then senses the current flowing through the bit line connected to NAND strings containing concurrently programmed memory cells. In another embodiment, the simultaneous programming component 150 separately programs the first memory cell and the second memory cell in response to sensing current through one of the first memory cell 1221 and the second memory cell 1231, as previously described. As previously described, the separate programming can be performed in the same manner as the initial programming of the first memory cell 1221 and the second memory cell 1231, or the separate programming can be performed differently, for example by separately programming the first memory cell 1221 and the second memory cell 1231 and/or with a different programming pulse structure such as conventional programming or via multi-pulse programming or the like.

13 13 illustrates one embodiment of a method 1309 for simultaneously programming cells of a memory array. The method 1309 may be performed each time one or more of the non-volatile memory elements 123 are to be programmed. Process 1309 may be performed by die controller 220, for example, using the various circuitry described in 1B are shown. Alternatively, method 1309 can be performed with other hardware such as controller 244 1B and/or the non-volatile storage media controller 126 1A to be executed.

As shown, the method 1309 may begin 1310 with a step 1312 of selecting a bit line corresponding to memory cells (e.g., non-volatile memory elements 123 of memory array 200) to be programmed. In one embodiment, concurrent programming component 150 receives a command to program one or more of non-volatile memory elements 123 of memory array 200. The command may be received in die controller 220, for example. Such a command can be received in the programming circuitry 284 of the die controller 220 .

In a step 1314, word lines are selected for memory cells in two different blocks or, in alternative embodiments, in a common NAND chain within the same block. In one embodiment, the word lines are electrically connected in separate blocks as previously described.

In a step 1316, a programming pulse is applied to the connected word lines to program the memory cells in the two different blocks simultaneously. This can be done by the programming circuit 284, which can apply the programming pulse to both selected word lines simultaneously, thereby programming the first memory cell 1221 and the second memory cell 1231.

In a step 1320, a verify pulse is simultaneously applied to the connected word lines. This can be done by verification circuitry 286, for example.

In a step 1322, current flow through one of the first memory cell and the second memory cell is sensed to determine whether the first and second memory cells 1221, 1231 have been correctly programmed. As previously described, when memory array 200 is a conventional architecture NAND array, current flow through the bit line in response to application of the verify pulse may indicate that the first memory cell and/or the second memory cell has not been correctly programmed.

In one embodiment, the "sense stream" includes a charged capacitor, which is then connected to a bit line by applying a voltage pulse to the word line. In response, if the memory cell has a threshold voltage at or below the voltage level on the word lines, the memory cell conducts a current flowing from the bit line a current draw can flow. In this embodiment, current sensing is simply determining how much the capacitor discharged when connected to the bit line.

The method 1309 proceeds to a step 1318 in response to both the first memory cell and the second memory cell being correctly programmed. In step 1318, data written in step 1316 to one of the first memory cell 1221 and the second memory cell 1231 is read and used to program a multi-level cell in an SLC-TLC compression (folding) process. The SLC-TLC compression process can be performed using any prior art method. In some embodiments, the data is retrieved from the first memory cell 1221 and/or the second memory cell 1231 and then combined with other data (such as a double bit stored in a third memory cell and a fourth memory cell) to form the value to be stored in the multi-level cell (e.g. 0, 1 or 2). The value is then written into the multilevel cell.

The method continues at step 1324 and the simultaneous programming component 150 overwrites the second memory cell. As used herein, "overwriting" includes the concurrent programming component 150 storing a different data value in the memory cell in a subsequent programming operation (which may occur after the second memory cell is first erased). In other examples, in step 1324, the second memory cell is marked for reuse, erased, or otherwise prepared for use to store other data. The method 1309 then ends 1350.

In response to one of the first memory cell and the second memory cell being incorrectly programmed, the method 1309 proceeds to step 1326 and the programming circuit programs the first memory cell and the second memory cell separately. As previously mentioned, separate programming for the first memory cell 1221 and the second memory cell 1231 can be performed with the same single pulse methods as used in step 1316. Alternatively, the first memory cell 1221 and the second memory cell 1231 may be programmed separately and/or by using different methods such as multi-pulse programming.

After completing the separate programming operation in step 1326, the method proceeds to step 1320 and a verify pulse is again applied to the memory cells. Optionally, the verify pulse may be applied as in the previous iteration of step 1320, i. H. by applying the verify pulse to the word lines corresponding to the first memory cell 1221 and the second memory cell 1231 simultaneously. Alternatively, instead of step 1320, a modified verify process can be applied, in which the correct programming of the first memory cell 1221 and the second memory cell 1231 is individually evaluated, for example by applying the verify pulse only to the word line for the first memory cell 1221, reading the current through the bit line 1210c and then applying the verify pulse only to the word line for the second memory cell 1231, reading the current through the bit line 1210c again.

14 13 illustrates one embodiment of step 1326 for programming cells of a memory array separately. Step 1326 may be performed whenever the first memory cell and/or the second memory cell is not programmed correctly. In some embodiments, it may not be known whether it was the first memory cell 1221 or the second memory cell 1231 that was not programmed correctly; thus, step 1326 may entail programming both the first memory cell 1221 and the second memory cell 1231 separately. Step 1326 may be performed by the die controller 220 using, for example, the various circuitry described in FIG 1B are shown. Alternatively, step 1326 can be accomplished with other hardware such as controller 244 1B and/or the non-volatile storage media controller 126 1A to be executed.

As shown, step 1326 may begin with step 1412 where a conventional verify pulse is applied to the first memory cell 1221 . In this embodiment, it may not be known which of the two memory cells 1221, 1231 was programmed incorrectly. Thus, in this embodiment, each of the two memory cells 1221, 1231 is programmed independently. Thus, the first memory cell 1221 and the second memory cell 1231 are not electrically coupled to perform step 1412 and step 1420 (described below). If desired, the second memory cell 1231 can be reprogrammed simultaneously with the reprogramming of the first memory cell 1221 by independently and simultaneously applying program voltages to the corresponding word lines for the first memory cell 1221 and the second memory cell 1231.

In a step 1414, it is determined whether the first memory cell is correctly programmed. In In one example, a current is sensed at a sensing component attached to both ends of a NAND string that includes the first memory cell, and in response to the current flow through the first memory cell, it is determined that the first memory cell was not successfully programmed.

In response to the current sensing at step 1414, the method proceeds to step 1416 and an elevated programming pulse is applied, as described herein. Any suitable programming pulse increment can be used. In some embodiments, a look-up table of programming pulses or increments is used; each iteration of step 1414 sets the programming pulse to the next programming pulse or increases the programming pulse by the next increment in the look-up table.

In step 1418, as part of a conventional programming operation, a boosted programming pulse is applied to the first memory cell and step 1326 proceeds to step 1412 as previously described. In this embodiment of the method, steps 1414, 1416, 1418, and 1412 may be repeated many times. Method 1309 proceeds to step 1420 in response to the first memory cell being correctly programmed. In particular, if the first memory cell 1221 meets certain criteria such as exceeding a threshold number of programming pulses, to obtain a correct number of programming, the first memory cell 1221 can be marked for future reduced use or non-use. If desired, the first memory cell 1221 can continue to be used in the current memory operation. Alternatively, there is a possibility not to use the first memory cell 1221 and instead to write the data to be written into the first memory cell 1221 into another memory cell (possibly into a third block different from the first erase block 1220 and the second erase block 1230) .

In step 1420 a verify pulse is applied to the second memory cell 1231 . In a step 1426 it is determined whether the second memory cell 1231 is correctly programmed. In one example, a current is sensed at one of the first memory cell and the second memory cell and, in response to the current flow through the bit line, it is determined that the second memory cell was not successfully programmed. As described in connection with step 1412, the first memory cell 1221 and the second memory cell 1231 can optionally be electrically decoupled to perform step 1420 so that the programming of only the second memory cell 1231 can be verified.

In response to the current sensing at step 1426, the method 1309 proceeds to step 1424 and a programming pulse is increased as described herein. Any suitable method can be used to calculate the new programming pulse. As in step 1416, a lookup table or the like may be used.

In a step 1422, a boosted programming pulse is applied to the second memory cell 1231 and the step 1326 proceeds to step 1420 as previously described. Like steps 1412, 1414, 1416, and 1418, steps 1426, 1424, 1422, and 1420 can be repeated many times. Method 1309 proceeds to step 1320 in response to the second memory cell being correctly programmed.

Embodiments include programming the same data into different sets of memory cells at the same time. In one embodiment, the different sets of memory cells are all associated with the same set of bit lines. In one embodiment, the different sets of memory cells are all in the same plane. The voltage of the bit lines can be set according to a data pattern, where "n" copies of the data pattern are programmed simultaneously into n sets of memory cells, where n is an integer greater than 1.

Simultaneous programming can be used in programming memory cells to one bit per cell (SLC), two bits per cell, three bits per cell (TLC), four bits per cell (QLC), five bits per cell (QLC), and so on. the 15A - 15D show the threshold voltage (Vt) distributions obtained after simultaneous programming to different numbers of bits per cell. 15 shows the Vt distributions for SLC programming. First, the memory cells are erased up to the erase state ("1"). An erase verify voltage (Vev) can be used to verify if the memory cells are sufficiently erased. Then the same data is simultaneously programmed into different sets of memory cells. In one embodiment, selected memory cells are simultaneously programmed from the erase state to the data ("0") state. Optionally, a verify voltage (Vv) can be used to verify whether the Vt of the memory cells has reached the data state. A read voltage (Vr) can be used to distinguish between the erase state and the data state.

15B Figure 12 shows the Vt distribution that can result from a process of simultaneously programming memory cells to two bits per cell. First, the memory cells are erased to the erase state ("Er"). Then the memory cells can be programmed simultaneously to the different data states (A-state, B-state, C-state). Optionally, verify voltages (Vva, VvB, VvC) can be used to verify whether the Vt of the memory cells have reached their respective target data states. Reading voltages (VrA, VrB, VrC) can be used to distinguish between the states.

15C Figure 1 shows the Vt distribution that can result from a process of simultaneously programming memory cells to three bits per cell. First, the memory cells are erased to the erase state ("Er"). Then the memory cells can be simultaneously programmed to the different data states (A-state, B-state, C-state, D-state, E-state, F-state, G-state). Optionally, verify voltages (Vva, VvB, VvC, VvD, VvE, VvF, VvG) can be used to verify whether the Vt of the memory cells have reached their respective target data states. Reading voltages (VrA, VrB, VrC, VrD, VrE, VrF, VrG) can be used to distinguish between the states.

15D Figure 12 shows the Vt distribution that can result from a process of simultaneously programming memory cells to four bits per cell. First, the memory cells are erased until they reach the erased state ("S0"). Then the memory cells can be programmed simultaneously to the different data states (S0 - S15). Read voltages (Vr1-Vr15) can be used to distinguish between the states.

16 FIG. 16 is a flow diagram of one embodiment of a process 1600 for simultaneously programming different sets of memory cells. In one embodiment, each sentence is in a different erase block. Herein, the term “selected erase block” means an erase block in which memory cells are to be programmed. In some embodiments, there are three or more erase blocks selected in process 1600. Process 1600 can be used to program memory cells with one bit per cell (SLC), two bits per cell, three bits per cell (TLC), four bits per cell (QLC ), five bits per cell (PLC), or some other number of bits per cell.

Step 1602 includes applying voltages to the bit lines according to a data pattern to be programmed. In one embodiment, the voltages applied to the bit lines are adjusted according to data received at S/A data latch 1010. FIG. In one embodiment, a program enable voltage (e.g., 0V) is used to enable programming of a selected memory cell in a selected NAND string, and a program disable voltage (e.g., 2.5V) is used to disable programming in of an unselected NAND chain. The bit lines to which the program enable voltage is applied are referred to as selected bit lines. The bit lines that have the program-inhibit voltage applied are referred to as either program-inhibited bit lines or unselected bit lines.

In some embodiments, the data pattern corresponds to a data state. For example, with SLC memory cells, the cells either remain in the erase ("1") state or are programmed to a data ("0") state. Therefore, the data pattern may have a 0 for the cells that are to be programmed to the data state and a 1 for the cells that are to remain erased. Eventually, if two bits are programmed into each cell, the cells may end up in one of the following states: erase state, A-state, B-state, or C-state. Therefore, the data pattern in step 1602 may identify those cells that are to be programmed to the A-state, for example.

In step 1604, the system simultaneously applies a select voltage to the drain select gates of n sets of NAND strings. In one embodiment, the select voltage is applied to a common SGD line that interconnects the drain select gates of a set of NAND strings. In one embodiment, each set of NAND strings is associated with a series of conductive regions. Each conductive region is connected to the control gate of a memory cell in each NAND string in the set. In one embodiment, each set of NAND chains resides in a different selected erase block. Step 1604 may include applying the select voltage to an SGD line in each erase block simultaneously. The select voltage connects a selected NAND string to its respective selected bit line, turning on the drain select gate of the selected NAND string. However, the select voltage does not turn on the drain select gate of an unselected NAND string. For example, the select voltage may be 2.5V, the program enable voltage on a selected bit line may be 0V, and the program disable voltage on the unselected bit lines may be 2.5V.

In step 1606, the system simultaneously applies a program voltage to the control gates of n sets of selected memory cells. The program voltage is applied while the select voltage is applied to the drain select gates of the NAND strings and while the voltages are applied to the bit lines. Thus, the data pattern is simultaneously programmed into each set of selected memory cells. Thus n copies of the data pattern can be stored simultaneously. In one embodiment, each set of selected memory cells resides in a different selected erase block.

In step 1608, the system determines if there is another data pattern to be programmed at the same time. For example, if the process 1600 is used to program two bits per cell simultaneously, after programming the A state simultaneously, steps 1602-1606 may be repeated to program the B state. Thus, in this example, the first data pattern concurrently programs the A-state, a second data pattern concurrently programs the B-state, and a third data pattern concurrently programs the C-state. In this way, two or more bits can be programmed simultaneously per cell.

In some embodiments, the system verifies the programming of the memory cells that are programmed concurrently in process 1600. For example, the system may verify (for each memory cell to be programmed to a target data state) whether the Vt of a memory cell has reached a Vt associated with the target data state, which may be referred to herein as "verifying a data state". In some embodiments, the system does not verify the programming of memory cells that are programmed concurrently in process 1600.

17 17 is a flow diagram of one embodiment of a process 1700 for concurrently programming memory cells to NAND strings in different erase blocks. Step 1702 includes applying a program enable voltage to selected bit lines according to a data pattern to be programmed. Note that a program inhibit voltage (e.g., 2.5V) may be applied to unselected bit lines. In one embodiment, the program enable voltage (and program disable voltage) applied to the bit lines are adjusted according to data received at S/A data latch 1010 .

In step 1704, the system simultaneously connects each selected bit line to n selected NAND strings. In one embodiment, each selected bit line is connected to two selected NAND strings. In one embodiment, each selected bit line is connected to three selected NAND strings. In one embodiment, each selected bit line is connected to four selected NAND strings. Each selected bit line can be connected to five or more selected NAND strings. In one embodiment, the system applies a select voltage to drain select gates in the NAND strings to connect the selected bit lines to the selected NAND strings.

In step 1706, the system simultaneously applies a program voltage to the control gates of n sets of selected memory cells. The program voltage is applied while the selected bit lines are being connected to the selected NAND strings and while the program enable voltages are being applied to the selected bit lines. Thus, the data pattern is simultaneously programmed into each set of selected memory cells. Thus n copies of the data pattern can be stored. In one embodiment, each set of selected memory cells resides in a different selected erase block.

In step 1708, the system verifies each set of memory cells. In one embodiment, a verify voltage is applied to the control gates of all memory cells that are being programmed. For each selected bit line, the system can sense a current that can flow in response to the verify voltage on the bit line. In one embodiment, the system charges a sense capacitor and then connects it to the bitline (after the verify voltage is applied). The system then allows the bitline current, if any, to discharge the sense capacitor for a specified time. In one embodiment, if a selected memory cell associated with a bitline has not reached its target data state, the memory cell will conduct a significant current. Therefore, in one embodiment, the sense capacitor voltage subsequently falls below a clipping voltage when at least one selected memory cell has not reached its target data state.

In step 1710, the system determines whether all sets of memory cells have passed verified. This determination is based on sensing the bit lines. In one embodiment, the system assumes that all sets have passed if no more than a certain number of bit lines correspond to failed programming cases. Error correction algorithms are capable of a certain number in such cases to deal with mistakes. If all sets pass, the process is complete. If not all sets pass, in step 1712 the system verifies each set of memory cells separately. Any set verified as failing may receive additional programming. In some embodiments, steps 1708-1712 are not performed, in which case the memory cells are not verified.

In some embodiments, the system simultaneously programs n copies of a data pattern into corresponding n sets of memory cells in a multi-step cell programming process. 18 18 is a flowchart of one embodiment of the process 1800 of simultaneously programming n copies of a data pattern in n sets of memory cells in a multi-level cell programming process. The process 1800 is an embodiment of the process of FIG 16 . Step 1802 includes applying a program enable voltage (e.g., 0V) to selected bit lines according to an A-state. For example, all bit lines associated with memory cells to be programmed to the A-state receive the program enable voltage. All other bit lines receive a program inhibit voltage (e.g. 2.5V).

Step 1804 includes connecting each selected bit line to n selected NAND strings simultaneously. In one embodiment, each selected bit line is connected to two selected NAND strings. In one embodiment, each selected bit line is connected to three selected NAND strings. In one embodiment, each selected bit line is connected to four selected NAND strings. Each selected bit line can be connected to five or more selected NAND strings. In one embodiment, the system applies a select voltage to drain select gates in the NAND strings to connect the selected bit lines to the selected NAND strings.

Step 1804 may also include connecting each selected bit line to a different NAND string in n sets of NAND strings simultaneously. In one embodiment, each set of selected NAND chains resides in a different erase block. In one embodiment, there are two selected erase blocks. In one embodiment, there are three selected erase blocks. In one embodiment, there are four selected erase blocks. In one embodiment, there are more than four erase blocks selected. In one embodiment, the system connects each selected bit line to a selected NAND string in each selected erase block.

In step 1806, the system simultaneously applies an A-state program voltage to the control gates of n sets of selected memory cells. In one embodiment, each set of memory cells resides in a different selected erase block. In one embodiment, the system selects a magnitude of the A-state programming voltage that depends on a Vt associated with the A-state. In one embodiment, the A-state program voltage is of a magnitude sufficient for almost all memory cells to reach an A-state associated Vt with a single program pulse. In some embodiments, a certain number of memory cells may not reach the Vt associated with the A-state, and an error correction algorithm is used during a read operation to handle such underprogrammed memory cells. In one embodiment, the A-state program voltage increases the Vt of the memory cells from the erase state to a Vt associated with the A-state. For example, the size can be chosen such that most memory cells experience an increase in Vt from the erase state to above VvA (see for example 15B or 15B ).

In one embodiment, the process 1800 is used in a foggy fine programming process. In a foggy fine programming process, the memory cells are first programmed to be close to a final Vt for the states, but may have a Vt slightly below a final Vt for the state. A fine programming phase can then be used to finish programming the memory cells to the final Vt for the state. In one embodiment, the fine programming phase is performed for each set of memory cells individually (as opposed to programming each set of memory cells simultaneously). In one embodiment, the A-state program voltage increases the Vt of the memory cells from the erase state to a Vt close to the final Vt for the A-state, with the fine phase increasing the Vt if necessary. In relation to 15A For example, the target Vt for the A-state can be slightly lower than VvA for concurrent programming, using the fine programming phase to finish programming to at least VvA. As will be appreciated by those skilled in the art, during concurrent programming, even if some of the memory cells do not reach the Vt near the final A-state Vt, the fine programming phase can program those cells to the final A-state Vt.

Steps 1808, 1810, 1812 are similar to corresponding steps 1802, 1804, 1806, but for the B-state. One difference is that in step 1812 a B-state voltage is applied to the control gates of the selected memory cells. In one embodiment, the B-state program voltage has a greater magnitude than the A-state program voltage. In one embodiment, the B-state program voltage is of a magnitude sufficient to program almost all memory cells to a Vt associated with the B-state with a single programming pulse. In one embodiment, the B-state program voltage increases the Vt of the memory cells from the erase state to a final Vt associated with the B-state. In a foggy-fine embodiment, the B-state program voltage increases the Vt of the memory cells from the erase state to a Vt close to the final B-state Vt, with the fine phase increasing the Vt if necessary.

Steps 1814, 1816, 1818 are similar to corresponding steps 1802, 1084, 1806 but for the C-state. One difference is that in step 1818 a C-state voltage is applied to the control gates of the selected memory cells. In one embodiment, the C-state program voltage is greater in magnitude than the B-state program voltage (and therefore also greater than the A-state program voltage). In one embodiment, the C-state program voltage is of a magnitude sufficient to program almost all memory cells to a final Vt associated with the C-state with a single programming pulse. In one embodiment, the C-state program voltage increases the Vt of the memory cells from the erase state to a final Vt associated with the C-state. In a foggy fine embodiment, the C-state program voltage increases the Vt of the memory cells from the erase state to a Vt close to the final Vt associated with the C-state, with the fine phase increasing the Vt if necessary.

In one embodiment, the process 1800 is used at an initial stage of QLC programming. For example, the memory cells destined to land in one of S4 - S7 are programmed to the A state in process 1800, the memory cells destined to land in one of S8 - S11 are programmed to the B state in process 1800, and the memory cells that are to end up in one of S12-S15 are programmed to the C-state in process 1800. In one embodiment, in the final programming phase to the final states (S4 - S15), each set of memory cells is individually programmed and verified.

In some embodiments, the multi-level cell programming process programs memory cells to three bits per cell. 19 FIG. 1900 is a flow diagram of one embodiment of the process 1900 for concurrently programming memory cells in multiple erase blocks. Process 1900 describes programming for a D-state (steps 1902, 1904, 1906), an E-state (steps 1908, 1910, 1912), an F-state (steps 1914, 1916, 1918), and a G-state ( steps 1920, 1922, 1924). In one embodiment, process 1900 is performed after process 1800. Process 1900 is similar to process 1800 and will not be described in detail. In one embodiment, the program voltage is progressively increased for the data states that have a higher Vt. In one embodiment, the D-state program voltage is greater than the C-state program voltage, the E-state program voltage is greater than the D-state program voltage, the F-state program voltage is greater than the E-state program voltage , and the G-state program voltage is greater than the F-state program voltage. Process 1900 may be used in a foggy fine programming process as described in connection with process 1800.

It should be noted that neither process 1800 nor process 1900 explicitly describe a verification process. In some embodiments, process 1800 does not use program verification. In some embodiments, process 1900 does not use program verification. Optionally, program verification can be used with process 1800 or 1900. Such a verifying operation could be a simultaneous verifying of the n sets of memory cells as described herein. This program verification can be done for one or all data states. If all sets of memory cells pass program verification, programming can be terminated. If the condition "all sets of memory cells pass program verification" is not met, each set of memory cells can be verified separately.

The concepts of processes 1800 and 1900 can be extended to more than three bits per memory cell. In one embodiment of QLC programming, the program voltage is progressively increased for the higher Vt data states.

Applying a voltage, such as a program voltage, to more than one set of memory cells can result in greater RC stress. One reason is that the control gates of each set of memory cells with a sub different conductive region (or conductive plate). In one embodiment, each set of memory cells is connected to a different word line located in a different erase block. In one embodiment, the system selects the number of voltage generators (e.g., charge pumps) based on the number of sets of memory cells being programmed at one time. 20A Figure 12 is a block diagram circuit for providing voltages to erase blocks. Voltage generators 2002(1) - 2002(N) are shown. Each voltage generator 2002 may include a charge pump. Each voltage generator 2002 is set up to generate the same voltage. In 20A the voltage is referred to as VGEN, which is the same magnitude for each voltage generator 2002. In one embodiment, VGEN is a programming voltage (e.g., Vpgm). In one embodiment, VGEN is a channel gain voltage (e.g., Vpass). The channel boost voltage boosts the channel potential of the non-selected NAND chains to prevent or reduce program glitches. Each voltage generator 2002 can be selectively connected to an erase block via a switch 2004 . The switches 2004 may each include one or more transistors or the like.

20A also shows a level 2006 containing a number of erase blocks (BLK0 - BLKn) of memory cells (erase block BLK6 is selected). Sense amplifiers (S/A) 2010 are associated with the plane. The bit lines 2050 associated with the plane are also shown. The voltage on bit lines 2050 is adjusted according to data received at a data latch in S/A 2010 .

Voltage generator 2002(1) is activated with switch 2004(1) closed to electrically connect voltage generator 2002(1) to the selected erase block (BLK6). In one embodiment, voltage generator 2002(1) is connected to a conductive region (or plate) in the erase block that is connected to control gates of selected memory cells.

20B shows the same circuit as in 20A , but in this example three erase blocks (BLK2, BLK4, BLK6) are selected. Voltage generators 2002(1), 2002(2), and 2002(3) are each activated. In this example, switches 2004(1), 2004(2), and 2004(3) are each closed so that each of voltage generators 2002(1), 2002(2), and 2002(3) supplies VGEN to a common line 2005 that connected to each selected erase block (BLK2, BLK4, BLK6). Optionally, each voltage generator could be used to provide its VGEN to a separate selected erase block. For example, voltage generators 2002(1) could provide their VGEN for BLK6, voltage generators 2002(2) their VGEN for BLK4, and voltage generators 2002(3) their VGEN for BLK2.

21 further details how the circuits in the 20A and 20B can be electrically connected to conductive regions in corresponding erase blocks. 21 Figure 12 illustrates portions of two sets of NAND chains 2120, 2130. In one embodiment, each set of NAND chains resides in a different erase block. Bit lines 2110a, 2110b, 2110c are associated with each set of NAND chains 2120,2130. The two sets of NAND chains 2120, 2130 are in the same plane. NAND chain set 2130 includes NAND chains 2161, 2162, 2163, as well as other NAND chains used in 21 are not shown. The NAND chain set 2120 includes similar NAND chains that allow cells in the different blocks to be programmed simultaneously. A number of memory cells 2121, 2122, 2123, 2124, 2125, 2126 are circled to indicate cells that can be programmed simultaneously. For example, the same data can be programmed into cells 2121 and 2124 at the same time; the same data can be programmed simultaneously in cells 2122 and 2125; and the same data can be programmed in cells 2123 and 2126 at the same time. Each of these memory cells has a control gate electrically connected to a conductive region in the respective block. For example, the respective control gates of cells 2121 , 2122 and 2123 are electrically connected via a selected conductive region 2140 . The respective control gates of cells 2124, 2125 and 2126 are electrically connected via a selected conductive region 2150. FIG. The term "selected" is used to indicate that the memory cells connected to these lines are selected for programming.

The voltage on bit lines 2210a-2210c is adjusted according to data being written to memory cells in each NAND string set 2120,2130. Although in 21 As three bit lines 2210 are shown, an array of memory cells can of course include many more bit lines. Furthermore, although two sets of NAND chains are illustrated, one or more additional copies may optionally be programmed, for example in a third set of NAND chains (not shown), a fourth set of NAND chains (not shown), and so on.

As before in connection with the 20A and 20B described, the voltage generators 2002(1) - 2002(N) can be activated separately and connected to the line 2005 via the switches 2004(1) - 2004(N). In 21 an example of providing a programming voltage (VPGM) to the NAND string sets is shown. In particular, voltage generators 2002(1) and 2002(2) are each activated, each generating VPGM. Switches 2004(1) and 2004(2) are closed to provide VPGM through line 2005. Switches 2102 are set to electrically connect line 2005 to both selected conductive region 2140 and selected conductive region 2150 . Switches 2102 may include transistors or the like. Therefore, VPGM is provided to the selected conductive regions 2140 and 2150. Therefore, VPGM is provided to the control gates of memory cells 2121-2126. Instead of providing VPGM to line 2005, switches 2102 could be used to provide VPGM from voltage generator 2002(1) to selected conductive region 2150 and from voltage generator 2002(2) to selected conductive region 2140.

If additional NAND chains are to be included in the concurrent programming, additional voltage generators 2002 can be used to provide VPGM. In one embodiment, there is a one-to-one correspondence between the voltage generators 2002 and the NAND chain sets. That is, in one embodiment, a voltage generator 2002 is enabled for each NAND string. However, a one-to-one correspondence is not required.

21 Figure 12 illustrates an example of providing VPGM selected conductive regions connected to different NAND strings. Each set of NAND chains can reside in a different erase block. The voltage generators 2002 can be used to provide other voltages (e.g., Vpass) to unselected conductive regions. The term unselected is used to indicate that memory cells connected to these lines are not selected for programming. In one embodiment, a channel boost voltage (Vpass) is applied to the control gates of unselected memory cells connected to unselected conductive regions.

22 FIG. 2200 is a flow diagram of one embodiment of a process 2200 for providing voltages while programming. The process can be used to provide voltages (e.g., VPGM, Vpass) during various processes described herein. For example, process 2200 may be used at steps 1606, 1806, 1812, 1818, 1906, 1912, 1918, and/or 1924. In step 2202, the system activates a number of voltage generators 2002 based on a number of NAND string sets involved in simultaneous programming. In one embodiment, the system activates a voltage generator 2002 for each NAND chain set. In one embodiment, the system activates a number of voltage generators 2002 based on a number of erase blocks involved in concurrent programming. In one embodiment, the system activates a voltage generator 2002 for each selected erase block.

In step 2204, the system simultaneously connects the activated voltage generators 2002 to conductive regions. The conductive regions are connected to control gates of memory cells in respective NAND strings. In step 2204, the system may control switches 2004 and/or switches 2102. In one embodiment, the system simultaneously connects the activated voltage generators 2002 to multiple selected conductive regions (e.g., 2140, 2150) to provide VPGM. In one embodiment, the system simultaneously connects the activated voltage generators 2002 to one or more unselected conductive regions in each erase block to provide Vpass.

23 12 illustrates an example of a multi-stage charge pump 2300. The charge pump 2300 may be used in a voltage generator 2002. FIG. Vin is provided at input node 2302, so Vout is obtained at output node 2326. For example, three stages 2308, 2316 and 2324 are provided. Two or more stages can be used. For example, each stage may include switches and one or more flying capacitors. At the input, a capacitor Cin 2304 is connected to a ground node 2306 at one of its conductive layers. At a node 2310 located between the first stage 2308 and the second stage 2316, a capacitor Ca 2312 is connected to a ground node 2314 at one of its conductive layers. At a node 2318 located between the second stage 2316 and the third stage 2324, a capacitor Cb 2320 is connected to a ground node 2322 at one of its conductive layers. Finally, at the output node 2326, an output capacitor Cout 2328 is connected to a ground node 2330 at one of its conductive layers. A multi-stage charge pump can provide greater flexibility by providing a wider range of output voltages. Furthermore can include one or more capacitors in each stage for even greater flexibility.

The multi-stage charge pump 2300 operates under the control of the regulation and control circuitry 2317, which controls the switching in each stage. It is also possible to additionally or alternatively provide a regulation and control circuit in each stage. Charge is transferred from the first stage input node 2302 to a flying capacitor (not shown) in the first stage 2308 and from the first stage flying capacitor to node 2310 . Charge is then transferred from the second stage node 2310 to a flying capacitor (not shown) in the second stage and from the second stage flying capacitor to node 2318 . The charge is then transferred from node 2318 to a flying capacitor (not shown) in the third stage and from the third stage flying capacitor to output node 2326, assuming there are no more stages.

As can be seen from the foregoing description, one aspect includes a device having a plurality of sets of NAND strings. Each NAND chain has memory cells. Each memory cell has a control gate. Each NAND chain has drain select gates. The device includes a plurality of bit lines associated with the plurality of sets of NAND strings. Each bit line is associated with a different NAND string in each set of NAND strings. The device includes one or more management circuits connected to the plurality of sets of NAND strings and to the plurality of bit lines. The one or more management circuits are configured to apply voltages to the plurality of bit lines according to a data pattern, apply a select voltage to drain select gates of multiple sets of the NAND chains, and apply a programming pulse to control gates of a different set simultaneously selected memory cells in each respective set of the multiple sets of NAND chains, while the selection voltage is applied to the drain select gates of the multiple sets of NAND chains and the voltages are applied to the plurality of bit lines to simultaneously inject the data pattern into each set of selected memory cells to program.

In another aspect, the multiple sets of NAND chains includes at least three sets of NAND chains.

In another aspect, the one or more management circuits are configured to simultaneously apply the programming pulse to the control gates of the different set of selected memory cells in each respective set of the multiple sets of NAND chains to move each selected memory cell to a single bit per cell program.

In another aspect, the data pattern defines whether a selected memory cell is to be programmed to one of a plurality of data states. The one or more management circuits are configured to select a size of the programming pulse based on which of the plurality of data states is currently being programmed at the same time.

In another aspect, the data pattern corresponds to a first data state of a plurality of data states. The programming pulse is a first programming pulse applied by the one or more management circuits to simultaneously program selected memory cells directed to the first data state.

In another aspect, the one or more management circuits are further configured to: apply voltages to the plurality of bit lines according to a second data pattern, the second data pattern corresponding to a second data state of the plurality of data states; simultaneously applying the select voltage to the drain select gates of the multiple sets of the NAND strings; and simultaneously applying a second programming pulse to the control gates of the set of selected memory cells in each respective set of the plurality of sets of NAND chains while applying the select voltage to the drain select gates of the plurality of sets of NAND chains and the voltages are applied to the bit lines to simultaneously program the second data pattern into each set of selected memory cells.

In a further aspect, the device also has a multiplicity of voltage generators. The one or more management circuits are further configured to activate a number of the voltage generators based on a number of the sets of selected memory cells to be programmed simultaneously. The one or more management circuits are configured to connect the activated voltage generators to the control gates of the set of selected memory cells in each respective set of the multiple sets of NAND chains to simultaneously apply the programming pulse to the control gates.

In another aspect, the one or more management circuits are further configured to enable a separate voltage generator for each set of selected memory cells to be programmed simultaneously.

One aspect is a method, comprising: i) applying a program enable voltage to selected bit lines according to a data state to which "n" sets of non-volatile memory cells are to be programmed simultaneously, where n is an integer greater than 1; ii) connecting each selected bit line to n selected NAND strings simultaneously, including simultaneously connecting each selected bit line to a different NAND string in n sets of NAND strings; iii) applying a program pulse simultaneously to control gates of n sets of memory cells while the selected bit lines are connected to the respective n selected NAND chains and the program enable voltage is applied to the selected bit lines to simultaneously set each of the n sets of memory cells to a program threshold voltage distribution associated with the data state; and iv) repeating i), ii) and iii) for zero or more additional data states.

One aspect includes a system having a plurality of sets of NAND strings, each NAND string including non-volatile memory cells, each memory cell having a control gate. The system includes a plurality of conductive regions, each conductive region being connected to the control gate of a memory cell of each NAND string in a set of the NAND strings. The system includes a plurality of bit lines associated with the plurality of sets of NAND chains, with each bit line associated with a different NAND chain in each set of NAND chains. The system includes a variety of voltage generators. The system includes one or more management circuits connected to the plurality of sets of NAND chains, the plurality of conductive regions, the plurality of bit lines, and the plurality of voltage generators. The one or more management circuits are configured to activate a number of the voltage generators based on a number of the conductive regions that are to receive the same voltage magnitude during a programming operation that simultaneously programs the same data pattern into n sets of the memory cells. Each set of memory cells is in a different set of the plurality of sets of NAND strings, where n is an integer greater than 1. The one or more management circuits are configured to connect the activated voltage generators to the number of conductive regions to simultaneously apply the same magnitude of voltage to the number of conductive regions when programming the same data pattern into the n sets of memory cells at the same time.

A means for electrically connecting a first wordline and a second wordline may, in various embodiments, include a concurrent programming component 150, a die controller 220, a programming circuit 284, a non-volatile memory device interface 139, a non-volatile memory media controller 126, a device driver, a controller (e.g., (e.g., a device driver or the like) executing on a host computing device 110, a processor 111, or other logic hardware.

A means for electrically selecting a bit line may, in various embodiments, include a simultaneous programming component 150, a die controller 220, a programming circuit 284, a non-volatile storage device interface 139, a non-volatile storage media controller 126, a host computing device 110, a bus 127, a communication network 115, a device driver, a controller (e.g., a device driver or the like) executing on a host computing device 110, a processor 111, other logic hardware, and/or other executable code stored on a computer-readable storage medium , lock in.

A means for applying a single programming pulse to the connected word lines may, in various embodiments, include a simultaneous programming component 150, a die controller 220, a programming circuit 284, a non-volatile memory device interface 139, a non-volatile memory media controller 126, a memory client 116, a host Computing device 110, a bus 127, a communications network 115, a device driver, a controller (e.g., a device driver or the like) executing on a host computing device 110, a processor 111, other logical hardware, and/or other executables Include code stored on a computer-readable storage medium.

The present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments are to be considered in all respects only as illustrative and not restrictive consider. The scope of the disclosure is, therefore, indicated by the appended claims rather than by the foregoing description. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US17227820 [0001]
• US16024002 [0001]
• US Pat. No. 8,134,871 [0140]
• US9343141 [0144]

Claims (20)

facility comprising: a plurality of sets of NAND chains, each NAND chain having memory cells, each memory cell having a control gate, each NAND chain having drain select gates; a plurality of bit lines associated with the plurality of sets of NAND chains, each bit line associated with a different NAND chain in each set of NAND chains; and one or more management circuits coupled to the plurality of sets of NAND chains and to the plurality of bit lines, the one or more management circuits configured to: applying voltages to the plurality of bit lines according to a data pattern; applying a select voltage to drain select gates of multiple sets of the NAND chains; and simultaneously applying a programming pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of NAND chains while applying the select voltage to the drain select gates of the multiple sets of NAND chains and the voltages to the plurality of bit lines may be applied to simultaneously program the data pattern into each set of selected memory cells. Setup according to claim 1 , wherein the plurality of sets of NAND chains includes at least three sets of NAND chains. Setup according to claim 1 wherein the one or more management circuits are arranged to simultaneously apply the programming pulse to the control gates of the different set of selected memory cells in each respective set of the plurality of sets of NAND chains to program each selected memory cell to a single bit per cell. Setup according to claim 1 , wherein the data pattern defines whether a selected memory cell is to be programmed to one of a plurality of data states, wherein the one or more management circuits are configured to: select a magnitude of the programming pulse based on which of the plurality of data states is currently being programmed at the same time. Setup according to claim 1 wherein the data pattern corresponds to a first data state of a plurality of data states, the programming pulse is a first programming pulse applied by the one or more management circuits to simultaneously program selected memory cells directed to the first data state. Setup according to claim 5 wherein the one or more management circuits are further configured to: apply voltages to the plurality of bit lines according to a second data pattern, the second data pattern corresponding to a second data state of the plurality of data states; simultaneously applying the select voltage to the drain select gates of the multiple sets of the NAND strings; and simultaneously applying a second programming pulse to the control gates of the different set of selected memory cells in each respective set of the plurality of sets of NAND chains while applying the selection voltage to the drain select gates of the plurality of sets of NAND chains and the Voltages are applied to the bit lines to simultaneously program the second data pattern into each set of selected memory cells. Setup according to claim 1 , further comprising a plurality of voltage generators, wherein the one or more management circuits are further configured to: activate a number of the voltage generators based on a number of the sets of selected memory cells to be programmed simultaneously; and connecting the activated voltage generators to the control gates of the set of selected memory cells in each respective set of the plurality of sets of NAND chains to simultaneously apply the programming pulse to the control gates. Setup according to claim 7 , wherein the one or more management circuits are further configured to enable a separate voltage generator for each set of selected memory cells to be programmed simultaneously. A method comprising: i) applying a program enable voltage to selected bit lines according to a data state to which "n" sets of non-volatile memory cells are to be programmed simultaneously, where n is an integer greater than 1; ii) simultaneously connecting each selected bit line to n selected NAND strings, including simultaneously connecting each selected bit line to a different NAND string in n sets of NAND strings; iii) simultaneously applying a program pulse to control gates of n sets of memory cells while connecting the selected bit lines to the respective n selected NAND chains and the program enable voltage is applied to the selected bit lines to simultaneously program each of the n sets of memory cells to a threshold voltage distribution associated with the data state; and iv) repeating i), ii) and iii) for zero or more additional data states. procedure according to claim 9 wherein repeating the i), the ii) and the iii) for zero or more additional data states comprises: repeating the i), the ii) and the iii) for at least three additional data states. procedure according to claim 9 wherein repeating the i), the ii) and the iii) for zero or more additional data states comprises: repeating the i), the ii) and the iii) for at least three additional data states without verifying any of the data states. procedure according to claim 11 , further comprising: after programming the n sets of memory cells to the data states simultaneously, performing a fine programming phase individually on each of the n sets of memory cells. procedure according to claim 9 wherein repeating i), ii) and iii) for zero or more additional data states comprises: selecting a programming pulse magnitude for each respective data state that depends on a threshold voltage associated with the data state. procedure according to claim 9 , wherein repeating the i), the ii) and the iii) for zero or more additional data states comprises: repeating the i), the ii) and the iii) for three additional data states to simultaneously expand each of the n sets of memory cells to two programming bits per cell. procedure according to Claim 14 , further comprising: individually programming each of the n sets of memory cells to four bits per cell after simultaneously programming the n sets of memory cells to two bits per cell. system comprising: a plurality of sets of NAND strings, each NAND string including non-volatile memory cells, each memory cell having a control gate; a plurality of conductive regions, each conductive region being connected to the control gate of a memory cell of each NAND string in a set of the NAND strings; a plurality of bit lines associated with the plurality of sets of NAND chains, each bit line associated with a different NAND chain in each set of NAND chains; a variety of voltage generators; and one or more management circuits coupled to the plurality of sets of NAND chains, the plurality of conductive regions, the plurality of bit lines, and the plurality of voltage generators, the one or more management circuits configured to: Enabling a number of the voltage generators based on a number of the conductive regions intended to receive the same magnitude of voltage during a programming operation that simultaneously programs the same data pattern into n sets of the memory cells, each set of the memory cells being in a different set of the plurality of sets of NAND chains, where n is an integer greater than 1; and Connecting the activated voltage generators to the number of conductive regions to simultaneously apply the same magnitude of voltage to the number of conductive regions when simultaneously programming the same data pattern into the n sets of memory cells. system according to Claim 16 , where: the same voltage magnitude is a program voltage; and the number of conductive regions is n selected conductive regions, each set of memory cells is connected to one of the n selected conductive regions. system according to Claim 17 , wherein: the one or more management circuits are configured to select one of the voltage generators for each of the selected conductive regions. system according to Claim 16 , where: the same voltage magnitude is a boost voltage; and the number of conductive regions are unselected conductive regions. system according to Claim 16 , wherein the one or more management circuits are configured to perform the following while the activated voltage generators are connected to the number of conductive regions: applying a program enable voltage to selected bit lines according to a data state to which the n sets of memory cells are to be programmed simultaneously ; and connecting each selected bit line to n selected NAND strings simultaneously, including connecting each selected one simultaneously Bit line with a different NAND chain in n sets of NAND chains.

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