DE102022100837A1 - MEMORY CELL WITH OFFSET INTERCONNECT THROUGH-THROUGH - Google Patents

Abstract

This disclosure relates to an integrated chip in some embodiments. The integrated chip includes a bottom insulation structure disposed over a bottom dielectric structure enclosing an interconnect. The lower insulation structure has sidewalls that extend through the lower insulation structure. A bottom electrode is disposed along sidewalls and a top surface of the bottom isolation structure, a data storage structure is disposed on first inner sidewalls and a top surface of the bottom electrode, and a top electrode is disposed on second inner sidewalls and a top surface of the data storage structure. On the top surface of the top electrode is an interconnect via. The bottom surface of the bottom electrode is laterally outside of the bottom surface of the interconnect via.

Description

REFERENCE TO RELATED APPLICATIONS

This application is a partial continuation of U.S. Application No. 16/663,952 , filed October 25, 2019 and the benefits of the preliminary U.S. Application No. 62/880,816 claimed, filed July 31, 2019. In addition, this application also claims the benefit of the provisional patents filed on July 12, 2021 U.S. Application No. 63/220,683 . The content of the above patent applications is incorporated herein by reference in its entirety.

BACKGROUND

Many modern electronic devices include electronic memories configured to store data. Electronic memory can be volatile memory or non-volatile memory. Volatile memory stores data when powered, while non-volatile memory is capable of storing data when power is removed. Ferroelectric random access memory (FeRAM) devices are a promising candidate for next-generation non-volatile memory technologies. This is because FeRAM devices provide many advantages including fast writing, high durability, low power consumption, and low susceptibility to damage from radiation.

character list

• 1 illustriert eine Querschnittsansicht einiger Ausführungsformen eines integrierten Chips mit einer Speichervorrichtung, die eine untere Elektrode mit einer oberen Fläche mit einem Ausschnitt aufweist.
• 2A illustriert eine Querschnittsansicht einiger Ausführungsformen eines integrierten Chips mit einer ferroelektrischen Direktzugriffspeichervorrichtung (FeRAM-Vorrichtung), die eine untere Elektrode mit einer oberen Fläche mit einem Ausschnitt aufweist.
• 2B illustriert eine Draufsicht auf einige Ausführungsformen des integrierten Chips von 2A.
• 3 illustriert eine Querschnittsansicht einiger weiterer Ausführungsformen eines integrierten Chips mit einer FeRAM-Vorrichtung, die eine untere Elektrode mit einer oberen Fläche mit einem Ausschnitt aufweist.
• 4A bis 4B illustriert Querschnittsansichten einiger weiterer Ausführungsformen integrierter Chips mit einer FeRAM-Vorrichtung, die eine untere Elektrode mit einer oberen Fläche mit einem Ausschnitt aufweist
• 5 illustriert eine Querschnittsansicht einiger weiterer Ausführungsformen eines integrierten Chips mit einer FeRAM-Vorrichtung, die eine untere Elektrode mit einer oberen Fläche mit einem Ausschnitt aufweist.
• 6 illustriert eine Querschnittsansicht einiger weiterer Ausführungsformen eines integrierten Chips mit einer FeRAM-Vorrichtung, die eine untere Elektrode mit einer oberen Fläche mit einem Ausschnitt aufweist.
• 7 bis 17 illustrieren Querschnittsansichten einiger Ausführungsformen eines Verfahrens des Bildens eines integrierten Chips, der eine FeRAM-Vorrichtung aufweist, ohne einen Planarisierungsprozess zu verwenden, um eine untere Elektrode der FeRAM-Vorrichtung zu definieren.
• 18 illustriert ein Ablaufdiagramm einiger Ausführungsformen eines Verfahrens zum Bilden eines integrierten Chips mit einer FeRAM-Vorrichtung ohne Verwendung eines Planarisierungsprozesses zur Definition einer unteren Elektrode der FeRAM-Vorrichtung.
• 19A bis 19B illustrieren einige zusätzliche Ausführungsformen eines integrierten Chips mit einer Speichervorrichtung, die eine obere Elektrode und eine untere Elektrode mit einer unteren Fläche aufweist, die gegenüber einer unteren Fläche einer Interconnect-Durchkontaktierung, die mit der oberen Elektrode in Kontakt steht, verschoben ist.
• 20A bis 20B illustrieren einige zusätzliche Ausführungsformen eines integrierten Chips mit einer Speichervorrichtung, die eine obere Elektrode und eine untere Elektrode mit einer unteren Fläche aufweist, die gegenüber einer unteren Fläche einer Interconnect-Durchkontaktierung, die mit der oberen Elektrode in Kontakt steht, verschoben ist.
• 21 illustriert eine Draufsicht einiger zusätzlicher Ausführungsformen integrierter Chips mit einer Speichervorrichtung, die eine obere Elektrode und eine untere Elektrode mit einer unteren Fläche aufweist, die gegenüber einer unteren Fläche einer Interconnect-Durchkontaktierung, die mit der oberen Elektrode in Kontakt steht, verschoben ist.
• 22A bis 22G illustrieren Draufsichten einiger zusätzlicher Ausführungsformen integrierter Chips mit einer Speichervorrichtung, die eine obere Elektrode und eine untere Elektrode mit einer unteren Fläche aufweist, die gegenüber einer unteren Fläche einer Interconnect-Durchkontaktierung, die mit der oberen Elektrode in Kontakt steht, verschoben ist.
• 23A bis 23D illustrieren Draufsichten einiger zusätzlicher Ausführungsformen integrierter Chips mit einer Speichervorrichtung, die eine obere Elektrode und eine untere Elektrode mit einer unteren Fläche aufweist, die gegenüber einer unteren Fläche einer Interconnect-Durchkontaktierung, die die obere Elektrode kontaktiert, verschoben ist.

Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It is noted that various elements are not drawn to scale, as is customary in the industry. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for the sake of clarity of explanation.

• 1 1 illustrates a cross-sectional view of some embodiments of an integrated chip with a memory device having a bottom electrode with a top surface with a cutout.
• 2A 12 illustrates a cross-sectional view of some embodiments of an integrated chip having a ferroelectric random access memory (FeRAM) device having a bottom electrode with a cutout top surface.
• 2 B FIG. 12 illustrates a top view of some embodiments of the integrated chip of FIG 2A .
• 3 12 illustrates a cross-sectional view of some other embodiments of an integrated chip with a FeRAM device having a bottom electrode with a top surface with a cutout.
• 4A until 4B 12 illustrates cross-sectional views of some other embodiments of integrated chips with a FeRAM device having a bottom electrode with a top surface with a cutout
• 5 12 illustrates a cross-sectional view of some other embodiments of an integrated chip with a FeRAM device having a bottom electrode with a top surface with a cutout.
• 6 12 illustrates a cross-sectional view of some other embodiments of an integrated chip with a FeRAM device having a bottom electrode with a top surface with a cutout.
• 7 until 17 12 illustrate cross-sectional views of some embodiments of a method of forming an integrated chip having a FeRAM device without using a planarization process to define a bottom electrode of the FeRAM device.
• 18 12 illustrates a flow chart of some embodiments of a method for forming an integrated chip with an FeRAM device without using a planarization process to define a bottom electrode of the FeRAM device.
• 19A until 19B Figure 12 illustrates some additional embodiments of an integrated chip with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that contacts the top electrode.
• 20A until 20B Figure 12 illustrates some additional embodiments of an integrated chip with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that contacts the top electrode.
• 21 1 illustrates a top view of some additional embodiments of integrated chips with a memory device having a top electrode and a bottom electrode with a bottom has surface that is offset from a bottom surface of an interconnect via that is in contact with the top electrode.
• 22A until 22G 12 illustrate top views of some additional embodiments of integrated chips with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that contacts the top electrode.
• 23A until 23D 12 illustrate top views of some additional embodiments of integrated chips with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that contacts the top electrode.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for implementing various elements of the provided content. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, only examples and should not be construed as limiting. For example, forming a first member or a second member in the following description may include embodiments where the first and second members are formed in face-to-face contact, and may also include embodiments where other members are between the first and second members can be formed so that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and/or letters of the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or devices discussed.

Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like may be used herein for ease of description to indicate the relationship of one element or elements to one or more other element(s). ) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in a different orientation) and the spatially relative terms used herein shall be construed accordingly.

Ferroelectric random access memory (FeRAM) devices have a bottom electrode separated from a top electrode by a ferroelectric material. The ferroelectric material has an intrinsic electric dipole that can be switched between opposite polarities by the application of an external electric field. The different polarities provide different capacitances for the FeRAM device that represent different data states (e.g., a logical "0" or "1"), allowing the FeRAM device to store data digitally. For example, during a read operation, the various capacitances of a voltage on a bit line attached to a FeRAM device can be detected to output a data state that was stored by the FeRAM device.

FeRAM devices are typically formed by depositing a less insulating structure over a dielectric structure that encloses multiple interconnect layers. The lower isolation structure is patterned to form an opening that exposes one or more of the multiple interconnect layers. A lower electrode layer is formed within the opening and over the less insulating structure. A chemical mechanical planarization (CMP) process is subsequently performed on the bottom electrode layer to define a substantially planar top surface. A ferroelectric layer is formed over the substantially planar top surface of the bottom electrode layer and a top electrode layer is formed over the ferroelectric layer. A first patterning process is performed on the top electrode layer and the ferroelectric layer to define a top electrode and ferroelectric structure. Sidewall spacers are then formed along sides of the top electrode, followed by a second patterning process to define a bottom electrode.

The cost of using a CMP process to form the bottom electrode significantly increases the cost of forming an FeRAM device since CMP processes are relatively expensive processes. In addition, it has been considered that a residue of a slurry used by the CMP process may remain on a substrate after the CMP process is completed. The residual sludge can accumulate over alignment marks used during subsequent lithography processes and hence cover the alignment marks. The obscuration of the alignment marks reduces a photolithography process window for the overlying layers, resulting in reduced yield and/or reliability of the FeRAM devices.

This disclosure relates, in some embodiments, to a method of forming a FeRAM device that does not use a CMP process to form a bottom electrode. By not using a CMP process to form the bottom electrode, the cost of forming the FeRAM device can be reduced and a photolithography process window of overlying layers can be improved. In some embodiments, the resulting FeRAM device includes a bottom electrode corresponding generally to sidewalls and a top surface of an underlying less insulating structure, a ferroelectric material disposed over the bottom electrode, and a top electrode over the ferroelectric material. Because the bottom electrode is formed without using a CMP process, the bottom electrode has inner sidewalls that define a first cutout located within a top surface of the bottom electrode. The ferroelectric material and/or top electrode is disposed within the first cutout and may also have inner sidewalls defining further cutouts.

1 10 illustrates a cross-sectional view of some embodiments of an integrated chip 100 with a memory device having a bottom electrode with a top surface with a cutout.

The integrated chip 100 includes an access device 104 disposed within a substrate 102 . In some embodiments, the access device 104 may include a transistor device (e.g., a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like). In some embodiments, the substrate 102 may include a semiconductor material (e.g., silicon, germanium, or the like). A lower dielectric structure 106 is disposed over the substrate 102 and encloses the access device 104. The lower dielectric structure 106 further encloses a plurality of lower interconnect layers 108 that are electrically coupled to the access device 104. FIG. A lower isolation structure 110 is disposed over the lower dielectric structure 106 . The bottom insulation structure 110 includes sidewalls 110s that define an opening over an interconnect structure 108a of the plurality of bottom interconnect layers 108 .

A storage device 112 is disposed within the opening and over an upper surface 110u of the lower isolation structure 110 . The memory device 112 includes a data storage structure 116 disposed between a bottom electrode 114 and a top electrode 118 . The data storage structure 116 is configured to store either a first data state (e.g., an 'o') or a second data state (e.g., a '1') depending on bias voltages applied to the bottom electrode 114 and the top electrode 118 are applied. For example, to store the first data state in data storage structure 116, a first set of bias conditions may be applied to bottom electrode 114 and top electrode 118. FIG. Alternatively, to store the second data state in data storage structure 116, for example, a second set of bias conditions may be applied to bottom electrode 114 and top electrode 118. FIG.

Bottom electrode 114 comprises a conductive material that generally conforms to a top surface of interconnect structure 108a, sidewalls 110s of bottom isolation structure 110, and a top surface of bottom isolation structure 110. FIG. Because the conductive material of bottom electrode 114 generally conforms to the underlying layers, bottom electrode 114 has inner sidewalls 114s and a horizontally extending surface 114h that define a first cutout 115 within a top surface 114u of bottom electrode 114. The data storage structure 116 and/or the top electrode 118 are arranged within the first cutout 115 . In some embodiments, data storage structure 116 and/or top electrode 118 may also include inner sidewalls that define additional cutouts.

A hard mask 120 is disposed over memory device 112 and sidewall spacers 122 extend along outermost sidewalls of top electrode 118 and hard mask 120 . In some embodiments, the hard mask 120 and protective layer 124 may also have inner sidewalls that form additional cutouts. A top interconnect structure 128 is disposed within a top dielectric structure 126 over the protective layer 124 . Top interconnect structure 128 extends from a top surface of top dielectric structure 126 to top electrode 118.

The first cutout 115 in the top surface of the bottom electrode 114 indicates that the bottom electrode 114 without a planarization pro process (e.g. a CMP process) was formed. By forming the bottom electrode 114 without using a planarization process, the bottom electrode 114 can be formed at a lower cost than processes that use a CMP process to form a bottom electrode. In addition, a photolithography process window for the overlying layers can also be improved compared to processes using a CMP process to form a bottom electrode.

2A FIG. 200A illustrates a cross-sectional view 200A of some embodiments of an integrated chip having a ferroelectric random access memory (FeRAM) device having a bottom electrode with a top surface having a cutout.

As shown in cross-sectional view 200A, the integrated chip includes a bottom dielectric structure 106 disposed over a substrate 102 . The bottom dielectric structure 106 includes a plurality of bottom interlayer dielectric (ILD) layers 106a-106c stacked on top of each other and separated by etch stop layers 107a-107b. In some embodiments, the multiple lower ILD layers 106a-106c may be one or more of silicon dioxide, doped silicon dioxide (e.g., carbon-doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass ( FSG) or the like. In some embodiments, etch stop layers 107a-107b may include silicon carbide, silicon nitride, titanium nitride, tantalum nitride, or the like.

A plurality of bottom interconnect layers 108 are disposed within bottom dielectric structure 106 . The lower plurality of interconnect layers 108 includes conductive contacts 202, interconnect wires 204, and interconnect vias 206, each of which is surrounded by one of the lower plurality of ILD layers 106a-106c. For example, the conductive contact 202 may be encased by a first lower ILD layer 106a, a first one of the interconnect wires 204 may be encased by a second lower ILD layer 106b, and so on. In some embodiments, the interconnect wires 204 and the interconnect via 206 each include a diffusion barrier layer surrounding a metal core. In some embodiments, the metal core may include copper, tungsten, aluminum, or the like. In some embodiments, the diffusion barrier layer may include titanium nitride, tantalum nitride, or the like. In some embodiments, the metal core and the diffusion barrier layer may have top surfaces that are substantially coplanar. In other embodiments, the diffusion barrier layer may extend vertically over outermost edges of the metal core.

A bottom isolation structure 110 may be disposed over the multiple bottom ILD layers 106a-106c. In some embodiments, the bottom isolation structure 110 may have a thickness in a range between about 200 Angstroms and about 400 Angstroms. In other embodiments, the bottom isolation structure 110 may have a thickness in a range between about 225 Angstroms and about 325 Angstroms. The lower insulation structure 110 includes sidewalls 110s that define an opening that extends through the lower insulation structure 110 . In some embodiments, the sidewalls 110s may be oriented at an acute angle α measured with respect to a bottom surface of the bottom isolation structure 110 . In some embodiments, a duct extending between a top and bottom of each of the sidewalls 110s may be oriented at an acute angle α measured with respect to a bottom surface of the bottom isolation structure 110 . In some embodiments, the acute angle α is in a range between about 40° and about 50°. In such embodiments, the acute angle α may limit gap filling problems in fabricating an overlying memory device. In addition, the acute angle α ensures good uniformity of the overlying layers, resulting in uniform performance of an overlying memory device. In various embodiments, the bottom isolation structure 110 may include one or more of the following: silicon oxynitride, silicon dioxide, silicon carbide, silicon nitride, tetraethyl orthosilicate (TEOS), a low-x dielectric, or the like.

A FeRAM device 208 is disposed over the bottom isolation structure 110 . The FeRAM device 208 includes a ferroelectric material 210 sandwiched between a bottom electrode 114 and a top electrode 118 . The bottom electrode 114, the ferroelectric material 210 and the top electrode 118 each have an inner region 212 which is laterally enclosed by an outer region 214 . Layers within inner region 212 each have a cut-out, horizontally extending surface disposed laterally between and vertically below top surfaces of a corresponding layer within outer region 214 . For example, bottom electrode 114 has a horizontally extending surface within inner region 212 that lies laterally between and vertically under the top surfaces of bottom electrode 114 within outer region 214 .

In some embodiments shown in top view 200B of FIG 2 B (along line AA' from 2A) 1, the outer region 214 may extend continuously in an unbroken ring around the inner region 212 when viewing the FeRAM device 208 in plan view. In some embodiments, the top surface of bottom electrode 114 extends in opposite directions along opposite edges of inner region 212 by distances d ₁ and d ₂ that are substantially equal. In some such embodiments, bottom electrode 114 is substantially symmetrical about a line 220 that divides the bottom surface of bottom electrode 114 in two. In other embodiments, distances d ₁ and d ₂ may be different such that bottom electrode 114 is asymmetric about lead 220 .

Referring again to cross-sectional view 200A of FIG 2A (along line BB' from 2 B) For example, the bottom electrode 114 extends continuously from a bottom surface 114b that is directly above the plurality of bottom interconnect layers 108 to line the sidewalls 110s and a top surface 110u of the bottom insulation structure 110. FIG. Bottom electrode 114 has inner sidewalls disposed over bottom surface 114b. The inner sidewalls couple to the horizontally extending surface to define a first cutout within a top surface of bottom electrode 114 . The ferroelectric material 210 resides in the first cutout and lines the inner sidewalls and top surface of the bottom electrode 114 . The ferroelectric material 210 has inner sidewalls that are disposed over the bottom surface of the bottom electrode 114 and form a second cutout within the top surface of the ferroelectric material 210 . The top electrode 118 is disposed in the second cutout and lines the inner sidewalls and top surface of the ferroelectric material 210 . In some embodiments, top electrode 118 has inner sidewalls that are disposed over the bottom surface of bottom electrode 114 and that define a third cutout within the top surface of top electrode 118 .

In some embodiments, bottom electrode 114 and top electrode 118 may include one or more of the following: titanium, tantalum, tungsten, tantalum nitride, titanium nitride, or the like. In some embodiments, the ferroelectric material 210 may include a metal, a metal oxynitride, or a compound metal oxide. In various embodiments, the ferroelectric material 210 may include, for example, lead titanate, lead zirconate titanate (PZT), lead lanthanum zirconate titanate, strontium bismuth tantalate (SBT), bismuth lanthanum titanate (BLT), and bismuth neodymium titanate (BNT) or the like.

In some embodiments, bottom electrode 114, ferroelectric material 210, and/or top electrode 118 may each have a thickness in a range between about 50 Angstroms and about 150 Angstroms. In other embodiments, bottom electrode 114, ferroelectric material 210, and/or top electrode 118 may each have a thickness of about 100 Angstroms. The specified thicknesses of the bottom electrode 114, the ferroelectric material 210 and/or the top electrode 118 prevent the overall height of the FeRAM device 208 from being large enough to be used in other regions of an integrated chip (e.g. in a logic region) and /or cause process problems in overlying layers of an integrated chip. In some embodiments, bottom electrode 114, ferroelectric material 210, and/or top electrode 118 may each have a substantially equal thickness between the outermost sidewalls. In some alternative embodiments, inner region 212 of bottom electrode 114, ferroelectric material 210, and/or top electrode 118 may have a first thickness and outer region 214 of bottom electrode 114, ferroelectric material 210, and/or top electrode 118 may have a second thickness less than the first thickness.

A hard mask 120 is placed over the top electrode 118 . Sidewall spacers 122 are disposed along opposite sides of top electrode 118 and hard mask 120 . In some embodiments, sidewall spacers 122 may include the same material as hard mask 120. In some embodiments, hard mask 120 and sidewall spacers 122 may include, for example, a carbide (e.g., silicon carbide), a nitride (e.g., silicon nitride), an oxide (e.g., e.g., silicon oxynitride) or the like. In other embodiments, the sidewall spacers 122 may comprise a different material than the hardmask 120. In some such embodiments, the sidewall spacers 122 and hardmask 120 may extend to different heights (e.g., the hardmask 120 may have a top surface that underlies a top surface of the sidewall spacers 122 is cut out, or vice versa).

A protective layer 124 is disposed over sidewall spacers 122 and hard mask 120 . The protective layer 124 continuously extends from above the hard mask 120 to the lower isolation structure 110. In some embodiments For example, protective layer 124 may include a carbide, an oxide, a nitride, TEOS (tetraethylorthosilicate), or the like. In some embodiments, hard mask 120 and protective layer 124 may each have a thickness ranging between about 50 Angstroms and about 150 Angstroms. In other embodiments, hard mask 120 and protective layer 124 may each have a thickness of about 100 Angstroms.

A top dielectric structure 126 is disposed over the protective layer 124 . The top dielectric structure 126 may extend to within a section defined by sidewalls of the protective layer 124 . An upper interconnect structure 128 is disposed within upper dielectric structure 126 . The top interconnect structure 128 extends from a top surface of the top dielectric structure 126 to the top electrode 118. In some embodiments, the top dielectric structure 126 may be carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphorus silicate glass (BPSG) , fluorinated silicate glass (FSG), a porous dielectric or the like. In various embodiments, the top interconnect structure 128 may include an interconnect via 216 (e.g., a top electrode via (TEVA)) and/or an interconnect wire 218 . In some embodiments, top interconnect structure 128 may include a conductive material, such as copper, tungsten, and/or aluminum.

In operation, bias voltages may be applied to bottom electrode 114 and/or top electrode 118 . For example, one or more bias voltages may be applied during a write operation to cause charge carriers (e.g., electrons and/or holes) to accumulate in bottom electrode 114 and/or top electrode 118 . The charge carriers create electric fields that extend through the ferroelectric material 210 . The electric fields are designed to change the positions of the electric dipoles within the ferroelectric material 210 depending on the bias voltages. When the positions of the electric dipoles within the ferroelectric material 210 define a first polarization, the FeRAM device 208 digitally stores data as a first bit value (e.g., a logical "o"). Alternatively, when the positions of the electric dipoles within the ferroelectric material 210 define a second polarization, the FeRAM device 208 digitally stores data as a second bit value (e.g., a logical "1").

3 FIG. 3 illustrates a cross-sectional view of some embodiments of an integrated chip 300 with a FeRAM device having a bottom electrode with a top surface with a cutout.

The integrated chip 300 includes a FeRAM device 208 disposed over a substrate 102 via a bottom isolation structure 110 . The FeRAM device 208 includes a ferroelectric material 210 sandwiched between a bottom electrode 114 and a top electrode 118 . In some embodiments, bottom electrode 114 includes a liner 302 and a conductive layer 304 disposed over liner 302 . The liner 302 extends along sidewalls and a top surface of the lower isolation structure 110. In some embodiments, the liner 302 may include titanium nitride, tantalum nitride, or the like. In some embodiments, the conductive layer 304 may include titanium, tantalum, or the like.

The bottom electrode 114 has inner sidewalls that are disposed over a bottom surface of the bottom electrode 114 . The inner sidewalls are coupled between a horizontally extending surface of bottom electrode 114 and a top surface of bottom electrode 114 . In some embodiments, the horizontally extending surface of bottom electrode 114 extends along a first horizontal plane 306 that intersects sidewalls 110s of bottom isolation structure 110 . In some embodiments, ferroelectric material 210 and top electrode 118 extend continuously from directly above bottom isolation structure 110 to positions below a second horizontal plane 308 that extends along a top surface 110u of bottom isolation structure 110 . By keeping the ferroelectric material 210 and top electrode 118 below the second horizontal plane 308, the height of the FeRAM device 208 can be kept relatively low, thereby reducing process issues on layers overlying the FeRAM device.

A hard mask 120 is placed over the top electrode 118 . The hard mask 120 includes inner sidewalls coupled to a horizontally extending surface. In some embodiments, the horizontally extending surface extends along a third horizontal plane 310 that underlies lower surfaces of top electrode 118 . In other embodiments (not shown), the third horizontal plane 310 may be above a top surface of the top electrode 118 .

4A until 4B 1 illustrates cross-sectional views of some embodiments of integrated chips with a FeRAM device having a bottom electrode with a top surface with a cutout.

As in 4A As shown, an integrated chip 400 includes a first access device 104a and a second access device 104b disposed in a substrate 102. FIG. A first FeRAM device 208a is coupled to the first access device 104a and a second FeRAM device 208b is coupled to the second access device 104b. The first FeRAM device 208a and the second FeRAM device 208b each include a ferroelectric material 210 disposed between a bottom electrode 114 and a top electrode 118 . Bottom electrode 114 has sidewalls that define a first cutout within a top surface of bottom electrode 114 . The ferroelectric material 210 has sidewalls that define a second cutout within a top surface of the ferroelectric material 210 . The top electrode 118 is positioned within the second cutout and completely fills the second cutout. Top electrode 118 has a top surface that overlies ferroelectric material 210 entirely. In some embodiments, the top electrode 118 has a substantially flat top surface that extends continuously across the second cutout.

A top interconnect structure 128 extends through a top dielectric structure 126 disposed over the first FeRAM device 208a to contact the top electrode 118. FIG. In some embodiments, top interconnect structure 128 may contact top electrode 118 at a location that is directly above a top surface 114u of bottom electrode 114 . In some additional embodiments, the top interconnect structure 128 may contact the top electrode 118 at a location laterally spanning an outer edge of the top surface 114u of the bottom electrode 114 . in others, in 4B In the embodiments shown, an integrated chip 402 includes a top interconnect structure 128 that contacts top electrode 118 at a location directly over the cutout in bottom electrode 114 . It should be noted that the contact between the top interconnect structure 128 and the top electrode 118 in a position directly over the cutout within the bottom electrode may reduce the risks associated with overlay errors during lithography processes that are used to form the upper interconnect structure 128.

5 FIG. 5 illustrates a cross-sectional view of some embodiments of an integrated chip 500 with a FeRAM device having a bottom electrode with a top surface with a cutout.

The integrated chip 500 includes FeRAM devices 208a-208b each including a ferroelectric material 210 sandwiched between a bottom electrode 114 and a top electrode 118. FIG. A hard mask 120 and a protective layer 124 are placed over the FeRAM devices 208a-208b.

The top electrode 118 has a top surface 118u that extends laterally from just above a top surface 210u of the ferroelectric material 210 to just above the bottom surface 114b of the bottom electrode 114 . In some embodiments, top surface 118u of top electrode 118 is disposed entirely over a top surface of bottom electrode 114 . In some additional embodiments, the top surface 118u of the top electrode 118 may also entirely overlie a top surface of the ferroelectric material 210 . In such embodiments, the top electrode 118 completely fills a section in the top surface 210u of the ferroelectric material 210 . In some embodiments, the top surface 118u of the top electrode 118 is a curved surface.

A top interconnect structure 128 extends through the hard mask 120 and protective layer 124 to contact the top electrode 118 . In some embodiments, top interconnect structure 128 may contact top electrode 118 at a location that is directly above bottom surface 114b of bottom electrode 114 . In such embodiments, the top surface 118u of the top electrode 118 may be tapered such that it intersects the sidewalls of the top electrode 118 at a non-zero angle as measured with respect to a horizontal plane. In some embodiments, the hard mask 120 and protective layer 124 may also have top surfaces that are sloped to intersect with the sidewalls of the top electrode 118 at non-zero angles measured with respect to horizontal planes. In other embodiments (not shown), the top interconnect structure 128 may contact the top electrode 118 at a location that is laterally offset from a lowest point along the top surface 118u of the top electrode 118 .

6 6 illustrates a cross-sectional view of some embodiments of an integrated chip 600 with a FeRAM device having a bottom elec rode having a top surface with a cutout.

The integrated chip 600 includes a substrate 102 having an embedded memory region 602 and a logic region 604. Within the embedded memory region 602, a plurality of lower interconnect layers 108 within a lower dielectric structure 106 are disposed. The multiple bottom interconnect layers 108 are coupled between the access devices 104a-104b disposed within the substrate 102 and the FeRAM devices 208a-208b disposed over a bottom isolation structure 110. FIG. The FeRAM devices 208a-208b each include a ferroelectric material 210 sandwiched between a bottom electrode 114 and a top electrode 118. FIG.

In some embodiments, the access devices 104a-104b each include a gate electrode 104g disposed vertically above the substrate 102 and laterally between a source region 104s and a drain region 104d. The gate electrode 104g may be coupled to a word line, WL ₁ or WL ₂ while the source region 104s may be coupled to a source line SL. The drain region 104d is coupled to one of the FeRAM devices 208a or 208b, which is further coupled to a bit line, BL ₁ or BL ₂ .

Within the logic region 604, one or more additional interconnect layers 608-612 are disposed within the lower dielectric structure 106 over the substrate 102. FIG. The one or more additional interconnect layers 608-612 include a conductive contact 608, an interconnect wire 610, and an interconnect via 612. The one or more additional interconnect layers 608-612 are connected to a logic device 606 that resides within the Substrate 102 is arranged. In some embodiments, logic device 606 may include a transistor device (e.g., a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like).

7 until 17 17 illustrate cross-sectional views 700-1700 of some embodiments of a method of forming an integrated chip having a FeRAM device without using a planarization process to define a bottom electrode of the FeRAM device. Even if too 7 until 17 are described with reference to a method, it should be noted that the 7 until 17 structures disclosed are not limited to such a method, but may stand on their own as structures independent of the method.

As in the cross-sectional view 700 from 7 As shown, a substrate 102 is provided. The substrate 102 includes an embedded memory region 602 and a logic region 604. An access device 104 is formed within the embedded memory region 602 of the substrate 102 and a logic device 606 is formed within the logic region 604 of the substrate 102. FIG. In various embodiments, the substrate 102 can be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more dies on a wafer, as well as any other type of semiconductor and/or or epitaxial layers associated therewith. In some embodiments, access device 104 and/or logic device 606 may include a transistor. In some such embodiments, access device 104 and/or logic device 606 may be formed by depositing a gate dielectric film and a gate electrode film over substrate 102 . The gate dielectric film and the gate electrode film are subsequently patterned to form a gate dielectric (e.g. 104g) and a gate electrode (e.g. 104e). The substrate 102 may subsequently be implanted to form a source region (e.g. 104s) and a drain region (e.g. 104d) within the substrate 102 on opposite sides of the gate electrode (e.g. 104e).

As shown in cross-sectional view 800 of FIG 8th As shown, a plurality of lower interconnect layers 108 are formed within a lower dielectric structure 106 that includes one or more lower interlayer dielectrics (ILD) 106a-106b over the substrate 102. FIG. In some embodiments, the one or more bottom ILD layers 106a-106b may include a first bottom ILD layer 106a and a second bottom ILD layer 106b separated by a first etch stop layer 107a. In some embodiments, the multiple bottom interconnect layers 108 may include a conductive contact 202 and an interconnect wire 204 . In some additional embodiments (not shown), the multiple bottom interconnect layers 108 may further include an interconnect via. The plurality of bottom interconnect layers 108 may be formed by placing one or more bottom ILD layers 106a-106b (e.g., an oxide, a low-k dielectric, or an ultra-low-k dielectric) over the substrate 102 is formed, the bottom ILD layer is selectively etched to define a via hole and/or trench within the bottom ILD layer, a conductive material (e.g., copper, aluminum, tungsten, etc.) within the via hole and/or a trench, and a planarization process (e.g., a chemical mechanical planarization (CMP) process) is performed.

As in the cross-sectional view 900 from 9 As shown, a lower insulation structure 110 is formed over the lower dielectric structure 106 . In some embodiments, the bottom isolation structure 110 may include one or more oxides, silicon nitride, silicon carbide, silicon oxynitride, TEOS, a metal oxide, a metal nitride, a metal carbide, or the like. In some embodiments, the bottom insulation structure 110 may be formed by one or more different deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.) to a thickness in one range between about 200 Angstroms and about 400 Angstroms.

As in the cross-sectional view 1000 of 10 As shown, lower isolation structure 110 is selectively patterned to define a plurality of openings 1002 extending through lower isolation structure 110 . The plurality of openings 1002 expose an interconnect structure 108a of the plurality of bottom interconnect layers 108. In some embodiments, the bottom isolation structure 110 may be selectively patterned by exposing the bottom isolation structure 110 to an etchant 1004 corresponding to a patterned masking layer 1006 formed on the bottom Insulation structure 110 is arranged. In some embodiments, the patterned masking layer 1006 may include a photoresist material, a hard mask, or the like. In some embodiments, the etchant 1004 may comprise a dry etchant (e.g., comprising fluorine or chlorine).

As shown in cross-sectional view 1100A of FIG 11A As shown, a bottom electrode layer 1102 is formed over bottom isolation structure 110 and within openings 1002 . The bottom electrode layer 1102 extends through the bottom insulation structure 110 to the interconnect structure 108a. The bottom electrode layer 1102 has sidewalls 1102s and a horizontally extending surface 1102h that define a first cutout 115 within a top surface 1102u of the bottom electrode layer 1102. FIG. The first cutout 115 is directly above the bottom surface 1102b of the bottom electrode layer 1102. In some embodiments, the bottom electrode layer 1102 may be formed by depositing a liner followed by depositing a conductive material. In some such embodiments, the liner may be formed over the lower insulation structure 110 and within the openings 1002 before the conductive material is formed over the liner and within the openings 1002. FIG. In some embodiments, the conductive material may include one or more of the following materials: tantalum, tantalum nitride, titanium, titanium nitride, tungsten, platinum, or the like. In various embodiments, the liner may include an adhesive layer configured to increase adhesion between adjacent layers and/or a diffusion barrier layer configured to prevent diffusion between adjacent layers. In some embodiments, the liner may include one or more of the following: titanium nitride, platinum, aluminum-copper, gold, titanium, tantalum, tungsten, tungsten nitride, or the like.

As shown in cross-sectional view 1100B of FIG 11B As shown, a data storage layer is formed over the bottom electrode layer 1102 and within the first portion (115 of 11A) educated. In some embodiments, the data storage layer may include a ferroelectric layer 1104 disposed over the bottom electrode layer 1102 and within the first portion (115 of 11A) is formed. Ferroelectric layer 1104 has sidewalls 1104s and a horizontally extending surface 1104h that define a second cutout 1106 within a top surface 1104u of ferroelectric layer 1104 and directly above bottom surface 1102b of bottom electrode layer 1102. FIG. In some embodiments, the ferroelectric layer 1104 may include a binary oxide, a ternary oxide, a quaternary oxide, or the like. In some embodiments, ferroelectric layer 1104 may include hafnium oxide doped with silicon, zirconium, gadolinium, or the like.

As shown in cross-sectional view 1100C of FIG 11C As shown, a top electrode layer 1108 is formed over the ferroelectric layer 1104 and within the second portion (1106 of 11B) educated. The top electrode layer 1108 has sidewalls 1108s and a horizontally extending surface 1108h that define a third cutout 1110 within a top surface 1108u of the top electrode layer 1108 and directly above the bottom surface 1102b of the bottom electrode layer 1102. FIG. In some embodiments, the top electrode layer 1108 may include one or more of the following: tantalum, tantalum nitride, titanium, titanium nitride, tungsten, platinum, or the like.

As in the cross-sectional view 1100D 11D shown is a hard mask layer 1112 above the top electrode layer 1108 and within the third cutout (1110 from 11C ) educated. In some embodiments, the hard mask layer 1112 has sidewalls 1112s and a horizontally extending surface 1112h that define a fourth cutout 1114 within a top surface 1112u of the hard mask layer 1112 and directly above the bottom surface 1102b of the bottom electrode layer 1102. In other embodiments (not shown), the sidewalls 1112s of the hard mask layer 1112 may meet at a point that is directly above the bottom surface 1102b of the bottom electrode layer 1102 to form the fourth cutout 1114 . In some embodiments, the hard mask layer 1112 may include one or more of the following: titanium nitride, silicon oxide, silicon nitride, silicon carbon nitride, a metal oxide (e.g., titanium oxide, aluminum oxide, etc.), or the like.

As in the cross-sectional view 1200 from 12 As shown, a first patterning process to define a top electrode 118 and a hard mask 120 is performed. The first patterning process selectively exposes the hard mask layer (1112 from 11D ) and the top electrode layer (1108 from 11D ) for an etchant 1204 after a masking layer 1202 (e.g., a photoresist material, a hard mask, or the like) to define the top electrode 118 and the hard mask 120. FIG.

In some embodiments, after the completion of the first patterning process, the hard mask 120 has a central region 120c and a peripheral region 120p enclosing the central region 120c. In some embodiments, the central region 120c may be a portion of the hardmask 120 that is directly above the third cutout (1110 in 11C ) is located. In some embodiments, the hard mask 120 may have a thickness that varies within the central region 120c of the hard mask 120, while the hard mask 120 may have a thickness that is substantially constant over the peripheral region 120p. The thickness variations within the central region 120c cause the hardmask 120 to have different thicknesses at different lateral locations within the central region 120c, as seen in the cross-sectional view 1200. FIG. In some embodiments, the thickness variations within the central region 120c of the hard mask 120 may be due to non-uniform deposition of the hard mask layer (1112 in 11D ) via cutouts within the bottom electrode layer 1102, the ferroelectric layer 1104, and the top electrode layer (1106 in 11C ) resulting from forming the respective layers without using a planarization process (e.g., a CMP process).

As in the cross-sectional view 1300 from 13 As shown, sidewall spacers 122 are formed along sidewalls of top electrode 118 and hard mask 120 . In some embodiments, sidewall spacer 122 may completely cover sidewalls of top electrode 118 and/or hard mask 120 . In various embodiments, the sidewall spacers 122 may include titanium nitride, silicon oxide, silicon nitride, silicon dioxide, silicon carbon nitride, silicon oxynitride, a metal oxide (e.g., titanium oxide, aluminum oxide, etc.), or the like. In some embodiments, the sidewall spacers 122 may be formed by forming a spacer layer over the substrate. In some embodiments, the spacer layer may be formed using a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). The spacer layer is subsequently exposed to an etchant (e.g., a dry etchant) that removes the spacer layer from horizontal surfaces. Removing the spacer layer from horizontal surfaces leaves a portion of the spacer layer along opposite sides of the top electrode 118 and the hard mask 120 as the sidewall spacers 122.

As in the cross-sectional view 1400 from 14 1, a second patterning process is performed to define a first FeRAM device 208a and a second FeRAM device 208b, each including a ferroelectric material 210 disposed between a bottom electrode 114 and the top electrode 118. FIG. The second patterning process selectively exposes the ferroelectric layer (1104 off 13 ) and the bottom electrode layers (1102 from 13 ) for an etchant 1402 to define the ferroelectric material 210 and the bottom electrode 114. FIG. In some embodiments, the second patterning process may further etch the bottom isolation structure 110 to cause the bottom isolation structure 110 to have a smaller thickness laterally outward of the bottom electrode 114 than directly below the bottom electrode 114.

As in the cross-sectional view 1500 from 15 As shown, a protective layer 124 is formed over the first FeRAM device 208a and the second FeRAM device 208b. The protective layer 124 has sidewalls 124s and a horizontally extending surface 124h that define a fifth cutout 1502 located within a top surface 124u of the protective layer 124 and directly above a bottom surface 114b of the lower electrode 114 is located. In some embodiments, the protective layer 124 may be formed using a deposition technique (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In various embodiments, the protective layer 124 may include one or more of the following: silicon carbide, tetraethyl orthosilicate (TEOS), or the like.

As in the cross-sectional view 1600 from 16 As shown, a top dielectric structure 126 is formed over protective layer 124 . The top dielectric structure 126 is formed to cover the first FeRAM device 208a and the second FeRAM device 208b. In some embodiments, the top dielectric structure 126 may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, or the like). In various embodiments, the top dielectric structure 126 may be silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphoric acid glass (PSG), borophosphoric silicate glass (BPSG), fluorinated silicate glass (FSG), a porous dielectric (e.g., porous carbon-doped silicon dioxide), or include the like.

As shown in cross-sectional view 1700 of 17 As shown, a top interconnect structure 128 is formed in top dielectric structure 126 within embedded memory region 602 and one or more additional interconnect layers 610-612 are formed in top dielectric structure 126 within logic region 604. In some embodiments, the top interconnect structure 128 may include an interconnect via 216 (e.g., a top electrode via (TEVA)) and/or an interconnect wire 218 . In some embodiments, the one or more other interconnect layers 610 - 612 may include an interconnect via 612 and an interconnect wire 610 . The top interconnect structure 128 and the one or more additional interconnect layers 610-612 may be simultaneously formed by selectively etching the top dielectric structure 126 to define via holes and/or trenches within the top dielectric structure 126, a conductive material ( e.g., copper, aluminum, etc.) within the vias and/or trenches and to perform a planarization process (e.g., a chemical-mechanical planarization process). In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process.

In some embodiments, interconnect via 216 may be formed to extend through peripheral region 120p of hard mask 120 to contact a top surface of top electrode 118 . By having the via 216 extend through the peripheral region 120p of the hardmask 120, an etch process used to form the interconnect via 216 avoids etching through the different thicknesses of the hardmask 120 within the central region 1200, resulting in a poor etch of a via hole (which could result, for example, in an over-etch that could result in a high resistance connection between the interconnect via 216 and the top electrode 118, or which could result in an under-etch that could result in an open circuit ). Since the hard mask 120 has a substantially constant thickness within the peripheral region 120p, the process window of an etch process for forming the interconnect via 216 can be improved. The improvement of the process window of the etching process allows a better integration of high-density memory arrays (e.g. high-density FeRAM arrays) in an integrated chip. Additionally, due to the improved process window, the etch process may be able to completely remove a portion of the hard mask 120 over the top electrode 118 without damaging the top electrode 118, thereby providing a good electrical connection between the top electrode 118 and the interconnect via 216 can be reached. In some embodiments, the interconnect via 216 has a bottom surface 216b that is centered on a first vertically extending line 1702 and that is laterally offset a first non-zero distance 1706 from a second vertically extending line 1704 that is extends through a center of a bottom surface 114b of the bottom electrode 114 . In some embodiments, interconnect via 216 is directly over a substantially flat top surface of top electrode 118.

18 18 illustrates a flow chart of some embodiments of a method 1800 for forming an integrated chip with an FeRAM device without using a planarization process to define a bottom electrode of the FeRAM device.

While method 1800 is illustrated and described herein as a series of actions or events, it is understood that the illustrated order of such actions or events is not to be construed in a limiting manner. For example, some actions may occur in different orders and/or concurrently with other actions or events different from those illustrated and/or described herein are. Furthermore, not all acts illustrated may be required in order to practice one or more aspects or embodiments of the description herein. Furthermore, one or more of the actions presented herein may be performed in one or more separate actions and/or phases.

At 1802, an access device is formed in a substrate. 7 FIG. 7 illustrates a cross-sectional view 700 of some embodiments corresponding to action 1802. FIG.

At 1804, a plurality of bottom interconnect layers are formed in a bottom dielectric structure over the substrate. 8th 8 illustrates a cross-sectional view 800 of some embodiments that correspond to action 1804. FIG.

At 1806, a lower insulation structure is formed over the lower dielectric structure. The bottom insulation structure is formed to have openings overlying an interconnect structure of the multiple bottom interconnect layers. 9 until 10 18 illustrates cross-sectional views 900-1000 of some embodiments that correspond to action 1806. FIG.

At 1808, a bottom electrode layer, a ferroelectric layer, a top electrode layer, and a hard mask layer are sequentially formed over the bottom isolation structure. 11A until 11D 1100A-1100D, cross-sectional views illustrate some embodiments corresponding to action 1808. FIG.

At 1810, a first patterning process is performed on the top electrode layer and the hard mask layer to define a top electrode and a hard mask. 12 1200 illustrates a cross-sectional view of some embodiments that correspond to action 1810. FIG.

At 1812, sidewall spacers are formed along the sidewalls of the top electrode and hardmask. 13 1300 illustrates a cross-sectional view of some embodiments that correspond to action 1812. FIG.

At 1814, a second patterning process is performed on the ferroelectric layer and the bottom electrode layer to define a first FeRAM device and a second FeRAM device each having a ferroelectric material sandwiched between a bottom electrode and the top electrode. 14 1400 illustrates a cross-sectional view of some embodiments that correspond to action 1814. FIG.

At 1816, a protective layer is formed over the first FeRAM device and the second FeRAM device. 15 1500 illustrates a cross-sectional view of some embodiments that correspond to action 1816. FIG.

At 1818, a top interconnect structure is formed in a top dielectric structure disposed over the protection layer. 16 until 17 1600-1700 illustrate cross-sectional views of some alternative embodiments that action 1818 corresponds to.

19A 19 illustrates a cross-sectional view of some additional embodiments of integrated chips 1900 with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that contacts the top electrode.

The integrated chip 1900 includes a memory device 112 (e.g., an FeRAM device) disposed over a bottom isolation structure 110 over a substrate 102 . The memory device 112 includes a data storage structure 116 disposed between a bottom electrode 114 and a top electrode 118 . In some embodiments, the bottom electrode 114 may contact an interconnect structure 108a disposed within a bottom dielectric structure 106 below the bottom isolation structure 110 . In some embodiments, bottom electrode 114 includes a liner 302 and a conductive layer 304 disposed over liner 302 . The liner 302 extends along sidewalls and a top surface of the lower insulation structure 110. The liner 302 may be configured to act as a diffusion barrier and/or adhesive layer.

Bottom electrode 114, data storage structure 116, and top electrode 118 are conformally disposed over bottom insulating structure 110 such that bottom electrode 114, data storage structure 116, and top electrode 118 each have a non-planar top surface (e.g., a top surface with a concave profile in a central region). For example, bottom electrode 114 has one or more first interior sidewalls that connect to a first horizontally extending surface to define a first cutout within a top surface of bottom electrode 114 . The data storage structure 116 is disposed within the first section and includes another second inner sidewall connected to a second horizontally extending surface to define a second section within a top surface of the Data storage structure 116 and to be defined directly above the first pane. The top electrode 118 is disposed within the second cutout and includes one or more third inner sidewalls that meet at a point overlying the second cutout to define a third cutout within a top surface 118u of the top electrode 118 . In some embodiments, the one or more third interior sidewalls may include curved sidewalls. In some embodiments, the top surface 118u of the top electrode 118 is a substantially planar surface.

A hard mask 120 is placed over the top electrode 118 . The hard mask 120 extends continuously from the top surface 118u of the top electrode 118 to just between the third inner sidewalls of the top electrode 118 such that the hard mask 120 is located within the third cutout. In some embodiments, the hardmask 120 includes one or more inner sidewalls 120s that meet at a point overlying the third cutout to form a fourth cutout within a top surface of the hardmask 120 . In some embodiments, the one or more inner sidewalls 120s may include curved sidewalls. The hard mask 120 has a central region 1200 that spans the third cutout within the top electrode 118 and a peripheral region 120p that encloses the central region 120c. In some embodiments, the hard mask 120 can have a thickness that varies within the central region 120c of the hard mask 120 . The thickness variations within the central region 120c cause the hard mask 120 to have different thicknesses at different lateral positions within the central region 120c. For example, the hard mask 120 can have a first thickness t ₁ in a first position and a second thickness t ₂ in a second position, which differs from the first thickness t ₁ . In some embodiments, the thickness of the hard mask 120 varies over a first range of vertical distances within the central region 120c and the thickness of the hard mask 120 varies over a second B of vertical distances, smaller than the first range, within the peripheral region 120p.

An interconnect via 216 (e.g., a top electrode via or a top electrode via (TEVA)) is disposed in a top dielectric structure 126 (e.g., a top ILD layer) that overlies the memory device 112 and the bottom isolation structure 110 is located. Interconnect via 216 extends through hard mask 120 to contact top electrode 118 . A bottom surface 216b of the interconnect via 216 is centered on a first vertically extending line 1702 that is laterally offset a first non-zero distance 1706 from a second vertically extending line 1704 that is on a bottom surface 114b of the bottom electrode 114 is centered. By offsetting the first vertical line 1702 laterally from the second vertical line 1704, the interconnect via 216 may be offset from the third cutout. In some embodiments, interconnect via 216 may have a bottom surface 216b that is laterally separated from one or more inner sidewalls 120s of hardmask 120 by a second non-zero distance 1902 .

As in the 1904 plan view of 19 As shown, in some embodiments, a protrusion 1906 (e.g., a border) of a bottom surface (114b of 19A) of the lower electrode (114 of 19A) completely laterally outward of a protrusion 1908 (e.g., a boundary) of a bottom surface (216b of 19A) of interconnect via (216 from 19A) lie. In some embodiments, the bottom surface protrusion 1906 of the bottom electrode may extend laterally beyond the bottom surface protrusion 1908 of the interconnect via along a first direction 1912 . In some additional embodiments, the bottom electrode bottom surface protrusion 1906 may be laterally separated from the interconnect via bottom surface protrusion 1908 by a third non-zero distance 1910 along a second direction 1914 that is perpendicular to the first direction 1912 .

By contacting top surface 118u of top electrode 118 at a lateral location that is outside of bottom surface 114b of bottom electrode 114 , interconnect via 216 may terminate on a relatively flat region of top electrode 118 . Terminating in the relatively flat region of top electrode 118 avoids having to etch through the various thicknesses of hard mask 120 when manufacturing interconnect via 216 . By avoiding the need to etch through the variable thickness of the hard mask 120 during fabrication of the interconnect via 216, non-uniformities in the etch can be avoided, resulting in a relatively low probability of poor contact between the top electrode 118 and the interconnect via 216 and prevents an open circuit or relatively low contact resistance between interconnect via 216 and top electrode 118 .

20A 12 illustrates a cross-sectional view of some additional embodiments of integrated chips 2000 with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that contacts the top electrode.

The integrated chip 2000 includes a memory device 112 disposed over a substrate 102 via a bottom isolation structure 110 . The memory device 112 includes a data storage structure 116 disposed between a bottom electrode 114 and a top electrode 118 . In some embodiments, a hard mask 120 is placed over the top electrode 118 . The hard mask 120 may include one or more inner sidewalls 120s that form a cutout within a top surface of the hard mask 120 . In some embodiments, the one or more inner sidewalls 120s are curved and meet at a point that is directly above a bottom surface 114b of the bottom electrode 114 .

In some embodiments, memory device 112 may be asymmetric about a vertically extending line 2002 bisecting bottom surface 114b of bottom electrode 114 . For example, in some embodiments, memory device 112 may extend a first distance 2004 beyond a first edge of bottom surface 114b and a second distance 2006 beyond an opposite second edge of bottom surface 114b. In such embodiments, the top electrode 118 may include a first top surface 118u ₁ and a second top surface 118u ₂ as viewed along the cross-sectional view of FIG 20A . The first top surface 118u ₁ may have a first width that is greater than a second width of the second top surface 118u ₂ .

In some embodiments, an interconnect via 216 may be disposed within a top dielectric structure 126 (eg, a top ILD layer) over the memory device 112 . Interconnect via 216 may contact first top surface 118u ₁ . Having the interconnect via 216 contact the first top surface 118u ₁ improves the chances that the interconnect via 216 will extend through a region of the hardmask 120 with a uniform thickness. In some embodiments, a bottom surface 216b of interconnect via 216 is laterally separated from one or more inner sidewalls 120s of hardmask 120 by a non-zero distance.

In some embodiments, bottom electrode 114 and/or top electrode 118 may include one or more of the following: titanium, titanium nitride, tantalum, tantalum nitride, tungsten, platinum, ruthenium, iridium, molybdenum, or the like. In some embodiments, bottom electrode 114 and top electrode 118 may include or be made of the same material. In some embodiments, bottom electrode 114 and top electrode 118 may comprise different materials or be the same material. In some embodiments, bottom electrode 114 may include a liner 302 and a conductive layer 304 over liner 302 . In some such embodiments, the liner 302 may include titanium nitride, tantalum nitride, or the like, and the conductive layer 304 may include titanium, tantalum, or the like.

In some embodiments, data storage structure 116 may include a ferroelectric material. In some such embodiments, data storage structure 116 may comprise binary oxide, such as hafnium oxide (eg, HfO ₂ ). In other such embodiments, the data storage structure 116 may include a ternary oxide, such as hafnium silicate (e.g., HfSiO _x ), hafnium zirconate (e.g., HfZrO _x ), barium titanate (e.g., BaTiO ₃ ), lead titanate (e.g., PbTiO ₃ ), strontium titanate ( e.g. SrTiO ₃ ), aluminum scandium nitride (e.g. AlScN), aluminum gallium nitride (e.g. AlGaN), aluminum yttrium nitride (e.g. AlYN), doped hafnium oxide (e.g with a dopant of silicon, zirconium, yttrium, aluminum, gadolinium, strontium, lanthanum, scandium, germanium or the like). In other such embodiments, the data storage structure 116 may comprise a quaternary oxide such as lead zirconate titanate (e.g. PZT, PbZr _x Ti _y O _z ), barium strontium titanate (e.g. BaSrTiO _x ), strontium bismuth tantalite (e.g. SBT, SrBi ₂ Ta ₂ O _e ) or the like.

20B FIG. 12 illustrates a 2008 top view of some embodiments consistent with the integrated chip of FIG 20A correspond.

As in the 2008 top view of 20B As shown, in some embodiments, the boundary of the top electrode 118 can have a rectangular shape with a first width 2010 extending along a first direction 1912 and a second width 2012 extending along the second direction 1914 perpendicular to the first direction 1912 is. The second width 2012 is greater than the first width 2010.

A protrusion 1906 on the bottom surface of the bottom electrode and a protrusion 1908 on the bottom surface of the interconnect via tion are both located over the top electrode 118 boundary. In some embodiments, the bottom surface protrusion 1906 of the bottom electrode has a third width 2014 along the first direction 1912 and a fourth width 2016 along the second direction 1914. In some embodiments, the third width 2014 and the fourth width 2016 may be substantially the same . In some embodiments, the bottom surface interconnect via protrusion 1908 has a fifth width 2018 along the first direction 1912 and a sixth width 2020 along the second direction 1914. In some embodiments, the fifth width 2018 and the sixth width 2020 may be substantially the same being.

In some embodiments, the bottom surface protrusion 1906 of the bottom electrode may be separated from the bottom surface protrusion 1908 of the interconnect via by a distance 2022 measured along the second direction 1914 . In some embodiments, the distance 2022 may be greater than the fourth width 2016 and/or the sixth width 2020.

21 FIG. 2100 illustrates a top view 2100 of some additional embodiments of an integrated chip with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that is in contact with the top electrode.

As in the top view 2100 of 21 As shown, in some embodiments, a top electrode boundary 118 may have a first width 2010 extending along a first direction 1912 and a second width 2012 extending along a second direction 1914 . In some embodiments, the first width 2010 may range from about 10 nanometers (nm) to about 10000 nm, from about 100 nm to about 5000 nm, or other similar values. In some embodiments, the second width 2012 may range between about 10 nm and about 10000 nm, between about 100 nm and about 5000 nm, or other similar values. In some embodiments, the first width 2010 and the second width 2012 may be substantially the same, such that the boundary of a top electrode 118 may have a substantially square shape.

A protrusion 1906 on the bottom surface of a bottom electrode and a protrusion 1908 on the bottom surface of the interconnect via are both located within the perimeter of the top electrode 118 . In some embodiments, bottom electrode bottom surface protrusion 1906 has a third width 2014 along first direction 1912 and a fourth width 2016 along second direction 1914. In some embodiments, interconnect via bottom surface protrusion 1906 has a fifth width 2018 along the first direction 1912 and a sixth width 2020 along the second direction 1914. In some embodiments, the third width 2014, the fourth width 2016, the fifth width 2018, and the sixth width 2020 can each range between about 10 nm and about 1000 nm, between about 100 nm and about 500 nm or other similar values. In some embodiments, the third width 2014 and the fourth width 2016 may be substantially the same. In some embodiments, the fifth width 2018 and the sixth width 2020 may be substantially the same.

In some embodiments, a center (e.g., a geometric center) of the bottom surface protrusion 1906 of the bottom electrode and a center (e.g., a geometric center) of the bottom surface protrusion 1908 of the interconnect via may be separated by a spacing 2102 be separated from each other. In some embodiments, the distance may be greater than fourth width 2016 and/or sixth width 2020. In some embodiments, distance 2102 may be in a range between about 1 nm and about 1000 nm, between about 10 nm and about 500 nm, or others similar values.

It should be noted that the protrusion 1906 on the bottom surface of the bottom electrode, the border of the top electrode 118, and the protrusion 1908 on the bottom surface of the interconnect via have different geometries, sizes, and/or positions in different embodiments. The different geometries, sizes and positions allow to achieve different operating parameters and design considerations. 22A until 22G 12 illustrate top views of some additional embodiments of integrated chips with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that contacts the top electrode.

As in the top view 2200 from 22A As shown, in some embodiments, the perimeter of top electrode 118 may have a rounded shape (e.g., a substantially circular shape, a substantially oval shape, etc.). The rounded shape has one or more rounded outer sidewalls that define the perimeter of top electrode 118 . In some embodiments, the protrusion 1906 on the bottom surface of the bottom electrode and protrusion 1908 on the bottom surface of the interconnect via have different shapes than the boundary of the top electrode 118. For example, protrusion 1906 on the bottom surface of the bottom electrode and protrusion 1908 on the bottom surface of the Interconnect via have a substantially square shape.

As shown in plan view 2202 of 22B As shown, in some embodiments, bottom electrode bottom surface protrusion 1906 may be separated from interconnect via bottom surface protrusion 1908 by a distance 2022 that is greater than a fourth width 2016 of bottom surface protrusion 1906 of bottom surface electrode and/or a sixth width 2020 of the protrusion 1908 of the bottom surface of the interconnect via. In some embodiments, distance 2022 may be greater than about 1 nm, greater than about 10 nm, greater than about 100 nm, greater than about 1000 nm, or other similar values.

As shown in plan view 2204 of 22C As shown, in some embodiments, the bottom surface protrusion 1906 of the bottom electrode may laterally overlap a portion but not all of the bottom surface protrusion 1908 of the interconnect via by a non-zero distance 2206 . Bottom electrode bottom surface protrusion 1906 extends laterally beyond an outermost limit of via bottom surface protrusion 1908 such that interconnect via bottom surface protrusion 1908 does not completely overlap bottom electrode bottom surface protrusion 1906 . An overlap between the protrusions can reduce the size of a memory device. In some such embodiments, the center of the bottom surface protrusion 1906 of the bottom electrode is separated from the center of the bottom surface protrusion 1908 of the interconnect via by a distance 2102 that is less than a fourth width 2016 of the bottom surface protrusion 1906 of the bottom electrode and/or a sixth width 2020 of the protrusion 1908 of the bottom surface of the top electrode.

As in the top view 2208 of 22D As shown, in some embodiments, the boundary of the top electrode 118 may have a rectangular shape with a first width 2010 and a second width 2012 that is greater than the first width 2010. In some embodiments, the protrusion 1906 may be the bottom surface of the bottom electrode have a rectangular shape with a third width 2014 and a fourth width 2016 that is greater than the third width 2014. In some embodiments, the protrusion 1908 of the bottom surface of the interconnect via may have a rectangular shape with a fifth width 2018 and a sixth width 2020 that is less than the fifth width 2018. By having the interconnect via bottom surface protrusion 1908 extend along a long axis 1908a that does not intersect the bottom surface protrusion 1906 of the bottom electrode, the second width 2012 of the upper electrode 118 are reduced while the projections e can remain laterally offset from each other. Additionally, when the interconnect via bottom surface protrusion 1908 extends along a long axis 1908a that intersects a long axis 1906a that extends along the bottom electrode bottom surface protrusion 1906, negative electrical effects caused by Critical dimension (CD) errors are caused in a patterning process used to form the top electrode 118 .

In some embodiments, a center of the bottom surface protrusion 1906 of the bottom electrode may be separated from a center of the bottom surface protrusion 1908 of the interconnect via by a distance 2102 that extends along both the first direction 1912 and the second direction 1914 . In some embodiments, standoff 2102 may extend a greater length along second direction 1914 than along first direction 1912. In some embodiments, interconnect via bottom surface protrusion 1908 may extend over one or more outer edges of bottom surface protrusion 1906 extending out from the bottom electrode surface as seen in plan view 2208 .

As in the top view 2210 of 22E As shown, in some embodiments, the bottom surface protrusion 1906 of the bottom electrode may have a substantially square shape with a third width 2014 and a fourth width 2016 substantially equal to the third width 2014 . In some embodiments, the tab 1908 of the bottom surface of the interconnect via may have a rectangular shape with a fifth width 2018 and a sixth width 2020 that is greater than the fifth width 2018. In some embodiments, the tab 1906 of the bottom of the bottom Electrode extending beyond one or more outer edges of the protrusion 1908 of the bottom surface of the interconnect via as seen in the top view 2210 .

As shown in plan view 2212 of 22F As shown, in some embodiments, the boundary of the top electrode 118 may have a rectangular shape with a first width 2010 and a second width 2012 that is greater than the first width 2010. In some embodiments, the protrusion 1906 may be the bottom surface of the bottom electrode have a substantially square shape with a third width 2014 and a fourth width 2016 approximately equal to the third width 2014. In some embodiments, the bottom surface interconnect via protrusion 1908 may have a substantially square shape with a fifth width 2018 and a sixth width 2020 substantially equal to the fifth width 2018 . In some embodiments, the third width 2014 may be greater than the fifth width 2018.

As shown in plan view 2214 of 22G As shown, in some embodiments, the boundary of the top electrode 118 may have a rectangular shape with a first width 2010 and a second width 2012 that is greater than the first width 2010. In some embodiments, the protrusion 1906 may be the bottom surface of the bottom electrode have a substantially square shape with a third width 2014 and a fourth width 2016 approximately equal to the third width 2014. In some embodiments, the bottom surface interconnect via protrusion 1908 may have a substantially square shape with a fifth width 2018 and a sixth width 2020 substantially equal to the fifth width 2018 . In some embodiments, the third width 2014 may be less than the fifth width 2018.

23A until 23D 12 illustrate top views of some additional embodiments of integrated chips with a memory device having a top electrode and a bottom electrode with a bottom surface that is offset from a bottom surface of an interconnect via that contacts the top electrode. As in the plan views 23A until 23D As shown, the bottom surfaces of the bottom electrode and the interconnect via may have different shapes. In some embodiments, it may be beneficial to shape the bottom surface of the bottom electrode to have a different shape than the bottom surface of the interconnect via (e.g., because the bottom electrode is formed with a different etch process, the one has a different depth of field, due to critical dimension (CD) errors or the like).

As in the top view 2300 from 23A As shown, in some embodiments, bottom electrode bottom surface protrusion 1906 may have a substantially square shape and interconnect via bottom surface protrusion 1908 may have a substantially circular shape.

As shown in plan view 2302 of 23B As shown, in some embodiments, the bottom surface protrusion 1906 of the bottom electrode and the bottom surface protrusion 1908 of the interconnect via may have substantially circular shapes.

As shown in plan view 2304 of 23C 1, in some embodiments, bottom electrode bottom surface protrusion 1906 may have a substantially square shape and interconnect via bottom surface protrusion 1908 may have a polygonal shape extending along two or more sides of protrusion 1906 of FIG lower surface of the lower electrode.

As shown in plan view 2306 of 23D As shown, in some embodiments, bottom electrode bottom surface protrusion 1906 may have a substantially circular shape and interconnect via bottom surface protrusion 1908 may have a substantially square shape.

Accordingly, in some embodiments, this disclosure relates to a memory device having a bottom electrode and a top electrode that are not formed by a planarization process (e.g., a CMP process). The bottom electrode of the memory device has a bottom surface that is laterally offset from a bottom surface of an overlying interconnect via and contacts the top electrode of the memory device. By laterally offsetting the bottom surfaces of the bottom electrode and the interconnect via, a good electrical connection is provided between the interconnect via and the top electrode.

In some embodiments, this disclosure relates to an integrated chip. The integrated chip includes a bottom insulation structure disposed over a bottom dielectric structure enclosing an interconnect, the bottom insulation structure having sidewalls extending through the bottom insulation structure; a bottom electrode disposed along sidewalls and a top surface of the bottom isolation structure; a data storage structure, disposed on first inner sidewalls and a top surface of the bottom electrode; a top electrode disposed on second interior sidewalls and a top surface of the data storage structure; and an interconnect via disposed on a top surface of the top electrode, wherein a bottom surface of the bottom electrode is laterally outward of a bottom surface of the interconnect via. In some embodiments, a bottom surface boundary of the bottom electrode is laterally separated from a bottom surface boundary of the interconnect via by a non-zero distance as viewed from a top view of the bottom electrode and measured along a first direction. In some embodiments, the bottom surface of the bottom electrode has a first width measured along the first direction, the first width being less than the non-zero distance. In some embodiments, the bottom surface of the bottom electrode laterally overlaps a portion, but not all, of the bottom surface of the interconnect via. In some embodiments, the top surface of the top electrode is a substantially planar surface. In some embodiments, the top electrode has third inner sidewalls that connect to opposite sides of a horizontally extending surface to form a cutout within the top surface of the top electrode, with the bottom surface of the interconnect via laterally outward of the cutout within the upper surface of the upper electrode. In some embodiments, the integrated chip further includes a hard mask disposed over the top electrode, the hard mask having a substantially constant thickness over the top surface of the top electrode and a variable thickness over the cutout within the top surface of the top electrode. wherein the variable thickness of the hard mask varies over several different thicknesses. In some embodiments, the integrated chip further includes a hardmask disposed over the top electrode and having one or more curved sidewalls defining a cutout within a top surface of the hardmask, with the interconnect via laterally of the cutout within the top surface the hard mask is offset. In some embodiments, a bottom surface boundary of the bottom electrode is laterally separated from a bottom surface boundary of the interconnect via along a first direction; and the bottom surface boundary of the bottom electrode extends laterally beyond an outermost edge of the bottom surface boundary of the interconnect via along a second direction perpendicular to the first direction.

In other embodiments, this disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and having a bottom surface in contact with a bottom interconnect; a top electrode; a data storage structure disposed between the bottom electrode and the top electrode, the data storage structure comprising a ferroelectric material; and an interconnect via disposed on the top electrode, wherein a protrusion of a bottom surface of the interconnect via has a first center that is offset from a second center of a protrusion of the bottom surface of the bottom electrode. In some embodiments, the first center of the protrusion of the bottom surface of the interconnect via is separated from the second center of the protrusion of the bottom surface of the bottom electrode by a distance ranging from about 1 nanometer (nm) to about 1000 nm. In some embodiments, the bottom electrode has one or more first interior sidewalls that connect to a first horizontally extending surface to form a first cutout that is within a top surface of the bottom electrode and directly above the bottom electrode of the bottom surface located. In some embodiments, the tab of the bottom surface of the interconnect via is separated from the tab of the bottom surface of the bottom electrode by a non-zero distance. In some embodiments, the top electrode has one or more inner sidewalls that define a cutout that is within a top surface of the top electrode and is laterally offset from an outermost sidewall of the interconnect via. In some embodiments, the integrated chip further includes a dielectric extending from the cutout located within the top surface of the top electrode to opposite sides of the interconnect via. In some embodiments, the integrated chip further includes a hard mask over the top electrode having a central region of variable thickness and a peripheral region of substantially constant thickness, wherein the interconnect via extends through the peripheral region of the hard mask. In some embodiments, the integrated chip further includes a hard mask disposed over the top electrode and a central region having a thickness that varies over a first range of vertical thicknesses and a peripheral region having a thickness that varies over a second range of vertical thicknesses , which is smaller than the first range of vertical thicknesses, wherein the interconnect via extends through the peripheral region of the hard mask. In some execution forms In general, the peripheral region of the hard mask has a substantially constant thickness. In some embodiments, the integrated chip further includes a hard mask disposed over the top electrode and having one or more inner sidewalls that are curved and meet at a point that is directly over the bottom surface of the bottom electrode, the bottom surface of the interconnect via is laterally separated from the one or more inner sidewalls by a non-zero distance.

In other embodiments, this disclosure relates to a method of forming an integrated chip. The method includes forming a bottom insulation structure over an interconnect within a bottom dielectric structure over a substrate; removing a portion of the lower insulation structure to define an opening extending through the lower insulation structure to the interconnect; sequentially and conformally depositing a bottom electrode layer, a data storage layer, and a top electrode layer over the bottom isolation structure; patterning the bottom electrode layer, the data storage layer, and the top electrode layer to define a memory device having a data storage structure disposed between a bottom electrode and a top electrode; and forming an interconnect via on a substantially flat top surface of the top electrode, wherein a center of a bottom surface of the bottom electrode is laterally separated from a center of a bottom surface of the interconnect via.

The above outlines elements of various embodiments so that those skilled in the art may better understand aspects of this disclosure. Those skilled in the art should note that they can readily use this disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and/or achieve the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of this disclosure and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of the documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US16663952 [0001]
• US62880816 [0001]
• US63220683 [0001]

Claims (20)

Integrated chip comprising: a bottom insulation structure disposed over a bottom dielectric structure enclosing an interconnect, the bottom insulation structure having sidewalls that extend through the bottom insulation structure; a bottom electrode disposed along sidewalls and a top surface of the bottom isolation structure; a data storage structure disposed on first inner sidewalls and a top surface of the bottom electrode; a top electrode disposed on second interior sidewalls and a top surface of the data storage structure; and an interconnect via disposed on a top surface of the top electrode, wherein a bottom surface of the bottom electrode is laterally outward of a bottom surface of the interconnect via. Integrated chip after claim 1 wherein a bottom surface boundary of the bottom electrode is laterally separated from a bottom surface boundary of the interconnect via by a non-zero distance as viewed from a top view of the bottom electrode and measured along a first direction. Integrated chip after claim 2 , wherein the bottom surface of the bottom electrode has a first width measured along the first direction, the first width being less than the non-zero distance. The integrated chip of any preceding claim, wherein the bottom surface of the bottom electrode laterally overlaps a portion but not all of the bottom surface of the interconnect via. An integrated chip as claimed in any preceding claim, wherein the top surface of the top electrode is a substantially planar surface. The integrated chip of any preceding claim, wherein the top electrode has third inner sidewalls coupled to opposite sides of a horizontally extending surface to define a cutout within the top surface of the top electrode, the bottom surface of the interconnect via laterally outside the cutout within the top surface of the top electrode. Integrated chip after claim 6 , further comprising: a hard mask disposed over the top electrode, the hard mask having a substantially constant thickness over the top surface of the top electrode and a variable thickness over the cutout within the top surface of the top electrode, the variable thickness of the hard mask varies over several different thicknesses. An integrated chip according to any one of the preceding claims, further comprising: a hardmask disposed over the top electrode and having one or more curved sidewalls defining a cutout within a top surface of the hardmask, wherein the interconnect via is laterally offset from the cutout within the top surface of the hardmask. Integrated chip according to one of the preceding claims, wherein a bottom surface boundary of the bottom electrode is laterally separated from a bottom surface boundary of the interconnect via along a first direction; and wherein the bottom surface boundary of the bottom electrode extends laterally beyond an outermost edge of the bottom surface boundary of the interconnect via along a second direction that is perpendicular to the first direction. Integrated chip comprising: a bottom electrode disposed over a substrate and having a bottom surface in contact with a bottom interconnect; a top electrode; a data storage structure located between the bottom electrode and the top electrode, the data storage structure comprising a ferroelectric material; and an interconnect via disposed on the top electrode, wherein a protrusion of a bottom surface of the interconnect via has a first center offset from a second center of a protrusion of the bottom surface of the bottom electrode. Integrated chip after claim 10 wherein the first center of the protrusion of the bottom surface of the interconnect via is separated from the second center of the protrusion of the bottom surface of the bottom electrode by a distance ranging from about 1 nanometer (nm) to about 1000 nm. Integrated chip after claim 10 or 11 wherein the bottom electrode has one or more first inner sidewalls connected to a first horizontally extending surface to define a first cutout located within a top surface of the bottom electrode and directly above the bottom surface of the bottom electrode . Integrated chip according to any of the preceding Claims 10 until 12 wherein the tab of the bottom surface of the interconnect via is separated from the tab of the bottom surface of the bottom electrode by a non-zero distance. Integrated chip according to any of the preceding Claims 10 until 13 wherein the top electrode has one or more inner sidewalls that define a cutout that is within a top surface of the top electrode and is laterally offset from an outermost sidewall of the interconnect via. Integrated chip after Claim 14 , further comprising: a dielectric extending from within the cutout located within the top surface of the top electrode along opposite sides of the interconnect via. Integrated chip according to any of the preceding Claims 10 until 15 , further comprising: a hard mask over the top electrode having a central region with a variable thickness and a peripheral region with a substantially constant thickness, wherein the interconnect via extends through the peripheral region of the hard mask. Integrated chip after claim 10 until 15 , further comprising: a hard mask disposed over the top electrode and a central region having a thickness that varies over a first range of vertical thicknesses and a peripheral region having a thickness that varies over a second range of vertical thicknesses, the is less than the first range of vertical thicknesses, wherein the interconnect via extends through the peripheral region of the hard mask. Integrated chip after Claim 17 , wherein the peripheral region of the hard mask has a substantially constant thickness. Integrated chip according to any of the preceding Claims 10 until 15 , further comprising: a hard mask disposed over the top electrode and having one or more inner sidewalls that are curved and meet at a point that is directly above the bottom surface of the bottom electrode, the bottom surface of the interconnect - the via is laterally separated from the one or more inner sidewalls by a non-zero distance. A method of forming an integrated chip, comprising: forming a bottom insulation structure over an interconnect within a bottom dielectric structure over a substrate; removing a portion of the lower insulation structure to define an opening extending through the lower insulation structure to the interconnect; sequentially and conformally depositing a bottom electrode layer, a data storage layer, and a top electrode layer over the bottom isolation structure; patterning the bottom electrode layer, the data storage layer, and the top electrode layer to define a memory device having a data storage structure disposed between a bottom electrode and a top electrode; and forming an interconnect via on a substantially flat top surface of the top electrode, wherein a center of a bottom surface of the bottom electrode is laterally separated from a center of a bottom surface of the interconnect via.

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