DE102021212454A1 - METHODS OF TRAINING AND/OR EXECUTING A CONVOLUTION-BASED NEURAL NETWORK USING AN APPROXIMATED FOURIER FAST TRANSFORMATION - Google Patents

Abstract

A method is described for training and/or executing a convolutional neural network (CNN) using an approximate fast Fourier transform (AFFT), the method comprising: providing at least two input signals; performing a convolution, comprising: approximating a Fourier transform for each of the at least two input signals to obtain at least two approximate fast Fourier transforms (AFFT); calculating a Hadamard product of the at least two approximate Fast Fourier Transforms (AFFT) to obtain an approximate convolution result in the frequency domain; approximating an inverse Fourier transform to obtain an approximate inverse fast Fourier transform (iAFFT); and outputting the inverse (iAFFT) as an approximate convolution result in the time domain. A circuit for training and/or executing a convolution-based neural network and a computer program product are also described.

Description

The present invention relates to a method for the approximate calculation of butterfly units of a Fourier transformation of a signal, a circuit for the approximate calculation of butterfly units of a Fourier transformation of a signal, and a corresponding computer program product.

The progressive development of the Internet of Things (loT) leads to an ubiquity of intelligent systems. These are directly embedded in applications and consist of sensors for recording the environment, processors for direct data processing and external communication interfaces. The relocation of the calculations required for processing close to the action (edge computing) using embedded systems leads to new challenges, especially with regard to resource requirements (energy, runtime, memory, etc.). For this purpose, optimized and specialized systems and methods are sought [1], which can also be used under real-time requirements with low latencies.

A method for calculating frequency spectra or convolutions that is particularly important for digital signal processing, e.g.

In addition, the development of the Internet of Things (loT) leads to the collection of large amounts of data. In order to be able to control this volume of data, it is essential to shift the calculations required for data processing close to the action (edge computing). Machine learning models and methods are often used to extract knowledge from the collected data. The convolutional neural networks (CNNs), which can use the Fourier transformation, form a model type that is particularly important for the processing of image or audio data, for example. The inference and the training of CNNs are characterized by a high computational effort due to the large number of convolution operations required. The use of CNNs in edge systems with limited resources therefore requires software and hardware architectures that are specialized and optimized in terms of resource requirements (energy, runtime, memory, etc.).

$$y\left[k\right]={\displaystyle \sum _{j=0}^{N-1}{e}^{-i2\pi \frac{jk}{N}}}\cdot x\left[j\right]={\displaystyle \sum _{j=0}^{N-1}\text{cos}\left(2\pi \frac{jk}{N}\right)}\cdot x\left[j\right]-i{\displaystyle \sum _{j=0}^{N-1}\text{sin}\left(2\pi \frac{jk}{N}\right)}\cdot x\left[j\right]$$

As already mentioned, the basis for transforming time-discrete, finite signals into the frequency domain is the discrete Fourier transform (DFT) [2]: $$\overrightarrow{y}=W\cdot \overrightarrow{x}=W_{\mathrm{right}}\cdot \overrightarrow{x}-i{W}_i\cdot \overrightarrow{x}$$

$$y\left[k\right]={\displaystyle \sum _{j=0}^{N-1}{e}^{-\mathrm{<figure-callout\; id="2"\; label="i"\; filenames="DE102021212454A1\_0038.png,DE102021212454A1\_0039.png"\; state="\{\{state\}\}">i</figure-callout>}2\pi \frac{jk}{N}}}\cdot x\left[j\right]={\displaystyle \sum _{j=0}^{N-1}\text{cos}\left(2\pi \frac{jk}{N}\right)}\cdot x\left[j\right]-i{\displaystyle \sum _{j=0}^{N-1}\text{sin}\left(2\pi \frac{jk}{N}\right)}\cdot x\left[j\right]$$

in Matrix-Vektor-Schreibweise. Für eine Komponente y[k] im Frequenzbereich erfolgt die Berechnung nach Gleichung (1b) über die komponentenweise Multiplikation mit der entsprechenden Zeile der DFT-Matrix W und Summation der Produkte. Die Vektoren $\overrightarrow{\text{x}}$

und $\overrightarrow{\text{y}}$

können dabei reell- oder komplexwertig sein. Die DFT-Matrix W besitzt einen Realteil W_r und einen Imaginärteil W_i und lässt sich wie folgt schreiben: $$\begin{array}{l}W=\left({\left(e^{-i2\pi \frac{jk}{N}}\right)}_{k,j}\right)=W_r-i{W}_i=\left({\left(w_r\right)}_{k,j}\right)-i\left({\left(w_i\right)}_{k,j}\right)\\ =\left({\left(\text{cos}\left(2\pi \frac{jk}{N}\right)\right)}_{k,j}\right)-i\left({\left(\text{sin}\left(2\pi \frac{jk}{N}\right)\right)}_{k,j}\right)\end{array}$$

Equation (1a) describes the transformation into the frequency domain for a signal vector $\overrightarrow{\text{x}}$

in matrix vector notation. For a component y[k] in the frequency domain, the calculation is carried out according to equation (1b) via component-wise multiplication with the corresponding row of the DFT matrix W and summation of the products. The Vectors $\overrightarrow{\text{x}}$

and $\overrightarrow{\text{y}}$

can be real or complex. The DFT matrix W has a real part W _r and an imaginary part W _i and can be written as follows: $$\begin{array}{l}W=\left({\left(e^{-\mathrm{<figure-callout\; id="2"\; label="i"\; filenames="DE102021212454A1\_0038.png,DE102021212454A1\_0039.png"\; state="\{\{state\}\}">i</figure-callout>}2\pi \frac{jk}{N}}\right)}_{k,j}\right)=W_{\mathrm{right}}-i{W}_i=\left({\left(w_{\mathrm{right}}\right)}_{k,j}\right)-i\left({\left(w_i\right)}_{k,j}\right)\\ =\left({\left(\text{cos}\left(2\pi \frac{jk}{N}\right)\right)}_{k,j}\right)-i\left({\left(\text{sin}\left(2\pi \frac{jk}{N}\right)\right)}_{k,j}\right)\end{array}$$

Da die Invertierung der DFT-Matrix äquivalent zur konjugiert komplexen Darstellung ihrer Komponenten ist, kann die Berechnung der iDFT analog zur Berechnung der DFT erfolgen.The reversal of the DFT, i.e. the transformation of discrete frequency spectra into time-discrete signals, is called inverse DFT (iDFT). It is done by multiplying the inverted DFT matrix W ^-1 by a vector in the frequency domain and scalar multiplication by a constant factor $\frac{1}{\text{N}}.$

Since the inversion of the DFT matrix is equivalent to the complex conjugate representation of its components, the iDFT can be calculated analogously to the calculation of the DFT.

The basis for the FFT or the inverse FFT (iFFT) is the algorithm according to Cooley-Tukey [3] [4] [5]. The method allows a DFT or iDFT to be broken down into smaller DFT calculation blocks and so-called butterfly units according to the divide-and-conquer principle. This already reduces the number of arithmetic operations required. By using the method recursively, the DFT can be represented exclusively with the help of the butterfly units. The butterfly units can have different numbers of input values. An FFT made up of butterfly units with n inputs is called a radix-n FFT. FFT variants with different butterfly units (split radix and mixed radix FFT) are also known. Depending on the arrangement of the input values when dividing the DFT into butterfly units, a distinction is also made between Decimation-in-Time (DIT) and Decimation-in-Frequency (DFT) FFT.

der sich wie folgt schreiben lässt: $$W_N^k=e^{-\left(i\frac{2\pi k}{N}\right)}=\text{cos}\left(\frac{2\pi k}{N}\right)-i\text{ sin}\left(\frac{2\pi k}{N}\right)=w_{r,N}^k-i{w}_{i,N}^k$$

A DIT or DIF Radix-2 butterfly unit are, for example, in 10a and 10b shown schematically. A DIT or DIF radix-2 butterfly unit consists of a complex multiplication and two complex additions/subtractions (four real multiplications and six real additions/subtractions). Analogously, butterfly units with more than two input values can also be described. An essential operation is multiplication by a twiddle factor. ${\text{W}}_{\text{N}}^{\text{k}},$

which can be written as follows: $$W_N^k=e^{-\left(\mathrm{<figure-callout\; id="2"\; label="i"\; filenames="DE102021212454A1\_0038.png,DE102021212454A1\_0039.png"\; state="\{\{state\}\}">i</figure-callout>}\frac{2\pi k}{N}\right)}=\text{cos}\left(\frac{2\pi k}{N}\right)-i\text{sin}\left(\frac{2\pi k}{N}\right)=w_{\mathrm{right},N}^k-i{w}_{i,N}^k$$

x und a sind die komplexen Ein- bzw. Ausgaben der Multiplikation.The following formula describes the calculations to be performed when multiplying by a rotation factor within a DIT/DIF radix-n butterfly unit: $$\begin{array}{c}a=W_N^k\cdot x=\left(w_{\mathrm{right},N}^k-i{w}_{i,N}^k\right)\cdot \left(x_{\mathrm{right}}+i{x}_i\right)\\ =\left(w_{\mathrm{right},N}^k\cdot x_{\mathrm{right}}+w_{i,N}^k\cdot x_i\right)+i\left(w_{\mathrm{right},N}^k\cdot x_i-w_{i,N}^k\cdot x_{\mathrm{right}}\right)\end{array}$$

x and a are the complex inputs and outputs of multiplication, respectively.

Previous approaches to increasing the energy efficiency and performance of the (i)DFT or (i)FFT are based on approximate calculation methods using the quantization of the rotation factors or input variables, as well as on methods for the multiplication-free representation of the calculations. Various works investigate the influence of quantization widths and types (uniform and non-uniform quantization) on the resulting accuracy of the FFT and the algorithmic derivation of optimal quantization widths for the respective application requirements [6] [7] [8]. Furthermore, it was researched how multiplication-free calculations of the FFT can be carried out. The resource-intensive multiplications are usually replaced by shift operations and additions or subtractions by breaking down the rotation factors using the sum-of-powers-of-two or canonical signed digit representation [9] [10] or so-called lifting -Structures [11] are used. Furthermore, multiplications can be replaced using distributed arithmetic [12].

U.S. 7,428,564 B2 describes an FFT processor with an address generator for resorting the rotation factors, so that certain butterfly units can be performed without multiplication. WO 0 055 757 A1 describes a fast multiplication-free discrete cosine transform in which multiplications are replaced by additions/subtractions and shift operations. U.S. 8,239,442 describes a hardware accelerator that can be used as an FFT butterfly unit or FIR filter unit. US5917737 describes a DFT using a binary kernel function and a static implementation of the DFT as a circuit for a fixed number of input values.

Previous approaches to accelerating convolution-based neural networks mainly relate to resource-optimized inference. This includes methods for quantization of weights and inputs of the networks [13], [14], [15], methods for eliminating weights that do not significantly contribute to the functionality of the network (pruning) [16], [17], [18 ] and the automated search for network architectures that are adapted to the underlying hardware [19], [20], [21]. There are also hardware architectures, especially for the inference of quantized CNNs, which have been implemented as application-specific integrated circuits (ASIC) [22] or on field programmable gate arrays (FPGAs) [23].

To accelerate the training of convolution-based neural networks, training data are pre-filtered in terms of their importance in order to directly save calculation steps that do not contribute to the functionality of the network [24]. A disadvantage of this method lies in the complete dependence of the possible degree of optimization on the input data. An actually possible optimization is therefore not known in advance.

The convolution theorem is used in existing work to accelerate the training and inference of convolution-based neural networks [25], [26], [27]. The convolution between an input and the convolution core in the time domain can thus be replaced by a point-wise multiplication in the frequency domain. The number of operations required can thus be reduced by repeated use of the Fast Fourier Transform (FFT) and its inverse.

U.S. 10,902,318 B2 describes a method for optimizing the number of memory operations required when using the FFT or the Winograd transform to calculate the convolutions in CNNs. U.S. 9,904,874 B2 describes a hardware system for processing camera images using CNNs. CNN execution is accelerated by using a dedicated time-to-frequency domain converter.

An object of the present invention is to provide an improved method, an improved circuit and an improved computer program product with which resource requirements for inference and training of convolution-based neural networks, in particular of 1D and 2D CNNs, are reduced to enable their efficient use (inference and training) on embedded, resource-constrained systems, while reducing a computational complexity of the convolutional layers in the convolutional-based neural networks.

This object is solved by the subject matter of the independent patent claims.

The core idea of the present invention is to reduce the resource requirements of the inference and the training of convolution-based neural networks using an approximated FFT and its inverse based on binary and/or ternary quantized butterfly units, in particular based on a quantization with bit widths of less than or equal to 8 bits. By reducing the calculation complexity of the FFT with the help of the approximation, the calculation complexity of the convolution layers in the convolution-based neural networks is reduced at the same time.

The proposed method is aimed at accelerating the training and inference of 1D and 2D CNNs by reducing the number of operations needed for the convolutional layers. The basis of the invention is the representability of all calculations of the convolution layers in CNNs for the forward and backward pass as convolution (1D or 2D) and the associated applicability of the convolution theorem.

According to the proposal, the method for training and/or executing a convolution-based neural network (convolutional neural network, CNN) using an approximate fast Fourier transform (AFFT) includes providing at least two input signals and performing a convolution, in particular on the basis of the at least two input signals . As such, the convolution comprises approximating a Fourier transform for each of the at least two input signals to obtain at least two approximate fast Fourier transforms (AFFT); calculating a Hadamard product of the at least two approximate Fast Fourier Transforms (AFFT) to obtain an approximate convolution result in the frequency domain; and then approximating an inverse Fourier transform to obtain an approximated inverse fast Fourier transform (iAFFT). Approximating an inverse Fourier transform corresponds to applying an inverse approximate fast Fourier transform (iAFFT) to the result of the Hadamard product to obtain an approximate inverse fast Fourier transform (iAFFT). Applying the inverse approximate FFT involves previously calculating the inverse approximate fast Fourier transform (iAFFT). After performing the convolution, the inverse (iAFFT) is output as an output signal in the form of an approximate convolution result in the time domain. To approximate the Fourier transform, the method comprises, for each of the at least two input signals, decomposing a Fourier transform of a signal into a number of butterfly units with at least two input values; and approximating the butterfly units by quantization of actual rotation factors associated with the butterfly units to obtain approximate rotation factors. Each of the rotation factors includes a real part and an imaginary part, such as shown in Equation (3). puts. In the present case, the butterfly units and thus the rotation factors are approximated, ie approximated.

According to a further aspect of the present invention, a circuit for performing convolutions in the context of training and/or executing a convolution-based neural network (Convolutional Neural Network, CNN) by means of an approximate fast Fourier transform (AFFT) is proposed, which is based on an FPGA , In particular as an ASIC or as part of a system-on-chip (SoC), is implemented. The circuit is designed to perform a method for training and/or executing a convolutional neural network (CNN) using an approximate fast Fourier transform (AFFT).

The FFT or its inverse required for the convolution of discrete-time signals in the frequency domain are approximated as proposed, i.e. the result of the convolution also represents an approximation binary or ternary quantization of the rotation factors (bit width 1 or 2), and subsequent calculation with a correction factor.

The solution of the butterfly unit approximated, in particular in a binary or ternary manner, as described herein relates to the transformation of discrete time-domain signals into the frequency domain with the aid of the discrete Fourier transformation. The number of arithmetic operations and memory accesses can thus be reduced in the approximated FFT (AFFT). In particular, the number of energy-intensive multiplications can be significantly reduced up to the point where the FFT can be executed without multiplication.

In addition, a computer program product is proposed which includes instructions which, when executed by a computer, cause the latter to execute the proposed method, in particular with the proposed circuit.

• 1 ein detailliertes Ablaufdiagramm zur Berechnung der Parameter der approximierten Schmetterlingseinheiten;
• 2 eine schematische Darstellung von binär quantisierten Drehfaktoren;
• 3 eine schematische Darstellung von ternär quantisierten Drehfaktoren;
• 4 eine mittlere quadratische Abweichung zwischen den Drehfaktoren und den zugehörigen ternär quantisierten approximierten Drehfaktoren für verschiedene Schwellenwerte;
• 5 eine mittlere quadratische Abweichung zwischen den Drehfaktoren und den zugehörigen ternär quantisierten approximierten Drehfaktoren für verschiedene Schwellenwerte;
• 6 eine in einer Schaltung einsetzbaren Hardwarearchitektur zur multiplikationslosen Berechnung einer binär approximierten Schmetterlingseinheit mit Korrekturfaktor;
• 7 eine in einer Schaltung einsetzbaren Hardwarearchitektur zur multiplikationslosen Berechnung einer ternär approximierten Schmetterlingseinheit mit Korrekturfaktor;
• 8 eine in einer Schaltung einsetzbaren Hardwarearchitektur zur multiplikationslosen Berechnung einer binär approximierten Schmetterlingseinheit;
• 9 eine in einer Schaltung einsetzbaren Hardwarearchitektur zur multiplikationslosen Berechnung einer ternär approximierten Schmetterlingseinheit;
• 10a schematische Darstellung einer DIT-Radix-2-Schmetterlingseinheit;
• 10b schematische Darstellung einer DIF-Radix-2-Schmetterlingseinheit;
• 11 schematischer Ablauf einer approximierten Faltung mittels AFFT zwischen zwei 1 D-Eingaben;
• 12 schematischer Ablauf einer approximierten Faltung mittels 2D-AFFT zwischen zwei 2D-Eingaben; und
• 13 schematischer Ablauf der 2D-AFFT.

Advantageous refinements of the present invention are the subject matter of the dependent patent claims. Preferred embodiments of the present invention are explained in detail below with reference to the accompanying drawings. Show it:

• 1 a detailed flowchart for calculating the parameters of the approximated butterfly units;
• 2 a schematic representation of binary quantized rotation factors;
• 3 a schematic representation of ternary quantized rotation factors;
• 4 a mean square deviation between the rotation factors and the associated ternary quantized approximate rotation factors for different threshold values;
• 5 a mean square deviation between the rotation factors and the associated ternary quantized approximate rotation factors for different threshold values;
• 6 a hardware architecture that can be used in a circuit for the multiplication-free calculation of a binary approximated butterfly unit with a correction factor;
• 7 a hardware architecture that can be used in a circuit for the multiplication-free calculation of a ternary approximated butterfly unit with a correction factor;
• 8th a hardware architecture that can be used in a circuit for the multiplication-free calculation of a binary approximated butterfly unit;
• 9 a hardware architecture that can be used in a circuit for the multiplication-free calculation of a ternary approximated butterfly unit;
• 10a schematic representation of a DIT radix-2 butterfly unit;
• 10b schematic representation of a DIF radix-2 butterfly unit;
• 11 Schematic sequence of an approximated convolution using AFFT between two 1D inputs;
• 12 schematic sequence of an approximated convolution using 2D-AFFT between two 2D inputs; and
• 13 schematic sequence of the 2D AFFT.

Individual aspects of the invention described herein are described below in the 1 until 13 described. In synopsis of 1 until 9 and 11 until 13 the principle of the present invention is illustrated while 10a and 10b Fig. 5 shows a schematic representation of known butterfly units 500. In the present application, the same reference numbers relate to the same elements or elements with the same effect, with not all reference numbers being presented again in all drawings, insofar as they are repeated.

All definitions of terms provided in this application can be applied both to the methods described and to the circuits or computer program products described. The explanations of terms are not constantly repeated in order to avoid redundancies as far as possible.

In the present case, the terms input signal are used synonymously with input value or input or input data. The terms quantization value and threshold value are also used synonymously with one another. In the methods described, it is initially important that a value/signal is made available for further calculation. What physical meaning this/-it value/signal can have is revealed to a person skilled in the art from the context in which the described methods are used or emerges in detail from the further description in the context.

On the one hand, the present technical teaching comprises a method for calculating the parameters required for the optimal approximation of the FFT, which is explained in more detail in the flowchart 1 is shown. On the other hand, the present technical teaching comprises a hardware architecture for butterfly units, which is schematically shown in FIGS 6 until 9 is shown and can be implemented using a hardware description language on Field Programmable Gate Arrays (FPGAs), as an application-specific integrated circuit (ASIC) or as part of a system-on-chips (SoCs). In the 6 until 9 The hardware structures illustrated are thus a pictorial representation of a circuit proposed herein. Furthermore, on the basis of the method for the approximate calculation of butterfly units of a Fourier transformation of a signal, an improved method for training and/or executing a convolution-based neural network (convolutional neural network, CNN) using an approximate fast Fourier transformation (AFFT) can be provided, which schematically in the 11 and 12 is sketched.

The method described for the approximate calculation of butterfly units of a Fourier transformation of a signal comprises representing a number of butterfly units of a Fourier transformation and then approximating the number of butterfly units by means of quantization of, in particular actual, rotation factors associated with the butterfly units in order to approximate rotation factors obtained, wherein a bit width of a quantized, approximated rotation factor is less than or equal to 8 bits. As can be seen from Equation (3), a real rotation factor includes a real part and an imaginary part.

The present invention is explained below on the binary and ternary quantization of the butterfly units. However, the quantization described herein is also applicable to others, such as quaternary or quintary etc. quantization.

mittels binärer oder ternärer Quantisierung. Ferner kann ein Korrekturfaktor die Approximation der Drehfaktoren weiter verbessern.The basis of the binary or ternary approximated butterfly unit is the approximation of the rotation factors ${\text{W}}_{\text{N}}^{\text{k}}$

using binary or ternary quantization. Furthermore, a correction factor can further improve the approximation of the rotation factors.

In the flow chart after 1 At a start 110, input data 120 are first used, which can include N values, where N is a natural number and specifies a number of input data. For example, N can be a number of acquired data (samples) of an input signal. The following applies: N = number of input samples. The input values/signals 120 define the underlying Discrete Fourier Transform (DFT). The input values 120 are, in particular, detected signals. The DFT is represented in a butterfly graph or graph structure 140 in a butterfly decomposition 130 . The graph structure 140, which comprises a number of butterfly units 500 (see 10a , 10b ) can be displayed visually for a user, for example. Here, for example, a form of representation of the butterfly units 500, as in the 10a and 10b shown, are used. In other words, a number of butterfly units of a Fourier transform are first represented. The representation 130 is initially as a decomposition 130 of a matrix of the overall system into butterflies units (sub-matrices) so that further arithmetic operations can be carried out. Furthermore, the representation 130 can be understood as making it visually visible to a user, for example in the form of a graph structure 140. The butterfly units include rotation factors 150, which are to be approximated. For this purpose, the rotation factors are quantized, ie divided into sub-areas. Each rotation factor 150 corresponds to a butterfly unit.

An approximation 160 is first discussed below using the examples of a binary quantization and a ternary quantization (quantization type 190). The method described here preferably takes place with a binary or ternary quantization. However, other quantizations/quantization types 190 are also possible.

In binary quantization, an interval [r _min , r _max ] is divided into two sub-areas and a data point d _i ∈ [r _min , r _max ] is coded or assigned according to its affiliation with one of the sub-areas, so that (d _i ) _B ∈ {-1, 1}.

In ternary quantization, an interval [r _min , r _max ] is divided into three sub-areas and a data point d _j ∈ [r _min , r _max ] is coded or assigned according to its affiliation with one of the sub-areas, so that (d _j ) _T ∈ {-1, 0, 1}.

In the method described, a data point is thus generally encoded according to its association with one of the P=2 ^(B-1) +1 partial areas. Here, B is a natural number less than or equal to 8 and indicates the bit width.

One bit for binary quantization and two bits for ternary quantization are required to represent the two or three possible output values of the quantization. Binary and ternary quantization differ in the resulting accuracy, ie the deviation from the data point d _i . For example, the data point d _i is an input of the quantization. The quantization input includes a real part and an imaginary part of the rotation factor to be quantized. The selection of the quantization type 190, i.e. whether binary or ternary, after the in 1 The method presented can be done by the user or by an estimation, which can be carried out by an algorithm. In the case of an estimation using an algorithm, there is no direct decision by the user. To start a calculation of the estimate, the user inputs a sample signal and a required accuracy estimate into a program running the algorithm. The program can then automatically estimate, in particular derive, which type of quantization makes sense. The user can also decide on this or the estimation can be used to determine whether a multiplication-free approximation 170 should be carried out, in which a correction factor α=1 applies to all rotation factors, or whether an approximation 180 should be carried out with a reduced number of necessary multiplications, in which an optimal value for the correction factor α=α _opt is to be determined for all rotation factors. Setting α=α _opt in step 180 of 1 means that α _opt is used as a parameter in the calculation, which is to be determined as part of a minimization problem.

beschreiben: $$q_B\left(w\right)={\left(w\right)}_B=\{\begin{array}{rr}\hfill -\mathrm{1,}& \hfill w<0\\ \hfill \mathrm{1,}& \hfill w\ge 0\end{array}$$

$$q_T\left(w,t\right)={\left(w\right)}_T=\{\begin{array}{cc}-\mathrm{1,}& w<-t\\ \mathrm{0,}& \left|w\right|\le t\\ \mathrm{1,}& w>t\end{array}$$

The quantization of the rotation factors 150 is applied to the real and imaginary parts, which both lie in the interval [-1, 1] due to trigonometric relationships. The quantization functions can generally be $\text{w}\in \left\{{\text{w}}_{\text{right},\text{N}}^{\text{k}},{\text{w}}_{\text{i},\text{N}}^{\text{k}}\right\}$

describe: $$q_B\left(w\right)={\left(w\right)}_B=\{\begin{array}{rr}\hfill -\mathrm{1,}& \hfill w<0\\ \hfill \mathrm{1,}& \hfill w\ge 0\end{array}$$

$$q_T\left(w,t\right)={\left(w\right)}_T=\{\begin{array}{cc}-\mathrm{1,}& w<-\mathrm{<figure-callout\; id="0"\; label="t"\; filenames="DE102021212454A1\_0031.png,DE102021212454A1\_0032.png"\; state="\{\{state\}\}">t</figure-callout>}\\ \mathrm{0,}& \left|w\right|\le \mathrm{<figure-callout\; id="1"\; label="t"\; filenames="DE102021212454A1\_0031.png,DE102021212454A1\_0036.png"\; state="\{\{state\}\}">t</figure-callout>}\\ \mathrm{1,}& w>t\end{array}$$

welche dem halboffenen Intervall ] t, 1] der Quantisierungsfunktion q_T(w) zuzuordnen sind. In dem zweiten Teilbereich 302 liegen die Werte der Drehfaktoren 150, welche dem halboffenen Intervall ] -t, -1] der Quantisierungsfunktion q_T(w) zuzuordnen sind. In dem dritten Teilbereich 303 liegen die Werte der Drehfaktoren 150, welche dem geschlossenen Intervall [-t, t] der Quantisierungsfunktion q_T(w) zuzuordnen sind. In_2 sind die zwei Teilbereiche 201 und 202 wie folgt zuzuordnen. In dem ersten Teilbereich 202 liegen die Werte der Drehfaktoren $w_{r\text{/}i,N,}^k$

welche dem geschlossenen Intervall [0 , 1] der Quantisierungsfunktion q_B(w) zuzuordnen sind. In dem zweiten Teilbereich 201 liegen die Werte der Drehfaktoren 150, welche dem halboffenen Intervall ] 0, -1] der Quantisierungsfunktion q_B(w) zuzuordnen sind Die 2 und 3 zeigen somit die binäre bzw. ternär quantisierten Drehfaktoren, welche durch Gleichung (3) beschrieben sind.Equation (5a) describes the binary quantization, which is used in 2 is shown schematically. Equation (5b) describes the ternary quantization, which is used in 3 is shown schematically. In the 2 and 3 the binary or ternary quantization of the imaginary part 215 and the real part 225 of the rotation factors 150 is shown in the interval [−1, 1] in relation to a wave vector k. In ternary quantization, the parameter t ∈ [0, 1] describes a threshold value that divides the interval [-1, 1] into the three sub-ranges 301, 302 and 303 by using it in the positive and negative range. In 3 the threshold is shown as dashed lines 300 in the positive (t) and negative (-t) regions. The dashed lines 300 run parallel to the k-axis. The values of the rotation factors are in the first sub-area 301 $w_{\mathrm{right}\text{/}i,N}^k,$

which are to be assigned to the half-open interval ] t, 1] of the quantization function q _T (w). The values of the rotation factors 150, which are to be assigned to the half-open interval ]−t,−1] of the quantization function q _T (w), lie in the second sub-area 302 . The values of the rotation factors 150, which are to be assigned to the closed interval [-t, t] of the quantization function q _T (w), lie in the third sub-area 303 . In_ 2 the two partial areas 201 and 202 are to be assigned as follows. The values of the rotation factors lie in the first partial area 202 $w_{\mathrm{right}\text{/}i,N,}^k$

which are to be assigned to the closed interval [0, 1] of the quantization function q _B (w). The values of the rotation factors 150, which are to be assigned to the half-open interval ] 0, -1] of the quantization function q _B (w) Die, are in the second sub-area 201 2 and 3 thus show the binary or ternary quantized rotation factors, which are described by equation (3).

In the method described, the quantization by means of N bits leads to a quantization of the rotation factors in P=2 ^(B-1) +1 partial areas, where B is a natural number less than or equal to 8 and B indicates the bit width. In the case of binary quantization, in which the bit length is one bit, ie B=1, the quantization thus leads to 2 ^(1-1) +1=2 ⁰ +1=2 partial areas. With ternary quantization, in which the bit length is two bits, ie B=2, the quantization thus leads to 2 ^(2-1) +1=2 ¹ +1=3 partial areas. The value 0 (see equation (5b) or (6b)) is possible with ternary quantization. The so-called mid-tread quantization is used here.

$${\left(w\right)}_T\cdot x=\{\begin{array}{ll}-x,\hfill & {\left(w\right)}_T=-1\hfill \\ \mathrm{0,}\hfill & {\left(w\right)}_T=0\hfill \\ x,\hfill & {\left(w\right)}_T=1\hfill \end{array}$$

With the help of binary or ternary quantization, a multiplication with the rotation factors can be replaced by a conditional decision: $${\left(w\right)}_B\cdot x=\{\begin{array}{cc}-x,& {\left(w\right)}_B=-1\\ x,& {\left(w\right)}_B=1\end{array}$$

$${\left(w\right)}_T\cdot x=\{\begin{array}{ll}-x,\hfill & {\left(w\right)}_T=-1\hfill \\ \mathrm{0,}\hfill & {\left(w\right)}_T=0\hfill \\ x,\hfill & {\left(w\right)}_T=1\hfill \end{array}$$

By replacing the multiplication with a conditional decision, the approximation 170 can be made multiplication-free (see 1 ) or at least with a reduced number of multiplications 180. Equations (5a) and (5b) each give quantized rotation factors 192 (see 1 ) of binary or ternary quantization.

In the method described, a multiplication with the rotation factors is preferably replaced by a conditional decision in the case of a quantization in P partial areas. As a result, the resource requirements of the method described can be reduced. In the method, quantization is applied to a real part and an imaginary part of the real rotation factors.

In order to minimize the error between the approximated and actual rotation factors, a correction factor α can also be used. The method described preferably includes, in particular in the case of a binary or ternary quantization, minimizing an error between the approximated rotation factors and the actual rotation factors by using a correction factor α. Depending on the selection of the correction factor α, this can lead to an approximation 170 without multiplication or to an approximation 180 with a reduced number of necessary multiplications. Here “choice of correction factor” refers to whether α=1 is set for all rotation factors, as in 170 der 1 given, or whether α=α _opt is to be determined for all rotation factors, as in 180 der 1 specified.

If α=1 is set for all rotation factors according to step 170 and the quantization type 190 is selected as binary, the binary quantization q _B (w) is applied 189 to all rotation factors. Here, as the quantized rotation factors (w) _B are determined in step 192, ie the approximated rotation factors. After the approximate rotation factors have been determined, the method for the approximate calculation of butterfly units of a Fourier transformation of a signal is ended 194. The approximate rotation factors can then be used for further use, for example in a subsequent method.

If α=1 is set for all rotation factors according to step 170 and the quantization type 190 is selected as ternary, an optimal threshold value t is first calculated according to step 185. The threshold value t divides the value range of the quantization functions in ternary quantization into three sub-ranges. Then, using the calculated threshold value t 191 , the ternary quantization q _T (w) is applied 193 to all rotation factors. Here, the quantized rotation factors (w) _T are determined in step 192, ie the approximated rotation factors. After the approximate rotation factors have been determined, the method for the approximate calculation of butterfly units of a Fourier transformation of a signal is ended 194. The approximate rotation factors can then be used for further use, for example in a subsequent method.

If α=a _opt is to be determined for all rotation factors according to step 180 and the quantization type 190 is selected as binary, an optimal correction factor a _opt for all rotation factors is first calculated in step 187 . After the correction factor 188 has been calculated, the binary quantization q _B (w) is applied 189 to all rotation factors. Here, as the quantized rotation factors (w) _B are determined in step 192 using the optimal correction factor α _opt , ie the approximated rotation factors are determined. After the approximate rotation factors have been determined, the method for the approximate calculation of butterfly units of a Fourier transformation of a signal is ended 194. The approximate rotation factors can then be used for further use, for example in a subsequent method.

If α=α _opt is to be determined for all rotation factors according to step 180 and the quantization type 190 is selected as ternary, an optimal threshold value t and an optimal correction factor a _opt for all rotation factors are first calculated in step 186 . After the correction factor 188 and the threshold value 191 have been calculated, the ternary quantization q _T (w) is applied 193 to all rotation factors. Here, the quantized rotation factors (w) _T are determined in step 192 using the optimal correction factor α _opt and using the optimal threshold value t, ie the approximated rotation factors are determined. After the approximate rotation factors have been determined, the method for the approximate calculation of butterfly units of a Fourier transformation of a signal is ended 194. The approximate rotation factors can then be used for further use, for example in a subsequent method.

The individual approximation steps are explained in detail below. The approximation of the quantized rotation factors can consequently be described in general as: $$W_N^k=w_{\mathrm{right},N}^k-i{w}_{i,N}^k\approx a\left({\left(w_{\mathrm{right},N}^k\right)}_{B\text{/}T}-i{\left(w_{i,N}^k\right)}_{B\text{/}T}\right)=a{\left(W_N^k\right)}_{B\text{/}T}$$

und der Approximation $\mathrm{\alpha }{\left({\text{W}}_{\text{N}}^{\text{k}}\right)}_{\text{B/T}}$

minimiert wird. Dies kann durch folgendes Optimierungsproblem beschrieben werden: $$\begin{array}{l}\underset{\mathrm{\alpha }}{\text{min}}\left|{\text{W}}_{\text{N}}^{\text{k}}-\mathrm{\alpha }{\left({\text{W}}_{\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right|=\underset{\mathrm{\alpha }}{\text{min}}\left|{\text{W}}_{\text{N}}^{\text{k}}-\mathrm{\alpha }{\left({\text{W}}_{\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right|\\ =\underset{\mathrm{\alpha }}{\text{min}}\left|\left({\text{w}}_{\text{r},\text{N}}^{\text{k}}-\mathrm{\alpha }{\left({\text{w}}_{\text{r},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)-\text{i}\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}-\mathrm{\alpha }{\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)\right|\\ =\underset{\mathrm{\alpha }}{\text{min}}\sqrt{{\left({\text{w}}_{\text{r},\text{N}}^{\text{k}}-\mathrm{\alpha }{\left({\text{w}}_{\text{r},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)}^2+{\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}-\mathrm{\alpha }{\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)}^2}\end{array}$$

The correction factor α can be determined in such a way that the approximation of the rotation factors according to equation (7) becomes optimal. This means that the error between the, particularly actual, rotation factor ${\text{W}}_{\text{N}}^{\text{k}}$

and the approximation $\mathrm{a}{\left({\text{W}}_{\text{N}}^{\text{k}}\right)}_{\text{B/T}}$

is minimized. This can be described by the following optimization problem: $$\begin{array}{l}\underset{\mathrm{a}}{\text{at least}}\left|{\text{W}}_{\text{N}}^{\text{k}}-\mathrm{a}{\left({\text{W}}_{\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right|=\underset{\mathrm{a}}{\text{at least}}\left|{\text{W}}_{\text{N}}^{\text{k}}-\mathrm{a}{\left({\text{W}}_{\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right|\\ =\underset{\mathrm{a}}{\text{at least}}\left|\left({\text{w}}_{\text{right},\text{N}}^{\text{k}}-\mathrm{a}{\left({\text{w}}_{\text{right},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)-\text{i}\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}-\mathrm{a}{\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)\right|\\ =\underset{\mathrm{a}}{\text{at least}}\sqrt{{\left({\text{w}}_{\text{right},\text{N}}^{\text{k}}-\mathrm{a}{\left({\text{w}}_{\text{right},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)}^2+{\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}-\mathrm{a}{\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)}^2}\end{array}$$

If, to solve the optimization problem, the derivation of the expression to be minimized is formed according to equation (8) and set equal to 0, then after equivalent transformation for α we get: $$a=\frac{{\text{w}}_{\text{right},\text{N}}^{\text{k}}\cdot {\left({\text{w}}_{\text{right},\text{N}}^{\text{k}}\right)}_{B\text{/}T}+{\text{w}}_{\text{i},\text{N}}^{\text{k}}\cdot {\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}\right)}_{B\text{/}T}}{{\left({\left({\text{w}}_{\text{right},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)}^2+{\left({\left({\text{w}}_{\text{i},\text{N}}^{\text{k}}\right)}_{B\text{/}T}\right)}^2}=a_{Opt}$$

In the case of ternary quantization, the threshold value t can also be chosen for any correction factor α, so that the approximation becomes optimal, ie the error between an actual Rotation factor and the associated approximate rotation factor becomes minimal. To do this, the mean square deviation between all rotation factors and their approximations must be minimized: $$\underset{t}{\text{at least}}\frac{1}{N}{\displaystyle \sum _{k=0}^{N-1}{\left|{\text{W}}_{\text{N}}^{\text{k}}-a\cdot q_T\left({\text{W}}_{\text{N}}^{\text{k}},t\right)\right|}^2}$$

Since the quantization function q _T (w,t) is only partially differentiable, the problem cannot be solved analytically. Numerical or graphical methods can be used to solve the problem. The 4 and 5 show an example of the term to be optimized according to equation (10) (mean square deviation between actual and approximate rotation factor) for N = 1024 and α = 1 ( 4 ) as well as N = 1024 and α = α _opt ( 5 ). The resulting mean square deviation 400 between the actual and approximate rotation factor is in each case plotted against the threshold value t. The minimum of the function, which describes the mean square deviation between the actual and the approximate rotation factor, and thus the optimal threshold values are at t = 0.5 for α = 1 ( 4 ) and at t = 0.38 for α = α _opt ( 5 ).

The method described therefore preferably comprises the steps of forming a derivation of the error to be minimized; and performing at least one equivalent transformation to obtain an expression for the correction factor α, in particular for an optimal correction factor α _opt . The method described also preferably includes, in particular in the case of ternary quantization, a selection of the threshold value t for an arbitrary correction factor α.

A threshold value or quantization values for approximating the rotation factors are preferably chosen in such a way that the approximated rotation factors can be written as a power of two or as a sum of powers of two.

Each butterfly unit of the number of butterfly units also has a different number of input values or an equal number of input values. Only the dimension of the input values must correspond to each other.

The method for the approximate calculation of butterfly units of a Fourier transformation of a signal is preferably carried out on the basis of the fast Fourier transformation FFT. The method can be used for 1D FFT or 2D FFT.

The multiplication with the rotation factors 150 within the radix-n-butterfly units according to equation (4) can be approximated with the correction factor α as follows: $$\begin{array}{l}a\approx a*={\left(W_N^k\right)}_{B\text{/}T}\cdot x=a\left({\left(w_{\mathrm{right},N}^k\right)}_{B\text{/}T}+i{\left(w_{i,N}^k\right)}_{B\text{/}T}\right)\cdot \left(x_{\mathrm{right}}+i{x}_i\right)\\ =a\left({\left(w_{\mathrm{right},N}^k\right)}_{B\text{/}T}\cdot x_{\mathrm{right}}-{\left(w_{i,N}^k\right)}_{B\text{/}T}\cdot x_i\right)\\ +ia\left({\left(w_{\mathrm{right},N}^k\right)}_{B\text{/}T}\cdot x_i+{\left(w_{i,N}^k\right)}_{B\text{/}T}\cdot x_{\mathrm{right}}\right)\end{array}$$

und x) auf zwei, da nur noch die Real- und Imaginärteile des Ergebnisses mit dem Korrekturfaktor α multipliziert werden müssen. Bei dem Korrekturfaktor α handelt e sich um eine a-priori bekannte Konstante. A-priori bekannte Konstante bedeutet vorliegend, dass der Korrekturfaktor α nach Anwendung des Verfahrens aber vor Anwendung in der Applikation (Hardware/ Schaltung 100) bekannt ist. Eine Multiplikation mit dem Korrekturfaktor 188, wie in den 6 und 7 gezeigt ist, kommt somit ohne Hardware-Multiplizierer aus.The number of real multiplications thus reduces from four (between the real and imaginary parts of ${\text{W}}_{\text{N}}^{\text{k}}$

and x) to two, since only the real and imaginary parts of the result have to be multiplied by the correction factor α. The correction factor α is a constant that is known a priori. In the present case, a constant known a priori means that the correction factor α is known after the method has been used but before it is used in the application (hardware/circuit 100). A multiplication by the correction factor 188, as in the 6 and 7 is shown, thus does not require a hardware multiplier.

Equation (11) can be used to derive corresponding hardware architectures for DIF/DIT radix-n butterfly units, which can be implemented using a hardware description language on FPGAs, as an ASIC or as part of system-on-chips (SoCs). 6 and 7 show an example of a template for implementing a hardware structure of a binary or ternary DIT radix-2 butterfly unit with correction factor α. The templates after 6 and 7 serve to implement the hardware structure in a circuit for the approximate calculation of butterfly units of a Fourier transformation of a signal. The circuit is preferably implemented on an FPGA, in particular as an ASIC or as part of a system on chips (SoCs).

6 and 7 show a hardware architecture that can be used in a circuit 100 for the multiplication-free calculation of a binary ( 6 ) or ternary ( 7 ) approximated butterfly unit 500 with correction factor 188, multiplexers (BMUX/TMUX) 600 being provided in circuit 100. 8th and 9 show a hardware architecture that can be used in a circuit 100 for the multiplication-free calculation of a binary ( 8th ) or ternary ( 9 ) approximated butterfly unit 500, where multiplexers (BMUX/TMUX) 600 are provided in the circuit 100. The 6 until 9 thus show the hardware architecture, which is necessary to carry out the steps 170 to 194 according to 1 to realize.

The circuit for the approximate calculation of butterfly units of a Fourier transform of a signal comprises a number of M:1 multiplexers, where M=2,...,256 is a natural number. M indicates the number of inputs of the multiplexer(s). The circuit is designed to replace a multiplication based on a quantization of, in particular actual, rotation factors associated with butterfly units without actual hardware multipliers before a signal flow by at least one multiplexer of the number of multiplexers. The multiplications with the rotation factors are replaced by an M:1, in particular a 2:1 or 3:1 multiplexer (BMUX or TMUX). The 2:1 or 3:1 multiplexers can be used in particular with binary or ternary quantization.

The real and imaginary parts can then be multiplied by the correction factor α and calculated using the second input value of the butterfly unit, as is the case, for example, in 6 and 7 is sketched. The circuit is therefore preferably designed to calculate an output signal at a multiplexer with a second input value. Furthermore, the circuit is preferably designed to calculate a real part and an imaginary part of the output signal at the multiplexer with a correction factor α before a calculation with the second input value.

The real or imaginary part of the binary or ternary quantized rotation factors can be represented by one bit in the binary case and two bits in the ternary case. The bit width and form of representation (integer, floating point = floating point number) of the input values can in principle be arbitrary. However, the blocks for addition, subtraction, sign inversion and multiplication with reduced complexity should be adapted in the case of quantization with a larger bit width according to the selected bit width and representation form (integer, floating point) of the input values.

For the case α = 1, a butterfly unit can be approximated without multiplication (see 170 in 1 ) and equation (4) can be further simplified to: $$\begin{array}{l}a\approx a**={\left(W_N^k\right)}_{B\text{/}T}\cdot x=\left({\left(w_{\mathrm{right},N}^k\right)}_{B\text{/}T}+i{\left(w_{i,N}^k\right)}_{B\text{/}T}\right)\cdot \left(x_{\mathrm{right}}+i{x}_i\right)\\ =\left({\left(w_{\mathrm{right},N}^k\right)}_{B\text{/}T}\cdot x_{\mathrm{right}}-{\left(w_{i,N}^k\right)}_{B\text{/}T}\cdot x_i\right)\\ +i\left({\left(w_{\mathrm{right},N}^k\right)}_{B\text{/}T}\cdot x_i+{\left(w_{i,N}^k\right)}_{B\text{/}T}\cdot x_{\mathrm{right}}\right)\end{array}$$

Equation (12) can be used to derive corresponding hardware architectures for DIF/DIT radix-n butterfly units. 8th and 9 show an example of a template for implementing a hardware structure of a multiplication-free binary or ternary DIT radix-2 butterfly unit.

With the method described for the approximate calculation of butterfly units of a Fourier transformation of a signal or the circuit described for the approximate calculation of butterfly units of a Fourier transformation of a signal, analogous to the hardware architecture shown in FIGS. 6, 7, 8 and 9, multiplexer based architectures for approximate butterfly units with purely real input values, more than two input values (radix-n) and DIF partitioning can be built. Also the templates 8th and 9 serve to implement the hardware structure in a circuit for the approximate calculation of butterfly units of a Fourier transformation of a signal. The circuit is preferably implemented on an FPGA, in particular as an ASIC or as part of a system on chips (SoCs).

In any case, the circuit is designed to carry out the method described for the approximate calculation of butterfly units of a Fourier transformation of a signal.

According to a further aspect, a computer program product is described which includes instructions which, when executed by a computer, cause the computer to use the method for approximate to calculate butterfly units of a Fourier transform of a signal. The computer program product is preferably implemented in a described circuit for the approximate calculation of butterfly units of a Fourier transformation of a signal.

The method described for the approximate calculation of butterfly units of a Fourier transformation of a signal can significantly reduce the number of multiplications required for an FFT or iFFT and thus the calculation complexity and resource consumption of the transformation between the time and frequency domain and the calculation speed can be increased. This is an advantage over the prior art. The described method thus enables the presented hardware architectures, which require either no or a reduced number of multiplications, but no hardware multipliers, to calculate an FFT butterfly unit. This is accompanied by an increase in energy efficiency and performance.

The quantization of the rotation factors required to calculate the FFT also leads to a reduction in memory requirements. Since the method described for the approximate calculation of butterfly units of a Fourier transformation of a signal and the associated optimization of the FFT is based on an approximate calculation, i.e. an approximation, i.e. a reduction in the accuracy of the result, another advantage of the method described is the optimal approximation of the rotation factors. This enables an optimal approximation of the result despite strong quantization of the rotation factors.

Technical areas of application of the method described and the corresponding circuit can be found in all areas of digital signal processing. In the field of condition monitoring of systems, for example, the analysis of structure-borne noise signals plays a crucial role. In many cases, time-domain signals are recorded using acceleration or acoustic emission sensors. To extract relevant information, these discrete signals are then examined using FFT-based methods in the frequency domain or time-frequency domain. Sensor signals of other sizes are also transformed into the frequency domain or time-frequency domain in order to extract relevant information, e.g. current or force.

Since the method for the approximate calculation of butterfly units of a Fourier transformation of a signal enables fast and approximate calculation of frequency spectra, relevant frequency bands can be quickly identified and extracted for compressed storage of information.

It is also conceivable to use non-optimal parameters, as described herein, for approximating the FFT in the described method. It is also conceivable to use other hardware architectures in order to carry out the approximate calculation of a butterfly unit.

Similar analysis methods are also used to process audio signals. The method described allows all FFT-based methods to be approximated. Since the 2D FFT can also be expressed using the 1D variant, the method described can also be applied to 2D input data, i.e. to the FFT-based processing of image data, for example.

In addition, the method for the approximate calculation of butterfly units of a Fourier transform of a signal by exploiting the convolution theorem, which states that convolutions in the time domain are equivalent to point-by-point multiplication in the frequency domain, can be used not only for signal analysis but also for signal manipulation. The method described can also be used in all areas of application of discrete convolution, such as control systems or in acoustics.

Convolution also forms the basis of convolutional neural networks (CNN) in the field of machine learning, which are primarily used for real-time object recognition in the fields of autonomous driving or robotics. By using the convolution theorem, a reduction in the complexity of the calculation and thus an accelerated calculation is possible. With the help of the method presented, this approach can again be significantly optimized and accelerated by reducing the computational complexity of the transformation. A further field of application of the invention is lossy data compression.

Based on the method for approximately calculating butterfly units of a Fourier transform of a signal, an improved method for training and/or executing a convolutional neural network (CNN) using an approximate Fast Fourier Transform (AFFT) execution can be provided of a convolutional neural network uses inference, ie the application of the trained network to arrive at a conclusion or prediction for a given input. The convolution calculations of the convolution-based neural network required for the inference and the training are approximated by the AFFT.

The further proposed method for training and/or executing a convolution-based neural network using an approximate fast Fourier transformation includes providing at least two input signals. The input signals can be 1D or 2D signals. For example, audio signals and/or image signals can be involved. Furthermore, the method for training and/or executing a convolution-based neural network includes performing a convolution. As such, the convolution comprises approximating a Fourier transform for each of the at least two input signals to obtain at least two approximate fast Fourier transforms (AFFT); calculating a Hadamard product of the at least two approximate Fast Fourier Transforms (AFFT) to obtain an approximate convolution result in the frequency domain; and approximating an inverse Fourier transform to obtain an approximated inverse fast Fourier transform (iAFFT). Approximating an inverse Fourier transform corresponds to applying an inverse approximate fast Fourier transform (iAFFT) to the result of the Hadamard product. After performing the convolution, the method for training and/or executing a convolution-based neural network includes outputting the inverse approximate fast Fourier transform (iAFFT) as an output signal, in particular as an approximate result of the convolution in a time domain. As suggested, the FFT necessary for the convolution of time-discrete signals in the frequency domain or their inverse are approximated. As a result, the result of the convolution also represents an approximation. The FFT is approximated as already described in connection with the method for the approximate calculation of butterfly units of a Fourier transformation of a signal, preferably via a binary or ternary quantization of the rotation factors, in particular with a bit width B of one or two. However, approximations with higher bit widths are also conceivable, as is also described in connection with the method for the approximate calculation of butterfly units of a Fourier transformation of a signal. Subsequent offsetting with the correction factor α is also preferably carried out. With the approximated FFT (AFFT), the number of arithmetic operations and memory accesses can be reduced. In particular, the number of energy-intensive multiplications can be significantly reduced up to the point where the FFT can be executed without multiplication. This advantage can then finally be transferred to the convolution, so that the method for training and/or executing a convolution-based neural network can also work in a resource-optimized manner.

The method for training and/or executing a convolution-based neural network for approximating the Fourier transform for each of the at least two input signals preferably includes a decomposition of a Fourier transform of a signal into a number of butterfly units with at least two input values and an approximation of the butterfly units by means of quantization of rotation factors associated with the butterfly units, in particular actual rotation factors, in order to obtain approximate rotation factors. In other words, to approximate the Fourier transform of each of the at least two input signals, the method for approximately calculating butterfly units of a Fourier transform of a signal is used. The statements already made regarding the method for the approximate calculation of butterfly units of a Fourier transformation of a signal therefore also apply to the method for training and/or executing a convolution-based neural network, to which reference is hereby made. Consequently, the fast Fourier transformation is preferably approximated via a quantization of rotation factors. When approximating the Fourier transform, a multiplication by rotation factors in a quantization into P bins is replaced by a conditional decision (see details above).

A dimension of the input signals is preferably arbitrary. However, the at least two input signals should be of the same dimension, particularly preferably either 1D or 2D in each case. The at least two input signals preferably have the same dimension, but can have different lengths with regard to their entries in one of the dimensions. The dimensions and thus also the length of the entries in the dimensions must be matched to one another. This can be achieved by inserting zeros (zero padding) in order to match the dimension of the at least two input signals to one another. For example, in the 1D case, it is the length of the input signal, wel are to be aligned with each other. In the 2D case, for example, a height and a width of the input signals would have to be adjusted. The terms filter kernel and convolution kernel are synonyms. It is a vector or matrix that is convolved with an input signal. A CNN ultimately applies a large number of filters in the convolutional layers to an input using the convolution. For example, convolution kernels typically have smaller dimensions than the input values, which should be matched before applying the AFFT as just described.

11 and 12 show the basic process of the approximated convolution for 1D and 2D input signals. 11 and 12 represent the convolution after matching the dimensions of the two inputs. According to 11 two 1D input values are convolved and according to 12 two 2D input values are convolved. Both 11 and 12 After the input values 200 have been provided, the common feature is the calculation of the approximate Fourier transform AFFT 210 and the subsequent calculation of a Hadamard product 220 and the calculation of the approximate inverse fast Fourier transform (iAFFT) 230. Finally, a single output signal 240 is output which has the same dimension as the two input values 200.

The convolution is preferably calculated in a forward step (forward pass) of the convolution-based neural network between at least one first input value (Input 1) of a neural layer of a first input signal 200a of the at least two input signals 200 and convolution cores 200b of the neural layer. Convolution kernels are through a second input signal 200b of the at least two input signals 200 in the 11 and 12 shown. Since the convolution cores 200b generally have smaller dimensions than the first input signal 200a, the signals 200a, 200b must be matched to one another before the AFFT is applied. This can be achieved by inserting zeros (zero padding).

The convolution in a backward step (backward pass) of the convolution-based neural network between input values (input 1) of a neural layer of a first input signal 200a of the at least two input signals 200 and error gradients 200b (input 2) and the convolution between filter kernels 200a (input 1) is preferred. and calculates the error gradient 200b (Input 2). Error gradients 200b are due to a second input signal 200b of the at least two input signals 200 in the 11 and 12 shown. The backward step is composed of the convolution between the input data 200a of the respective layer (input 1) and the error gradient 200b (input 2) as well as the convolution between the filter cores 200a (input 1) and the error gradient 200b (input 2). Here, too, the dimensions may need to be adjusted.

The same reference numerals are used here for the terms convolution kernel 200b, error gradient 200b and second input value 200b in order to be understood in the language of FIG 11 and 12 to point out that depending on whether a backward step (backward pass) or a forward step (forward pass) of the convolution-based neural network takes place, the second input signal 200b has a different physical meaning, but it is always an input signal 200. The same applies to the terms filter core 200a, input data 200a and first input signal 200a.

The folding as such is preferably in one dimension (1D) (See 11 ) or in two dimensions (2D) (see 12 ). Dimensions higher than 2D would also be conceivable.

In the case of a two-dimensional (2D) convolution of the convolution-based neural network, the approximate fast Fourier transformation 210 (AFFT) is preferably first applied to all rows 310 of the two-dimensional input signal 200 and then to all columns 320 of an intermediate result. It is conceivable to use an overlap-and-save (“overcut and save”) or an overlap-and-add (“overlap and add”) fold during the fold. With these convolutions, the input signal is broken down, the AFFT-based convolution is applied to the segments and the filter core, and finally a recombination by means of overlap-and-add or overlap-and-save. For 2D CNNs, a 2D AFFT is performed that approximates a 2D FFT. The 2D AFFT will follow 13 realized by the ordinary AFFT. 13 shows the course of the 2D-AFFT, which follows blocks 210 in 12 are equivalent to.

The method for training and/or executing a convolution-based neural network can also be implemented by a circuit for performing convolutions as part of the training and/or executing a convolution-based neural network. The circuit for performing convolutions in the context of training and/or executing a convolution-based neural network (Convolutional Neural Network, CNN) by means of an approximate fast Fourier transformation (AFFT), which is implemented on an FPGA, in particular as an ASIC or as part of a system on chips (SoCs), is designed to use the method for training and/or or executing a convolution-based neural network. In particular, a circuit for the approximate calculation of butterfly units of a Fourier transformation of a signal is implemented in the circuit for performing convolutions as part of the training and/or execution of a convolution-based neural network. The circuit for training and executing a convolution-based neural network also includes other components whose basic functionalities should be known to a person skilled in the art and are therefore not explained further.

A further aspect comprises a computer program product comprising instructions which, when executed by a computer, cause it to execute the method for training and/or executing a convolutional neural network.

The method described for training and/or executing a convolution-based neural network can significantly reduce the number of arithmetic operations required for the calculation of convolution layers in 1D and 2D CNNs and thus the calculation complexity and the resource consumption of entire networks during inference and training and the Calculation speed can be increased. This represents a significant advantage of the method for training and / or running a convolution-based neural network or the circuit for performing convolutions in the context of training and / or running a convolution-based neural network. The method can be on software-programmable processors and in the form of dedicated Hardware architectures can be implemented on FPGAs or as ASIC. There is also the possibility of integrating the method in the form of software-programmable hardware acceleration in system-on-chips (SoCs). By applying the convolution theorem and calculating the approximated convolution using the AFFT, it is possible to use the transformations between the time and frequency domain, which are necessary for the resource-saving convolution in the frequency domain (Hadamard product = point-wise multiplication), with or without a reduced number of implement multiplications. Most importantly, hardware multipliers are not required. This is associated with an increase in energy efficiency and performance.

Technical areas of application of the method for training and/or executing a convolution-based neural network can be found in all areas where CNNs are used on resource-constrained embedded and edge systems in the form of software, e.g. on microprocessors and embedded GPUs, or digital hardware, e.g. as ASIC or on FPGAs should be. Integration as software-programmable hardware acceleration in SoCs is also conceivable. It is particularly noteworthy that the method described for training and/or executing a convolution-based neural network can be used for both inference and training of CNNs.

The method for training and/or executing a convolution-based neural network can be applied in areas in which CNN inference plays a role, for example in image processing, in particular in object recognition in autonomous driving or person tracking in camera systems, or in applications of Audio signal processing, especially in Natural Language Processing (NLP) for keyword recognition and language assistance systems. The method for training and/or executing a convolution-based neural network can also be used beneficially for intelligent sensor technology in the field of predictive maintenance with CNN-based signal processing in the sensor for diagnostic and forecasting tasks.

In addition, the method for training and/or executing a convolution-based neural network enables the resource-saving training of CNNs, which can be used in the area of autonomous, self-learning or unsupervised learning systems. This can be used, for example, for trainable data compression using autoencoders.

One area of application in the field of predictive maintenance is the autonomous learning of the prediction of the remaining service life of critical machine components such as roller bearings or tools in CNC machines. The data can be annotated autonomously by recording data during the service life of the critical component from the embedded System is provided with time stamps and the end of the component's lifetime is determined with the help of external information (e.g. from the machine control system) or unsupervised clustering processes. Since large amounts of data are recorded over the lifetime of the component, which are not efficiently cached or sent due to limited memory resources of embedded systems and edge systems the trainable data compression using CNN-based autoencoders can also be used here.

In the field of robotics, too, tasks and skills must be learned and expanded adaptively. One example is a robotic arm equipped with a camera for sorting objects based on adaptively learned object recognition, including distance information that is recorded by additional distance sensors during operation.

Although some aspects have been described in the context of a method, it is understood that these aspects also represent a description of a corresponding device, so that a block or a component of a device can also be understood as a corresponding method step or as a feature of a method step and vice versa . For reasons of redundancy, the present invention is not presented in the form of a device. Some or all of the method steps could be performed by (or using) hardware apparatus, such as a microprocessor, a programmable computer, or electronic circuitry. In some embodiments, some or more of the essential process steps can be performed by such an apparatus.

In the foregoing Detailed Description, in part, various features were grouped together in examples in order to streamline the disclosure. This type of disclosure should not be interpreted as an intention that the claimed examples have more features than are expressly recited in each claim. Rather, as the following claims reflect, subject matter may lie in less than all features of a single disclosed example. Thus the following claims are hereby incorporated into the Detailed Description, where each claim may stand as its own separate example. While each claim may stand as its own separate example, it should be noted that although dependent claims in the claims refer back to a specific combination with one or more other claims, other examples also include a combination of dependent claims with the subject-matter of each other dependent claim or a combination of each feature with other dependent or independent claims. Such combinations are contemplated unless it is stated that a specific combination is not intended. Furthermore, it is intended that a combination of features of a claim with any other independent claim is also included, even if that claim is not directly dependent on the independent claim.

Depending on particular implementation requirements, embodiments of the invention may be implemented in hardware, or in software, or at least partially in hardware, or at least partially in software. Implementation can be performed using a digital storage medium such as a floppy disk, a DVD, a BluRay disk, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, a hard disk or other magnetic or optical Memory are carried out on which electronically readable control signals are stored, which can interact with a programmable computer system in such a way or interact that the respective method is carried out. Therefore, the digital storage medium embodying the proposed teaching may be computer-readable.

Some exemplary embodiments according to the teaching described herein thus comprise a data carrier which has electronically readable control signals which are able to interact with a programmable computer system in such a way that one of the features described herein is carried out as a method.

In general, exemplary embodiments of the teaching described herein can be implemented as a computer program product with a program code, the program code being effective to carry out one of the methods when the computer program product runs on a computer.

The program code can also be stored on a machine-readable carrier, for example.

Other embodiments include the computer program for performing any of the features described herein as a method, the computer program being stored on a machine-readable medium. In other words, an exemplary embodiment of the method according to the invention is therefore a computer program that has a program code for performing one of the methods described herein when the computer program runs on a computer.

A further embodiment of a proposed method is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for performing one of the features described herein is recorded as a method. The data carrier or digital storage medium or computer-readable medium is typically tangible and/or non-transitory.

A further exemplary embodiment of the proposed method is therefore a data stream or a sequence of signals which represents the computer program for carrying out one of the methods described herein. For example, the data stream or sequence of signals may be configured to be transferred over a data communication link, such as the Internet.

Another embodiment includes a processing device, such as a computer or programmable logic device, configured or adapted to perform a method of the system described herein.

A further exemplary embodiment comprises a computer on which the computer program for carrying out the method for the system described herein is installed.

A further embodiment according to the invention comprises an apparatus or a system which is designed to transmit a computer program for carrying out at least one of the features described herein in the form of a method to a recipient. The transmission can take place electronically or optically, for example. For example, the recipient may be a computer, mobile device, storage device, or similar device. The device or the system can, for example, comprise a file server for transmission of the computer program to the recipient.

In some embodiments, a programmable logic device (e.g., a field programmable gate array, an FPGA) may be used to perform some or all of the functionality of the methods and apparatus described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor to perform the method described herein. Generally, in some embodiments, the method is performed by any hardware device. This can be hardware that can be used universally, such as a computer processor (CPU), or hardware that is specific to the method, such as an ASIC.

The embodiments described above are merely illustrative of the principles of the present invention. It is understood that modifications and variations to the arrangements and details described herein will occur to those skilled in the art. Therefore, it is intended that the invention be limited only by the scope of the following claims and not by the specific details presented in the description and explanation of the embodiments herein.

State of the art

1. [1] M. Horowitz, "1.1 Computing's Energy Problem (and what we can do about it)," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 .
2. [2] JG Proakis and DG Manolakis, Digital Signal Processing (3rd ed.): Principles, Algorithms, and Applications, Prentice-Hall, Inc., 1996 .
3. [3] JW Cooley and JW Tukey, "An Algorithm for the Machine Calculation of Complex Fourier Series," 1965 .
4. [4] JW Cooley, PAW Lewis, and PD Welch, "Historical Notes on the Fast Fourier Transform," 1967 .
5. [5] JW Cooley, PAW Lewis, and PD Welch, "The Fast Fourier Transform and its Applications," 1969 .
6. [6] Liu W, Liao Q, Qiao F, Xia W, Wang C, Lombardi F, "Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition," IEEE Transactions on Circuits and Systems I: Regular Papers, 2019 .
7. [7] Q Liao, W Liu, F Qiao, C Wang, and F Lombardi, "Design of Approximate FFT with Bit-width Selection Algorithms," 2018 IEEE International Symposium on Circuits and Systems (ISCAS)" 2018 .
8. [8th] R. Teymourzadeh, MJ Abigo, and MV Hoong, "Static quantised radix-2 fast Fourier transform (FFT)/inverse FFT processor for constraints analysis," International Journal of Electronics, 2013 .
9. [9] SC Chan and PM Yiu, "An efficient multiplierless approximation of the fast Fourier transform using sum-of-powers-of-two (SOPOT) coefficients," IEEE Signal Processing Letters, 2002 .
10. [10] W Perera and P Rayner, "Optimal design of multiplierless DFTS and FFTS," ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1986 .
11. [11] Suzuki T, Kyochi S, Tanaka Y, Ikehara M, Aso H, "Multiplierless lifting based FFT via fast Hartley transform," 2013 IEEE International Conference on Acoustics, Speech and Signal Processing, 2013 .
12. [12] M Jiang, B Yang, R Huang, TY Zhang, and YY Wang, "Multiplierless fast Fourier transform architecture," Electronics Letters, 2007 .
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QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

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Non-patent Literature Cited

• M. Horowitz, "1.1 Computing's Energy Problem (and what we can do about it)," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 [0111]
• J.G. Proakis and D.G. Manolakis, Digital Signal Processing (3rd ed.): Principles, Algorithms, and Applications, Prentice-Hall, Inc., 1996 [0111]
• J.W. Cooley and J.W. Tukey, "An Algorithm for the Machine Calculation of Complex Fourier Series," 1965 [0111]
• J.W. Cooley, P.A.W. Lewis and P.D. Welch, "Historical Notes on the Fast Fourier Transform," 1967 [0111]
• J.W. Cooley, P.A.W. Lewis and P.D. Welch, "The Fast Fourier Transform and its Applications," 1969 [0111]
• Liu W, Liao Q, Qiao F, Xia W, Wang C, Lombardi F, "Approximate Designs for Fast Fourier Transform (FFT) With Application to Speech Recognition," IEEE Transactions on Circuits and Systems I: Regular Papers, 2019 [0111]
• Q Liao, W Liu, F Qiao, C Wang, and F Lombardi, "Design of Approximate FFT with Bit-width Selection Algorithms," 2018 IEEE International Symposium on Circuits and Systems (ISCAS)" 2018 [0111]
• R Teymourzadeh, MJ Abigo and MV Hoong, "Static quantised radix-2 fast Fourier transform (FFT)/inverse FFT processor for constraints analysis," International Journal of Electronics, 2013 [0111]
• S C Chan and P M Yiu, "An efficient multiplierless approximation of the fast Fourier transform using sum-of-powers-of-two (SOPOT) coefficients," IEEE Signal Processing Letters, 2002 [0111]
• W Perera and P Rayner, "Optimal design of multiplierless DFTS and FFTS," ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing, 1986 [0111]
• Suzuki T, Kyochi S, Tanaka Y, Ikehara M, Aso H, "Multiplierless lifting based FFT via fast Hartley transform," 2013 IEEE International Conference on Acoustics, Speech and Signal Processing, 2013 [0111]
• M Jiang, B Yang, R Huang, T Y Zhang, and Y Y Wang, "Multiplierless fast Fourier transform architecture," Electronics Letters, 2007 [0111]
• M Rastegari, V Ordonez, J Redmon, and A Farhadi, "XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks," 2016 [0111]
• Hubara I, Courbariaux M, Soudry D, El-Yaniv R, and Bengio Y, "Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations," 2016 [0111]
• H Alemdar, V Leroy, A Prost-Boucle, and F Petrot Ternary Neural Networks for Resource-Efficient AI Applications [0111]
• Han S, Mao H, and Dally WJ, "Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding," 2016 [0111]
• H Li, A Kadav, I Durdanovic, H Samet, and H P Graf, "Pruning Filters For Efficient ConvNets," 2017 [0111]
• E Wang, JJ Davis, PYK Cheung, and GA Constantinides, "LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference," 2020 [0111]
• W. Jiang, X. Zhang, E.H.-M. Sha, L Yang, Q Zhuge, Y Shi, and J Hu, "Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search," 2019. [0111]
• Colangelo P, Segal O, Speicher A, and Margala M, "AutoML for Multilayer Perceptron and FPGA Co-design," 2020 [0111]
• F Conti, PD Schiavone, and L Benini, "XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference," 2018 [0111]

Claims (12)

A method of training and/or executing a convolutional neural network (CNN) using an approximate fast Fourier transform (AFFT), the method comprising: providing at least two input signals; performing a convolution, which includes: approximating a Fourier transform for each of the at least two input signals to obtain at least two approximate fast Fourier transforms (AFFT); calculating a Hadamard product of the at least two approximate Fast Fourier Transforms (AFFT) to obtain an approximate convolution result in the frequency domain; approximating an inverse Fourier transform to obtain an approximate inverse fast Fourier transform (iAFFT); and Output of the inverse (iAFFT) as an approximate convolution result in the time domain. procedure after claim 1 , comprising for approximating the Fourier transform for each of the at least two input signals: decomposing a Fourier transform of a signal into a number of butterfly units having at least two input values; approximating the butterfly units by quantization of rotation factors associated with the butterfly units to obtain approximate rotation factors. Method according to one of the preceding claims, in which the approximation of the fast Fourier transformation takes place via a quantization of rotation factors. procedure after claim 3 , where when approximating the Fourier transform, a multiplication with rotation factors is replaced by a conditional decision in the case of a quantization in P sub-regions. Method according to one of the preceding claims, wherein a dimension of the input signals is arbitrary. Method according to one of the preceding claims, wherein the at least two input signals are of the same dimension, in particular the dimension of the at least two input signals is adjusted to one another by inserting zeros. Method according to one of the preceding claims, in which the convolution in a forward step (Forward Pass) of the convolution-based neural network between input values (Input 1) of a neural layer of a first input signal of the at least two input signals and convolution kernels (Input 2) of the neural layer is calculated. Method according to any of the preceding Claims 1 until 7 , in which the convolution in a backward step (backward pass) of the convolution-based neural network between input values (Input 1) of a neural layer of a first input signal of the at least two input signals and error gradients (Input 2) and the convolution between filter kernels (Input 1) and the error gradients (Input 2) is calculated. Method according to one of the preceding claims, in which the folding is carried out in one dimension (1D) or in two dimensions (2D). Method according to one of the preceding claims, wherein in a two-dimensional (2D) convolution of the convolution-based neural network, the approximate fast Fourier transform (AFFT) is first applied to all rows of the two-dimensional input signal and then to all columns of an intermediate result. Circuit for performing convolutions as part of the training and/or execution of a convolution-based neural network (convolutional neural network, CNN) using an approximate fast Fourier transform (AFFT), which as an FPGA, in particular as an ASIC or as part of a system on chips (SoCs), is implemented and the circuit is designed to use a method according to one of Claims 1 until 10 to perform. A computer program product comprising instructions which, when executed by a computer, cause the computer to carry out the method according to any one of Claims 1 until 10 to execute.

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