DE102021210714A1 - Device for switching a transistor when a voltage is applied - Google Patents

Abstract

The present invention relates to a device (1) for switching a transistor (2) when voltage is applied, comprising a transistor (2) which has a control input (2a) and two switching inputs (2b, 2c), the transistor (2) via the control input (2a) is set to an on state by applying a first potential and to an off state by applying a second potential, a transformer (3) having a primary coil unit (3a) and a secondary coil unit (3b), the primary Coil unit (3a) is coupled to one of the switching inputs (2b, 2c) of the transistor (2) in order to induce a current into the secondary coil unit (3b) when, in the switched-on state, a current flows through the switching inputs (2b, 2c) of the Transistor (2) flows, a first capacitance (4) which is coupled to the secondary coil unit (3b) in such a way that it is charged by the current induced in the secondary coil unit (3b), and a switching unit (5) which is used to is set up to couple the control input (2a) of the transistor (2) to the first capacitance (4) when the transistor (2) is switched to the off state in order to increase a potential difference between the first and the second potential.

Description

State of the art

The present invention relates to a device for switching a transistor. In this case, the invention relates in particular to switching processes in which the voltage change and the current change overlap in time. When switching over, the change in the drain-source voltage and the transition in the drain current are superimposed, this is also referred to as hard switching.

Inductive loads, such as electric motors, are often switched by inverters. Such inverters include power semiconductors through which flowing currents are switched. In order to minimize losses during hard switching operations, attempts are usually made to achieve faster switching operations. However, a disadvantage of faster switching operations is that higher displacement currents flow through a gate-drain capacitance of the semiconductor, which in turn charges a gate-source capacitance of the voltage-controlled semiconductor. Steep edges when a transistor is switched off, so-called high slew rates, can lead to the semiconductor switching on unintentionally. This effect is known as Miller induced turn-on. Compared to silicon semiconductors, wide bandgap semiconductors often present a low threshold for switching and are therefore susceptible to this effect. In order to counteract this effect, a negative bias voltage by a so-called negative bias voltage is advantageous. It is known that charge pumps can be used to generate such a negative bias. However, these are complex to implement. It is also possible to use buck-boost bootstrap circuits.

Disclosure of Invention

The device according to the invention for switching a transistor when a voltage is applied comprises a transistor which has a control input and two switching inputs, the transistor being switched to an switched-on state by applying a first potential to the control input and being switched to an off-state by applying a second potential to the control input is offset, a transformer having a primary coil assembly and a secondary coil assembly, wherein the primary coil assembly is coupled to one of the switching inputs of the transistor to induce a current in the secondary coil assembly when in the on state a current flows through the switching inputs of the transistor , a first capacitance which is coupled to the secondary coil unit in such a way that it is charged by the current induced in the secondary coil unit and a switching unit which is adapted to connect the control input of the transistor to the to couple the first capacitance when the transistor is placed in the off state to increase a potential difference between the first and second potentials.

The transistor is in particular a power transistor, for example a MOSFET. The control input is preferably a gate contact of the transistor and the switching inputs are composed of a source contact and a drain contact. Different voltages between the control input and one of the switching inputs are defined by the first potential and the second potential, which leads to the switching of the transistor. In particular, a gate-source voltage across the transistor is defined by the first potential and the second potential. In the switched-on state, the transistor provides a low-impedance connection between its drain and source contact, ie between its switching inputs. In a switched-off state, the transistor provides a high-impedance connection between its drain and source contact, ie between its switching inputs.

The transformer includes a primary coil assembly and a secondary coil assembly. The primary coil unit includes in particular at least one primary coil and the secondary coil unit includes in particular at least one secondary coil. The primary coil assembly is inductively coupled to the secondary coil assembly.

The primary coil unit is connected to one of the switching inputs of the transistor, in particular to a source contact of the transistor. If a current flows through the transistor via the switching inputs, this current also flows through the primary coil unit and generates a voltage drop across it. This is transformed to the secondary coil unit and induces a current there. The first capacitance is in particular a capacitor. The first capacitance is coupled to the secondary coil unit in such a way that it is charged by the current induced in the secondary coil unit. The first capacitance is charged in particular in that a current flow is impressed into the secondary coil unit and the first capacitance provides the charge required for this current. As a result of the discharge of charge from the first capacitance, this becomes negatively charged. The first capacitance is considered to be charged when it has a potential difference between its connection poles.

The switching unit is set up to couple the control input of the transistor to the first capacitance. At a time when the control input of the transistor is coupled to the first capacitance, the transistor is also placed in the off state. The potential difference between the first and the second potential is increased by the potential of the first capacitance. The first potential and the second potential are present at the control input of the transistor at different times. A voltage drop is described via the potential difference, which occurs at the control input of the transistor when the transistor changes from the switched-on state to the switched-off state. The first potential is in particular a positive potential and the second potential is in particular a ground potential. However, the second potential is preferably also drawn to this negative potential by a negative potential provided by the first capacitance. The potential difference is thus increased by pulling the second potential to a negative potential and leaving the first potential unchanged. For example, the transistor is switched on by applying a potential of 12 V to its control input and is switched off by applying a potential of 0 V. However, this potential difference is increased by means of the first capacitance, so that the transistor is switched to the switched-on state by applying the first potential of 12 V, for example, and is switched to the switched-off state by applying a second potential of −2 V.

By increasing the potential difference in this way, it is avoided, among other things, that the second potential is unintentionally switched via the gate-drain capacitance.

The dependent claims show preferred developments of the invention.

A diode is preferably connected between the first capacitor and the secondary coil unit, which is arranged in such a way that it enables current to flow from the capacitor to the secondary coil unit in its conducting direction. The current flow from the capacitance to the secondary coil unit corresponds to the current that is induced in the secondary coil unit when the transistor is switched to the on state. It is thus achieved that charges are withdrawn from one pole of the first capacitance and flow through the secondary coil unit due to the conducting direction. If the current flowing through the secondary coil unit is reduced, these charges cannot flow back to the capacitance since they would flow against the conducting direction of the diode. Thus, the first capacitance initially remains in a charged state and does not discharge itself. By using the diode, synchronization of additional switching units can be dispensed with.

It is also advantageous if the first capacitance is coupled to a first side with a first pole of a voltage source and is coupled to a second side via the diode and the secondary coil unit to the second pole of the voltage source, the first pole of the voltage source also being connected to is coupled to the same switching input of the transistor to which the primary coil unit is also coupled. The first pole of the voltage source is in particular a negative pole of the voltage source. In this case, the voltage source is connected in particular with its first pole to a source contact of the transistor. In this case, the diode is preferably connected to the first capacitance with an anode side and connected to the secondary coil unit with a cathode side. The voltage source is in particular the same voltage source that provides the first potential for switching the transistor with its second pole. A circuit is thus created through which a voltage drop is generated relative to the first pole of the voltage source, ie relative to the negative pole. This creates a negative potential which can be used as a second potential for switching the transistor to the off state.

It is advantageous if the first potential is a positive potential and the second potential is drawn to a negative potential by the first capacitance. Because the second potential is pulled to a negative potential, a current flow between a drain and a gate contact of the transistor can briefly increase the gate voltage without reaching the threshold voltage, and unwanted switching operations can thus be prevented.

It is also advantageous if the device comprises a second capacitance which is connected to the first capacitance via the secondary coil unit in order to be charged via the current induced in the secondary coil unit, the second capacitance being coupled to the control input of the transistor in this way that the first potential is provided via the second capacitance. The second capacitance is thus charged by the first capacitance, and the current flowing out of the first capacitance is caused by the current induced in the secondary coil unit, which is induced in the secondary coil unit when the transistor is brought into the on state. The second capacity is thus by one induced current caused by the switched current. Since the first potential is provided via the second capacitance and only small currents flow through the transistor, it is possible for a voltage required for switching the transistor, in particular a required gate-source voltage, to be provided by the second capacitance without that it must also be fully charged by a voltage source.

It is advantageous if the device includes a charging circuit which is set up to charge the first capacitance and/or the second capacitance. The charging circuit preferably includes a current source. Although the second capacitance is charged by the induced voltage of the secondary coil unit, it is advantageous precisely in an initial phase if the second capacitance and/or the first capacitance is precharged when the device is put into operation. For example, a first switching operation would only be possible with difficulty or not at all if the second capacitance is not charged. This cannot be charged via the first capacitance either, since this does not yet carry any charge in an initial stage. A charging circuit is therefore advantageous by which the first capacitance and/or the second capacitance is charged independently of the current induced in the secondary coil unit.

Furthermore, it is advantageous if the switching device is also set up to couple the control input of the transistor to a unit providing the first potential in order to switch the transistor to the switched-on state and to isolate the control input of the transistor from the unit providing the first potential and then connect to the second potential to place the transistor in the off state. The unit providing the first potential is in particular the voltage source, which is also coupled to the first capacitance, or the second capacitance.

The switching unit preferably comprises two switches connected in phase opposition, a first switch of the two switches being arranged to couple the control input of the transistor to the unit providing the first potential or to separate it from it, and a second switch of the two switches being arranged to to couple or disconnect the control input of the transistor to the first capacitance. The first switch is in an on state whenever the second switch is in an off state. Accordingly, whenever the second switch is in an on state, the first switch is in an off state. The first and the second switch are thus connected in phase opposition. In this case, the first switch always couples the control input of the transistor to the unit providing the first potential when the transistor is to be switched to the switched-on state. Correspondingly, the first switch isolates the control input of the transistor from the unit providing the first potential if the transistor is to be switched to the switched-off state. At the same time, the first capacitance is always coupled to the control input of the transistor when the transistor is switched to the off state.

This enables it to increase the potential difference between the first and the second potential through its stored charge, in particular by pulling the second potential to a negative potential.

Preferably the transformer is a coreless planar transformer. Thus, the transformer can in particular be fully integrated on a printed circuit board. This prevents unnecessary construction volume and creates a particularly light construction.

An inverter which includes the device for switching a transistor has all the advantages of the device. The device is particularly suitable for hard switching of a transistor.

character list

• 1 ein Schaltbild einer erfindungsgemäßen Vorrichtung gemäß einer ersten Ausführungsform der Erfindung,
• 2 ein Schaltbild einer erfindungsgemäßen Vorrichtung gemäß einer zweiten Ausführungsform der Erfindung,
• 3 eine Visualisierung eines zeitlichen Verlaufs eines Laststromes durch eine Spule welche am Drain-Kontakt angeschlossen ist und einer über den Transistor anliegenden Drain-Source-Spannung,
• 4 eine Visualisierung eines zeitlichen Verlaufs einer Gate-Source-Spannung des Transistors und eine zugehörige Vergrößerung,
• 5 eine Visualisierung eines zeitlichen Verlaufs einer über eine erste Kapazität anliegenden Spannung und eines in eine sekundäre Spuleneinheit induzierten Stromes, und
• 6 eine Visualisierung einer über eine erste Kapazität anliegenden minimalen Spannung abhängig von einem durch den Transistor fließenden Laststromes sowie einer Anstiegszeit einer Drain-Source-Spannung des Transistors abhängig von dem durch den Transistor fließenden Laststrom.

Exemplary embodiments of the invention are described in detail below with reference to the accompanying drawings. In the drawing is:

• 1 a circuit diagram of a device according to the invention according to a first embodiment of the invention,
• 2 a circuit diagram of a device according to the invention according to a second embodiment of the invention,
• 3 a visualization of a time course of a load current through a coil which is connected to the drain contact and a drain-source voltage across the transistor,
• 4 a visualization of a time profile of a gate-source voltage of the transistor and an associated enlargement,
• 5 a visualization of a time course of a voltage present across a first capacitance and a current induced in a secondary coil unit, and
• 6 a visualization of a minimum voltage present across a first capacitance as a function of a load current flowing through the transistor and a rise time of a drain-source voltage of the transistor as a function of the load current flowing through the transistor.

Embodiments of the invention

1 shows a circuit diagram of a device 1 for switching a transistor 2. The device 1 is suitable for hard switching of the transistor 2.

Transistor 2 is a MOSFET transistor. The transistor 2 comprises a control input 2a and two switching inputs 2b, 2c, the transistor 2 being switched via the control input 2a by application of a first potential to an on state and by application of a second potential to an off state. The control input 2a is a gate contact of the transistor 2. The switching inputs 2b, 2c are formed from a first switching input 2b and a second switching input 2c. In this case, the first switching input 2b is a drain contact of the transistor 2 and the second switching input 2c is a source contact of the transistor 2. A switching voltage Vsw to be switched is provided at the first switching input 2b. This can be the switching potential of a step-up converter, for example. The gate-source voltage V _GS of the transistor 2 is defined by the first potential and the second potential, ie a voltage between the control input 2a and the second switching input 2c is defined.

The device 1 further comprises a transformer 3, which is a coreless, planar transformer. The transformer 3 includes a primary coil unit 3a, which is a primary coil of the transformer 3, and a secondary coil unit 3b, which is a secondary coil of the transformer 3. The transformer 3 is formed by two coils formed on one or more conductor plates, which are inductively coupled to one another. A first side of the primary coil unit 3a is coupled to the second switching input 2c of the transistor 2 and a second side is coupled to a ground potential. If the transistor 2 is switched to an switched-on state, a load current i _L flows via the two switching inputs 2b, 2c of the transistor 2 and as a coil current is through the primary coil unit 3a. A magnetic field is built up by the primary coil unit 3a, through which an induction current i _ind is induced in the secondary coil unit 3b. In this case, the induction current i _ind flows, in particular, in a time range immediately after the transistor 2 has switched to the switched-on state.

The device 1 comprises a switching unit 5, which comprises a first switch 5a and a second switch 5b. The switching unit 5 is part of a driver unit which controls the switching of the transistor 2 . For example, the driver unit is a driver unit of an inverter.

The first switch 5a and the second switch 5b are connected in phase opposition. This means that the first switch 5a is in an open state whenever the second switch 5b is in a closed state and vice versa. The first and the second switch 5a, 5b are thus never in a closed or in an open state at the same time. The first switch 5a is coupled to a positive pole of a voltage source 7 via a series resistor R _i . The voltage source 7 is a DC voltage source. A second side of the first switch 5a is connected to the control input 2a of the transistor 2 via an on-resistance _Rgon . A negative pole of the voltage source 7 is connected to the second switching input 2c of the transistor 2 . A gate-source voltage V _GS can thus be applied to the transistor 2 via the first switch 5a. The gate-source voltage V _GS depends on the DC voltage provided by the voltage source 7, the series resistor R _i and the on-resistance R _Gon .

If the first switch 5a is closed, the first potential is thus applied to the control input 2a of the transistor. If the first switch 5a is opened, no potential is applied to the control input 2a of the transistor 2 at least via the first switch 5a. The potential which is present at the control input 2a of the transistor 2 when the first switch 5a is open, ie when the transistor 2 is in an off state, could be regarded as a zero potential. However, this second potential is pulled to a negative potential by a first capacitance 4 of the device 1 . For this it is necessary that the first capacitor 4 is charged with a corresponding polarity.

The first capacitance 4 is charged by means of a diode 6 of the device 1 and the secondary coil unit 3b of the transformer 3. The first capacitance 4 of the device 1 is coupled to a first side with the positive pole of the voltage source 7 . The first capacitance 4 is coupled to an anode side of the diode 6 with a second side. The cathode side of the diode 6 is coupled to a first side of the secondary coil unit 3b. The second side of the secondary coil unit 3b is together with the first side of the first capa capacity 4 and the second switching input 2 c of the transistor 2 coupled to the negative pole of the voltage source 7 .

The second side of the first capacitance 4 is also coupled to the control input 2a of the transistor 2 via the second switch 5b of the switching unit 5 and via a turn-off resistor R _GOff . Due to the arrangement of the diode 6 and its connection to the first capacitor 4 and the secondary coil unit 3b, the diode 6 is arranged in its forward direction in such a way that it enables a current to flow from the capacitor 4 to the secondary coil unit 3b.

When the transistor 2 is turned on, the load current i _L flows through the transistor 2 and the primary coil unit 3a. This causes a current to flow in the opposite direction in the secondary coil unit 3b. By this opposite current, which is called i _ind in 1 is marked, charge carriers are withdrawn from the first capacitance 4 via the diode 6 and flow away via the primary coil unit 3a. The second contact of the first capacitor 4 is thus brought to a negative potential. If the current induced in the secondary coil unit 3b decreases, the corresponding charges cannot flow back into the first capacitance 4, since this is prevented by the diode 6, which prevents the corresponding current flow through its blocking direction. A negative potential is thus generated at the first capacitance 4 . The second switch 5b is in an open state at this time since the first switch 5a is closed to put the transistor 2 in the on state.

When the transistor 2 is switched off, the first switch 5a is opened and the second switch 5b is closed. Thus, the negative potential provided at the first capacitor 4 is applied to the control input 2a of the transistor 2 via the turn-off resistor R _GOff . Thus, the second potential is pulled to a negative potential. A negative gate-source voltage is thus applied to the transistor. This prevents the transistor 2 from being unintentionally switched on again by capacitive currents between its drain and gate. Only when the first switch 5a is closed again and the second switch 5b is correspondingly opened is the transistor 2 switched back to the low-impedance state, and the cycle described above is repeated.

In 2 a device 1 for switching a transistor 2 when a voltage is applied is described according to a second embodiment of the invention. The second embodiment of the invention is based on the same principles as the device 1 described in the first embodiment of the invention. However, this second embodiment differs from the first embodiment of the invention in that the second side of the secondary coil unit 3b is not connected to the second control input 2b of the transistor 2, the first side of the first capacitance 4 and the negative pole of the voltage source 7, but that the second side of the secondary coil unit 3b is connected to the switching unit 5 on a side of the first switch 5a facing away from the transistor 2. This first side of the first switch 5a is also connected to a first side of a second capacitance 8, which can also be referred to as the turn-on capacitance. The second side of the second capacitance 8 is connected to the second control input 2b of the transistor 2 and to the first side of the first capacitance 4 .

When the transistor 2 is turned on, the induction current i _ind is induced in the secondary coil unit 3b. In this case, as in the first embodiment, the second side of the first capacitor 4 is brought to a negative potential. The current flowing away from the first capacitance 4 flows into the second capacitance 8 via the secondary coil unit 3b. This is sometimes also due to the fact that this current cannot flow off via the control input 2a of the transistor 2. The second capacitance 8 is thus charged.

If the transistor 2 is switched to the switched-off state, then the control input 2a is also pulled to a negative potential via the negative potential provided by the first capacitance 4 . If the transistor 2 is switched back to the switched-on state, then the first potential and thus the gate-source voltage V _GS for switching on the transistor 2 is provided by the charges stored in the second capacitance 8 . The second capacitance 8 is thus charged by the current induced in the secondary coil unit 3b and makes this charge available for switching the transistor 2 at its control input 2a. The second capacitance 8 is thus connected to the first capacitance 4 via the secondary coil unit 3b in order to be charged via the current induced in the secondary coil unit 3b, the second capacitance 8 being coupled to the control input 2a of the transistor 2 in such a way that the first potential is provided via the second capacitor 8 .

The device 1 according to the second embodiment preferably comprises a charging circuit 9 which is set up to charge the first capacitance 4 and/or the second capacitance 8 . For this purpose, the charging circuit includes, for example, the span voltage source 7, which is connected to its positive pole via the series resistor R _i and a second diode 10 to the first side of the second capacitor 8. The voltage source 7 is connected to the second side of the second capacitance 8 with its negative pole. The second diode 10 prevents the charge stored in the second capacitor 8 from flowing in the direction of the voltage source 7 when the second capacitor 8 is charged. Thus, when the device 1 is in operation, no current is taken from the voltage source 7 for charging the second capacitance 8 if the latter is sufficiently charged by the secondary coil unit 3b. In a corresponding manner, the first capacitor 4 is coupled to the negative pole of the voltage source 7 via a pre-charging resistor 11 and a third diode 12 . As a result, the first capacitance 4 can also be precharged by the voltage source 7 .

The device 1 according to the second embodiment of the invention has the advantage that hardly any current for operating the device 1 is drawn from the voltage source 7, as a result of which consumption of the device 1 is minimized. A first charge for these capacitors 4, 8 is provided by the voltage source 7 only in an initial phase, in which the first capacitor 4 and the second capacitor 8 are not yet charged.

According to the embodiments described above, the switching on of the transistor 2 leads to a current gradient of a source current Is of the transistor 2. This results in a voltage drop across a primary winding, i.e. across the primary coil unit 3a, of the transformer 3. In order to ensure a sufficient current gradient and thus a sufficient To achieve a voltage drop, so-called hard switching is advantageous. The voltage drop across the primary coil unit 3a is transformed to the secondary coil unit 3b and is optionally amplified according to the number of turns of the transformer 3.

When a voltage across the secondary coil unit 3b is high enough, the induced current i _ind discharges the first capacitance 4, which is a buffer capacitance for a negative gate voltage supply of the transistor 2. According to the first embodiment, the voltage drop across the secondary coil unit 3b is discharged to the source contact of the transistor 2 when it exceeds the forward voltage of the first diode 6. FIG. According to the second embodiment, the first capacitance 4 is discharged into the second capacitance 8 in order to provide a positive voltage supply for the gate of the transistor 2. FIG. The charge of the first capacitance 4 is thus reused to provide a potential at the gate of the transistor 2 . To do this, however, the voltage across the secondary coil unit 3b must exceed a turn-on voltage of the transistor 2 and exceed the forward voltage of the first diode 6 before the first capacitor 4 is discharged. For an initial starting of the device 1, the voltage source 7 is provided in the second embodiment, by which a voltage V _Don is provided. According to both embodiments, a maximum negative voltage is limited by a maximum voltage drop across the secondary coil unit 3b caused by a maximum current gradient.

However, the first and second embodiments of the invention are exemplary embodiments of the invention, and further modifications are possible. In particular, a negative current gradient can also be used during turn-off by adjusting the polarity of the transformer. Instead of a single diode 4, a rectifier can optionally be used in order to discharge the first capacitance 4 when the transistor is switched on and off. However, this increases the complexity of the circuit. Three-stage gate drivers could be used to reduce charge transported to the first capacitance 4 .

Exemplary signals of the circuit according to the second embodiment are described below.

So is in 3 on the left is the load current i _L in a coil which is connected to the drain potential of the transistor together with a freewheeling diode parallel to the coil. In 3 an associated course of a drain-source voltage, ie a voltage across the switching inputs 2b, 2c of the transistor, is shown on the right. The drain-source voltage shows a high overshoot due to the slew rate of the switching signal, which is chosen to be particularly high. The transistor 2 is a gallium nitrite bipolar field effect transistor. This is designed to switch a load current i _L of 15 amperes. It can be seen that an overvoltage peak increases from 335 volts to 360 volts. This is because the rate of rise of the gate-source voltage is also increased, which is caused by the potential through the first capacitance 4 being lowered.

The associated gate-source voltage of transistor 2 is in 4 shown. where is in 4 on the right, a different dimensioning of the time axis was chosen to make details visible. It can be seen that the voltage at the gate of the transistor 2 alternately jumps from a first potential to a second potential. The voltage applied as the gate-source voltage when transistor 2 is turned off becomes, decreases over time. This means that the second potential is pulled further to a negative potential by the first capacitance 4 . At the same time, however, the difference between the first and the second potential increases.

After a settling time of about 250 ms, a maximum voltage of -2.5 V is reached, which defines the second potential. This is also in particular in 4 shown on the right. It can also be seen that the voltage provided by the second capacitor 8, which defines the first potential, rises in a similar manner and has settled after approximately 250 ms. So this voltage increases from about 5V to 5.2V. An initial voltage is provided, for example, by the voltage source 7 and is selected to be 5V. The rise in the first potential and the fall in the second potential is caused by the two capacitances 4, 8, which charge one another.

A course of the voltage V _Doff , which is a voltage drop across the first capacitance 4, is in 5 shown. The first capacitance 4 shows ripple currents which are caused by the discharging when the transistor 2 is switched on and the charging when the second transistor 2 is switched off. The discharging, ie the negative charging, takes place because of the transformer 3 and the positive charging takes place because of the charge provided by the second capacitor 8 . This is also referred to as C _On . The charge of the first capacitance 4, on the other hand, is referred to as C _Off . The two operations of turning the transistor 2 on and turning the transistor 2 off are in 5 marked.

The first capacitor 4 is charged with a constant current, which is described as follows: $$I_{\text{driver}}=C_{\text{off}}\cdot \frac{\mathrm{i.e}{v}_{\text{Doff}}}{\mathrm{i.e}t}=100\text{nF}\cdot \frac{80\text{<figure-callout id="1" label="mV" filenames="DE102021210714A1\_0006.png,DE102021210714A1\_0007.png" state="{{state}}">mV</figure-callout>}}{1\mathrm{\mu }\text{s}}=\mathrm{8th}\text{mA}\text{.}$$

The current I _driver is an active current of the gate driver and must be taken into account below. Especially at low switching frequencies fsw, this current leads to a substantial charge generated by the gate driver (Q _GD ). This charge is described as follows: $$Q_{\text{DG}}=\frac{I_{\text{driver}}}{{ƒ}_{\text{bw}}}=\frac{\mathrm{8th}\text{mA}}{230kH\mathrm{e.g}}=35\text{nC}\text{.}$$

The amplitude of the total ripple currents across the first capacitor 4 can be adjusted by setting the capacitance values of the first capacitor 4 accordingly. A lower ripple current results in a longer settling time, necessitating a trade-off between the advantages and disadvantages of lower ripple currents.

The induction current i _ind flowing through the secondary coil unit 3b is in 5 shown on the right. In particular, an overshoot of the source current is leads to a noticeable increase in the charging time. For example, the rise time TR _20-80 of the drain-source voltage, which is intended for a rise from 20% to 80% of the supply voltage V _sw , is only 4.6 nanoseconds. This is also in 6 shown on the right at a load current of 15 A. In contrast, the induction current i _ind is induced for a duration of approx. 25 nanoseconds. The charge transported by the secondary coil unit 3b is withdrawn from the first capacitance 4 and leads to the following voltage drop: $$\mathrm{i.e}{v}_{\text{Doff}}=\frac{Q_{\text{TFF}}}{C_{\text{off}}}=\frac{54\text{<figure-callout id="100" label="nC" filenames="DE102021210714A1\_0008.png,DE102021210714A1\_0009.png" state="{{state}}">nC</figure-callout>}}{100\text{nF}}=0.54\text{V}.$$

In the previous considerations of 3 until 5 only operation with switching of the maximum load current of 15 A was considered. In the case of lower loads, the resistance values R0 of the pre-charging resistor 11 and the characteristics of the third diode 12 define the voltage drop across the first capacitor 4 . this is in 6 shown on the left, where the average voltage drop across the first capacitance 4 is shown there for an increasing load current i _L , which flows through the switching inputs 2b, 2c of the transistor 2 in the switched-on state.

A distinction can be made between two different operating modes. For low load currents i _L the voltage drop across the first capacitance 4 is constant and consistent with the forward voltage across the third diode 12. The condition for this is that the charge transported into the first capacitance is higher than discharging the first capacitance 4 via the transformer 3. So: $$v_{\text{Doff}}={\mathrm{<figure-callout\; id="0"\; label="v\; D"\; filenames="DE102021210714A1\_0008.png,DE102021210714A1\_0009.png"\; state="\{\{state\}\}">v</figure-callout>}}_{\text{D}}\text{for}{Q}_{\text{TFF}}<Q_{\text{G}}+Q_{\text{DG}}.$$

An important condition for this state is that the additional current pulse caused by discharging a gate capacitance of the transistor 2 does not cause a significant increase in voltage due to the precharge resistor 11 11 (R0). The gate charge (Q _G ) of the semiconductor used has an average value of 4.5 nC when charged from 0 to 6V. However, if the condition defined by formula 1.4 is exceeded, the device 1 is in the second state. If the charge (Q _TFF ), which is discharged from the first capacitor 4, is greater than the sum of the charges Q _G and Q _GD , ie the charges of a gate capacitance and the charge generated by the gate driver, the first capacitance 4 is discharged.

ist. Q_TFF, also die von der ersten Kapazität abgeführte Ladung, erreicht ihr Maximum für hohe Ströme, wobei ein minimaler, von dem Transformator 3 verursachter Spannungsabfall über die erste Kapazität 4 begrenzt wird.In this case, the charge of the gate capacitance Q _G increases since a higher voltage difference is present at the gate of the transistor 2, the charge increasing until an equilibrium between the charges is reached, ie $${\text{Q}}_{\text{TFF}}={\text{Q}}_{\text{G}}+{\text{Q}}_{\text{DG}}$$

is. Q _TFF , ie the charge removed from the first capacitance, reaches its maximum for high currents, with a minimum voltage drop across the first capacitance 4 caused by the transformer 3 being limited.

In summary, it can thus be said that increasing the potential difference between the first and the second potential works less efficiently when the currents switched by the transistor 2 are lower than when comparatively higher load currents i _L are switched. Shorter switching times are achieved by pulling down the second potential only when a specific condition is met. What is also achieved in this way is that the higher the load current, the further the second potential is pulled down. However, these effects are not to be regarded as critical when the device 1 is in operation, since precisely in the case of low currents, the longer rise time means that the transistor 2 does not switch unintentionally. If higher currents are switched, which could often lead to an unwanted switching of the transistor 2, then the device 1 works to an extent in which the second potential is lowered particularly efficiently and faulty switching of the transistor 2 is thus prevented.

In addition to the above disclosure, reference is made explicitly to the disclosures of 1 until 6 referred.

Claims (10)

Device (1) for switching a transistor (2) when voltage is applied, comprising: a transistor (2) which comprises a control input (2a) and two switching inputs (2b, 2c), the transistor (2) being switched on by applying a first potential to the control input (2a) and by applying a second potential the control input (2a) is set to a switched-off state, a transformer (3) with a primary coil unit (3a) and a secondary coil unit (3b), the primary coil unit (3a) being coupled to one of the switching inputs (2b, 2c) of the transistor (2) in order to supply a current to the secondary to induce the coil unit (3b) when a current flows through the switching inputs (2b, 2c) of the transistor (2) in the switched-on state, a first capacitance (4) which is coupled to the secondary coil unit (3b) in such a way that it is charged by the current induced in the secondary coil unit (3b), and a switching unit (5) which is set up to couple the control input (2a) of the transistor (2) to the first capacitance (4) when the transistor (2) is switched to the off state in order to compensate a potential difference between the first and to increase the second potential. Device (1) according to claim 1 , characterized in that a diode (6) is connected between the first capacitor (4) and the secondary coil unit (3b), which is arranged in such a way that in its conducting direction it allows a current to flow from the capacitor (4) to the secondary coil unit ( 3b) allows. Device (1) according to claim 2 , wherein the first capacitance (4) is coupled with a first side to a first pole of a voltage source (7) and with a second side via the diode (6) and the secondary coil unit (3b) to the first pole of the voltage source (7) is coupled, wherein the first pole of the voltage source (7) is further coupled to the same switching input of the transistor (2) with which the primary coil unit (3a) is also coupled. Device (1) according to one of the preceding claims, wherein the first potential is a positive potential and the second potential is pulled to a negative potential by the first capacitance (4). Device (1) according to one of the preceding claims, further comprising a second capacitance (8) which is connected to the first capacitance (4) via the secondary coil unit (3b) in order to be charged via the current induced in the secondary coil unit, wherein the second capacitance (8) is coupled to the control input (2a) of the transistor (2) in such a way that the first potential is provided via the second capacitance (8). Device (1) according to claim 5 , further comprising a charging circuit (9) which is set up to charge the first capacitance (4) and/or the second capacitance (8). Device (1) according to one of the preceding claims, wherein the switching unit (5) is further set up to couple the control input (2a) of the transistor (2) to a unit providing the first potential in order to switch the transistor (2) into the switched-on to put in a state and separating the control input (2a) of the transistor (2) from the unit providing the first potential in order to switch the transistor (2) to the switched-off state. Device (1) according to claim 7 , wherein the switching unit (5) comprises two switches (5a, 5b) connected in phase opposition, wherein - a first switch (5a) of the two switches (5a, 5b) is arranged to connect the control input (2a) of the transistor (2) to the to couple the first potential-providing unit or to separate it from it, and - a second switch (5b) of the two switches (5a, 5b) is arranged to connect the control input (2a) of the transistor (2) to the first capacitance (4) connect or disconnect from it. Apparatus (1) according to any one of the preceding claims, wherein the transformer (3) is a coreless planar transformer. An inverter comprising the device according to any one of the preceding claims.

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