DE102021205172A1 - Storage device and method for checking storage contents - Google Patents

Abstract

Memory device and method for checking memory contents of a memory module with multiple registers. The contents of the individual registers are checked cyclically, periodically one after the other within specified time intervals. This ensures that an error or an inconsistency in the stored data is detected within the specified time period

Description

The present invention relates to a memory device and a method for checking memory contents. The present invention also relates to a control device with such a memory device.

State of the art

Although the present invention is described below in relation to a control device in a motor vehicle, the invention is not limited thereto. Rather, the basic principle according to the invention can be applied to any memory devices, in particular memory devices with a plurality of memory registers.

For numerous control or regulation tasks, for example in connection with driver assistance systems in the automotive sector, it is necessary to calculate control commands using a number of previously recorded or generated input data. To this end, the required input data can be stored in a suitable storage device. The input data provided by this memory device can then be read out in order to generate control commands. For example, a driver assistance system can evaluate input data from one or more radar sensors, optical sensors, such as one or more cameras, or the like.

In order to possibly detect an error in the stored data, a test value can be calculated for the individual stored data values and this test value can be stored in connection with the corresponding data value. For example, the check value can be a checksum, which is calculated using a predefined algorithm. Alternatively, one or more parity bits can also be used.

The pamphlet DE 602 106 58 T2 describes a semiconductor memory device having a memory array storing data values and corresponding error correction values. In the case of a write access, an error correction generator generates a correction value. In the case of a read access, a check is made as to whether the corresponding correction value matches a correction value calculated for the data word that has been read out.

Disclosure of Invention

The present invention discloses a memory device, a control device and a method for checking memory contents with the features of the independent patent claims. Further advantageous embodiments are the subject matter of the dependent patent claims.

• Eine Speichervorrichtung mit einem Speichermodul und einem Prüfmodul. Das Speichermodul umfasst mehrere Speicherregister. Jedes Speicherregister des Speichermoduls ist dazu ausgelegt, einen Datenwert und einen zu dem Datenwert korrespondierenden Prüfwert zu speichern. Das Prüfmodul ist dazu ausgelegt, den Datenwert eines Speicherregisters unter Verwendung des korrespondierenden Prüfwerts zu überprüfen. Insbesondere ist das Prüfmodul dazu ausgelegt, die Datenwerte einer vorbestimmten Gruppe von Speicherregister innerhalb einer vorbestimmten Zeitspanne zu überprüfen. Die Überprüfung der Datenwerte der vorbestimmten Gruppe von Speicherregistern innerhalb einer vorbestimmten Zeitspanne wird periodisch wiederholt. Das Überprüfen der Datenwerte in der Gruppe von Speicherregistern erfolgt sequentiell, das heißt, nacheinander.

Accordingly, it is provided:

• A memory device having a memory module and a test module. The memory module includes multiple memory registers. Each memory register of the memory module is designed to store a data value and a check value corresponding to the data value. The check module is designed to check the data value of a storage register using the corresponding check value. In particular, the checking module is designed to check the data values of a predetermined group of storage registers within a predetermined period of time. The checking of the data values of the predetermined group of storage registers within a predetermined period of time is repeated periodically. The checking of the data values in the group of storage registers is carried out sequentially, that is to say one after the other.

• Eine Steuervorrichtung mit einer erfindungsgemäßen Speichervorrichtung. Die Steuervorrichtung ist insbesondere dazu ausgelegt, Steuersignale unter Verwendung der in den Speicherregistern der Speichervorrichtung gespeicherten Datenwerte zu generieren.

Furthermore, it is provided:

• A control device with a memory device according to the invention. The control device is designed in particular to generate control signals using the data values stored in the memory registers of the memory device.

• Ein Verfahren zur Überprüfung von Speicherinhalten eines Speichermoduls. Das Speichermodul umfasst mehrere Speicherregister. Jedes der mehreren Speicherregister ist dazu ausgelegt, jeweils einen Datenwert und einen zu dem Datenwert korrespondierenden Prüfwert zu speichern. Das Verfahren umfasst einen Schritt zum Auslesen eines Datenwerts und eines korrespondierenden Prüfwerts aus einem der mehreren Speicherregister. Weiterhin umfasst das Verfahren einen Schritt zum Überprüfen des ausgelesenen Datenwerts unter Verwendung des ausgelesenen korrespondierenden Prüfwerts. Das Auslesen sowie das Überprüfen des Datenwerts unter Verwendung des korrespondierenden Prüfwerts wird hierbei für alle Datenwerte einer vorbestimmten Gruppe von Speicherregistern innerhalb einer vorbestimmten Zeitspanne nacheinander ausgeführt. Insbesondere erfolgt das Auslesen und Überprüfen der Datenwerte innerhalb der vorbestimmten Zeitspanne periodisch.

Finally it is provided:

• A method of checking the memory contents of a memory module. The memory module includes multiple memory registers. Each of the multiple storage registers is designed to store a data value and a check value corresponding to the data value. The method includes a step of reading a data value and a corresponding check value from one of the plurality of storage registers. Furthermore, the method comprises a step for checking the data value that has been read out using the corresponding check value that has been read out. The reading out and checking of the data value using the corresponding test value is carried out one after the other for all data values of a predetermined group of storage registers within a predetermined period of time. In particular, the data values are read out and checked periodically within the predetermined period of time.

Advantages of the Invention

The present invention is based on the finding that when data is written, read or stored in a memory, in particular a semiconductor memory, a malfunction can result in a change in a data value to be stored, for example. If such a falsified data value is used as a basis for further operations, such as the control of a technical system, an undesirable malfunction can occur. However, the calculation of test values for checking data values that have been read out requires a computing power that is not negligible. If several data values are used in parallel for control or regulation tasks, it may not be possible to check all the data in parallel within a required period of time at the time of reading.

It is therefore an idea of the present invention to take this knowledge into account and to provide a memory device and a corresponding method which already enables memory contents to be checked in advance. In this way, the reliability of the data values stored in the individual registers of such a memory device can be guaranteed with high reliability.

The memory contents of the individual memory registers are checked one after the other. Therefore, only a relatively small amount of computing power is required to check the data values in the individual memory registers. Since all of the memory registers to be checked are checked for consistency one after the other within a specified time period, it can be ensured that a change, in particular a falsification, of data values in the memory registers is detected within this specified time period. It can thus be ensured that an error in the data values is identified within this specified time period and further processing of erroneous data values can thus be stopped within this specified time period.

If, for example, the data values of such a memory device are used as the basis for functions of a driver assistance system in a motor vehicle, it can be ensured that an inconsistency in the stored data values is detected within the specified time period. Consequently, it can be ensured that the corresponding function of the system is not continued longer than the predetermined period of time based on erroneous data values.

If an error or an inconsistency is detected in the data values stored in the memory device, appropriate steps can be taken. For example, a system that is controlled or regulated on the basis of the data stored in the storage device can be switched to emergency operation or possibly stopped. If necessary, the system can continue to be operated at least partially with the exclusion of the data values identified as faulty.

According to one embodiment, the checking module is designed to provide an error signal if an error has been detected during the periodic checking of the data value of a memory register. Additionally or alternatively, an error signal can also be provided if the output module has detected an error in a data value that has been read out.

The signaling of an error can be provided to a connected data processing device, for example. This data processing device can, for example, initiate appropriate steps after an error or an inconsistency in the stored data values has been signaled. For example, a system that is controlled or regulated using the data values stored in the storage device can be transferred to a safe operating mode or the system can be stopped completely. Furthermore, it is possible to continue to operate the system, for example, excluding the data values identified as faulty.

According to one embodiment of the memory device, the checking module is designed to check the data values of the memory registers one after the other at a predefined clock rate. The specified clock rate can in particular be a clock rate at which the memory device is operated. For example, the clock rate can be a clock rate at which individual data values can be written to or read from the memory register of the memory module, as well as a clock rate at which the memory device can also provide the data values of several, in particular all, memory registers in parallel. In this case, the checking module can be designed to check the data value of a memory register for each cycle.

According to one embodiment, the checking module is designed to check the data values of all memory registers of the predetermined group of memory registers exactly once within the predetermined period of time. Checking of the individual storage registers takes place ter with a predetermined clock rate, n clocks are therefore required for a number of n memory registers. If the checking of the predetermined number of storage registers is already completed before the end of the predetermined period of time, the checking device can be deactivated, if necessary, until the data values are checked again. In this way, for example, energy consumption can be reduced. If the memory module includes more memory registers than can be checked within the specified period of time, the memory registers of the memory module can be divided into a number of groups of memory registers. In this case, a separate test module can be provided for each group of the multiple groups of storage registers.

Correspondingly, according to one embodiment, the memory device can comprise a memory module with a plurality of groups of memory registers, a separate test module being provided for each group of memory registers. In this way, it can be made possible for the consistency of the data values in the individual memory registers to be checked within a relatively short period of time, even when there is a large number of memory registers in the memory module.

According to one embodiment, the memory module is designed to provide the data values of the multiple memory registers in parallel to a data processing system. Such a data processing system can thus simultaneously receive and process the data values provided in parallel from the plurality of memory registers. For example, control commands or the like can be calculated on the basis of the data values provided in parallel.

According to one embodiment, the predetermined period of time within which all data values of a group of memory registers are checked is less than or equal to a fault-tolerant time interval (FTTI), a fault detection time interval (FDTI) or a fault handling time interval (FHTI ). Such time intervals are known from ISO 26262, for example. Such a fault-tolerant time interval designates, for example, a period of time in which a system can or may continue to be operated even with faulty input values. In particular, a system can continue to be operated within such an FTTI without a hazard or significant malfunction occurring.

According to one embodiment, the memory device includes an input module. The input module is designed to receive a data value and an address for a memory register of the memory module. The input module is also designed to calculate a check value for the received data value and/or the address. Furthermore, the input module is designed to write the received data value and the corresponding check value calculated thereto into a memory register, which is specified by the received address. Additionally or alternatively, the memory device includes an output module. The output module is designed to receive an address for a storage register. Furthermore, the output module is designed to read out the data value and the check value from the storage register specified by the received address. Furthermore, the output module is designed to check the data value that has been read out using the corresponding check value that has been read out. Finally, the output module can output the data value that has been read out. In particular, the output module can output a signal in this context if an inconsistency between the read data value and the corresponding test value has been detected.

According to one embodiment, at least the memory module and the test module are implemented on a common microchip. Furthermore, the additional components, such as the input module and/or the output module, can also be implemented on the common chip. In addition, other components, which use the data values stored in the memory module, for example, can also be implemented on the microchip. Alternatively, an interface can be implemented on the microchip, which forwards the data values stored in the individual memory registers in parallel to a further connected component, for example a data processing device or the like.

The above configurations and developments can be combined with one another as desired, insofar as this makes sense. Further refinements, developments and implementations of the invention also include combinations of features of the invention described above or below with regard to the exemplary embodiments that are not explicitly mentioned. In particular, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic forms of the invention.

character list

• 1: eine schematische Darstellung eines Blockschaubilds, einer Speichervorrichtung gemäß einer Ausführungsform; und
• 2: eine schematische Darstellung eines Ablaufdiagramms, wie es einem Verfahren zur Überprüfung von Speicherinhalten gemäß einer Ausführungsform zugrunde liegt.

Further features and advantages of the invention are explained below with reference to the figures. show:

• 1 12 is a schematic representation of a block diagram of a memory device according to an embodiment; and
• 2 FIG. 1: a schematic representation of a flow chart as a basis for a method for checking memory contents according to an embodiment.

Description of the embodiments

1 FIG. 1 shows a schematic representation of a block diagram of a memory device 1 according to an embodiment. The memory device 1 comprises a memory module 10 and a test module 20. Furthermore, the memory device 1 can comprise an input module 30 and/or an output module 40.

The memory module 10 includes a plurality of memory registers 11-i. In particular, a data value can be stored in a first part 12-i and a corresponding test value can be stored in a second part 13-i in each storage register 11-i. The check value can be a value that is calculated in any way using the corresponding data value. For example, it can be a checksum such as a CRC value. However, the use of one or more parity bits is also possible. In addition, any other calculation basis can of course also be provided for creating a test value that corresponds to the data value. As an alternative to a pure test value, it is also possible to use it as a code that also allows error correction. Error correction codes (ECC) of this type, such as a Hamming code, initially enable classification as to whether an error has occurred. If an error has been identified, it can be determined using the code whether the detected error can be corrected. If the detected error can be corrected, a correction can be carried out directly at the output

In order to write to the individual memory registers 11-i, an address value A can be provided at the input module 30, for example, which specifies an address for one of the memory registers 11-i. In parallel with this, a data value D can be provided at the input module 30 . The input module 30 can then calculate a corresponding test value using the data value D provided. This calculated test value can then be stored in the storage register 11-i specified by the address A together with the data value provided.

For reading out individual data values, for example, an address A can be provided at the output module 40, which address specifies one of the memory registers 11-i. The output module 40 can then read out the memory register 11-i specified by the address A and the check value corresponding thereto. The output module 40 then calculates a test value using the read data value and compares this calculated test value with the test value read from the storage register 11-i. If the calculated test value and the read test value agree with one another, the data value read out is classified as correct. Alternatively, if there is a discrepancy between the calculated check value and the read check value, an error in the read data value (or the read check value) can be detected. If such an error is detected, an error signal F can be output, for example. In addition, the read data value D can be output by the output module 40, possibly independently of the result of the check. If necessary, the data value D can also only be output if the checking of the test value that has been read out with the calculated test value indicates an error-free data value.

In addition to the sequential writing and reading out of data values in individual storage registers 11-i, it is also possible to provide several or possibly all data values of the storage registers 11-i in parallel. For example, the data values of the individual memory registers 11-i can be provided as data values D1 to Dn via a suitable interface of the memory device 1. Alternatively, it is also possible to forward the data values D1 to Dn from the memory module 10 directly to a suitable further processing device within a memory chip. In particular when a plurality of data values Di are provided in parallel in the storage registers 11-i, the individual data values Di can also be forwarded without an immediate check of the corresponding test values.

In order to also ensure that the data values stored in the storage registers 11-i are error-free, the test module 20 can be used to periodically check the individual data values in the storage registers 11-i using the corresponding test values. The individual data values and the corresponding test values are sequentially read out and checked one after the other by the test module 20 . For this purpose, the test module 20 reads a data value and the corresponding test value from a memory register 11-i. The test module 20 then calculates a test value for the data value read out and compares it calculated test value with the corresponding read test value. If the calculated test value and the read test value match, the data value (and the corresponding test value) is classified as error-free. If, on the other hand, the calculated check value and the check value read out differ from one another, then this is an indication of an error in the stored data value or in the corresponding check value. In this case, an error can be signaled by outputting an error signal F, for example.

As previously noted, any suitable operation may be initiated (or stopped) upon detection of an error in the stored data values (or the corresponding test values). For example, when an error is signaled by the error signal F, an interrupt or the like can be triggered. After detecting an error, for example, the control of a system can be adjusted accordingly or, if necessary, stopped completely.

The data values are checked sequentially by the check module 20 using the corresponding check values in the individual memory registers 11, i.e. a data value and a corresponding check value are read out one after the other and the data value and the corresponding check value are then checked for consistency. If, for example, the memory device 1 is operated at a predetermined clock rate, then the content of a memory register 11-i can be checked for each cycle of the clock rate. Correspondingly, n clock cycles are therefore required for a number of n memory registers. To check all memory registers 11-i of the memory module 10, for example, all memory registers can be read out and checked cyclically. After the last memory register 11-n has been checked, the first memory register 11-1 can then be checked again. Of course, any other suitable scheme is also possible, which enables all required memory registers 11-i to be read out and checked. After all storage registers have been checked one after the other, a new cycle can be started for the next check of all storage registers 11-i. In this way, the storage registers 11-i can be periodically checked for consistency or freedom from errors.

In particular, if the data values stored in the storage registers 11-i are used as a basis for further operations, such as calculating control commands or the like, it is desirable that an error or an inconsistency in the stored data values be detected within a specified period of time becomes. Such a period of time, within which an error in the data values must be detected, can be specified, for example, by a so-called fault-tolerant time interval (FTTI). Such a time interval designates a maximum period of time during which a system may continue to be operated with faulty data (see e.g. ISO 26262). In addition, periods of time within which an error should/must be detected within a system are also known under the term Fault Detection Time Interval (FDTI) or Fault Handling Time Interval (FHTI).

In order to ensure compliance with the aforementioned condition of error detection within an FTTI or the like, the checking module 20 checks all data values in the storage registers 11-i in a time period which does not exceed a predetermined FTTI. If it is not possible to check all the memory registers 11-i of the memory module 20 by sequentially reading out and checking the individual memory registers 11-i using a single checking module 20, the memory registers 11-i of the memory module 10 can be divided into two or more groups of memory registers 11-i be subdivided. In this case, a separate test module 20 can be provided for each group of memory registers 11-i. The individual test modules 20 can each be operated in parallel.

If, on the other hand, an individual test module 20 can carry out the test more quickly than is specified by the specified time interval, for example the FTTI, even with a sequential check of the individual data values and the corresponding test values in the storage registers 11-i, the test module 20 can carry out up to one pause the renewed check of the register contents and, for example, be deactivated. In this way, the energy consumption of the system can be reduced.

2 shows a schematic representation of a flowchart on which a method for checking memory contents of a memory module is based. The method can be implemented, for example, using the components of the memory device 1 described above. Correspondingly, the memory device 1 can include any components that are required to implement the method described below. Analogously, the method described below can also include any additional steps that have already been described above in connection with the memory device 1 .

In step S1, a data value and a corresponding check value are read from one of the plurality of storage registers 11-i.

In step S2, the data value read out is checked using the corresponding check value read out. For this purpose, for example, a test value can be calculated for the data value read out. The calculated test value can be compared with the read test value. If the test value read out and the calculated test value deviate from one another, an error can be signaled.

The data values are read out and checked using the corresponding test values for all data values and test values of a predetermined group of storage registers within a predetermined time period, in particular within an FTTI, for example. Furthermore, the reading and checking of all the contents of the storage registers 11-i of the group of storage registers are repeated periodically.

In summary, the present invention relates to a memory device and a method for checking memory contents of a memory module with a plurality of registers. The contents of the individual registers are checked cyclically, periodically one after the other within specified time intervals. This ensures that an error or an inconsistency in the stored data is detected within the specified time period.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• DE 60210658 T2 [0005]

Claims (10)

Storage device (1), comprising: a memory module (10) comprising a plurality of memory registers (11-i), each memory register (11-i) being designed to store a data value and a check value corresponding to the data value; and a check module (20) designed to check the data value of a memory register (11-i) using the corresponding check value, wherein the checking module (20) is also designed to periodically check the data values of a predetermined group of storage registers (11-i) one after the other periodically within a predetermined period of time. Storage device (1) according to claim 1 , wherein the checking module (20) is designed to provide an error signal (F) if an error has been detected during the periodic checking of the data value of a memory register. Storage device (1) according to claim 1 or 2 , wherein the test module (20) is designed to check the data values of the memory registers (11-i) one after the other at a predetermined clock rate, and wherein the test module (20) is designed to check the data value of a memory register (11-i) per cycle to check. Storage device (1) according to one of Claims 1 until 3 , wherein the data values of all storage registers (11-i) of the predetermined group of storage registers (11-i) are each checked exactly once within the predetermined period of time. Storage device (1) according to one of Claims 1 until 4 , wherein the memory module (10) comprises a plurality of groups of memory registers (11-i), and wherein a separate test module (20) is provided for each group of memory registers (11-i). Storage device (1) according to one of Claims 1 until 5 , wherein the memory module (10) is designed to provide the data values of the plurality of memory registers (11-i) in parallel to a data processing system, and wherein the predetermined period of time corresponds at most to a fault-tolerant time interval of the data processing system. Storage device (1) according to one of Claims 1 until 6 , having an input module (30) designed to receive a data value (D) and an address (A) for a memory register (11-i) of the memory module (20), a check value for the received data value (D) and /or to calculate the received address (A) and to write the received data value (D) and the calculated check value into the storage register (11-i) specified by the address (A); and an output module (40) adapted to receive an address (A) for a storage register (11-i), the data value and the check value from the storage register (11-i) specified by the received address (A) to read out, to check the read out data value using the corresponding test value and to output the read out data value. Storage device (1) according to one of Claims 1 until 7 , wherein the memory module (10) and the test module (20) are implemented in a common microchip. Control device, with a storage device (1) according to one of Claims 1 until 8th , wherein the control device is designed to generate control signals using the data values stored in the storage registers (11-i). Method for checking memory contents of a memory module (10) with a plurality of memory registers (11-i), the plurality of memory registers (11-i) each being designed to store a data value and a test value corresponding to the data value, with the steps: reading (S1) a data value and a corresponding check value from one of the plurality of storage registers (11-i); and Checking (S2) the data value read out using the corresponding check value read out; wherein the reading out (S1) and the checking (S2) are carried out periodically within a predetermined period of time one after the other for the data values of a predetermined group of storage registers (11-i).

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