DE102021128986A1 - Tile-based phased array architecture for a multi-band phased array structure and communication method - Google Patents

Abstract

A radio frequency integrated circuit (RFIC) and method of communicating are provided. The RFIC includes phase locked loop (PLL) and data stream circuitry and a plurality of tiles in communication with the PLL and data stream circuitry. The plurality of tiles includes at least one tile for each frequency band of the RFIC. The plurality of tiles are configured to communicate with a data stream signal between tiles in a cascading sequence. Each tile of the plurality of tiles includes a plurality of up/down converter mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (RF). Each tile also includes a plurality of front-end (FE) elements, each in communication with a corresponding antenna and up/down converter of the plurality of up/down converters.

Description

priority

This application is based on and claims priority under 35 USC §119(e) of US provisional patent application serial number filed on February 1, 2021 in the United States Patent and Trademark Office 63/144,222 , the contents of which are incorporated herein by reference.

Area

The present disclosure relates generally to multi-band phased arrays, and more particularly to tile-based multi-band phased arrays.

background

High speed data transfer between mobile communication devices requires a high bandwidth communication channel. A 5th generation (5G) cellular technology has been extended into the millimeter (mm) wave frequency band to exploit the wide frequency bands that are available. Phased array techniques refer to the use of multiple transmit/receive antennas spaced at distances proportional to a carrier wavelength. These techniques play a critical role in maintaining the mm-wave data links. In addition, as the n260 high frequency band (37-40 GHz) and the n257 low frequency band (26.5-29.5 GHz) move towards greater commercialization, higher frequency bands (e.g. 47.2-48.2 GHz, 40-43 GHz and 60 GHz).

Typically, phased arrays employing a phase-shifting radio frequency (RF) architecture are deployed in a single-chip array or a multi-chip modular phased array.

1 Figure 12 is a diagram illustrating a single-chip complementary metal-oxide-semiconductor (CMOS) phased array. A single phased array chip 102 receives signals at an intermediate frequency (IF) from a center chip in a superheterodyne architecture. The single phased array chip 102 converts the signals from the IF to radio frequency (RF) and transmits the signals through one or more antennas at the RF. Accordingly, the IF is the input frequency to the single phased array chip 102 and the RF is the frequency at which the signals are sent to or received from one or more antennas of the single phased array chip 102 .

The single phased array chip 102 integrates all front-end (FE) elements 104-1 through 104-n required to drive the respective antennas. An FE element contains circuits that are repeated for each antenna. Specifically, each FE element includes a low-noise amplifier (LNA) 106, a power amplifier (PA) 108, phase shifter (PS) 110, and a transmit/receive (T/R) switch 112. During transmission of data stream signals A and B, a converts On-chip distribution network (or data stream circuitry) 114 with an up/down converter mixer converts the data stream signals A and B from an intermediate frequency (IF) to a radio frequency (RF) and transmits the converted signals to the corresponding FEs 104-1 through 104-n . The architecture lends itself to a small form factor solution since all radio elements such as clock generation circuitry, calibration circuitry and microprocessors are integrated onto the same die.

A conventional multi-chip phased array can also be combined with a printed circuit board (PCB). A unitary element on the PCB can be a small gun (e.g., a 2x2 or four element core). Each beam generation chip contains only a PA, LNA and PS. The distribution network (the data stream circuit) and the phase-locked loop (PLL) are not included in the beamformer chip.

Although the architecture on the PCB is more easily scalable than that on 1 , it occupies a larger area due to the multi-chip approach. Consequently, the architecture on the PCB is not suitable for mobile devices with a limited amount of area for components. Also, this architecture inherently consumes more power due to transitions between multiple chips and the PCB.

short version

According to one embodiment, a radio frequency integrated circuit (RFIC) is provided. The RFIC includes PLL and data stream circuitry and a plurality of tiles associated with the PLL and data stream circuitry. The plurality of tiles includes at least one tile for each frequency band of the RFIC. The plurality of tiles are configured to communicate with a data stream signal between tiles in a cascading sequence. Each tile of the plurality of tiles includes a plurality of up/down converter mixers for converting the data stream signal between an IF and an RF. Each tile also contains a plurality of FE elements, each associated with a corresponding antenna and uplink /down converter mixer of the plurality of up/down converter mixers.

According to one embodiment, a method for communicating a data stream signal using an RFIC is provided. At least one data stream signal is received at one of a plurality of tiles of the RFIC. The plurality of tiles includes at least one tile for each frequency band of the RFIC. The plurality of tiles are configured to communicate between tiles in a cascading sequence. Each tile of the plurality of tiles includes a plurality of up/down converter mixers and a plurality of FE elements. Each of the plurality of FE elements is in communication with a corresponding one of the antenna and an up/down converter mixer of the plurality of up/down converter mixers. The at least one data stream signal is converted between an IF and an RF at the plurality of up/down converter mixers of the ones of the plurality of tiles.

character list

• 1 ein Diagramm ist, das ein Einzelchip-CMOS-Phased-Array darstellt;
• 2 ein Diagramm ist, das eine Tri-Band-Mehrfacheingabe-Mehrfachausgabe(MIMO)-Phased-Array-HFIC nach einer Ausführungsform darstellt;
• 3 und 4 Diagramme sind, die Doppelband-MIMO-Phased-Array-HFICs nach einer Ausführungsform darstellen;
• 5 ein Diagramm ist, das eine Struktur einer einzelnen Kachel einer HFIC nach einer Ausführungsform darstellt;
• 6 ein Diagramm ist, das mehrere kaskadierte Kacheln einer HFIC nach einer Ausführungsform darstellt;
• 7 ein Flussdiagramm ist, das ein Verfahren zum Kommunizieren eines Datenstromsignals mittels einer HFIC nach einer Ausführungsform darstellt;
• 8 ein Flussdiagramm ist, das ein Verfahren zum Verarbeiten eines Datenstromsignals für eine Kommunikation mittels einer HFIC nach einer Ausführungsform darstellt;
• 9 ein Flussdiagramm ist, das ein Verfahren zum Verarbeiten eines Datenstromsignals für eine Kommunikation mittels einer HFIC nach einer weiteren Ausführungsform darstellt; und
• 10 ein Blockdiagramm einer elektronischen Vorrichtung in einer Netzwerkumgebung nach einer Ausführungsform ist.

For a more thorough understanding of the above and other aspects, features and advantages of certain embodiments of the present disclosure, the following detailed description is taken in conjunction with the accompanying drawings, in which:

• 1 Figure 12 is a diagram illustrating a single chip CMOS phased array;
• 2 Figure 12 is a diagram illustrating a tri-band multiple input multiple output (MIMO) phased array RFIC according to one embodiment;
• 3 and 4 Figure 12 are diagrams illustrating dual band MIMO phased array RFICs according to one embodiment;
• 5 Figure 12 is a diagram illustrating a structure of a single tile of an RFIC according to one embodiment;
• 6 Figure 12 is a diagram illustrating multiple cascaded tiles of an RFIC according to one embodiment;
• 7 FIG. 12 is a flow diagram illustrating a method for communicating a data stream signal using an RFIC according to one embodiment;
• 8th Fig. 12 is a flow diagram illustrating a method of processing a data stream signal for communication using an RFIC according to one embodiment;
• 9 Fig. 12 is a flow diagram illustrating a method of processing a data stream signal for communication using an RFIC according to another embodiment; and
• 10 Figure 12 is a block diagram of an electronic device in a network environment according to one embodiment.

Detailed description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same elements are given the same reference numbers even though they are shown in different drawings. In the following description, specific details, such as detailed configurations and components, are provided only to facilitate an overall understanding of the embodiments of the present disclosure. Thus, it should be apparent to those skilled in the art that various changes and modifications can be made in the embodiments described herein without departing from the scope of the present disclosure. In addition, for the sake of clarity and brevity, descriptions of well-known functions and constructions are omitted. The terms described below are terms defined in consideration of the functions in the present disclosure, and may differ according to users, users' intentions, or habits. Thus, the definitions of terms throughout this specification should be determined based on the contents.

The present disclosure can have various modifications and various embodiments, of which embodiments will be described below in detail with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to the embodiments but includes all modifications, equivalents and alternatives within the scope of the present disclosure.

Although the terms containing an atomic number such as first, second, etc. can be used to describe various elements, the structural elements are not limited by these terms. The terms are only used to distinguish one element from another element. For example, without departing from the scope of the present disclosure, a first structural element may be referred to as a second structural element. Similarly, the second structural element can also be referred to as the first structural element. As used herein, the term "and/or" includes any and all combinations of one or more related items.

The terms used herein are merely used to describe various embodiments of the present disclosure, but are not intended to limit the present disclosure. Singular forms are intended to contain plural forms unless the context clearly dictates otherwise. In the present disclosure, it is understood that the terms "including" or "comprising" indicate the presence of a feature, number, step, operation, structural element, part, or combination thereof, and the presence or likelihood of addition of one or more features, numbers, steps, operations, structural elements, parts or combinations thereof.

Unless otherwise defined, all terms used herein have the same meanings as those understood by a person skilled in the art to which the present disclosure is directed. Terms, such as those defined in commonly used dictionaries, should be interpreted to have the same meanings as the meanings of the relevant prior art context and should not be interpreted to have an idealized or overly formal meaning have meaning unless clearly defined in the present disclosure.

The electronic device according to an embodiment may be one of various types of electronic devices. The electronic devices may include, for example: a portable communication device (e.g., a smartphone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to an embodiment of the disclosure, an electronic device is not limited to those described above.

The terms used in the present disclosure are not intended to limit the present disclosure, but are intended to include various changes, equivalents, or substitutions for a corresponding embodiment. With respect to the descriptions of the accompanying drawings, the same reference numbers may refer to similar or related elements. A singular form of a noun corresponding to an item may contain one or more of the elements, unless the relevant context clearly dictates otherwise. As used herein, any phrase such as "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C" and "at least one of A, B, or C" includes all possible combinations of the items listed together in accordance with any of the sentences. As used herein, terms such as "1st," "2nd," "first," and "second" may be used to distinguish a corresponding component from another component, but are not intended to to constrain the components in other aspects (e.g. importance or order). It is intended that when an element (e.g. a first element), with or without the term 'operative' or 'communicative', is meant to be 'coupled', 'connected', 'with' another element (e.g. a second element). when “connected” or referred to as “coupled” to that, it indicates that the element may be coupled to the other element directly (e.g., wired), wirelessly, or through a third element.

As used herein, the term "module" may include an entity implemented in hardware, software, or firmware, and may be used interchangeably with other terms such as "logic," "logic block," "part," and "circuit." will. A module may be a single integral component or a minimum unit or portion thereof configured to perform one or more functions. For example, a module according to one embodiment may be implemented in application specific integrated circuit (ASIC) form.

Embodiments of the disclosure relate to a phased array architecture supporting multiple 5G mm wavebands with a single phased array RFIC. Specifically, the embodiments provide a single-chip, tile-based phased array architecture. More specifically, a modular architecture is provided in which the phased array is formed by cascaded tiles. Each band has a dedicated tiling structure (e.g. vertical tiles) for a multi-band phased array.

Each tile contains up/down converter mixers. Accordingly, a signal from each tile is combined with the IF, which is well suited for multi-band structures where the RF frequency spans are nearly 24 GHz (e.g. 24.25-48 GHz). Embodiments can also be used with multi-band structures that have RF frequency spans with ceilings that exceed 48 GHz.

Compared with the traditional architecture 1 , which requires RF phase shifting and RF signal combining, the tile-based approach allows the signal distribution network (data stream circuitry) to be simplified. This simplification reduces loss in the distribution network and saves power.

The single chip approach allows integration of FE elements (i.e. those components located between the antenna and the mixer), a PLL, a calibration circuit and a microprocessor within a compact die. Furthermore, the tile-based approach allows for a scalable structure in terms of bandage.

Each tile contains FE elements and up/down converter mixers. In contrast to the conventional architecture's RF phase shifting and RF signal combining, the tile-based approach uses RF or local oscillator (LO) phase shifting with IF signal combining. Thus, signal combining is performed at IF rather than HF. In a multi-band phased array, the RF signal can span an octave of bandwidth from 24.5 GHz to 47.5 GHz. Achieving a flat frequency response over such a wide bandwidth results in higher power consumption. With IF signal combining, the signal distribution is at a common IF for all bands, eliminating such power consumption concerns.

2 FIG. 12 is a diagram illustrating a tri-band MIMO phased array RFIC according to an embodiment of the disclosure. Specifically, the tri-band refers to 2 to low band (LB) 28, high band (HB) 39 and ultra high band (UHB) 47.

For signal transmission via the RFIC, a PLL 202 and a signal distribution circuit (data stream circuit) accept up to two data streams A and B at the IF (eg, IF A 204 and IF_B 206). Data streams A and B can be transmitted from a middle chip to the RFIC in a superheterodyne architecture. After amplification/buffering during the IF, the data streams A and B are distributed to tiles of the RFIC. Two tiles are provided for each of frequency bands 28, 39 and 47 (eg one tile for each data stream), resulting in a total of six tiles. The PLL 202 and signal distribution circuitry are preferably located in the center of the RFIC with outwardly extending tiles. Even though 2 Figure 12 illustrates the tiles extending outward with increasing frequency bands, the embodiments are not limited to such an arrangement and the tiles may be arranged in any order. For example, the tiles can extend outward with decreasing frequency bands.

IF_A 204 is distributed to a first tile 208 of frequency band 28, a second tile 210 of frequency band 39, and a third tile 212 of frequency band 47. IF_B 204 is distributed to a fourth tile 214 of frequency band 28, a fifth tile 216 of frequency band 39, and a sixth tile 218 of frequency band 47. Although this embodiment represents six tiles and three specific frequency bands, any number of tiles representing any frequency band may be provided. Furthermore, a single stream of data can be delivered to only half of the tiles, or the single stream of data can be delivered to all of the tiles.

Each tile contains a multiplexer/demultiplexer and two-way splitter/combiner 220 (i.e. 1:2) to distribute the signal to a top and bottom half of the tile or to pass the signal to a next adjacent tile in the cascading sequence of tiles . Each tile also includes first and second clock multiplier circuits 222 and 224 and first and second up/down converter mixers 226 and 228, one of each pair for the top and bottom halves of the tile. The data stream is upconverted from IF to RF at first and second up/down converter mixers 226 and 228 using a clock frequency signal from first and second clock multiplier circuits 222 and 224 .

The top and bottom halves of the tile also contain first and second two-way splitter/combiners 230 and 232 for distributing the data stream signal to four FE elements. More specifically, the first two-way splitter/combiner 230 splits the data stream signal between first and second FE elements 234 and 236 at a top half of the tile, and the second two-way splitter/combiner 232 splits the data stream signal between a third and fourth FE element 238 and 240 on a lower half of the tile. An FE element contains circuits that are repeated for each antenna of the tile.

For signal reception via the RFIC, data stream signals are received via the antennas of a tile and processed by the corresponding FE elements 234-240. Upper half signals are combined at first two-way splitter/combiner 230 and lower half signals are combined at second two-way splitter/combiner 232 before the respective combined signals at first and second up/down converter mixers 226 and 228, respectively be down-converted by the first and second clock multiplier circuits 222 and 224 using the clock frequency signal. Converted Signals The top and bottom halves are combined at the two-way splitter/combiner 220 and through the multiplexer/demultiplexer which passes them to the PLL and data stream circuitry directly or through a previous adjacent tile in the cascading sequence of tiles.

3 and 4 12 are diagrams illustrating dual band MIMO phased array RFICs according to embodiments of the disclosure. Specifically, the double band refers to 3 on frequency bands 39 and 47 and the dual band 4 refers to frequency bands 28 and 39. For scalability, the tiles are developed such that a transition between tri-band/dual-band/single-band structures only requires removal of unused tiles. Accordingly, components 302, 304, 306, 310, 312, 316, and 318 correspond to FIG 3 Components 202, 204, 206, 210, 212, 216 and 218 referred to above with reference to FIG 2 be described in detail. 3 excludes tiles 208 and 214 corresponding to frequency band 28. Also, components 402, 404, 406, 408, 410, 414, and 416 correspond to FIG 4 Components 202, 204, 206, 208, 210, 214 and 216 referred to above with reference to FIG 2 be described in detail. 4 excludes tiles 212 and 218 corresponding to frequency band 47.

Due to the fact that each tile of the RFIC is cascaded and is self-contained without overlapping, the tile-based approach relies on proper signal/clock distribution.

Tiles of different frequency bands of the HFIC operate at different carrier frequencies (F _HF,BAND ). A common intermediate frequency (F _IF ) for a signal is transmitted to all tiles. Thus a clock frequency (F _CLK = F _HF,BAND - F _IF ) for up/down converter mixers also differs for tiles of different frequency bands. To generate the other clock frequency, a common low frequency reference clock input (F _REF ) is distributed across the RFIC. Each tile accepts and buffers the reference clock input (F _REF ) and sends the reference clock input (F _REF ) to a next tile in the cascading sequence of tiles. The clock multiplier circuits in each tile generate the clock frequency (F _CLK ) for the corresponding tile by multiplying the reference clock by a predefined value. A different predefined value can be preset for each tile.

According to one embodiment, a tile in the cascade of tiles on the RFIC is sequentially activated. If a tile is activated from both the left and right sides of the circuit, these may be required for the same frequency band. Without interband carrier aggregation, the combiner structure is simplified.

5 FIG. 12 is a diagram illustrating a structure of a single tile of an RFIC according to an embodiment of the disclosure. Concretely, when the HFIC is used for a transmission 5 represents a single tile 502 for a frequency band 28 (LB) receiving a distributed IF signal A (data stream signal) that is input to a multiplexer/demultiplexer 504 operating as a demultiplexer with one input line and two output lines (1:2) is used. If the tile 502 corresponds to an active channel, the data stream signal is output from the demultiplexer 504 to a two-way splitter/combiner 506 with one input line and two output lines (1:2). The two output lines of the two-way splitter/combiner 506 distribute the data stream signal to a lower and an upper half of the tile 502. When the tile 502 corresponds to an inactive channel, the data stream signal is output by the demultiplexer 504 to a through channel connected to an opposite one end of tile 502 is output to a next tile in the cascading sequence of tiles. The data stream signal continues to cascade through the plurality of pages of the RFIC until it reaches a page corresponding to an active channel.

The reference clock input (F _REF ) is input to first and second clock multiplier circuits 508 and 510 in the top and bottom halves of tile 502 and then output via a through channel from an opposite end of tile 502 to a next tile in the cascading sequence of tiles . The reference clock input (F _REF ) is sent to each page of the HFIC. The first and second clock multiplier circuits 508 and 510 buffer the reference clock input (F _REF ) and multiply the reference clock input (F _REF ) by a predefined value N, resulting in a clock frequency (F _CLK ). Tiles are preset with different values N to result in the appropriate clock frequency (F _CLK ) for a given tile.

When the RFIC corresponds to an active channel during a transmission, the first and second clock multiplier circuits 508 and 510 can feed the clock frequency (F _CLK ) to a corresponding first and second up/down converter mixer 512 and 514, one each in the upper and lower halves the tile is 502. The first and second up/down converter mixers 512 and 514 are also supplied with the data stream signal from the two-way splitter/combiner 506 . Using the clock frequency (F _CLK ), the first and second up-convert /down converter mixers 512 and 514 up the data stream signal from an IF to an HF operating at a carrier frequency (F _HF,BAND ). The first up/down converter mixer 512 transmits the upconverted data stream signal to a first two-way splitter/combiner 516 which splits the data stream signal between first and second FE elements 520 and 522 of tile 502 . Similarly, the second up/down converter mixer 514 provides the up-converted data stream signal to a second two-way splitter/combiner 518 which splits the data stream signal between third and fourth FE elements 524 and 526 .

Each of the FE elements 520-526 includes a PS 528, an LNA 530, a PA 532, and a T/R switch 534. When the RFIC corresponds to an active channel during transmission, the data stream signal is passed through the PS 528, the PA 532 and the T/R switch 534 of each FE element before it is transmitted by means of a corresponding antenna at the HF. If the PS 528 is an RF PS, the tile uses two up/down converter mixers. If the PS 528 is a LO-PS, the tile uses four up/down converter mixers.

When the HFIC is used for receiving a data stream signal at the HF through the antennas of tile 502 (e.g. tile 502 corresponds to an active channel), the signal is passed through the T/R switch 534, the LNA 530 and the PS 528 of the FE elements 520-526 provided. Data stream signals from the first and second FE elements 520 and 522 are combined at the first two-way splitter/combiner 516 . Data stream signals from the third and fourth FE elements 524 and 526 are combined at the second two-way splitter/combiner 518 . Combined data stream signals are transmitted from the first and second two-way splitter/combiners 516 and 518 to the first and second up/down converter mixers 512 and 514, which convert the data signals using the clock frequency (F _CLK ) from the first and second clock multiplier circuits 508 and 510 down-converting from the HF to the IF, respectively. The down-converted signals are sent from the first and second up/down-converter mixers 512 and 514 to the two-way splitter/combiner 506, which combines the down-converted signals. The multiplexer/demultiplexer 504 acts as a multiplexer and receives the combined signal from the two-way splitter/combiner 506 and outputs the combined signal from the tile 502 . The signal is output from the tile 502 to a PLL and data stream circuitry of the RFIC, either directly or via one or more previous tiles in the cascading sequence of tiles in the RFIC.

If the HFIC is used for receiving, but the tile 502 corresponds to an inactive channel, the multiplexer 504 receives a signal from a subsequent tile in the cascading sequence and the multiplexer 504 passes this signal through the PLL and data stream circuitry of the HFIC either directly or advance to tiles in the HIFC by means of one or more previous tiles in the cascading sequence.

6 FIG. 12 is a diagram illustrating multiple cascaded tiles of an RFIC according to an embodiment of the disclosure. specifically 6 Figure 12 illustrates a cascade of a first tile 602 for frequency band 28 (LB), a second tile 604 for frequency band 39 (HB), and a third tile 606 for frequency band 47 (UHB). Each tile has structure and components corresponding to those described above regarding 5 be described on.

When the RFIC transmits a data stream signal, the reference clock input (F _REF ) and the data stream signal are provided in a cascading manner from tile to tile. Specifically, the reference clock input (F _REF ) is cascaded through each of the first through third tiles 602-606 while the data stream signal is cascaded through the tiles corresponding to inactive channels until a tile corresponding to an active channel is reached.

When the RFIC receives a data stream signal, the reference clock input (F _REF ) is provided in the same cascading manner from tile to tile. When the data stream signal is received by the antennas of the third tile 606, the signal is output from the third tile 606 and cascades in a reverse direction through the second tile 604 and the first tile 602 before reaching the PLL and data stream circuitry of the RFIC. When the data stream signal is received by the antennas of the second tile 604, the signal is output from the second tile 604 and cascades in a reverse direction through the first tile 602 before reaching the PLL and data stream circuitry of the RFIC. When the data stream signal is received by the antennas of the first tile 602, the signal is output from the first tile 602 to the PLL and data stream circuitry of the RFIC.

Each tile has a different predefined value N ₁ , N ₂ , N ₃ for use in their respective clock multiplier circuits. Accordingly, each tile can have a different clock speed (F _CLK ) and operates at a different carrier frequency (F _HF,BAND ).

Referring to 7 12 is a flowchart depicting a method for communicating a data stream signal using an RFIC according to an embodiment of the disclosure. At 702, a reference clock signal is transmitted to each tile of the RFIC in a cascading sequence. The HFIC contains a pair of tiles for each frequency band of the HFIC. At 704, a data stream signal is received at a tile of the RFIC. At 706, the reference clock signal is multiplied by a predefined value at clock multiplier circuits of the tile to generate a clock frequency for the tile. At 708, the data stream signal is processed and converted between an IF and an RF at up/down converter mixers of the tile using the clock frequency of the tile. The tile corresponds to an active channel.

8th FIG. 12 is a flow diagram illustrating a method of processing a data stream signal for communication via an RFIC according to an embodiment of the disclosure. Specifically, the procedure is over 8th a detailed description of 708 from 7 , when the RFIC transmits a data stream signal and the data stream signal is transmitted to the tile by a PLL and data stream circuit of the RFIC. At 802, the data stream signal received at the tile is upconverted from an IF to an RF at the upconverter/downconverter mixer of the tile using the clock frequency of the tile. At 804, the converted data stream signal is communicated to FE elements of the tile for transmission via respective antennas.

9 FIG. 12 is a flow chart illustrating a method of processing a data stream signal for communication via an RFIC according to another embodiment of the disclosure. Specifically, the procedure is over 9 a detailed description of 708 from 7 , when the RFIC receives a data stream signal. At 902, data stream signals are received via antennas and correspond to FE elements of the tile. At 904, the data stream signals are down-converted from an RF to an IF at the up/down converter mixers based on the clock frequency from the clock multiplier circuits. At 906, the down-converted data stream signals are combined and the combined data stream signal is output from the tile to a PLL and data stream circuit of the RFIC either directly or via one or more previous tiles in the cascading sequence of tiles of the RFIC.

10 12 is a block diagram of an electronic device in a network environment according to one embodiment. Referring to 10 An electronic device 1001 in a network environment 1000 can communicate with an electronic device 1002 by means of a first network 1098 (e.g. a short-range wireless communication network) or by means of a second network 1099 (e.g. a long-range wireless communication network) with an electronic device 1004 or a server 1008 communicate. The electronic device 1001 can communicate with the electronic device 1004 via the server 1008 . Electronic device 1001 may include processor 1020, memory 1030, input device 1050, audio output device 1055, display device 1060, audio module 1070, sensor module 1076, interface 1077, haptic module 1079, camera module 1080, power management module 1088, a battery 1089, a communication module 1090, a subscriber identification module (SIM) 1096 or an antenna module 1097. In one embodiment, at least one (eg, the display device 1060 or the camera module 1080) of the components may be omitted from the electronic device 1001, or one or more other components may be added to the electronic device 1001. Some of the components can be implemented as a single integrated circuit (IC). For example, the sensor module 1076 (eg, a fingerprint sensor, an iris sensor, or an illuminance sensor) may be embedded in the display device 1060 (eg, a display).

For example, processor 1020 may execute software (eg, program 1040) to control at least one other component (eg, hardware or software component) of electronic device 1001 coupled to processor 1020, and may perform various data processing or -perform calculations. As at least a portion of the data processing or computations, processor 1020 may load into volatile memory 1032 a command or data received from another component (e.g., sensor module 1076 or communication module 1090), the command or data that stored in volatile memory 1032, and store resulting data in non-volatile memory 1034. The processor 1020 may include a main processor 1021 (eg, a central processing unit (CPU) or an applications processor (AP)) and an auxiliary processor 1023 (eg, a graphics processing unit (GPU), an image signal processor (ISP), a sensor hub processor, or a communications processor (CP)), which is independent of or in connection with the main processor 1021 is operable included. Additionally or alternatively, the auxiliary processor 1023 can be set up to consume less power than the main processor 1021 or to perform a specific function. The auxiliary processor 1023 can be implemented such that it is separate from the main processor 1021 or is part of it.

The auxiliary processor 1023 can perform at least some of the functions or states related to at least one component (e.g. the display device 1060, the sensor module 1076 or the communication module 1090) among the components of the electronic device 1001 instead of the main processor 1021, while the main processor 1021 in a inactive (e.g. sleeping) state, or together with the main processor 1021 while the main processor 1021 is in an active state (e.g. running an application). Adjunct processor 1023 (e.g., an image signal processor or a communications processor) may be implemented as part of another component (e.g., camera module 1080 or communications module 1090) that functionally relates to adjunct processor 1023.

Memory 1030 may store various data used by at least one component (e.g., processor 1020 or sensor module 1076) of electronic device 1001. The various data may include, for example, software (e.g. program 1040) and input data or output data for an instruction related thereto. Memory 1030 may include volatile memory 1032 or non-volatile memory 1034 .

The program 1040 may be stored in memory 1030 as software and may include an operating system (OS) 1042, middleware 1044, or an application 1046, for example.

Input device 1050 may receive a command or data used by another component (e.g., processor 1020) of electronic device 1001 from outside (e.g., a user) of electronic device 1001. The input device 1050 may include a microphone, a mouse, or a keyboard, for example.

The sound output device 1055 can output sound signals to the outside of the electronic device 1001 . The audio output device 1055 may include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as playing multimedia or recording, and the receiver can be used to receive an incoming call. The receiver can be implemented as separate from or part of the speaker.

The display device 1060 can visually communicate information externally (e.g., to a user) of the electronic device 1001 . The display device 1060 may include, for example, a display, a hologram device, or a projector, and control circuitry for controlling a corresponding one of the display, the hologram device, and the projector. The display device 1060 may include touch circuitry configured to detect a touch or sensor circuitry (e.g., a pressure sensor) configured to measure the intensity of a force generated by the touch.

The audio module 1070 can convert a sound into an electrical signal and vice versa. The audio module 1070 may receive the audio via the input device 1050 or output the audio via the audio output device 1055 or a headset of an external electronic device 1002 directly (e.g., wired) or wirelessly coupled to the electronic device 1001 .

Sensor module 1076 may sense an operating condition (e.g., power or temperature) of electronic device 1001 or an environmental condition (e.g., a condition of a user) external to electronic device 1001 and then generate an electrical signal or data value corresponding to the sensed condition. The sensor module 1076 can be, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor contain.

Interface 1077 may support one or more specified protocols to be used for electronic device 1001 to be coupled to external electronic device 1002 directly (e.g., wired) or wirelessly. Interface 1077 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

A connection port 1078 may include a connector by which the electronic device 1001 can be physically connected to the external electronic device 1002 . The connection port 1078 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

The haptic module 1079 can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that can be detected by a user through haptics or kinesthetic sensation. The haptic module 1079 may include a motor, a piezoelectric element, or an electrical stimulator, for example.

The camera module 1080 can capture a still image or a moving image. The camera module 1080 may include one or more lenses, image sensors, image signal processors, or flashlights.

The power management module 1088 can manage power supplied to the electronic device 1001 . The power management module 1088 may be implemented as at least a portion of, for example, a power management integrated circuit (PMIC).

The battery 1089 can power at least one component of the electronic device 1001 . The battery 1089 may include a primary cell that is non-rechargeable and a secondary cell that is rechargeable, or a fuel cell, for example.

The communication module 1090 can establish a direct (e.g. wired) communication channel or a wireless communication channel between the electronic device 1001 and the external electronic device (e.g. the electronic device 1002, the electronic device 1004 or the server 1008) and perform a communication by means of the support established communication channel. Communications module 1090 may include one or more communications processors that operate independently of processor 1020 (e.g., the AP) and supports direct (e.g., wired) communication or wireless communication. The communication module 1090 may be a wireless communication module 1092 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 1094 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module) included. A corresponding one of these communication modules can be established using the first network 1098 (e.g., a short-range communication network such as Bluetooth™, Wireless-Fidelity (Wi-Fi)-Direct, or an Infrared Data Association (IrDA) standard) or the second network 1099 ( e.g., a wide area communications network such as a cellular network, the Internet, or a computer network (e.g., LAN or Wide Area Network (WAN)) communicate with the external electronic device These different types of communication modules can be implemented as a single component (e.g., a single IC). or can be implemented as multiple components (e.g., multiple ICs) that are separate from each other. The wireless communication module 1092 can connect the electronic device 1001 to a communication network, such as the first network 1098 or the second network 1099, using subscriber information (e.g., international mobile subscriber ID identity (IMSI)) stored in subscriber identification module 1096 identify and authenticate.

The antenna module 1097 can send or receive a signal or power outside (e.g., to the external electronic device) of the electronic device 1001 . The antenna module 1097 can contain one or more antennas and at least one antenna suitable for a communication method used in the communication network, such as the first network 1098 or the second network 1099, can be used, for example by the communication module 1090 (e.g. the wireless communication module 1092) can be selected. The signal or power can then be transmitted or received between the communication module 1090 and the external electronic device via the selected at least one antenna.

At least some of the components described above may be coupled together and communicate signals therebetween by means of an interperipheral communication technique (e.g., a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industrial processor interface (MIPI)).

Commands or data can be sent or received between the electronic device 1001 and the external electronic device 1004 via the server 1008 coupled to the second network 1099 . Each of the electronic devices 1002 and 1004 may be a device of the same type as the electronic device 1001 or a different type than that. All or some operations to be performed on the electronic device 1001 can be performed on one or more of the external electronic devices 1002, 1004 or 1008 to be executed. For example, if electronic device 1001 is to perform a function or service automatically or in response to a request from a user or other device, instead of or in addition to performing the function or service, electronic device 1001 may perform the one or more require external electronic devices to perform at least part of the function or service. The one or more external electronic devices receiving the request may perform the at least a portion of the requested function or service or an additional function or service related to the request and transmit a result of the performance to the electronic device 1001 transmitted. The electronic device 1001 may provide the result, with or without further processing of the result, as at least part of a response to the challenge. For example, cloud computing, distributed computing, or client-server computing can be used for this purpose.

An embodiment may be implemented as software (e.g., program 1040) that includes one or more instructions stored on a storage medium (e.g., internal memory 1036 or external memory 1038) hosted by a machine (e.g., electronic device 1001 ) can be read. For example, a processor of electronic device 1001 may invoke and execute at least one of the one or more instructions stored in the storage medium, with or without using one or more other components under the control of the processor. Thus, a machine is operable to perform at least one function in accordance with the at least one instruction being called. The one or more instructions may include code generated by a compiler or code executable by an interpreter. A machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term "non-transitory" indicates that the storage medium is a tangible device and does not contain a signal (e.g. an electromagnetic wave), but this term does not distinguish between where data is stored semi-permanently in the storage medium and where the data is stored in the storage medium transiently .

According to one embodiment, a method of the disclosure may be included and provided in a computer program product. The computer program product can be traded as a product between a seller and a buyer. The computer program product can be distributed in the form of a machine-readable storage medium (e.g. a compact disk read-only memory (CD-ROM)) or can be distributed online or between two user devices (e.g. smartphones) directly using an app store (e.g. Play Store™). When distributed online, at least part of the computer program product may be created temporarily, or at least temporarily stored, in the machine-readable storage medium, such as a manufacturer's server storage, an app store server, or a relay server.

According to one embodiment, each component (e.g., a module or a program) of the components described above may include a single entity or multiple entities. One or more of the components described above may be omitted, or one or more other components may be added. Alternatively or additionally, a plurality of components (e.g. modules or programs) can be integrated into a single component. In this case, the integrated component may still perform one or more functions of each of the plurality of components in the same or similar manner as performed by a corresponding one of the plurality of components prior to integration. Operations performed by the module, program, or other component may be performed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations may be performed in a different order or omitted, or one or more other operations may be added.

Although specific embodiments of the present disclosure have been described in the detailed description of the present disclosure, the present disclosure can be modified in various forms without departing from the scope of the present disclosure. Thus, the scope of the present disclosure is not to be determined solely based on the described embodiments, but rather is to be determined based on the appended claims and the equivalents thereto.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US 63/144222 [0001]

Claims (20)

Radio Frequency Integrated Circuit (RFIC) comprising: a phase locked loop (PLL) and data stream circuit; a plurality of tiles in communication with the PLL and data streaming circuitry, having at least one tile for each frequency band of the RFIC, the plurality of tiles configured to communicate with a data streaming signal between tiles in a cascading sequence, and wherein each tile of the plurality of tiles: a plurality of up/down converter mixers for converting the data stream signal between an intermediate frequency (IF) and a radio frequency (HF); and a plurality of front end (FE) elements, each in communication with a corresponding antenna and an up/down converter mixer of the plurality of up/down converter mixers. HFIC after claim 1 , wherein: the PLL and data stream circuit provides a reference clock signal to each tile in the cascading sequence; and each tile further comprises a plurality of clock multiplier circuits, and when a given tile of the plurality of tiles receives the reference clock signal: the plurality of clock multiplier circuits multiplies the reference clock signal by a predefined value to generate a respective clock frequency for the given tile; and the predetermined tile transmits the reference clock signal to a next tile in the cascading sequence via a first pass-through channel. HFIC after claim 2 , where tiles from different frequency bands are preset with different predefined values. HFIC after claim 2 , each tile further comprising a demultiplexer and when the given tile receives the data stream signal from the PLL and data stream circuitry in the cascading sequence: the demultiplexer transmits the data stream signal to the next tile in the cascading sequence by means of a second through channel when the given tile receives a corresponds to an inactive channel and transmits the data stream signal to the plurality of up/down converter mixers when the predetermined tile corresponds to an active channel. HFIC after claim 4 wherein each tile further comprises a two-way splitter/combiner and when the given tile corresponds to the active channel: the two-way splitter/combiner receives the data stream signal from the demultiplexer and splits the data stream signal between the plurality of up/down converter mixers , and the plurality of up/down converter mixers up-convert the data stream signals from IF to RF based on the clock frequency from the clock multiplier circuits. HFIC after claim 5 , wherein each of the plurality of FE elements includes a phase shifter, a power amplifier, a low noise amplifier, and a transmit/receive switch. HFIC after claim 6 , where: the two-way splitter/combiner splits the data stream signal between two up/down converter mixers when the phase shifter is an RF phase shifter, and the two-way splitter/combiner splits the data stream signal between four up/down converter mixers when the phase shifter is a local oscillator (LO) phase shifter. HFIC after claim 5 wherein each tile further comprises a pair of two-way splitter/combiners that split the converted data stream signals into the plurality of FE elements for transmitting the converted data stream signals via the corresponding antennas. HFIC after claim 2 wherein each tile further comprises a pair of two-way splitter/combiners and when the given tile receives data stream signals from the respective antennas: the plurality of FE elements transmit the data stream signals to the pair of two-way splitter/combiners which combine the data stream signals; and the pair of two-way splitter/combiners communicate the combined data stream signals to the plurality of up/down converter mixers, which convert the combined data stream signals from RF to IF based on the clock frequency from the clock multiplier circuits. HFIC after claim 9 , wherein each of the plurality of FE elements includes a phase shifter, a power amplifier, a low noise amplifier, and a transmit/receive switch. HFIC after claim 10 wherein: the combined data stream signals are sent to two up/down converter mixers when the phase shifter is an RF phase shifter; and the combined data stream signals are sent to four up/down converter mixers if the phase shifter is an LO phase shifter. HFIC after claim 6 wherein each tile further comprises: a two-way splitter/combiner that converts converted data stream signals from the plurality of up/down converter mixers; and a multiplexer receiving the combined converted data signal from the two-way splitter/combiner and outputting the combined converted data signal to the PLL and data stream circuitry directly or via a previous page in the cascading sequence. A method of communicating a data stream signal using a radio frequency integrated circuit (RFIC), the method comprising: receiving at least one data stream signal at one of a plurality of tiles of the HFIC, the plurality of tiles having at least one tile for each frequency band of the HFIC, the plurality of tiles configured to communicate between tiles in a cascading sequence, and each tile of the The plurality of tiles includes a plurality of up/down converter mixers and a plurality of front end (FE) elements, each of the plurality of FE elements being in communication with a corresponding antenna and an up/down converter mixer of the plurality of up/down converters. down converter mixers; and converting the at least one data stream signal between an intermediate frequency (IF) and a radio frequency (HF) at the plurality of up/down converter mixers of the ones of the plurality of tiles. procedure after Claim 13 , further comprising: transmitting a reference clock signal from a phase locked loop (PLL) and data stream circuit of the RFIC to each tile of the cascading sequence; and when a given tile of the plurality of tiles receives the reference clock signal: multiplying the reference clock signal by a predefined value at a plurality of clock multiplier circuits to generate a respective clock frequency for the given tile; and transmitting the reference clock signal to a next tile in the cascading sequence via a first through channel. procedure after Claim 14 , where tiles of different frequency bands are set with different predefined values. procedure after Claim 14 , wherein the at least one data stream signal is transmitted via the RFIC and receiving the at least one data stream signal comprises: transmitting a data stream signal of the PLL and data stream circuitry of the RFIC to one or more of a plurality of tiles of the RFIC in the cascading sequence. procedure after Claim 16 wherein converting the at least one data stream signal comprises: when the predetermined tile corresponds to an active channel: upconverting the data stream signal from the IF to the RF at the plurality of up/down converter mixers based on the clock frequency from the clock multiplier circuits; and transmitting the up-converted data stream signal to the plurality of FE elements for transmission over the corresponding antennas; and if the given tile corresponds to an inactive channel, transmitting the data stream signal to a next tile in the cascading sequence via a second pass-through channel. procedure after Claim 14 , wherein the at least one data stream signal is received via the RFIC, and receiving the at least one data stream signal comprises: receiving data stream signals via antennas and corresponding FE elements of the one of the plurality of tiles of the RFIC. procedure after Claim 18 , wherein converting the at least one data stream signal comprises: down-converting the data stream signals from the RF to the IF at the plurality of up/down converter mixers based on the clock frequency of the clock multiplier circuits. procedure after claim 19 , further comprising: combining the down-converted data stream signals at a combiner to produce a combined data stream signal; transmitting the combined data stream signal to the PLL and data stream circuitry directly or through a previous tile in the cascading sequence.

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