DE102021127129B4 - Device and method for detecting an electrical line current with an optimized sampling rate - Google Patents

Abstract

The invention relates to a device and an associated method for detecting an electrical line current (ILTG) in a line. The device includes a shunt resistor (113), a pre-filter (120), an amplifier (130), an analog-to-digital converter (200) and an oversampling and decimation filter (300). The electric line current (ILTG) flows through the shunt resistor (113), so that a shunt resistor voltage (US) drops across it. The pre-filter (120) pre-filters the shunt resistance voltage (US) to an amplifier input voltage (Ue). The amplifier (130) detects the amplifier input voltage (Ue) and amplifies it to form an amplifier output signal (133). The analog to digital converter (200) samples the amplifier output signal (133) at a sample rate and converts it to a decimation filter input signal (301). The oversampling and decimation filter (300) filters the decimation filter input signal (301) into a decimation filter output signal (302). The device provides the decimation filter output signal (302) as a measurement signal for at least one value of the electrical line current (ILTG) in the line. The oversampling and decimation filter (300) filters the shunt resistor voltage (US) to an amplifier input voltage (Ue) depending on a value of the amplifier output signal (133) as a timer input value.

Description

The invention relates to a device and a method for detecting a current value of a line current using a shunt resistor.

When a current value of a line current is detected, very small currents also occur. These very small currents result in very small voltage drops across the shunt resistor.
In analog-to-digital conversion of such very small input signals with very small voltage values for the voltage drop across the shunt resistor, the averaging of several measured values required for noise suppression leads to long conversion times. However, these long conversion times are critical in many applications.
When converting very small input signals from analog to digital, noise leads to different digital values when the input signal is constant. Oversampling by averaging over several cycles can reduce this influence (over-sampling and decimation - OSR). However, this increases the time until a valid measurement value is available. This effect plays a subordinate role for input signals with a larger amplitude, since other disturbance variables determine the overall accuracy in this range, such as the reference, the temperature response and the gain error.
To increase the signal-to-noise ratio (SNR) for small input signals, the device increases the number of measurements (over-sampling rate [OSR]), with the device then averaging the measurements. For each doubling of the accuracy, the device requires a quadrupling of the number of measurements that the device requires to determine the measurement result. This requirement quickly leads to a very high number of necessary scans (measurements) which the device averages for one measurement run. This high number of measurements leads to very long conversion times.

The DE 10 2011 078 698 B3 already discloses a device and a method for detecting an electrical line current in a line.
The DE 10 2011 078 698 B3 however, has no ability to vary resolution according to signal amplitude.

The object of the invention is to create a solution that does not have the above disadvantages of the prior art and has other advantages.

To solve the problem, a device and a method according to the independent claims are proposed.

Further advantageous configurations of the invention can be found in the dependent claims, the description and the figures.

The invention includes a dynamic adjustment of the averaging of the measured values, which measured values are recorded by evaluation electronics on a sensor element of a sensor.

The evaluation electronics include an analog-to-digital converter.

During the acquisition of the measured values, the evaluation electronics dynamically adapts a speed of its analog-to-digital converter according to a size of an input signal of the evaluation electronics, so that a conversion that is optimal for the input signal takes place.

The number of measurements that the evaluation electronics carry out on the sensor element per unit of time is then dependent on the size of the input signal, i.e. the level on the sensor element of the sensor. For small input signals, the evaluation electronics selects a significantly larger number of sampling points and thus measured values in order to obtain good noise suppression (signal-to-noise ratio [SNR]) in this range. In the range of higher input voltages, the evaluation electronics selects a lower sampling rate and thus a lower over-sampling rate (OSR). At the same time, with a suitable structure, the evaluation electronics can change the speed of its subsystem of analog-to-digital converter and the subsequent oversampling and decimation filter inversely to the oversampling rate (OSR). The speed of the device results from the sampling rate of the analog-to-digital converter multiplied by the number of samples that the subsequent oversampling and decimation filter uses for the averaging. This is possible because the settling time to 1 LSB is shorter with small input voltages than with large input voltages.

The invention relates to a device for detecting an electrical line current I _LTG in a line. In this case, the electrical line current I _LTG flows from a first node to a third node. The device has a shunt resistor. The device includes a first resistor. The value of the first resistor can be 0 ohms. The first resistor can also be just a line section of an electrical line. The device includes a second resistor. The value of the second resistor can be 0 ohms. The second resistor can also be just a line section of an electrical line.

The shunt resistor typically has a first terminal and a second terminal. The first resistor has a first terminal and a second terminal. The second resistor has a first terminal and a second terminal.

The first node electrically connects the first terminal of the shunt resistor directly or indirectly to the first terminal of the first resistor.

The third node electrically connects the second terminal of the shunt resistor directly or indirectly to the first terminal of the second resistor.

The electrical line current I _LTG flows through the shunt resistor.

The purpose of the device is to determine the value of the electric line current I _LTG .

In particular, the device includes an amplifier and an analog-to-digital converter. In particular, the device comprises an overhaul and decimation filter.

In particular, the rework and decimation filter is a linear filter. As a result, an increase in the input signal results in a corresponding proportional change in the output signal.

In particular, the device includes a signal path. In particular, the signal path extends from the shunt resistor to the output of the oversampling and decimation filter. The shunt resistor serves as the signal source and the oversampling and decimation filter as the measured value output.

In particular, the signal path includes the amplifier and the analog-to-digital converter. In particular, the amplifier is placed between the shunt resistor and the output of the oversampling and decimation filter.

In particular, the analog-to-digital converter is placed between the shunt resistor and the output of the oversampling and decimation filter.

The amplifier has a positive (+) input. The amplifier also has a negative input (-). Furthermore, the amplifier has an output in the form of an output signal from the amplifier.

The analog-to-digital converter has an analog input and a digital output signal.

The rework and decimation filter has a digital input and an output with an output signal.

A second node electrically connects the second terminal of the first resistor directly or indirectly through a pre-filter to the positive input (+) of the amplifier.

A fourth node electrically connects the second terminal of the second resistor directly or indirectly via the pre-filter to the negative (-) input of the amplifier.

The output of the amplifier is electrically connected to the input of the analog-to-digital converter. The digital output of the analog to digital converter is electrically connected to the input of the oversampling and decimation filter. The digital output of the analog-to-digital converter can typically include several electrical lines. The analog-to-digital converter samples the analog value of the input signal of the analog-to-digital converter at sampling times. The sampling times are preferably periodic with a temporal sampling period. In the sense of this document, the reciprocal of the sampling period is the sampling frequency. For the purposes of this document, the sampling frequency divided by 2π is the sampling rate. In order to determine a sampling period, a suitable measuring device records the time interval between a first sampling time and a second sampling time immediately following in time. At these sampling times, the analog/digital converter converts the analog value of the input signal of the analog/digital converter into a digital value. The analog-to-digital converter outputs this digital value as a digital output signal. After this sampling, the analog-to-digital converter uses the digital output signal to signal the relevant sampling value to the input of the oversampling and decimation filter.

The output values of the output signal of the processing and decimation filter represent at least temporarily the current values recorded by the device for a line current I _LTG through the shunt resistor. The limitation to "temporarily" comes about because the analog-to-digital converter only can detect the current value of the line current I _LTG at the sampling times. In contrast to the prior art, the document presented here now proposes that the device additionally comprises a timer unit. In particular, the timer unit detects at least one timer input value signal. The value of such a timer input value signal denotes the document presented here also as a timer input value in the following.

In particular, the timer unit records at least one respective timer input value. The timer unit preferably detects a plurality of timer input values.

The document presented here goes into more detail below about the nature of the timer input value signals proposed by way of example and the associated timer input value proposed by way of example.

The core idea of the invention is that the timer unit at least temporarily influences at least one signal transmission property of a sub-device within the signal path between the shunt resistor and the output signal of the oversampling and decimation filter as a function of at least one detected respective timer input value.

1. a) ein Vorfilter,
2. b) der Verstärker und
3. c) der Analog-Digital-Wandler und der Überabtastungs- und Dezimations-Filter.

For purposes of this document, the exemplary sub-devices are within the signal path between the shunt resistor and the output of the oversampling and decimation filter

1. a) a pre-filter,
2. b) the amplifier and
3. c) the analog to digital converter and the oversampling and decimation filter.

• • die Eingangsspannung U_e des Verstärkers,
• • das Verstärkerausgangssignal des Verstärkers,
• • das Eingangssignal des Analog-Digital-Wandlers,
• • das Ausgangssignal des Analog-Digital-Wandlers,
• • das Eingangssignal des Überabtastungs- und Dezimations-Filters bzw. das Dezimationsfiltereingangssignal, und
• • das Ausgangssignal des Überabtastungs- und Dezimations-Filters bzw. das Dezimationsfilterausgangssignal.

Possible timer input value signals within the meaning of this document are:

• • the input voltage U _e of the amplifier,
• • the amplifier output signal of the amplifier,
• • the input signal of the analog-to-digital converter,
• • the output signal of the analog-to-digital converter,
• • the input signal of the oversampling and decimation filter or the decimation filter input signal, and
• • the output signal of the oversampling and decimation filter or the decimation filter output signal.

• • das Verstärkerausgangssignal des Verstärkers,
• • das Eingangssignal des Analog-Digital-Wandlers und
• • das Ausgangssignal des Überabtastungs- und Dezimations-Filters bzw. des Dezimationsfilterausgangssignals.

In particular, the use of the following timer input value signals is preferred:

• • the amplifier output signal of the amplifier,
• • the input signal of the analog-to-digital converter and
• • the output signal of the oversampling and decimation filter or the decimation filter output signal.

This device has the advantage that the device can increase the sampling rate in the case of small signal amplitudes, while the device can take into account a longer settling time in the case of large signal amplitudes. In this way, the device optimizes the relative resolution or the time until this resolution is reached.

In one configuration of the device, the timer unit can influence at least one, in particular several, in particular all sampling times of the analog/digital converter. This influence is an influence on a signal transmission property in a sub-device in said signal path. In the case of this embodiment, the sub-device in question is the analog-to-digital converter. According to the proposal, the device carries out this influencing of the signal transmission property of the analog/digital converter in this embodiment as a function of the at least one detected respective timer input value. Possible timer input values are described above. In this configuration of the device, the timer unit can, for example, also influence a filter or amplifier property in the signal path between the shunt resistor and the output signal of the oversampling and decimation filter as a signal transmission property depending on the at least one detected respective timer input value. As a result, the timer unit of the device can adapt the sampling rate to a level of the input signal, that is to say to the current value of the line current I _LTG . In this way, the timer unit of the device can also reconfigure the filters. This enables an optimal adaptation of the filtering in the pre-filter and/or an optimal adaptation of the filtering in the oversampling and decimation filter to the sampling rate of the analog-to-digital converter.

A further configuration of the device deals with individual sampling times. In this refinement of the device, the timer unit detects the sampling times of the analog/digital converter as a function of the at least one detected respective timer input value. As a result, the timing unit of the device a) can optimally adapt the sampling rate to the level of the input signal, ie to the current value of the line current I _LTG .

In a further refinement of the device, the timer unit of the device influences properties of the processing and decimation filter as a function of the at least one detected respective timer input value. Possible timer input values are explained above. As a result, the timer unit of the device can reconfigure the processing and decimation filter in such a way that the filtering in the oversampling and decimation filter is optimally adapted to the sampling rate of the analog-to-digital converter, for example.

In a further configuration of the device, the timer unit of the device influences properties of the processing and decimation filter in the form of filter frequencies and/or attenuations and/or amplifications of the processing and decimation filter as a function of the at least one detected respective timer input value. Possible timer input values are explained above. As a result, the timer unit of the device can reconfigure the processing and decimation filter in such a way that the filtering in the oversampling and decimation filter is optimally adapted to the sampling rate of the analog-to-digital converter, for example.

In a further refinement of the device, the timer unit influences properties of the pre-filter as a function of the at least one detected respective timer input value.

In a further configuration of the device, the timer unit influences properties of the pre-filter in the form of filter frequencies and/or attenuations and/or amplifications of the pre-filter as a function of the at least one detected respective timer input value. In the sense of this document, the pre-filter is preferably a low-pass or band-pass filter with an upper limit frequency f _oV .

In a further embodiment of the device, a timer input value signal is the input signal of the analog/digital converter, for example. The associated timer input value is then preferably an ADC input value of the input signal of the analog/digital converter. In this variant, too, the device can adapt the relative error to the signal level.

In a further configuration of the device, for example, the timer unit at least temporarily records values of the input signal of the analog/digital converter in the form of recorded ADC input values as timer input values of a timer input value signal. In this case, the timer unit preferably influences sampling times of the analog/digital converter as a function of detected ADC input values. In this variant, too, the device can adapt the relative error to the signal level.

In a further embodiment of the device, the timer unit acquires values of the input signal of the analog/digital converter at least at times in the form of acquired ADC input values as timer input values of a timer input value signal. In this case, the timer unit preferably influences properties of the processing and decimation filter, in particular the filter frequencies and/or the amplification and/or the attenuation of the processing and decimation filter, depending on detected ADC input values. This enables the optimal adaptation of the processing and decimation filter to the optimized sampling rate and the signal level of the line current value of the line current I _LTG .

In a further embodiment of the device, the timer unit acquires values of the input signal of the analog/digital converter at least at times in the form of acquired ADC input values as timer input values of a timer input value signal. In this case, the timer unit influences properties of the pre-filter, in particular the filter frequencies and/or the amplification and/or the damping of the pre-filter, depending on the ADC input values detected. As a result, the device adapts the pre-filter to the possibly changed sampling rates of the analog/digital converter.

In a further refinement of the device, the timer unit acquires values of the input signal of the analog/digital converter at least at times in the form of acquired ADC input values. These detected ADC input values are then used, for example, as timer input values of a timer input value signal. These timer input values of the timer input value signal then influence characteristics of the amplifier depending on the ADC input values thus detected. The properties of the amplifier that are influenced can include, in particular, the amplification and/or the attenuation of the amplifier. As a result, the device better adapts the behavior and properties of the amplifier to the possibly changed sampling rates of the analog/digital converter and/or the amplitude of the line current value of the line current I _LTG .

In a further embodiment of the device, a timer input value signal is the output signal of the analog/digital converter. An associated timer input value of the timer input value signal is then an ADC output value of the output signal of the analog/digital converter.

In a further refinement of the device, the timer unit preferably records values of the output signal of the analog/digital converter at least temporarily in the form of recorded ADC Output values as timer input values of a timer input value signal and influences sampling instants depending on detected ADC output values. The timer unit preferably influences several or all sampling times as a function of detected ADC output values.

In a further embodiment of the device, the timer unit records values of the output signal of the analog/digital converter at least at times. These detected values of the output signal of the analog/digital converter are preferably in the form of detected ADC output values. These sensed ADC output values serve as the timing inputs of a timing input signal. These timer input values of the timer input value signal affect properties of the revision and decimation filter in dependence on sensed ADC output values. The influenced properties of the processing and decimation filter can in particular include the filter frequencies and/or the amplification and/or the attenuation of the processing and decimation filter.

In a further refinement of the device, the timer unit preferably records values of the output signal of the analog/digital converter at least at times. The detected values of the output signal of the analog/digital converter are preferably in the form of detected ADC output values. These detected ADC output values are preferably used as the timer input values of a timer input value signal. The timer input values of the timer input value signal preferably influence properties of the pre-filter depending on detected ADC output values. The influenced properties of the pre-filter can in particular include the filter frequencies and/or the amplification and/or the attenuation of the pre-filter.

In a further embodiment of the device, the timer unit records values of the output signal of the analog/digital converter at least at times. The values of the output signal of the analog/digital converter are preferably in the form of detected ADC output values. These sensed sensed ADC output values preferably serve as the timer input values of a timer input value signal. The sensed timer input values of the timer input value signal affect characteristics of the amplifier depending on sensed ADC output values. The properties of the amplifier that are influenced can include, in particular, the amplification and/or the attenuation of the amplifier.

In a further embodiment of the device, a clock input value signal is the input signal of the oversampling and decimation filter. An associated timer input value is then a decimation filter input value of the input signal of the oversampling and decimation filter.

In a further refinement of the device, the timer unit acquires values of the input signal of the oversampling and decimation filter at least at times. The captured values of the oversampling and decimation filter input signal are preferably in the form of captured decimation filter input values. These detected decimation filter input values preferably serve as the timer input values of a timer input value signal. The timer input values of the timer input value signal influence the sampling instants depending on detected decimation filter input values.

In a further refinement of the device, the timer unit acquires values of the input signal of the oversampling and decimation filter at least at times. The captured values of the oversampling and decimation filter input signal are preferably in the form of captured decimation filter input values. The detected decimation filter input values preferably serve as timer input values of a timer input value signal. These timer input values of the timer input value signal preferably influence properties of the revision and decimation filter depending on detected decimation filter input values. Such properties of the processing and decimation filter can in particular be the filter frequencies and/or the amplification and/or the attenuation of the processing and decimation filter.

In a further refinement of the device, the timer unit acquires values of the input signal of the oversampling and decimation filter at least at times. The detected values of the input signal of the oversampling and decimation filter are preferably in the form of detected decimation filter input values. These detected decimation filter input values preferably serve as the timer input values of a timer input value signal. These timer input values of the timer input value signal influence properties of the pre-filter depending on detected decimation filter input values. In this case, properties of the pre-filter can be, in particular, the filter frequencies and/or the amplification and/or the attenuation of the pre-filter.

In a further embodiment of the device, the timer unit records at least time wise values of the input signal of the oversampling and decimation filter. The oversampling and decimation filter input signal values are preferably in the form of detected decimation filter input values. The detected decimation filter input values preferably serve as timer input values of a timer input value signal. The timer unit influences the properties of the amplifier by means of these timer input values of the timer input value signal. The timer unit thus influences the properties of the amplifier as a function of the detected decimation filter input values. In this case, such an influenced property of the amplifier can be, for example, the amplification and/or the attenuation of the amplifier.

In a further embodiment of the device, a clock input value signal is the output signal of the oversampling and decimation filter. In this embodiment, for example, a corresponding timer input value is a decimation filter output value of the output signal of the oversampling and decimation filter.

In a further embodiment of the device, the timer unit acquires values of the output signal of the oversampling and decimation filter at least at times. This acquisition of the oversampling and decimation filter output signal values is preferably in the form of acquired decimation filter output values. These detected decimation filter output values preferably serve as timer input values of a timer input value signal and influence sampling times as a function of detected decimation filter output values.

In a further embodiment of the device, the timer unit acquires values of the output signal of the oversampling and decimation filter at least at times. The oversampling and decimation filter output values are preferably in the form of detected decimation filter output values. The detected decimation filter output values preferably serve as timer input values of a timer input value signal. The timer input values of the timer input value signal preferably influence properties of the revision and decimation filter depending on detected decimation filter output values. Such properties of the processing and decimation filter can be, for example, in particular the filter frequencies and/or the amplification and/or the attenuation of the processing and decimation filter.

In a further embodiment of the device, the timer unit at least temporarily acquires values of the output signal of the oversampling and decimation filter in the form of acquired decimation filter output values as timer input values of a timer input value signal. In this refinement, the timer unit influences properties of the pre-filter as a function of detected decimation filter output values. Such properties of the pre-filter can be, for example, in particular the filter frequencies and/or the amplification and/or the attenuation of the pre-filter.

In terms of the document presented here, a sampling period represents the time between a first sampling time and a second sampling time. The first sampling time is a time when the analog value of the input signal of the analog-to-digital converter is sampled by the analog-to-digital converter. The second sampling time is a second time when the analog value of the input signal of the analog-to-digital converter is sampled by the analog-to-digital converter, the second sampling time immediately following the first sampling time.

In a further refinement of the device, the timer unit influences the sampling period of the analog/digital converter as a function of the at least one recorded respective timer input value.

According to a further refinement of the device, the duration of the sampling period is above the value of a sampling period limit value if absolute values of the detected ADC input values are below a first ADC input threshold value. Conversely, if magnitudes of the sensed ADC input values are above the first ADC input threshold, the duration of the sample period is less than the value of the sample period limit.

According to a further refinement of the device, the duration of the sampling period is above a sampling period limit value if amounts of the detected ADC output values are below a first ADC output threshold value. Conversely, in this configuration of the device, the sampling period is preferably below the sampling period limit value if magnitudes of the detected ADC output values are above the first ADC output threshold value.

According to a further refinement of the device, the sampling period is above a sampling period limit value if amounts of the detected decimation filter input values are below a first decimation filter input threshold value. In particular, the sample period is below the sample period limit when magnitudes of the detected decimation filter input values are above the first decimation filter input threshold.

According to a further refinement of the device, the sampling period is above a sampling period limit value if absolute values of the detected decimation filter output values are below a first decimation filter output threshold value. In particular, the sample period is below the sample period limit when magnitudes of the detected decimation filter output values are above the first decimation filter output threshold.

The oversampling and decimation filter preferably has an upper limit frequency f _o .

According to a further embodiment of the device, the oversampling and decimation filter attenuates signal components with a signal component frequency above the upper limit frequency f _o more than signal components with a signal component frequency directly below the upper limit frequency f _o . This means that the oversampling and decimation filter behaves like a low-pass filter for signal components with a signal component frequency at least in the vicinity of the cut-off frequency f _o of the oversampling and decimation filter. The technical teaching presented here expressly points out that the oversampling and decimation filter can also be a bandpass filter or another filter with a partial low-pass character, for example. In this configuration of the device, the timer unit preferably influences the upper limit frequency f _o of the oversampling and decimation filter as a function of the at least one detected timer input value.

According to a further embodiment of the device, in a first sub-configuration the upper cut-off frequency f _o of the oversampling and decimation filter is above a decimation cut-off frequency limit value if magnitudes of the detected ADC input values are below a second ADC input threshold value. In a second sub-configuration, the upper cutoff frequency f _o of the oversampling and decimation filter is below the decimation cutoff frequency limit when magnitudes of the sensed ADC input values are above the second ADC input threshold.

According to a further embodiment of the device, in the first sub-configuration the upper cut-off frequency f _o of the oversampling and decimation filter is above a decimation cut-off frequency limit if absolute values of the detected ADC output values are below a second ADC output threshold value. In a second sub-configuration, the upper cutoff frequency f _o of the oversampling and decimation filter is below the decimation cutoff frequency limit when magnitudes of the sensed ADC output values are above the second ADC output threshold.

According to a further embodiment of the device, in a first sub-configuration the upper cut-off frequency f _o of the oversampling and decimation filter is above a decimation cut-off frequency limit if absolute values of the detected decimation filter input values are below a second decimation filter input threshold value. In a second sub-configuration, the upper cutoff frequency f _o of the oversampling and decimation filter is below the decimation cutoff frequency limit when magnitudes of the detected decimation filter input values are above the second decimation filter input threshold.

According to a further embodiment of the device, in a first sub-configuration the upper cut-off frequency f _o of the oversampling and decimation filter is above a decimation cut-off frequency limit value if magnitudes of the detected decimation filter output values are below a second decimation filter output threshold value. In a second sub-configuration, the oversampling and decimation filter upper cutoff frequency f _o is above the decimation cutoff frequency limit when magnitudes of the detected decimation filter output values are above the second decimation filter output threshold.

According to a further embodiment of the device, the pre-filter preferably has an upper limit frequency f _oV . The pre-filter preferably attenuates signal components with a signal component frequency above the upper limit frequency f _oV more than signal components with a signal component frequency directly below the upper limit frequency f _oV . According to this configuration of the device, the timer unit influences the upper cut-off frequency f _oV of the pre-filter as a function of the at least one detected respective timer input value.

According to a further embodiment of the device, in a first sub-configuration the upper cut-off frequency f _oV of the pre-filter is above a pre-filter cut-off frequency limit if amounts of the detected ADC input values are below a third ADC input threshold value. In a second sub-configuration, the pre-filter upper cut-off frequency f _oV is below the pre-filter cut-off frequency limit when magnitudes of the sensed ADC input values are above the third ADC input threshold.

According to a further embodiment of the device, in a first sub-configuration, the upper cut-off frequency f _oV of the pre-filter is above a pre-filter cut-off frequency limit value if Amounts of the detected ADC output values are below a third ADC output threshold value. In a second sub-configuration, the pre-filter upper cut-off frequency f _oV is below the pre-filter cut-off frequency limit when magnitudes of the sensed ADC output values are above the third ADC output threshold.

According to a further embodiment of the device, in a first sub-configuration the upper cut-off frequency f _oV of the pre-filter is above a pre-filter cut-off frequency limit if amounts of the detected decimation filter input values are below a third decimation filter input threshold value. In a second sub-configuration, the pre-filter upper cut-off frequency f _oV is below a pre-filter cut-off frequency limit when magnitudes of the detected decimation filter input values are above the third decimation filter input threshold.

According to a further embodiment of the device, in a first sub-configuration the upper cut-off frequency f _oV of the pre-filter is above a pre-filter cut-off frequency limit value when amounts of the detected decimation filter output values are below a third decimation filter output threshold value. In a second sub-configuration, the pre-filter upper cut-off frequency f _oV is above a pre-filter cut-off frequency limit when magnitudes of the detected decimation filter output values are above the third decimation filter output threshold.

According to a further configuration of the device, the amplifier has properties with property values. The timer unit influences this property of the amplifier as a function of the at least one detected respective timer input value. Such properties of the amplifier can in particular be an amplification and/or an attenuation of the amplifier.

A further configuration of the device is possible in two different sub-configurations. In the first sub-expression, a property value of a property of the amplifier is above an amplifier property limit value if amounts of the detected ADC input values are below a fourth ADC input threshold value. In the first sub-expression, the property value of the property of the amplifier is below the amplifier property limit when magnitudes of the sensed ADC input values are above the fourth ADC input threshold. In the second, alternative sub-development, a property value of a property of the amplifier is below an amplifier property limit value if magnitudes of the detected ADC input values are below a fourth ADC input threshold value. In the second, alternative sub-expression, the property value of the property of the amplifier is above the amplifier property limit if absolute values of the detected ADC input values are above the fourth ADC input threshold value. The document presented here sees the variants a) and b) of this expression expressly as alternatives to each other.

According to a further configuration of the device, the device controls a property value of a property of the amplifier in a first way and in a second way. When controlled in the first manner, in a first sub-configuration a property value of a property of the amplifier is above an amplifier property limit when magnitudes of sensed ADC output values are below a fourth ADC output threshold. When controlled in the first manner, in a second sub-configuration a property value of a property of the amplifier is below the amplifier property limit when magnitudes of sensed ADC output values are above the fourth ADC output threshold. When controlled in the second manner, in a first sub-configuration, a property value of a property of the amplifier is below an amplifier property limit when magnitudes of sensed ADC output values are below a fourth ADC output threshold. When controlled in the second manner, in a second sub-configuration, a property value of a property of the amplifier is above the amplifier property limit when magnitudes of sensed ADC output values are above the fourth ADC output threshold. The document presented here therefore provides for the variants of the control of a property value of a property of the amplifier according to the first way and according to the second way expressly alternative to each other.

According to a further configuration of the device, the device controls a property value of a property of the amplifier in a first way and in a second way. When controlled in the first manner, in a first sub-configuration a property value of a property of the amplifier is above an amplifier property limit when magnitudes of the sensed decimation filter input values are below a fourth decimation filter input threshold. When controlled in the first manner, in a second sub-configuration a characteristic value of a characteristic of the amplifier is below the amplifier characteristic limit when magnitudes of the sensed decimation filter input values are above the fourth decimation filter input threshold. When controlled in the second manner, in a first sub-configuration, a property value of a property of the amplifier is below an amplifier property limit when amounts of the detected decimation filter input values are below a fourth decimation filter input threshold. When controlled in the second manner, in a second sub-configuration, a property value of a property of the amplifier is above the amplifier property limit when magnitudes of the sensed decimation filter input values are above the fourth decimation filter input threshold. The document presented here therefore provides for the variants of the control of a property value of a property of the amplifier according to the first way and according to the second way expressly alternative to each other.

According to a further configuration of the device, the device controls a property value of a property of the amplifier in a first way and in a second way. When controlled in the first manner, in a first sub-configuration a property value of a property of the amplifier is below an amplifier property limit when magnitudes of the sensed decimation filter output values are below a fourth decimation filter output threshold. When controlled in the first manner, in a second sub-configuration, a property value of a property of the amplifier is above the amplifier property limit when magnitudes of the sensed decimation filter output values are above the third decimation filter output threshold. When controlled in the second manner, in a first sub-configuration a property value of a property of the amplifier is above an amplifier property limit when magnitudes of the sensed decimation filter output values are below a fourth decimation filter output threshold. When controlled in the second manner, in a second sub-configuration, a property value of a property of the amplifier is below the amplifier property limit when magnitudes of the sensed decimation filter output values are above the third decimation filter output threshold. The document presented here therefore provides for the variants of the control of a property value of a property of the amplifier according to the first way and according to the second way expressly alternative to each other.

The above device corresponds to a method. This is a method for detecting an electrical line current I _LTG in a line. The electrical line current flows through a shunt resistor. As a result of this current flow, a shunt resistance voltage Us drops across the shunt resistor.

The method includes detecting and pre-filtering the shunt resistance voltage Us to form an amplifier input voltage U _e by means of a pre-filter.

The method also includes detecting and amplifying the amplifier input voltage U _e to form said amplifier output signal by means of an amplifier.

Furthermore, the method in the signal path includes sampling the amplifier output signal at a sampling rate to form a decimation filter input signal using an analog-to-digital converter.

In the signal path, the method also includes filtering the decimation filter input signal to form a decimation filter output signal by means of an oversampling and decimation filter.

The method also includes providing the decimation filter output signal as a measured value signal for at least one value of the electrical line current I _LTG in a line. In this case, the typically digital value of the decimation filter output signal represents the current value of the electrical line current I _LTG .

The method presented here is characterized in a first form in that the pre-filtering of the shunt resistance voltage U _S to form an amplifier input voltage U _e depends on a value of the amplifier output signal as a timer input value.

The method presented here is characterized in a second form in that the pre-filtering of the shunt resistance voltage U _S to form an amplifier input voltage U _e depends on a value of the decimation filter input signal as a timer input value.

The method presented here is distinguished in a third form in that the pre-filtering of the shunt resistance voltage U _S to form an amplifier input voltage U _e depends on a value of the decimation filter output signal as the timer input value.

The method presented here is distinguished in a fourth form in that the detection and amplification of the amplifier input voltage U _e to form an amplifier output signal depends on a value of the amplifier output signal as a timer input value.

The method presented here is distinguished in a fifth form in that the detection and amplification of the amplifier input voltage U _e to form an amplifier output signal depends on a value of the decimation filter input signal as a timer input value.

The method presented here is characterized in a sixth form by the fact that the Detecting and amplifying the amplifier input voltage U _e to form an amplifier output signal depends on a value of the decimation filter output signal as a timer input value.

The method presented here is distinguished in a seventh form in that the sampling of the amplifier output signal at a sampling rate for a decimation filter input signal depends on a value of the amplifier output signal as a timer input value.

The method presented here is characterized in an eighth embodiment in that the sampling of the amplifier output signal at a sampling rate for a decimation filter input signal depends on a value of the decimation filter input signal as a timer input value.

The method presented here is characterized in a ninth form in that the sampling of the amplifier output signal at a sampling rate for a decimation filter input signal depends on a value of the decimation filter output signal as a timer input value.

The method presented here is characterized in a tenth form in that the filtering of the decimation filter input signal to form a decimation filter output signal depends on a value of the amplifier output signal as a timer input value.

The method presented here is distinguished in an eleventh form in that the filtering of the decimation filter input signal to form a decimation filter output signal depends on a value of the decimation filter input signal as a timer input value.

The method presented here is distinguished in a twelfth form in that the filtering of the decimation filter input signal to form a decimation filter output signal depends on a value of the decimation filter output signal as a timer input value.

If necessary, the first to twelfth forms of the method can also be combined with one another if the technical teaching of the document presented here is reworked. Some of the characteristics represent feedback that can lead to instabilities. Therefore, it makes sense if the timer unit has a low-pass character in these cases and does not follow the changes arbitrarily quickly.

In a thirteenth form of the method presented here, a filter property of the pre-filtering of the shunt resistance voltage Us to form an amplifier input voltage U _e , in particular a pre-filter limit frequency f _oV , depends on the timer input value. With regard to the timer input values, the publication presented here again refers to the preceding text.

In a fourteenth form of the method presented here, a property of detecting and amplifying the amplifier input voltage U _e to form an amplifier output signal, in particular an amplification or an attenuation, depends on the timer input value.

In a fifteenth embodiment of the method presented here, a property of the sampling of the amplifier output signal to form a decimation filter input signal, in particular a sampling time and/or one with a sampling period, depends on the timer input value.

In a sixteenth form of the method presented here, a property of the filtering of the decimation filter input signal to form a decimation filter output signal, in particular a filter limit frequency f _o , depends on the timer input value.

In a seventeenth form of the method presented here, the method carries out the method step of pre-filtering in a first way or in a second way. When the method step of pre-filtering is carried out in the first way, in the case of a first sub-configuration the pre-filter cut-off frequency f _oV is above a pre-filter limit if amounts of timer input values are below a first input threshold value. When performing the method step of pre-filtering in the first manner, in the case of a second sub-configuration, is below the pre-filter limit if absolute values of timer input values are above the first input threshold value. When the method step of pre-filtering is carried out in the second way, in the case of a first sub-configuration the pre-filter cut-off frequency f _oV is below a pre-filter limit value if amounts of timer input values are below the first input threshold value.

In particular, the first input threshold consists of two different thresholds. In particular, the first input threshold consists of a higher threshold for switching on and a lower threshold for resetting. In this way it is avoided that switching is permanent when amounts of timer input values are close to the first input threshold value.

When the method step of pre-filtering is carried out in the second way, the pre-filter limit lies in the case of a second sub-configuration frequency f _oV above the pre-filter limit if magnitudes of timer input values are above the first input threshold. The document presented here therefore expressly provides alternative ways of carrying out the method step of pre-filtering according to the first way and according to the second way.

In an eighteenth form of the method presented here, the method carries out the method step of amplification in a first way or in a second way. When performing the step of gaining in the first manner, in the case of a first sub-configuration, the magnitude of the gain is above a gain limit when magnitudes of timer input values are below a second input threshold. In performing the step of gaining in the first manner, in the case of a second sub-configuration, the magnitude of the gain is below the gain limit when magnitudes of timer input values are above the second input threshold. When performing the step of gaining in the second manner, in the case of a first sub-configuration, the magnitude of the gain is below a gain limit when magnitudes of timer input values are below the second input threshold.

In particular, the second input threshold consists of two different thresholds. In particular, the second input threshold consists of a higher threshold for switching on and a lower threshold for resetting. In this way it is prevented that switching is permanent when amounts of timer input values are close to the second input threshold value.

When performing the step of amplification in the second manner, in the case of a second sub-configuration, the magnitude of the amplification is above the amplification limit when magnitudes of timer input values are above the second input threshold. The specification presented here therefore provides for the variants of carrying out the method step of amplification according to the first way and according to the second way to be expressly alternative to one another.

In a nineteenth form of the method presented here, the method carries out the method step of scanning in a first way or in a second way. In performing the sampling step in the first manner, in the case of a first sub-configuration, the sampling period is above a sampling period limit when magnitudes of timer input values are below a third input threshold.

In particular, the third input threshold consists of two different thresholds. In particular, the third input threshold consists of a higher threshold for switching on and a lower threshold for resetting. In this way it is avoided that switching is permanent when amounts of timer input values are close to the third input threshold value.

In performing the sampling step in the first manner, in the case of a second sub-configuration, the sampling period is below the sampling period limit when magnitudes of timer input values are above the third input threshold. In performing the sampling step in the second manner, in the case of a first sub-configuration, the sampling period is below the sampling period limit if magnitudes of timer input values are below the third input threshold. In performing the sampling step in the second manner, in the case of a second sub-configuration, the sampling period is above the sampling period limit when magnitudes of timer input values are above the third input threshold. The document presented here therefore expressly provides alternative ways of carrying out the method step of scanning according to the first way and according to the second way.

In a twentieth embodiment of the method presented here, the method carries out the method step of filtering in a first way or in a second way. When performing the method step of filtering in the first way, in the case of a first sub-configuration, the absolute value of the filter cut-off frequency f _o is above a filter cut-off frequency limit if absolute values of timer input values are below a fourth input threshold value. When performing the method step of filtering in the first way, in the case of a second sub-configuration, the absolute value of the filter cut-off frequency f _o is below the filter cut-off frequency limit if absolute values of timer input values are above the fourth input threshold value. When performing the method step of filtering in the second way, in the case of a first sub-configuration, the absolute value of the filter cut-off frequency f _o is below the filter cut-off frequency limit if absolute values of timer input values are below a fourth input threshold value. In particular, the fourth input threshold consists of two different thresholds. In particular, the fourth input threshold consists of a higher threshold to switch on and a lower threshold to reset. This prevents permanent switching when amounts of timer input values are close to the fourth input threshold value.

When performing the method step of filtering in the second way, in the case of a second sub-configuration, the absolute value of the filter cut-off frequency f _o is above the filter cut-off frequency limit if absolute values of timer input values are above the fourth input threshold value. The document presented here therefore expressly provides alternative ways of carrying out the method step of filtering according to the first way and according to the second way.

The device according to the invention and the method according to the invention enable sensor measurements with very small voltage drops across the sensor element of the sensor and the resulting very small input voltages.

By combining these two principles, the time to the averaged result remains independent of the input voltage.

With small input voltages, the signal-to-noise ratio (SNR) is increased compared to the prior art without increasing the measurement time.

For large input voltages, the SNR is no longer the limiting parameter for accuracy. In the attached example, the time for a measurement without loss of accuracy is reduced from 5.6ms to about 2.05ms.

Further advantageous configurations, features and functions of the invention are explained in connection with the examples shown in the figures.

• 1 eine schematische Darstellung einer Vorrichtung gemäß dem Stand der Technik;
• 2 ein Ausführungsbeispiel der erfindungsgemäßen Vorrichtung in einer schematischen Darstellung;
• 3 ein weiteres Ausführungsbeispiel der erfindungsgemäßen Vorrichtung in einer schematischen Darstellung;
• 4 ein weiteres Ausführungsbeispiel der erfindungsgemäßen Vorrichtung in einer schematischen Darstellung;
• 5 ein weiteres Ausführungsbeispiel der erfindungsgemäßen Vorrichtung in einer schematischen Darstellung;
• 6 ein weiteres Ausführungsbeispiel der erfindungsgemäßen Vorrichtung in einer schematischen Darstellung;
• 7 ein weiteres Ausführungsbeispiel der erfindungsgemäßen Vorrichtung in einer schematischen Darstellung;
• 8 ein Beispiel für eine dynamische Überabtastung in Abhängigkeit von der Verstärkereingangsspannung U_e am Verstärker einer erfindungsgemäßen Vorrichtung;
• 9 eine Gesamtwandelzeit T_G in Abhängigkeit der Verstärkereingangsspannung U_e und Betriebsbereiche einer erfindungsgemäßen Vorrichtung; und
• 10 einen Restfehler e durch Rauschen in Abhängigkeit von der Verstärkereingangsspannung U_e.

This shows:

• 1 a schematic representation of a device according to the prior art;
• 2 an embodiment of the device according to the invention in a schematic representation;
• 3 a further embodiment of the device according to the invention in a schematic representation;
• 4 a further embodiment of the device according to the invention in a schematic representation;
• 5 a further embodiment of the device according to the invention in a schematic representation;
• 6 a further embodiment of the device according to the invention in a schematic representation;
• 7 a further embodiment of the device according to the invention in a schematic representation;
• 8th an example of dynamic oversampling as a function of the amplifier input voltage U _e at the amplifier of a device according to the invention;
• 9 a total conversion time T _G as a function of the amplifier input voltage U _e and operating ranges of a device according to the invention; and
• 10 a residual error e due to noise as a function of the amplifier input voltage U _e .

1 FIG. 12 shows an example of the use of an oversampling and decimation filter 300 according to the prior art (SdT).

The example application shown comprises a circuit unit 100 and an analog-to-digital converter 200 and an oversampling and decimation filter 300.

The circuit unit 100 according to the prior art comprises a first node 101, a second node 102, a third node 103 and a fourth node 104.

Circuit unit 100 also includes a first resistor 111, a second resistor 112 and a shunt resistor 113.

The first resistor 111 can have a value of 0 ohms. The first resistor 111 can therefore also be just a line section of an electrical line.

The second resistor 112 may have a value of 0 ohms. The second resistor 112 can therefore also be just a piece of line of an electrical line.

The first node 101 is connected to a first terminal of the first resistor 111 and a first terminal of the shunt resistor 113 .

A second terminal of the first resistor 111 is connected to the second node 102 .

A second terminal of the shunt resistor 113 is connected to the third node 103 .

Furthermore, a first connection of the second resistor 112 is connected to the third node 103 . Furthermore, a second connection of the second resistor 112 is connected to the fourth node 104 .

Thus, the first terminal of the shunt resistor 113 is electrically connected directly or indirectly to the first terminal of the first resistor 111 and to the first node 101 . Furthermore, the second terminal of the shunt resistor 113 is electrically connected directly or indirectly to the first terminal of the second resistor 112 and to the third node 103 .

Circuit unit 100 further includes a capacitor C and an amplifier 130.

The analog to digital converter 200 is electrically connected to the amplifier 130 . Furthermore, the oversampling and decimation filter 300 is electrically connected to the analog-to-digital converter 200 .

A signal path extends from the shunt resistor 113 to an output of the oversampling and decimation filter 300. The signal path includes the shunt resistor 113, the amplifier 130, the analog to digital converter 200 and the oversampling and decimation Filter 300. The output of the amplifier 130 is electrically connected to the input of the analog/digital converter 200. Furthermore, the output of the analog-to-digital converter 200 is electrically connected to the input of the oversampling and decimation filter 300 .
In particular, the shunt resistor 113 serves as a signal source.
In particular, the output of the oversampling and decimation filter 300 serves as a measured value output.

The circuit unit 100 is here a circuit for a shunt measurement of a current I _LTG in a line. The line can be a data bus line, for example. For example, the shunt resistor 113 can be a bus shunt resistor for an auto-addressing device for use in an auto-addressing method of a LIN data bus or CAN data bus or another automotive data bus.

The electrical line current I _LTG flows from the first node 101 via the shunt resistor 113 to the third node 103. A shunt resistance voltage Us drops across the shunt resistor 113 in the process.

A first terminal of capacitor C is connected to second node 102 and a second terminal of capacitor C is connected to fourth node 104 .

A first amplifier input 131 of the amplifier 130 is connected to the second node 102 and a second amplifier input 132 of the amplifier 130 is connected to the fourth node 104 . Thus, the second connection of the first resistor 111 and the first connection of the capacitor C are connected to the first amplifier input 131 via the second node 102 .

Furthermore, the second connection of the second resistor 112 and the second connection of the capacitor C are connected to the second amplifier input 132 via the fourth node 104 . In particular, the first amplifier input 131 is a positive input (+) of the amplifier 130. In particular, the second amplifier input 132 is a negative input (-) of the amplifier 130.

The capacitor C forms with the first resistor 111 and the second resistor 112 and the shunt resistor 113 in the in 1 shown example a pre-filter 120.

The pre-filter 120 filters the shunt resistance voltage Us to an amplifier input voltage U _e of the amplifier 130.

The amplifier input voltage U _e drops between the positive input (+) 131 of the amplifier 130 and the negative input (-) 132 of the amplifier 130. The amplifier 130 has an amplifier output 133 . The amplifier output 133 outputs an amplifier output signal 134 . The amplifier 130 forms the value of the amplifier output signal 134 from the amplifier input voltage U _e by means of a linear mapping. The amplifier output signal 134 serves as the input signal of the analog/digital converter 200.

In particular, the amplifier output signal 134 corresponds to an analog input signal 201 of the analog-to-digital converter 200.

The analog-to-digital converter 200 samples the analog value of the input signal 201 at sampling times. The sampling times are preferably periodic with a temporal sampling period. In the sense of this document, the reciprocal of the sampling period is the sampling frequency. For the purposes of this document, the sampling frequency divided by 2π is the sampling rate. In order to determine a sampling period, a suitable measuring device records within the meaning of this document the time interval between a first sampling time and a second sampling time immediately following in time.

The analog-to-digital converter 200 converts the analog input signal 201 into a digital output signal 202 .

In this case, the analog/digital converter 200 converts the analog value of the input signal 201 into a digital value of the digital output signal 202 at these sampling times.

The output of analog-to-digital converter 200 may include multiple electrical lines.

The rework and decimation filter 300 has a digital input and an output. The digital output signal 202 of the analog-to-digital converter 200 serves as the decimation filter input signal 301.

After the sampling, the analog-to-digital converter 200 uses the digital output signal 202 to signal the relevant sampling value to the input of the oversampling and decimation filter 300.

At its output, the rework and decimation filter 300 provides a decimation filter output signal 302 .

In particular, the output values of the decimation filter output signal 302 represent at least temporarily the current values detected by the device for a line current I _LTG through the shunt resistor 113. The limitation to “temporarily” comes about because the analog-to-digital converter 200 is only active at the sampling times can detect the current value of the line current I _LTG .

In particular, the rework and decimation filter 300 is a linear filter. As a result, an increase in the input signal preferably results in a corresponding proportional change in the output signal.

According to the prior art, the first node 101 can be connected to further circuits, not shown here, or to one or more voltage and/or current sources, also not shown. For example, the in 1 be connected to one or more subsequent and/or preceding bus nodes or a bus master when the shunt resistor 113 is a bus shunt resistor in a LIN data bus with auto-addressing.

2 shows in an exemplary manner the basic principle of the device according to the invention. In the 2 shown device according to the invention comprises compared to in 1 prior art shown also has a timer unit 400. The timer unit 400 detects at least one timer input value signal 401.

in the in 2 illustrated embodiment of the invention, the amplifier output signal 134 serves as a timer input value signal or as a timer input value 401.

The amplifier output signal 134 corresponds in the in 2 illustrated example at the same time as an analog input signal 201 of the analog-to-digital converter 200. It is conceivable that between the amplifier output 133 and the input of the analog-to-digital converter 200 further signal processing sub-devices such as filters or the like are arranged in the signal path. The analog input signal 201 of the analog-to-digital converter 200 includes the amplifier output signal 134. If further signal processing sub-devices are used, the analog input signal 201 of the analog-to-digital converter 200 does not necessarily correspond to the amplifier output signal 134.

in the in 2 In the example shown, timer unit 400 controls the sampling rate and/or the sampling times of analog/digital converter 200 depending on the value of timer input value signal 401.

The timer unit 400 signals operating parameters of the analog-to-digital converter 200 to the analog-to-digital converter 200 via a sampling control line 402 . For example, the clock can be a sampling clock with a clock rate. This clock rate is then typically the sampling rate of analog/digital converter 200. Analog/digital converter 200 can also convert this clock rate of the clock into a sampling rate of a sampling clock of analog/digital converter 200 using a PLL or the like, for example. However, depending on the implementation, it can also be a serial or parallel data bus or the like with a data bus protocol.

Sampling typically requires compliance with Nyquist's theorem.

The resistance value of the first resistor 111 and the second resistor 112 are preferably different from 0 ohms, so that by scanning im on the circuit unit 100 subsequent analog-to-digital converter 200, the Nyquist condition remains satisfied.

The sampling of the input signal 201 of the analog/digital converter 200 or of the amplifier output signal 134 by the analog/digital converter 200 produces artefacts. To avoid these artefacts, the pre-filter 120 is provided on the one hand and the oversampling and decimation filter 300 is provided on the other.

If the sampling rate changes, the device or the proposed method should preferably adapt the limit frequencies.

The timing unit 400 therefore adapts the filter properties of the oversampling and decimation filter 300 to the sampling rate of the analog-to-digital converter 200 . Since the sampling rate of the analog-to-digital converter 200 depends on the timer input value 401, the filter properties of the oversampling and decimation filter 300 also depend on the timer input value 401. A relevant filter property of the oversampling and decimation filter 300 is preferably an upper limit frequency f _o of the oversampling and decimation filter 300.

In particular, the oversampling and decimation filter 300 is a low pass. However, more complex frequency-dependent spectral filter profiles of the oversampling and decimation filter 300 are also conceivable, which then typically always have an upper limit frequency f _o . The timer unit 400 preferably controls at least one filter property of the oversampling and decimation filter 300 by means of a decimation filter control line 403. The decimation filter control line 403 can include one or more lines. Typically, the oversampling and decimation filter 300 is a digital filter. Preferably, the lines of the decimation filter control line 403 then represent a control word that the oversampling and decimation filter 300 configures. It is also conceivable that the decimation filter control line 403 is a serial or parallel data bus.

in the in 2 In the example shown, timing unit 400 controls parameters of oversampling and decimation filter 300 via decimation filter control line 403. These parameters of oversampling and decimation filter 300, which timing unit 400 controls via decimation filter control line 403, are, for example, the frequency response and /or the amplification or the attenuation of the oversampling and decimation filter 300. In particular, it is the said upper limit frequency f _o of the oversampling and decimation filter 300.

Furthermore, the timer unit 400 controls in the in 2 example shown via the sampling control line 402 parameters of the analog-to-digital converter 200. These parameters of the analog-to-digital converter 200, which the timer unit 400 controls via the sampling control line 402, are, for example, the sampling rate or sampling times of the analog-to-digital converter 200.

In one variant, the pre-filter 120 does not include the second resistor 112. In the case of a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly referred to as ground).

In a further variant, the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In a further variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, in front of the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, behind the amplifier 130 .

3 shows a further embodiment of the device according to the invention. This in 3 The exemplary embodiment shown essentially corresponds to that in 2 illustrated embodiment.

This in 3 illustrated embodiment differs from that in 2 illustrated embodiment characterized in that the timer input value signal 401 of the timer unit 400 is not as in the example of 2 corresponds to the analog input signal 201 of the analog-to-digital converter 200 or to the amplifier output signal 134 . in the in 3 In the exemplary embodiment illustrated, the timer input value signal 401 of the timer unit 400 corresponds to the decimation filter output signal 302.

In a preferred embodiment, in which all components, ie the amplifier 130, the analog-to-digital converter 200 and the oversampling and decimation filter 400 are linear, the control behavior of a device according to the 3 into a system of 2 and vice versa.

while in the in 2 illustrated embodiment, the timer input value signal 401 is an analog signal, that is in the in 3 In the illustrated embodiment, the timer input value signal 401 is a digital signal. As a result, the spectral properties of the timer input value signal 401 differ.

in the in 2 In the exemplary embodiment illustrated, the timer unit 400 typically includes comparators and, if necessary, analog threshold generators for comparing the input signal 201 of the analog-to-digital converter 200 or the amplifier output signal 134 with threshold values of such generated threshold signals of the analog threshold generators.

When using the decimation filter output signal 302 as the timer input value signal 401, the behavior of the timer unit 400 must take into account the artefacts caused by the sampling.

in the in 3 In the example shown, timing unit 400 controls parameters of oversampling and decimation filter 300 via decimation filter control line 403. These parameters of oversampling and decimation filter 300, which timing unit 400 controls via decimation filter control line 403, are, for example, the frequency response and /or the amplification or the attenuation of the oversampling and decimation filter 300. In particular, it is the said upper limit frequency f _o of the oversampling and decimation filter 300.

Furthermore, the timer unit 400 controls in the in 3 example shown, parameters of the analog-to-digital converter 200 via the sampling control line 402. These parameters of the analog-to-digital converter 200, which the timer unit 400 controls via the sampling control line 402, are, for example, the sampling rate or sampling times of the analog-to-digital converter 200.

In one variant, the pre-filter 120 does not include the second resistor 112. In the case of a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly referred to as ground).

In a further variant, the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In a further variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, in front of the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, behind the amplifier 130 .

4 shows a further embodiment of the device according to the invention.

4 essentially corresponds to the 2 and the 3 .

4 differs from the 2 and 3 in that the timer input value signal 401 of the timer unit 400 in the in 4 illustrated embodiment corresponds to the output signal 202 of the analog-to-digital converter 200 or the decimation filter input signal 301 .

in the in 4 In the example shown, timing unit 400 controls parameters of oversampling and decimation filter 300 via decimation filter control line 403. These parameters of oversampling and decimation filter 300, which timing unit 400 controls via decimation filter control line 403, are, for example, the frequency response and /or the amplification or the attenuation of the oversampling and decimation filter 300. In particular, it is the said upper limit frequency f _o of the oversampling and decimation filter 300.

in the in 4 In the example shown, the timing unit 400 controls parameters of the analog-to-digital converter 200 via the sampling control line 402. These parameters of the analog-to-digital converter 200, which the timing unit 400 controls via the sampling control line 402, are, for example, the sampling rate or sampling times analog-to-digital converter 200.

In a variant, the pre-filter 120 does not include the second resistor 112. In the case of a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly referred to as ground).

In a further variant, the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In a further variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, in front of the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, behind the amplifier 130 .

5 shows a further embodiment of the device according to the invention.

in the in 5 illustrated embodiment, the timer unit 400 detects a plurality of timer input values 401.

in the in 5 In the example shown, a first timer input value 401a of the timer unit 400 corresponds to the amplifier output signal 134 or the analog input signal 201 of the analog-to-digital converter 200. A second timer input value 401b of the timer unit 400 corresponds in 5 illustrated example to the digital output signal 202 of the analog-to-digital converter 200 or the decimation filter input signal 301. A third timer input value 401c of the timer unit 400 corresponds in the in 5 example shown to the decimation filter output signal 302.

The timer unit 400 controls in the in 5 example shown, parameters of the analog-to-digital converter 200 and/or the oversampling and decimation filter 300 as a function of timer input values of the timer input value signals 401. A controlled parameter of the analog-to-digital converter 200 can be sampling times and/or sampling rates. A controlled parameter of the oversampling and decimation filter 300 can be said upper limit frequency f _o of the oversampling and decimation filter 300, for example.

in the in 5 In the example shown, the timer unit 400 controls parameters of the amplifier 130 via an amplifier control line 404. These parameters of the amplifier 130, which the timer unit 400 controls via the amplifier control line 404, are, for example, the frequency response and/or the gain or the attenuation of the amplifier 130 .

in the in 5 In the example shown, timing unit 400 controls parameters of oversampling and decimation filter 300 via decimation filter control line 403. These parameters of oversampling and decimation filter 300, which timing unit 400 controls via decimation filter control line 403, are, for example, the frequency response and /or the amplification or the attenuation of the oversampling and decimation filter 300. In particular, it is the said upper limit frequency f _o of the oversampling and decimation filter 300.

in the in 5 In the example shown, the timing unit 400 controls parameters of the analog-to-digital converter 200 via the sampling control line 402. These parameters of the analog-to-digital converter 200, which the timing unit 400 controls via the sampling control line 402, are, for example, the sampling rate or sampling times Analog to digital converter.

The time behavior of the timer unit 400 when generating the signal of the amplifier control line 404 is preferably set in such a way that the system is prevented from oscillating.

It is therefore advisable to use a system simulation to model the behavior of the system, for example with a program such as Maple, and to determine the natural frequencies of the open control loop and thus to suitably manipulate the poles of the loop function.

In one variant, the pre-filter 120 does not include the second resistor 112. In the case of a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly referred to as ground).

In a further variant, the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In a further variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

In particular, when using a non-clocked amplifier 130 is the pre-filter 120 at least partially, in particular completely, arranged in front of the amplifier 130.

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, behind the amplifier 130 .

6 shows a further exemplary embodiment of the device according to the invention.

6 essentially corresponds to the in 5 illustrated embodiment, wherein the in 6 illustrated embodiment comprises a switchable pre-filter 120.

in the in 6 In the exemplary embodiment shown, the timing unit 400 not only reconfigures the cut-off frequency f _o of the oversampling and decimation filter 300, but also one or more parameters of the pre-filter 120. To this end, the timing unit 400 signals to the pre-filter 120 via a pre-filter control line 405 which parameters the pre-filter 120 to use for filtering.

The timer unit 400 preferably records a plurality of timer input values 401.

in the in 6 In the example shown, the timer unit detects the first timer input value 401a, which corresponds to the analog input signal 201 of the analog/digital converter 200 or to the amplifier output signal 134. The second timer input value 401b of the timer 400 corresponds in the in 6 illustrated example the digital output signal 202 of the analog-to-digital converter 200 or the decimation filter input signal 301. The third timer input value 401c of the timer 400 corresponds in the in 6 example shown to the decimation filter output signal 302.

The timer unit 400 controls in the in 6 example shown, parameters of the analog-to-digital converter 200 and/or the oversampling and decimation filter 300 as a function of timer input values of the timer input value signals 401. A controlled parameter of the analog-to-digital converter 200 can be sampling times and/or sampling rates. A controlled parameter of the oversampling and decimation filter 300 can be said upper limit frequency f _o of the oversampling and decimation filter 300, for example.

in the in 6 In the example shown, the timer unit 400 controls parameters of the amplifier 130 via the amplifier control line 404. These parameters of the amplifier 130, which the timer unit 400 controls via the amplifier control line 404, are, for example, the frequency response and/or the gain or the attenuation of the amplifier 130 .

in the in 6 In the example shown, timing unit 400 controls parameters of oversampling and decimation filter 300 via decimation filter control line 403. These parameters of oversampling and decimation filter 300, which timing unit 400 controls via decimation filter control line 403, are, for example, the frequency response and /or the amplification or the attenuation of the oversampling and decimation filter 300. In particular, it is the said upper limit frequency f _o of the oversampling and decimation filter 300.

in the in 6 In the example shown, timer unit 400 controls parameters of prefilter 120 via prefilter control line 405. These parameters of prefilter 120, which timer unit 400 controls via prefilter control line 405, are, for example, the frequency response and/or the gain or the attenuation and/or the upper pre-filter limit frequency f _oV of the pre-filter 120. The timing unit 400 preferably increases the upper pre-filter limit frequency f _oV of the pre-filter 120 when the timing unit 400 increases the sampling rate of the analog/digital converter 200. The timing unit 400 preferably lowers the upper pre-filter limit frequency f _oV of the pre-filter 120 when the timing unit 400 lowers the sampling rate of the analog/digital converter 200 .

In one variant, the pre-filter 120 does not include the second resistor 112. In the case of a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly referred to as ground).

In a further variant, the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In a further variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, in front of the amplifier 130 .

In particular, when using a non-clocked amplifier 130 is the pre-filter 120 at least partially, in particular fully integrated in the amplifier 130.

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, behind the amplifier 130 .

7 shows a further embodiment of the device according to the invention.

while showing 7 an exemplary implementation of a switchable pre-filter 120 according to the in 6 illustrated embodiment.

in the in 7 The exemplary embodiment illustrated, the switchable pre-filter 120 comprises an analog multiplexer or an analog connection switch 140 and a plurality of capacitances C ₁ -C _n .

The analog multiplexer or an analog connection switch 140 is connected to the timing unit 400 via a pre-filter control line 405 .

According to a signaling of the timing unit 400 via the pre-filter control line 405, the analog multiplexer or analog connection switch 140 connects the second node 102 to one or more capacitances C ₁ to C _n . This interconnection results in a capacitance value of the capacitor C being able to be set as a function of a value transmitted by means of the pre-filter control line 405 .

In one variant, the pre-filter 120 does not include the second resistor 112. In the case of a pre-filter 120 without the second resistor 112, the third node 103 and the fourth node 104 form a reference potential (commonly referred to as ground).

In a further variant, the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In a further variant, the amplifier 130 is not clocked. In particular, the amplifier 130 operates continuously.

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, in front of the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is at least partially, in particular completely, integrated in the amplifier 130 .

In particular, when using a non-clocked amplifier 130 , the pre-filter 120 is arranged at least partially, in particular completely, behind the amplifier 130 .

8th shows an example of dynamic oversampling as a function of the amplifier input voltage U _e at the amplifier of a device according to the invention.

This in 8th The diagram shown shows a settling time Ts at the amplifier of a device according to the invention as a function of the amplifier input voltage U _e . Next shows the in 8th Diagram shown shows a sampling period T _smp of the device according to the invention as a function of the amplifier input voltage U _e compared to a corresponding sampling period T _smpSDT of a device according to the prior art.

This in 8th The diagram shown shows the settling time Ts at the amplifier and the sampling period T _smp of the device according to the invention, as well as the sampling period T _smpsDT of a device according to the prior art for an amplifier input voltage U _e in a range from 0 mV to 80 mV.

in the in 8th In the exemplary diagram shown, the analog-to-digital converter has a resolution of 12 bits without oversampling. The measurement error is, for example, within a gain error of ±0.5% plus ±4 LSB as an offset. The noise behavior of the measurement is approx. 32 LSB/Sigma in the example. The required oversampling rate for 1 LSB/Sigma is 1024 in the example shown.

The settling time T _s at the amplifier is strongly dependent on the amplifier input voltage U _e . This means that the settling time T _S can be measured much more quickly in the case of small amplifier input voltages U _e and thus in the case of small line currents I _LTG than in the case of conventional devices. Due to the strong dependency of the settling time T _S at the amplifier of a device according to the invention, the sampling period T _smp set by the timer unit can be significantly smaller for small amplifier input voltages U _e than for large amplifier input voltages U _e .

In the in the in 8th In the example shown in the diagram, the sampling period T _smp of the analog-to-digital converter is in a first operating range OA ₁ at a first value, for example at 2 μs. In a second operating range OA ₂ the sampling period T _smp of the analog/digital converter is at a second value, for example 3 μs. In a third operating range OA ₃ is the Sampling period T _smp of the analog-to-digital converter at a third value, for example 5.5 μs.

In contrast, the sampling period T _smpSDT of a device according to the prior art depends on the necessary sampling rate for the maximum possible amplifier input voltage U _e .

This results in the disadvantage for a device according to the prior art that for small amplifier input voltage U _e and thus for small line currents I _LTG the sampling rate T _smpsDT in devices according to the prior art is worse than the sampling period T _smp in the device according to the invention.

In the range of low amplifier input voltage U _e , an error due to the noise is dominant, but plays a subordinate role with high amplifier input voltage U _e . This enables the oversampling of the analog-to-digital converter to be adapted so that the device according to the invention can average a larger number of measured values from a larger number of measurements when the amplifier input voltage U _e is small than when the amplifier input voltage U _e is large. For example, the oversampling and decimation filter can perform this averaging. In particular, the timer unit of the device according to the invention reparameterizes the oversampling and decimation filter depending on the sampling period T _smp set by the timer unit, in order to thus optimize the evaluation of the measured values.

In particular, the analog-to-digital converter transmits the respective samples of the input signal of the analog-to-digital converter to the oversampling and decimation filter with a respective time stamp of the respective sample. Such a time stamp of the respective sample represents the sampling time of the sample and thus enables the oversampling and decimation filter to process samples of the analog-to-digital converter that the analog-to-digital converter has not sampled at equidistant sampling times. The oversampling and decimation filter can be implemented in two stages, for example. The analog-to-digital converter thus transmits samples of the analog-to-digital converter that are not equidistant in time to the oversampling and decimation filter via the output signal of the analog-to-digital converter. A first stage of the oversampling and decimation filter generates a data stream of interpolated and preferably temporally equidistant interpolated samples from these samples of the analog/digital converter that are not equidistant in time, for example by means of polynomial interpolation. A second stage of the oversampling and decimation filter then generates, for example, from the interpolated sample values which are now equidistant in time, a data stream of filtered and interpolated sample values which are equidistant in time. The oversampling and decimation filter then outputs the data stream of filtered and temporally equidistant, interpolated samples as the decimation filter output signal.

In particular, the total conversion time per measurement remains the same to minimize effort. This is important for further processing. The timing unit preferably adapts a sample time inversely to the number of averagings.

As explained above, the device according to the invention and the method according to the invention can also use equivalent values at other points in the signal path.

9 shows a total conversion time T _G depending on the amplifier input voltage U _e and the associated operating ranges OA ₀ , OA _1, OA ₂ , OA ₃ for an amplifier input voltage U _e of 0 mV to 80 mV. The operating ranges correspond to OA _1, OA ₂ , OA ₃ of 9 those in 8th The total conversion time T _G is the time between a first output time of the output of a first measured value via the decimation filter output signal and a second output time of the output of the first measured value via the decimation filter output signal. The total conversion time T _G is determined from the current sampling period T _smp of the analog-to-digital converter multiplied by the number of samples from the analog-to-digital converter over which the oversampling and decimation filter averages for the output of a measured value via the decimation filter output signal.

A zeroth operating range OA ₀ below a minimum conversion time of 2.05 ms, for example, is neither for the proposed device nor for a device from the prior art in 9 shown range of the amplifier input voltage U _e reachable.

In the first operating range OA ₁ of a device according to the invention, the oversampling and decimation filter averages over, for example, 1024 samples of the analog-to-digital converter. The timer unit sets the oversampling and decimation filter in this first working area OA ₁ such that the oversampling and decimation filter in this first working area OA ₁ averages over said 1024 samples of the analog-to-digital converter. In this first work area, the timer unit sets OA ₁ in the in 9 example shown, the analog-to-digital converter at the same time so that the sampling period T _SMP of the analog-to-digital converter in this first work area OA ₁ is an exemplary temporal has a length of 2 µs. The total conversion time T _G then results from multiplying the 1024 samples by the 2 μs per sample, ie the sampling period T _smp , for example 2.05 ms.

in the in 9 In the example shown, an exemplary upper first input voltage limit value of approximately 21 mV limits the first operating range OA ₁ towards higher input voltage values of the input voltage U _e of the amplifier. An example amplifier input voltage of 0V limited in the in 9 illustrated example, the first input voltage range of the amplifier input voltage U _e in the first operating range OA ₁ down.

In a second operating range OA ₂ of a device according to the invention, the oversampling and decimation filter averages over, for example, 682 samples of the analog/digital converter. The timer unit sets the oversampling and decimation filter in this second working area OA ₂ so that the oversampling and decimation filter in this second working area OA ₂ averages over the said 682 samples of the analog-to-digital converter. In this second work area, the timer unit sets OA ₂ in the in 9 example shown, the analog-to-digital converter at the same time in such a way that the sampling period T _SMP of the analog-to-digital converter in this second working area OA ₂ now has an exemplary time length of 3 μs. The total conversion time T _G then results from multiplying the 682 sample values by the 3 μs per sample value, ie the sample period T _smp , again to 2.05 ms, for example. The total conversion time T _G does not change significantly in the second operating range OA ₂ compared to the total conversion time T _G in the first operating range OA ₁ .

in the in 9 In the example shown, an exemplary upper second input voltage limit value of approximately 48 mV limits the second operating range OA ₂ towards higher input voltage values of the amplifier input voltage U _e .

in the in 9 In the example shown, the exemplary upper first input voltage limit of approximately 21 mV limits the second operating range OA ₂ to lower input voltage values of the amplifier input voltage U _e .

In a third operating range OA ₃ of a device according to the invention, the oversampling and decimation filter averages over, for example, 372 samples of the analog/digital converter. The timer unit sets the oversampling and decimation filter in this third working area OA ₃ so that the oversampling and decimation filter in this third working area OA ₃ averages over the said 372 samples of the analog-to-digital converter. In this third work area, the timer unit sets OA ₃ in the in 9 example shown, the analog-to-digital converter at the same time in such a way that the sampling period T _SMP of the analog-to-digital converter in this third working area OA ₃ now has an exemplary time length of 5.5 μs. The total conversion time T _G then results from multiplying the 372 samples by the 5.5 μs per sample, ie the sampling period T _smp , again to 2.05 ms, for example. The total conversion time T _G does not change significantly in the third operating range OA ₃ compared to the total conversion time T _G in the first operating range OA ₁ and compared to the total conversion time T _G in the second operating range OA ₂ .

in the in 9 In the example shown, an exemplary upper third input voltage limit value of approximately 80 mV limits the third operating range OA ₃ towards higher input voltage values of the amplifier input voltage U _e .

in the in 9 In the example shown, the exemplary upper second input voltage limit value of approximately 48 mV limits the third operating range OA ₃ to lower input voltage values of the amplifier input voltage U _e .

in the in 9 In the example shown, the third input voltage limit value of approximately 80 mV is at the same time the exemplary specification limit for the input voltage value of the amplifier input voltage U _e .

The timer unit preferably evaluates an overall conversion time specification. The timer unit calculates the number of sample values and the sample period T _smp as a function of this overall conversion time specification and the respective timer input values of the timer input value signals used.

As before, the number of samples corresponds to the number of samples of the analog-to-digital converter. The oversampling and decimation filter uses this number of samples to calculate an output value for outputting a measurement value via the decimation filter output signal.

When using a number of timer input values of different timer input value signals, the timer unit can use a polynomial with a number of different variables for this calculation, for example. The various variables of this polynomial can then be different timer input values of the different timer input value signals. In a proposed variant, the device according to the invention therefore preferably behaves like a device from the prior art if the total conversion time T _G specified for the timer unit in the form of said total conversion time specification is above a total conversion time limit value.

An operating range OA _SDT of a device according to the prior art is above a total conversion time T _G of 5.5 ms.

This overall conversion time limit results from a sampling period T _smp =T _SDT of 5.5 μs and an averaging over 1024 sample values of the analog/digital converter in the oversampling and decimation filter. A multiplication of the exemplary sampling period T _smp =T _SDT of 5.5 μs by the number of 1024 samples of the analog-to-digital converter for averaging in the oversampling and decimation filter results in this total conversion time limit of essentially 5.5 ms.

The preset total conversion time T _G is preferably specified for the timer unit by means of data transmission from a higher-level computer system to the timer unit and associated programming of a corresponding register in the timer unit. The total conversion time limit typically results from the construction of the proposed device and the properties of the technical teaching (semiconductor technology used) used to produce the device according to the invention. In addition, the properties of the application system in which the device according to the invention is used also play a role. A further influencing factor is the specifically selected form of realization of the analog-to-digital converter and the associated properties of said analog-to-digital converter. Of course, it is also conceivable for the total conversion time T _G to be preset at the factory in relation to the timer unit.

10 shows an example suitable for the 8th and 9 a residual error e due to noise as a function of the amplifier input voltage U _e . In the 10 The solid line shown corresponds to an exemplary specification limit for clarification purposes only.

For a device according to the invention, the dashed line represents an increase in the noise due to the reduction in the number of sampling points as the amplifier input voltage U _e increases. The dotted line represents the noise for a prior art device.

The noise for a device according to the invention increases due to the reduction in the number of samples of the analog-to-digital converter used for averaging in the oversampling and decimation filter from the first operating range OA ₁ to the second operating range OA ₂ and from the second operating range OA ₃ to the third Operating range OA ₃ , but the noise is still below the specification limit.

In particular, when constructing the device according to the invention, the resulting noise must be taken into account in comparison with the respective prescribed specification. This applies, for example, to the selection of the oversampling and decimation filter, the selection of the construction and the conversion method of the analog-to-digital converter and the specifications mentioned above.

Compared to the prior art, noise in the device according to the invention increases with an increase in the amplifier input voltage U _e . However, with a large amplifier input voltage U _{e ,} the noise plays a subordinate role.

The device according to the invention offers the advantage of dynamic oversampling as a function of the amplifier input voltage U _e . With small amplifier input voltages U _{e ,} the sampling period can be chosen to be very small. The sampling period T _smp set by the timer unit can be significantly smaller in the case of small amplifier input voltages U _e than in the case of large amplifier input voltages U _e .

In contrast, the sampling period T _smpsDT of a device according to the prior art depends on the necessary sampling rate for the maximum possible amplifier input voltage U _e .

This results in the disadvantage for a device according to the prior art that for small amplifier input voltage U _e and thus for small line currents I _LTG the sampling rate T _smpsDT in devices according to the prior art is worse than the sampling period T _smp in the device according to the invention.

Reference List

100

circuit unit

101

first knot

102

second knot

103

third node

104

fourth knot

111

first resistance

112

second resistance

113

shunt resistance

120

pre-filter

130

amplifier

131

first amplifier input

132

second amplifier input

133

amplifier output

134

Amplifier output signal

140

Analog multiplexer or analog connection switch

200

Analog to digital converter

201

analog input signal

202

digital output signal

300

Oversampling and decimation filters

301

Decimation filter input signal

302

Decimation filter output signal

400

timer unit

401

Timer input value signal / timer input value

401a

first timer input value

401b

second timer input value

401c

third timer input value

402

scan control line

403

decimation filter control line

404

amplifier control line

405

pre-filter control line

ILTG

line current

C

capacitor

U.S

shunt resistance voltage

Ue

amplifier input voltage

fo

upper cutoff frequency of the oversampling and decimation filter

foV

upper limit frequency of the pre-filter

TS

Settling time at the amplifier

tmp

Sampling period of a device according to the invention

TsmpSDT

Sampling period of a prior art device

OA

operating range

OA0

zero operating range

OA1

first operating area

OA2

second operating area

OA3

third operating area

OASDT

Operating range of a device according to the prior art

Claims (15)

Device for detecting an electrical line current (I _LTG ) in a line, comprising - a first circuit unit (100), - an analog-to-digital converter (200), and - an oversampling and decimation filter (300), wherein the electrical Line current flows through the first circuit unit (100), and wherein the first circuit unit (100) is set up to detect the time profile of the value of the electrical line current (I _LTG ) in the line and to convert it to an amplifier output signal (133), and wherein the analog-to-digital converter (200) is set up to sample the amplifier output signal (133) at a sampling rate and to convert it to a decimation filter input signal (301), and wherein the oversampling and decimation filter (300) is set up to sample the decimation filter input signal (301 ) to a decimation filter output signal (302), and wherein the device is set up to provide the decimation filter output signal (302) as a measured value signal for at least one value of the electrical line current (I _LTG ) in a line, characterized in that the analog-to-digital converter (200) is set up to sample the amplifier output signal (133) at the sampling rate for the decimation filter input signal (301) as a function of a value of the amplifier output signal (133) as a timer input value, and/or that the analog/digital converter (200) does this the amplifier output signal (133) is set up to sample at the sampling rate for the decimation filter input signal (301) as a function of a value of the decimation filter input signal (301) as a timer input value, and/or that the analog-to-digital converter (200) is set up to sample the amplifier output signal (133) to sample the decimation filter input signal (301) at a sampling rate depending on a value of the decimation filter output signal (302) as a timer input value, and/or that the oversampling and decimation filter (300) is set up to transmit the decimation filter input signal (301) to the to filter the decimation filter output signal (302) depending on the value of the amplifier output signal (133) as the timer input value, and/or that the oversampling and decimation filter (300) is set up to use the decimation filter to filter the input signal (301) to the decimation filter output signal (302) depending on the value of the decimation filter input signal (301) as a timer input value, and/or that the oversampling and decimation filter (300) is set up to convert the decimation filter input signal (301) to the decimation filter output signal (302) depending on the value of the decimation filter output signal (302) as a timer input value. Device according to claim 1 , characterized in that the first circuit unit (100) comprises - a shunt resistor (113) - a pre-filter (120), and - an amplifier (130), the electrical line current (I _LTG ) flowing through the shunt resistor (113 ) flows, and a shunt resistance voltage (Us) drops across the shunt resistance (113), the pre-filter (120) being set up to pre-filter the shunt resistance voltage (Us) to form an amplifier input voltage (U _e ), and the Amplifier (130) is set up to detect the amplifier input voltage (U _e ) and amplify it to form the amplifier output signal (133). Device according to one of Claims 1 until 2 , characterized in that a property of the analog/digital converter (200), in particular a sampling time and/or the sampling period, depends on the timer input value. Device according to one of Claims 1 until 2 , characterized in that a property of the oversampling and decimation filter (300), in particular a filter cut-off frequency (f _o ), depends on the timer input value. Device according to claim 3 , characterized in that the sample period is above a sample period limit when magnitudes of timer input values are below a third input threshold, and the sample period is below the sample period limit when magnitudes of timer input values are above the third input threshold, or the sample period is below the sample period limit when magnitudes of timer input values are below the third input threshold, and the sample period is above the sample period limit when magnitudes of timer input values are above the third input threshold. Device according to claim 4 , characterized in that a magnitude of the filter cutoff frequency (f _o ) is above a filter cutoff frequency limit when magnitudes of timer input values are below a fourth input threshold, and the magnitude of the filter cutoff frequency (f _o ) is below the filter cutoff frequency limit when magnitudes of timer input values are above the fourth input threshold or the magnitude of the filter cutoff frequency (f _o ) is below the filter cutoff frequency limit when magnitudes of timer input values are below a fourth input threshold, and the magnitude of the filter cutoff frequency (f _o ) is above the filter cutoff frequency limit when magnitudes of timer input values are above the fourth input threshold. Method for detecting an electric line current (I _LTG ) in a line by means of a device according to one of the preceding claims, wherein the electric line current (I _LTG ) flows through a shunt resistor (113) and via the shunt resistor (113) a shunt -Resistance voltage (Us) drops, the method comprising the following steps: - Pre-filtering the shunt resistance voltage (U _S ) to an amplifier input voltage (U _e ); - Detecting and amplifying the amplifier input voltage (U _e ) to an amplifier output signal (133); - sampling the amplifier output signal (133) at a sampling rate to form a decimation filter input signal (301); - filtering the decimation filter input signal (301) to a decimation filter output signal (302); - Providing the decimation filter output signal (302) as a measured value signal for at least one value of the electrical line current (I _LTG ) in a line, characterized in that the pre-filtering of the shunt resistance voltage (U _S ) to the amplifier input voltage (U _e ) and / or the detection and amplifying the amplifier input voltage (U _e ) to form the amplifier output signal (133), and/or sampling the amplifier output signal (133) at the sampling rate to form the decimation filter input signal (301), and/or filtering the decimation filter input signal (301) to form the decimation filter output signal (302 ) - depends on a value of the amplifier output signal (133) as a timer input value, and/or - depends on a value of the decimation filter input signal (301) as a timer input value, and/or - depends on a value of the decimation filter output signal (302) as a timer input value. procedure according to claim 7 , characterized in that a filter property of pre-filtering the shunt resistor voltage (Us) to the amplifier input voltage (U _e ), in particular a pre-filter cutoff frequency (f _oV ) of which depends on the timer input value. procedure according to claim 7 , characterized in that a property of detecting and amplifying the amplifier input voltage (U _e ) to form the amplifier output signal (133), in particular an amplification or an attenuation, depends on the timer input value. procedure according to claim 7 , characterized in that a property of the sampling of the amplifier output signal (133) to the decimation filter input signal (301), in particular a sampling time and/or one with a sampling period, depends on the timer input value. procedure according to claim 7 , characterized in that a property of the filtering of the decimation filter input signal (301) to the decimation filter output signal (302), in particular a filter cut-off frequency (f _o ), depends on the timer input value. procedure according to claim 8 , characterized in that the pre-filter cut-off frequency (f _oV ) is above a pre-filter limit when magnitudes of timer input values are below a first input threshold, and the pre-filter cut-off frequency (f _oV ) is below the pre-filter limit when magnitudes of timer input values are above the first input threshold, or the Pre-filter cut-off frequency (f _oV ) is below the pre-filter limit when magnitudes of timer input values are below the first input threshold, and pre-filter cut-off frequency (f _oV ) is above the pre-filter limit when magnitudes of timer input values are above the first input threshold. procedure according to claim 9 , characterized in that an amount of gain is above a gain limit when amounts of timer input values are below a second input threshold, and the amount of gain is below the gain limit when amounts of timer input values are above the second input threshold, or the amount of gain is below is the gain limit when magnitudes of timer input values are below the second input threshold, and the magnitude of the gain is above the gain limit when magnitudes of timer input values are above the second input threshold. procedure according to claim 10 , characterized in that the sample period is above a sample period limit when magnitudes of timer input values are below a third input threshold, and the sample period is below the sample period limit when magnitudes of timer input values are above the third input threshold, or the sample period is below the sample period limit when magnitudes of timer input values are below the third input threshold, and the sample period is above the sample period limit when magnitudes of timer input values are above the third input threshold. procedure according to claim 11 , characterized in that a magnitude of the filter cutoff frequency (f _o ) is above a filter cutoff frequency limit when magnitudes of timer input values are below a fourth input threshold, and the magnitude of the filter cutoff frequency (f _o ) is below the filter cutoff frequency limit when magnitudes of timer input values are above the fourth input threshold or the magnitude of the filter cutoff frequency (f _o ) is below the filter cutoff frequency limit when magnitudes of timer input values are below the fourth input threshold, and the magnitude of the filter cutoff frequency (f _o ) is above the filter cutoff frequency limit when magnitudes of timer input values are above the fourth input threshold.

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